Datasheet AD7896 Datasheet (Analog Devices)

2.7 V to 5.5 V, 12-Bit, 8 ␮s

C

ADC in 8-Lead SOIC/PDIP

FEATURES
100 kHz Throughput Rate
Fast 12-Bit Sampling ADC with 8 ␮s Conversion Time
8-Lead PDIP and SOIC
Single 2.7 V to 5.5 V Supply Operation
High Speed, Easy-to-Use Serial Interface
On-Chip Track-and-Hold Amplifier
Analog Input Range Is 0 V to Supply
High Input Impedance
Low Power: 9 mW Typ

GENERAL DESCRIPTION

The AD7896 is a fast, 12-bit ADC that operates from a single

2.7 V to 5.5 V supply and is housed in small 8-lead PDIP and
8-lead SOIC packages. The part contains an 8 µs successive
approximation ADC, an on-chip track-and-hold amplifier, an
on-chip clock, and a high speed serial interface.

Output data from the AD7896 is provided via a high speed,
serial interface port. This 2-wire serial interface has a serial
clock input and a serial data output with the external serial
clock accessing the serial data from the part.

In addition to the traditional dc accuracy specifications, such as
linearity, full-scale, and offset errors, the AD7896 is also speci­fied for dynamic performance parameters, including harmonic
distortion and signal-to-noise ratio.

The part accepts an analog input range of 0 V to V

and operates

DD

from a single 2.7 V to 5.5 V supply, consuming only 9 mW
typical. The V

input is also used as the reference for the part

DD

so that no external reference is required.

The AD7896 features a high sampling rate mode and, for low
power applications, a proprietary automatic power-down mode
where the part automatically goes into power-down once conver­sion is complete and “wakes up” before the next conversion cycle.

The part is available in a small, 8-lead, 0.3'' wide, plastic or
hermetic dual-in-line package (PDIP) and in an 8-lead, small
outline IC (SOIC).

*

FUNCTIONAL BLOCK DIAGRAM

AD7896

TRACK-AND-HOLD

V

IN

ONVST

AGND DGND BUSY SCLK SDATA

PRODUCT HIGHLIGHTS

CLOCK

AD7896

V

DD

12-BIT

ADC

OUTPUT

REGISTER

1. Complete, 12-bit ADC in an 8-Lead Package.
The AD7896 contains an 8 µs ADC, a track-and-hold ampli-
fier, control logic, and a high speed serial interface, all in an
8-lead PDIP. The V

input is used as the reference for the

DD

part, so no external reference is needed. This offers consider­able space saving over alternative solutions.

2. Low Power, Single-Supply Operation.
The AD7896 operates from a single 2.7 V to 5.5 V supply
and consumes only 9 mW typical. The automatic power­down mode, where the part goes into power down once
conversion is complete and “wakes up” before the next con­version cycle, makes the AD7896 ideal for battery-powered
or portable applications.

3. High Speed Serial Interface.
The part provides high speed serial data and serial clock lines
allowing for an easy, 2-wire serial interface arrangement.

*Patent Pending

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD7896–SPECIFICATIONS

(VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V. All specifications T
unless otherwise noted.)

MIN

to T

MAX

,

Test Conditions/

Parameter A Version1B Version J Version S Version Unit Comments

DYNAMIC PERFORMANCE

Signal-to-(Noise + Distortion) Ratio

2

3

@ 25°C707070 typ 70 dB min fIN = 10 kHz Sine Wave,

= 100 kHz

f

to T

T

MIN

MAX

70 dB min

SAMPLE

Total Harmonic Distortion (THD)3–80 –80 –80 typ –80 dB max fIN = 10 kHz Sine Wave,

= 100 kHz

f

Peak Harmonic or Spurious Noise

Intermodulation Distortion (IMD)

3

3

–80 –80 –80 typ dB max fIN = 10 kHz Sine Wave,

SAMPLE

f

= 100 kHz

SAMPLE

fa = 9 kHz, fb = 9.5 kHz,

= 100 kHz

f

SAMPLE

Second Order Terms –80 –80 –80 typ –80 dB max
Third Order Terms –80 –80 –80 typ –80 dB max

DC ACCURACY

Resolution 12 12 12 12 Bits
Minimum Resolution for Which No

Missing Codes Are Guaranteed 12 12 12 12 Bits
Relative Accuracy
Differential Nonlinearity
Positive Full-Scale Error
Unipolar Offset Error ± 4 ± 4 ± 5 ± 4LSB maxV

3

3

3

± 1 ± 1/2 ± 1 ± 1LSB max
± 1 ± 1 ± 1 ± 1LSB max
± 3 ± 1.5 ±3 ±3LSB max

= 5 V ± 10%

± 4 ± 3 ± 5 ± 4LSB maxV

DD

= 2.7 V to 3.6 V

DD

ANALOG INPUT

Input Voltage Range 0 to +V

DD

0to+V

0to+VDD0 to +VDDV

DD

Input Current ± 2 ± 2 ± 2 ± 5 µA max

LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

4

2.0 2.0 2.0 2.0 V min VDD = 2.7 V to 3.6 V

2.4 2.4 2.4 2.4 V

= 5 V ± 10%

DD

0.8 0.8 0.8 0.8 V max
± 10 ± 10 ±10 ± 10 µA max VIN = 0 V to V

DD

10 10 10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

2.4 2.4 2.4 2.4 V min I

0.4 0.4 0.4 0.4 V max I

SOURCE

= 1.6 mA

SINK

= 400 ␮A

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time

Mode 1 Operation 8 8 8 8.5 µs max

Mode 2 Operation

5

14 14 14 14.5 µs max

Track-and-Hold Acquisition Time31.5 1.5 1.5 1.5 µs max

REV. C–2–

AD7896

Test Conditions/

Parameter A Version1B Version J Version S Version Unit Comments

POWER REQUIREMENTS

V

DD

I

DD

Power Dissipation 10.8 10.8 10.8 10.8 mW max V
Power-Down Mode Digital Inputs @ DGND

@ 25°C 555 typ5µA max VDD = 2.7 V to 3.6 V

I

DD

to T

T
I
T

MIN

DD

MIN

MAX

@ 25°C50505050µA max VDD = 5 V ± 10%

to T

MAX

Power Dissipation @ 25°C 13.5 13.5 13.5 13.5 µW max VDD = 2.7 V

NOTES

1

Temperature ranges are as follows: A, B Versions: –40°C to +85°C; J Version: 0°C to +70°C; S Version: –55°C to +125°C.

2

Applies to Mode 1 operation. See the section on Operating Modes.

3

See Terminology.

4

Sample tested @ 25°C to ensure compliance.

5

This 14 µs includes the wake-up time from standby. This wake-up time is timed from the rising edge of CONVST , whereas conversion is timed from the falling edge
of CONVST, for narrow CONVST pulsewidth the conversion time is effectively the wake-up time plus conversion time, hence 14 µs. This can be seen from Figure 3.
Note that if the CONVST pulsewidth is greater than 6 µs, the effective conversion time will increase beyond 14 µs.

Specifications subject to change without notice.

2.7/5.5 2.7/5.5 2.7/5.5 2.7/5.5

V min/max

4444mA max Digital Input @ DGND,

= 2.7 V to 3.6 V

V

DD

5555mA max Digital Inputs @ DGND,

= 5 V ± 10%

V

DD

= 2.7 V, Typically 9 mW

DD

15 15 75 75 µA max VDD = 2.7 V to 3.6 V

150 150 500 500 µA max VDD = 5 V ± 10%

1

TIMING CHARACTERISTICS

(VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V)

Parameter A, B Versions J Version S Version Unit Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

NOTES

1

Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.4 V.

2

The SCLK maximum frequency is 10 MHz. Care must be taken when interfacing to account for the data access time, t

processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with. See Serial Interface section for more information.

3

Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2 V.

4

Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
of the part and as such is independent of external bus loading capacitances.

40 40 40 ns min CONVST Pulsewidth

2

40

2

40

3

60

3

100
10 10 10 ns min Data Hold Time after Falling Edge of SCLK

4

50

TO

OUTPUT

PIN

50pF

40
40

60
100

50

2

2

3

4

3

1.6mA

400␮A

1.6V

45
45

70
110

50

2

2

3

3

4

ns min SCLK High Pulsewidth
ns min SCLK Low Pulsewidth

Data Access Time after Falling Edge of SCLK
ns max VDD = 5 V ± 10%
ns max VDD = 2.7 V to 3.6 V

ns max Bus Relinquish Time after Falling Edge of SCLK

, and the setup time required for the user’s

4

, quoted in the timing characteristics is the true bus relinquish time

6

Figure 1. Load Circuit for Access Time and Bus
Relinquish Time

REV. C

–3–

AD7896

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

DD

Analog Input Voltage to AGND . . . . . . –0.3 V to V

Digital Input Voltage to DGND . . . . . . –0.3 V to V

Digital Output Voltage to DGND . . . . . –0.3 V to V

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Commercial (J Version) . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial (A, B Versions) . . . . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

ORDERING GUIDE

Temperature Linearity SNR Package

Model Range Error (LSB) (dB) Option*

AD7896AN –40°C to +85°C ± 170N-8
AD7896BN –40°C to +85°C ± 1/2 70 N-8
AD7896AR –40°C to +85°C ± 170R-8
AD7896AR-REEL –40°C to +85°C ± 170R-8
AD7896AR-REEL7 –40°C to +85°C ± 170R-8
AD7896BR –40°C to +85°C ± 1/2 70 R-8
AD7896BR-REEL –40°C to +85°C ± 1/2 70 R-8
AD7896BR-REEL7 –40°C to +85°C ± 1/2 70 R-8
AD7896JR 0°C to +70°C ±170R-8
AD7896JR-REEL 0°C to +70°C ±170R-8
AD7896SQ –55°C to +125°C ± 170Q-8
EVAL-AD7896CB Evaluation Board

*N = PDIP; Q = CERDIP; R = SOIC.

PDIP Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 125°C/W

␪

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 50°C/W

␪

JC

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 260°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . .450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 160°C/W

␪

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W

␪

JC

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4000 V

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7896 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. C–4–

PIN CONFIGURATION

T

AD7896

V

V

AGND

SCLK

1

IN

2

DD

3

4

AD7896

TOP VIEW

(Not to Scale)

8

7

6

5

BUSY

CONVS

DGND

SDATA

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1V

2V

IN

DD

Analog Input. The analog input range is 0 V to VDD.

Positive supply voltage, 2.7 V to 5.5 V.

3 AGND Analog Ground. Ground reference for track-and-hold, comparator, and DAC.

4 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7896.

A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for
10 ns after this falling edge so data can be accepted on the falling edge when a fast serial clock is used.
The serial clock input should be taken low at the end of the serial data transmission.

5 SDATA Serial Data Output. Serial data from the AD7896 is provided at this output. The serial data is clocked

out by the falling edge of SCLK, but the data can also be read on the falling edge of the SCLK. This is
possible because data bit N is valid for a specified time after the falling edge of the SCLK (data hold
time) and can be read before data bit N+1 becomes valid a specified time after the falling edge of SCLK
(data access time) (see Figure 4). Sixteen bits of serial data are provided with four leading zeros followed
by the 12 bits of conversion data. On the 16th falling edge of SCLK, the SDATA line is held for the data
hold time and then disabled (three-stated). Output data coding is straight binary.

6 DGND Digital Ground. Ground reference for digital circuitry.
7 CONVST Convert Start. Edge-triggered logic input. On the falling edge of this input, the track-and-hold goes into

its hold mode and conversion is initiated. If CONVST is low at the end of conversion, the part goes into
power-down mode. In this case, the rising edge of CONVST “wakes up” the part.

8 BUSY The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin goes high on the

falling edge of CONVST and returns low when the conversion is complete.

REV. C

–5–

AD7896

TERMINOLOGY
Relative Accuracy

This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end­points of the transfer function are zero scale (which is V

IN

=

AGND + 1/2 LSB), a point 1/2 LSB below the first code transi­tion (00 . . . 000 to 00 . . . 001), and full scale (which is V
AGND + V

– 1/2 LSB), a point 1/2 LSB above the last code

DD

IN

=

transition (11 ...110 to 11 ...111).

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Unipolar Offset Error

This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal V

voltage (AGND + 1 LSB).

IN

Positive Full-Scale Error

This is the deviation of the last code transition (11 ...110 to
11 . . . 111) from the ideal (V

= AGND + VDD – 1 LSB)

IN

after the offset error has been adjusted out.

Track-and-Hold Acquisition Time

Track-and-hold acquisition time is the time required for the
output of the track-and-hold amplifier to reach its final value,
within ± 1/2 LSB, after the end of conversion (the point at which
the track-and-hold returns into track mode). It also applies to a
situation where there is a step input change on the input voltage
applied to the selected V

input of the AD7896. It means that

IN

the user must wait for the duration of the track-and-hold acquisi­tion time after the end of conversion or after a step input change

before starting another conversion, to ensure the part

to V

IN

operates to specification.

Signal-to-(Noise + Distortion) Ratio

This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the fun­damental. Noise is the sum of all nonfundamental signals up to
half the sampling frequency (f

/2), excluding dc. The ratio is

S

dependent on the number of quantization levels in the digitiza­tion process; the more levels, the smaller the quantization noise.
The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Thus, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7896, it is defined as:

2

2

2

2

2

6

5

THD dB

() log=

20

VVVVV

++++

2

3

4

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,

, V5, and V6 are the rms amplitudes of the second through the

V

4

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2 and excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is deter­mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and
(fa – 2fb).

The AD7896 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa­rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
fundamental expressed in dB.

REV. C–6–

AD7896

CONVERTER DETAILS

The AD7896 is a fast, 12-bit ADC that operates from a single

2.7 V to 5.5 V supply. It provides the user with a track-and­hold, ADC, and serial interface logic functions on a single
chip. The ADC section of the AD7896 consists of a conven­tional successive approximation converter based on an R-2R
ladder structure. The internal reference for the AD7896 is
derived from V
input range of 0 V to V

, which allows the part to accept an analog

DD

. The AD7896 has two operating

DD

modes: the high sampling mode and the auto sleep mode
where the part automatically goes into sleep after the end of
conversion. These modes are discussed in more detail in the
Timing and Control section.

A major advantage of the AD7896 is that it provides all of the
preceding functions in an 8-lead package, PDIP or SOIC. This
offers the user considerable space saving advantages over alterna­tive solutions. The AD7896 consumes only 9 mW typical, making
it ideal for battery-powered applications.

Conversion is initiated on the AD7896 by pulsing the CONVST
input. On the falling edge of CONVST, the on-chip track-and­hold goes from track to hold mode and the conversion sequence
is started. The conversion clock for the part is generated inter­nally using a laser-trimmed clock oscillator circuit. Conversion
time for the AD7896 is 8 µs in the high sampling mode (14 µs
for the auto sleep mode), and the track-and-hold acquisition
time is 1.5 µs. To obtain optimum performance from the part,
the read operation should not occur during the conversion or
during 400 ns prior to the next conversion. This allows the part
to operate at throughput rates up to 100 kHz and achieves data
sheet specifications (see the Timing and Control section).

CIRCUIT DESCRIPTION
Analog Input Section

The analog input range for the AD7896 is 0 V to V

pin drives the input to the track-and-hold amplifier directly.

V

IN

DD.

The

This allows for a maximum output impedance of the circuit
driving the analog input of 1 kΩ. This ensures that the part will
be settled to 12-bit accuracy in the 1.5 µs acquisition time. This
input is benign with dynamic charging currents. The designed
code transitions occur on successive integer LSB values (i.e.,
1 LSB, 2 LSB, 3 LSB, . . . , FS – 1 LSB). Output coding is straight
(natural) binary with 1 LSB = FS/4096 = 3.3 V/4096 = 0.81 mV.
The ideal input/output transfer function is shown in Table I.

Table I. Ideal Input/Output Code Table for the AD7896

Analog Input

+FSR – 1 LSB

1

2

(3.299194) 111 . . . 110 to 111 . . . 111

Code Transition

+FSR – 2 LSB (3.298389) 111 . . . 101 to 111 . . . 110
+FSR/2 – 3 LSB (3.297583) 111 . . . 100 to 111 . . . 101
AGND + 3 LSB (0.002417) 000 . . . 010 to 000 . . . 011
AGND + 2 LSB (0.001611) 000 . . . 001 to 000 . . . 010
AGND + 1 LSB (0.000806) 000 . . . 000 to 000 . . . 001

NOTES

1

FSR is full-scale range and is 3.3 V with VDD = +3.3 V.

2

1 LSB = FSR/4096 = 0.81 mV with VDD = +3.3 V.

Track-and-Hold Section

The track-and-hold amplifier on the analog input of the AD7896
allows the ADC to accurately convert an input sine wave of full­scale amplitude to 12-bit accuracy. The input bandwidth of the

REV. C

–7–

track-and-hold is greater than the Nyquist rate of the ADC even
when the ADC is operated at its maximum throughput rate of
100 kHz (i.e., the track-and-hold can handle input frequencies
in excess of 50 kHz).

The track-and-hold amplifier acquires an input signal to 12-bit
accuracy in less than 1.5 µs. The operation of the track-and-
hold is essentially transparent to the user. With the high sampling
operating mode, the track-and-hold amplifier goes from its
tracking mode to its hold mode at the start of conversion (i.e.,
the rising edge of CONVST). The aperture time for the track­and-hold (i.e., the delay time between the external CONVST
signal and the track-and-hold actually going into hold) is typi­cally 15 ns. At the end of conversion (on the falling edge of
BUSY), the part returns to its tracking mode. The acquisition
time of the track-and-hold amplifier begins at this point. For the
auto shutdown mode, the rising edge of CONVST wakes up the
part and the track-and-hold amplifier goes from its tracking
mode to its hold mode 6 µs after the rising edge of CONVST
(provided that the CONVST high time is less than 6 µs). Once
again the part returns to its tracking mode at the end of conver­sion when the BUSY signal goes low.

Timing and Control

Figure 2 shows the timing and control sequence required to
obtain optimum performance from the AD7896. In the
sequence shown, conversion is initiated on the falling edge of
CONVST and new data from this conversion is available in the
output register of the AD7896 8 µs later. Once the read opera-
tion has taken place, another 400 ns should be allowed before
the next falling edge of CONVST to optimize the settling of the
track-and-hold amplifier before the next conversion is initiated.
With the serial clock frequency at its maximum of 10 MHz (5 V
operation), the achievable throughput time for the part is 8 µs
(conversion time) plus 1.6 µs (read time) plus 0.4 µs (acquisi-
tion time). This results in a minimum throughput time of 10 µs
(equivalent to a throughput rate of 100 kHz). A serial clock of
less than 10 MHz can be used, but this will in turn mean that
the throughput time will increase.

The read operation consists of 16 serial clock pulses to the output
shift register of the AD7896. After 16 serial clock pulses, the shift
register is reset and the SDATA line is three-stated. If there are
more serial clock pulses after the 16th clock, the shift register will
be moved on past its reset state. However, the shift register will be
reset again on the falling edge of the CONVST signal to ensure
that the part returns to a known state every conversion cycle. As a
result, a read operation from the output register should not
straddle across the falling edge of CONVST as the output shift
register will be reset in the middle of the read operation and the
data read back into the microprocessor will appear invalid.

The throughput rate of the part can be increased by reading
data during conversion. If the data is read during conversion, a
throughput time of 8 µs (conversion time) plus 1.5 µs (acquisi-
tion time) is achieved when a 10 MHz, (5 V operation) serial
clock is being used. This minimum throughput time of 9.5 µs is
achieved with a slight reduction in performance from the AD7896.
The advantage of this arrangement is that when the serial clock
is significantly lower than 10 MHz, the throughput time for this
arrangement will be significantly less than the throughput time
where the data is read after conversion. The signal-to-(noise +
distortion) number is likely to degrade by less than 1 dB while
the code flicker from the part will also increase (see the AD7896
Performance section).

AD7896

C

OPERATING MODES
Mode 1 Operation (High Sampling Performance)

The timing diagram in Figure 2 is for optimum performance in
Operating Mode 1 where the falling edge of CONVST starts the
conversion and puts the track-and-hold amplifier into its hold
mode. This falling edge of CONVST also causes the BUSY
signal to go high to indicate that a conversion is taking place.
The BUSY signal goes low when the conversion is complete,
which is 8 µs max after the falling edge of CONVST, and new
data from this conversion is available in the output register of
the AD7896. A read operation accesses this data. This read
operation consists of 16 clock cycles, and the length of this read
operation depends on the serial clock frequency. For the fastest
throughput rate (with a serial clock of 10 MHz at 5 V opera­tion), the read operation will take 1.6 µs. The read operation
must be complete at least 400 ns before the falling edge of
the next CONVST, which gives a total time of 10 µs for the full
throughput time (equivalent to 100 kHz). This mode of opera­tion should be used for high sampling applications.

Mode 2 Operation (Auto Sleep after Conversion)

The timing diagram in Figure 3 is for optimum performance in
Operating Mode 2 where the part automatically goes into sleep
mode once BUSY goes low after conversion and “wakes up”

t

= 8␮s

CONVERT

t

1

ONVST

before the next conversion takes place. This is achieved by
keeping CONVST low at the end of conversion, whereas it was
high at the end of conversion for Mode 1 operation. The rising
edge of CONVST “wakes up” the part. This wake-up time is 6
µs, at which point the track-and-hold amplifier goes into its hold
mode. The conversion takes 8 µs after this, provided the
CONVST has gone low, giving a total of 14 µs from the rising
edge of CONVST to the conversion being complete, which is
indicated by the BUSY going low. Note that since the wake­up time from the rising edge of CONVST is 6 µs, when the
CONVST pulsewidth is greater than 6 µs, the conversion will
take more than the 14 µs shown in the diagram from the rising
edge of CONVST. This is because the track-and-hold amplifier
goes into its hold mode on the falling edge of CONVST and
then the conversion will not be complete for a further 8 µs. In
this case, the BUSY will be the best indicator for when the
conversion is complete. Even though the part is in sleep mode,
data can still be read from the part. The read operation consists
of 16 clock cycles as in Mode 1 operation. For the fastest serial
clock of 10 MHz at 5 V operation, the read operation will take

1.6 µs, which must be complete at least 400 ns before the falling
edge of the next CONVST to allow the track-and-hold amplifier
to have enough time to settle. This mode is very useful when the
part is converting at a slow rate as the power consumption will
be significantly reduced from that of Mode 1 operation.

t

= 40ns MIN

1

BUSY

400ns MIN

SCLK

t

= 8␮s

CONVERT

CONVERSION IS

INITIATED AND

TRACK-AND-HOLD GOES

INTO HOLD

CONVERSION ENDS

8␮s LATER

SERIAL READ

OPERATION

READ OPERATION

SHOULD END 400ns

PRIOR TO NEXT

FALLING EDGE OF

CONVST

OUTPUT

SERIAL

SHIFT

REGISTER

IS RESET

Figure 2. Mode 1 Timing Operation Diagram for High Sampling Performance

t

= 6␮s

1

t

1

CONVST

BUSY

400ns MIN

SCLK

t

= 14␮s

CONVERT

PART

WAKES

UP

CONVERSION
IS INITIATED
TRACK-AND­HOLD GOES
INTO HOLD

CONVERSION

ENDS

14µs LATER

SERIAL READ

OPERATION

READ OPERATION

SHOULD END 400ns

PRIOR TO NEXT

FA LLING EDGE OF

CONVST

WAKE-UP

TIME

OUTPUT

SERIAL

SHIFT

REGISTER

IS RESET

Figure 3. Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated

REV. C–8–

AD7896

Serial Interface

The serial interface to the AD7896 consists of three wires: a
serial clock input (SCLK), the serial data output (SDATA), and
a conversion status output (BUSY). This allows for an easy-to­use interface to most microcontrollers, DSP processors, and
shift registers.

Figure 4 shows the timing diagram for the read operation to the
AD7896. The serial clock input (SCLK) provides the clock
source for the serial interface. Serial data is clocked out from the
SDATA line on the falling edge of this clock and is valid on both
the rising and falling edges of SCLK. The advantage of having
the data valid on both the rising and falling edges of the SCLK
is to give the user greater flexibility in interfacing to the
so that a wider range of microprocessor and

microcontroller inter-

part and

faces can be accommodated. This also explains the two timing
figures t

and t5 that are quoted on the diagram. The time t4 speci-

4

fies how long after the falling edge of the SCLK that the next data
bit becomes valid, whereas the time t

specifies how long after the

5

falling edge of the SCLK that the current data bit is valid for. The
first leading zero is clocked out on the first rising edge of
SCLK; note that the first zero may be valid on the first falling
edge of SCLK even though the data access time is specified
at 60 ns (5 V [A, B, J versions only]) for the other bits (and the
SCLK high time will be 50 ns with a 10 MHz SCLK). The reason
that the first bit will be clocked out faster than the other bits is
due to the internal architecture of the part. Sixteen clock pulses
must be provided to the part to access the full conversion result.

The AD7896 provides four leading zeros followed by the 12-bit
conversion result starting with the MSB (DB11). The last data
bit to be clocked out on the penultimate falling clock edge is the
LSB (DB0). On the 16th falling edge of SCLK, the LSB (DB0)
will be valid for a specified time to allow the bit to be read on
the falling edge of SCLK, and then the SDATA line is disabled
(three-stated). After this last bit has been clocked out, the SCLK
input should remain low until the next serial data read opera­tion. If there are extra clock pulses after the 16th clock, the
AD7896 will start over again with outputting data from its out­put register, and the data bus will no longer be three-stated even
when the clock stops. Provided the serial clock has stopped
before the next falling edge of CONVST, the AD7896 will
continue to operate correctly with the output shift register being
reset on the falling edge of CONVST. However, the SCLK line

must be low when CONVST goes low in order to reset the
output shift register correctly.

The serial clock input does not need to be continuous during
the serial read operation. The 16 bits of data (four leading zeros
and 12-bit conversion result) can be read from the AD7896 in a
number of bytes. However, the SCLK input must remain low
between the two bytes.

The maximum SCLK frequency is 10 MHz for 5 V operation
(giving a throughput of 100 kHz) and at 2.7 V the maximum
SCLK frequency is less than 10 MHz to allow for the longer
data access time, t

(60 ns @ 5 V, 100 ns @ 2.7 V (A, B, J

4

versions), 70 ns @ 5 V, 110 ns @ 2.7 V (S version)). Note that
at 3.0 V operation (A, B, J versions), an SCLK of 10 MHz
(throughput rate of 100 kHz) may be acceptable if the required
processor setup time is 0 ns (this may be possible with an ASIC
or FPGA). The data must be read in the next 10 ns, which is
specified as the data hold time, t

, after the SCLK edge.

5

The AD7896 counts the serial clock edges to know which bit
from the output register should be placed on the SDATA out­put. To ensure that the part does not lose synchronization, the
serial clock counter is reset on the falling edge of the CONVST
input provided the SCLK line is low. The user should ensure
that a falling edge on the CONVST input does not occur while
a serial data read operation is in progress.

MICROPROCESSOR/MICROCONTROLLER INTERFACE

The AD7896 provides a 3-wire serial interface that can be
used for connection to the serial ports of DSP processors and
microcontrollers. Figures 5 through 8 show the AD7896
interfaced to a number of different microcontrollers and DSP
processors. The AD7896 accepts an external serial clock and as
a result, in all interfaces shown here, the processor/controller is
configured as the master, providing the serial clock, with the
AD7896 configured as the slave in the system.

AD7896–8051 Interface

Figure 5 shows an interface between the AD7896 and the
8X51/L51 microcontroller. The 8X51/L51 is configured for its
Mode 0 serial interface mode. The diagram shows the simplest
form of the interface where the AD7896 is the only part connected
to the serial port of the 8X51/L51 and, therefore, no decoding
of the serial read operations is required.

REV. C

SCLK (I/P)

DOUT (O/P)

t

=

2

THREE-STATE

t

= 40ns MIN,

3

1234561516

t

= 60ns MAX,

4

t

2

t

3

4 LEADING ZEROS

t

= 10ns MIN,

5

t

4

t

= 50ns MAX @ 5V, A, B, VERSIONS

6

t

5

Figure 4. Data Read Operation

–9–

DB0DB10DB11

t

6

THREE-STATE

AD7896

To chip select the AD7896 in systems where more than one
device is connected to the 8X51/L51 serial port, a port bit,
configured as an output, from one of the 8X51/L51 parallel
ports can be used to gate on or off the serial clock to the AD7896.
A simple AND function on this port bit and the serial clock from
the 8X51/L51 will provide this function. The port bit should be
high to select the AD7896 and low when it is not selected.

The end of conversion is monitored by using the BUSY signal,
which is shown in the interface diagram of Figure 5, with the
BUSY line from the AD7896 connected to the Port P1.2 of the
8X51/L51 so the BUSY line can be polled by the 8X51/L51.
The BUSY line can be connected to the INT1 line of the
8X51/L51 if an interrupt driven system is preferred. These two
options are shown on the diagram.

Note also that the AD7896 outputs the MSB first during a read
operation while the 8X51/L51 expects the LSB first. Therefore,
the data that is read into the serial buffer needs to be rearranged
before the correct data format from the AD7896 appears in the
accumulator.

The serial clock rate from the 8X51/L51 is limited to signifi­cantly less than the allowable input serial clock frequency with
which the AD7896 can operate. As a result, the time to read
data from the part will actually be longer than the conversion
time of the part. This means that the AD7896 cannot run at its
maximum throughput rate when used with the 8X51/L51.

P1.2

8X51/L51

OR

INT1

P3.0

P3.1

BUSY

AD7896

SDATA

SCLK

Figure 5. AD7896 to 8X51/L51 Interface

AD7896–68HC11/L11 Interface

An interface circuit between the AD7896 and the 68HC11/L11
microcontroller is shown in Figure 6. For the interface shown,
the 68HC11/L11 SPI port is used and the 68HC11/L11 is con­figured in its single-chip mode. The 68HC11/L11 is configured
in the master mode with its CPOL bit set to a Logic 0 and its
CPHA bit set to a Logic 1. As with the previous interface, the
diagram shows the simplest form of the interface, where the
AD7896 is the only part connected to the serial port of the
68HC11/L11 and, therefore, no decoding of the serial read
operations is required.

Once again, to chip select the AD7896 in systems where more
than one device is connected to the 68HC11/L11 serial port, a
port bit, configured as an output, from one of the 68HC11/L11
parallel ports can be used to gate on or off the serial clock to the
AD7896. A simple AND function on this port bit and the serial
clock from the 68HC11/L11 will provide this function. The port
bit should be high to select the AD7896 and low when it is
not selected.

The end of conversion is monitored by using the BUSY signal
which is shown in the interface diagram of Figure 6. With the
BUSY line from the AD7896 connected to the Port PC2 of the
68HC11/L11, the BUSY line can be polled by the 68HC11/L11.

The BUSY line can be connected to the IRQ line of the
68HC11/L11 if an interrupt driven system is preferred. These
two options are shown in the diagram.

The serial clock rate from the 68HC11/L11 is limited to signifi­cantly less than the allowable input serial clock frequency with
which the AD7896 can operate. As a result, the time to read
data from the part will actually be longer than the conversion
time of the part. This means that the AD7896 cannot run at its
maximum throughput rate when used with the 68HC11/L11.

PC2 OR

68HC11/L11

MISO

IRQ

SCK

BUSY

AD7896

SCLK

SDATA

Figure 6. AD7896 to 68HC11/L11 Interface

AD7896–ADSP-2103/ADSP-2105 Interface

An interface circuit between the AD7896 and the ADSP­2103/ADSP-2105 DSP processor is shown in Figure 7. In the
interface shown, the RFS1 output from the ADSP-2103/
ADSP-2105s SPORT1 serial port is used to gate the serial clock
(SCLK1) of the ADSP-2103/ADSP-2105 before it is applied to
the SCLK input of the AD7896. The RFS1 output is configured
for active high operation. The BUSY line from the AD7896 is
connected to the IRQ2 line of the ADSP-2103/ADSP-2105 so
that at the end of conversion an interrupt is generated telling the
ADSP-2103/ADSP-2105 to initiate a read operation. The inter­face ensures a noncontinuous clock for the AD7896’s serial
clock input, with only 16 serial clock pulses provided and the
serial clock line of the AD7896 remaining low between data
transfers. The SDATA line from the AD7896 is connected to
the DR1 line of the ADSP-2103/ADSP-2105 serial port.

The timing relationship between the SCLK1 and RFS1 outputs
of the ADSP-2103/ADSP-2105 are such that the delay between
the rising edge of the SCLK1 and the rising edge of an active
high RFS1 is up to 30 ns. There is also a requirement that data
must be set up 10 ns prior to the falling edge of the SCLK1 to
be read correctly by the ADSP-2103/ADSP-2105. The data
access time for the AD7896 is 60 ns (5 V [A, B versions]) from
the rising edge of its SCLK input. Assuming a 10 ns propaga­tion delay through the external AND gate, the high time of the
SCLK1 output of the ADSP-2105 must be ≥ (30 + 60 +10
+10) ns, i.e., ≥110 ns. This means that the serial clock fre­quency with which the interface of Figure 7 can work is limited
to 4.5 MHz. However, there is an alternative method that allows
for the ADSP-2105 SCLK1 to run at 5 MHz (which is the max
serial clock frequency of the SCLK1 output). The arrangement
is where the first leading zero of the data stream from the
AD7896 cannot be guaranteed to be clocked into the ADSP­2105 due to the combined delay of the RFS signal and the data
access time of the AD7896. In most cases, this is acceptable as
there will still be three leading zeros followed by the 12 data
bits. For the ADSP-2103, the SCLK1 frequency will need to
be limited to <4 MHz to account for the 100 ns data access
time of the AD7896 at 3 V.

REV. C–10–

AD7896

An alternative scheme is to configure the ADSP-2103/ADSP-2105
such that it accepts an external noncontinuous serial clock. In
this case, an external noncontinuous serial clock is provided that
drives the serial clock inputs of both the ADSP-2103/ADSP-2105
and the AD7896. In this scheme, the serial clock frequency is
limited to 10 MHz by the AD7896.

IRQ2

ADSP-2103/

RFS1

ADSP-2105

SCLK1

DR1

BUSY

AD7896

SCLK

SDATA

Figure 7. AD7896 to ADSP-2103/ADSP-2105 Interface

AD7896–DSP56002/L002 Interface

Figure 8 shows an interface circuit between the AD7896 and the
DSP56002/L002 DSP processor. The DSP56002/L002 is con­figured for normal mode asynchronous operation with gated
clock. It is also set up for a 16-bit word with SCK as gated clock
output. In this mode, the DSP56002/L002 provides 16 serial
clock pulses to the AD7896 in a serial read operation. The
DSP56002/L002 assumes valid data on the first falling edge of
SCK so the interface is simply 2-wire as shown in Figure 8.

The BUSY line from the AD7896 is connected to the MODA/
IRQA input of the DSP56002/L002 so that an interrupt will be
generated at the end of conversion. This ensures that the read
operation will take place after conversion is finished.

MODA/IRQA

DSP56002/L002

SCK

BUSY

AD7896

SCLK

Figure 9 shows a histogram plot for 8192 conversions of a dc
input using the AD7896 with a 3.3 V supply. The analog input
was set at the center of a code transition. It can be seen that
almost all the codes appear in the one output bin, indicating
very good noise performance from the ADC. The rms noise
performance for the AD7896 for the plot below was 111 µV.

9000

f

= 95kHz,

8000

7000

6000

5000

4000

OCCURRENCE

3000

2000

1000

0

1005 1006

SAMPLE

f

= 8.33MHz,

SCLK

AIN CENTERED ON CODE 1005
RMS NOISE = 0.138 LSB

CODE

Figure 9. Histogram of 8192 Conversions of a DC Input

The same data is presented in Figure 10 as in Figure 9, except
that in this case, the output data read for the device occurs
during conversion. This has the effect of injecting noise onto the
die while bit decisions are being made and this increases the
noise generated by the AD7896. The histogram plot for 8192
conversions of the same dc input now shows a larger spread of
codes with the rms noise for the AD7896 increasing to 279 µV.
This effect will vary depending on where the serial clock
edges appear with respect to the bit trials of the conversion
process. It is possible to achieve the same level of performance
when reading during conversion as when reading after conver­sion, depending on the relationship of the serial clock edges to
the bit trial points.

SDR

SDATA

Figure 8. AD7896 to DSP56002/L002 Interface

AD7896 PERFORMANCE
Linearity

The linearity of the AD7896 is determined by the on-chip 12-bit
DAC. This is a segmented DAC that is laser trimmed for 12-bit
integral linearity and differential linearity. Typical relative accu­racy numbers for the part are ±1/4 LSB, while the typical DNL
errors are ±1/2 LSB.

Noise

In an ADC, noise exhibits itself as code uncertainty in dc appli­cations and as the noise floor (in an FFT, for example) in ac
applications. In a sampling ADC like the AD7896, all informa­tion about the analog input appears in the baseband from dc
to 1/2 the sampling frequency. The input bandwidth of the
track-and-hold exceeds the Nyquist bandwidth and, therefore,
an antialiasing filter should be used to remove unwanted
signals above f

/2 in the input signal in applications where

S

such signals exist.

REV. C

–11–

8000

f

7000

6000

5000

4000

3000

OCCURRENCE

2000

1000

0

1004

1005 1006

CODE

= 95kHz,

SAMPLE

f

= 8.33MHz,

SCLK

AIN CENTERED ON
CODE 1005, RMS
NOISE = 0.346 LSB

Figure 10. Histogram of 8192 Conversions with
Read during Conversion

AD7896

Dynamic Performance (Mode 1 Only)

With a combined conversion and acquisition time of 9.5 µs, the
AD7896 is ideal for wide bandwidth signal processing applications.
These applications require information on the ADC’s effect on the
spectral content of the input signal. Signal-to-(noise + distortion),
total harmonic distortion, peak harmonic or spurious noise, and
intermodulation distortion are all specified. Figure 11 shows a
typical FFT plot of a 10 kHz, 0 V to 3.3 V input after being digi­tized by the AD7896 operating at a 102.4 kHz sampling rate.
The signal-to-(noise + distortion) ratio is 71.5 dB and the total
harmonic distortion is –82.4 dB.

–20

–40

–60

dB

–80

–100

–120

–0

0

10240

FREQUENCY

f

SAMPLE

f

= 10kHz

IN

SNR = 71.54dB
THD = –82.43dB

409603072020480

(Hz)

= 102.4kHz

51200

Figure 11. AD7896 FFT Plot

Effective Number of Bits

The formula for signal-to-(noise + distortion) ratio (see the
Terminology section) is related to the resolution or number of
bits in the converter. Rewriting the formula below gives a mea­sure of performance expressed in effective number of bits (N)

N = (SNR 1.76)/6.02

where SNR is the signal-to-(noise + distortion) ratio.

The effective number of bits for a device can be calculated from
its measured signal-to-(noise + distortion) ratio. Figure 12
shows a typical plot of effective number of bits versus frequency
for the AD7896 from dc to f

SAMPLING

/2. The sampling frequency
is 102.4 kHz. The plot shows that the AD7896 converts an input
sine wave of 51.2 kHz to an effective numbers of bits of 11.25,
which equates to a signal-to-(noise + distortion) level of 69 dB.

12.00

11.75

11.50

11.25

EFFECTIVE NUMBER OF BITS

11.00
0 51.225.6

INPUT FREQUENCY

(kHz)

Figure 12. Effective Number of Bits vs. Frequency

Power Considerations

In the automatic power-down mode, the part can be operated
at a sample rate that is considerably less than 100 kHz. In this
case, the power consumption will be reduced and will depend
on the sample rate. Figure 13 shows a graph of the power con­sumption versus sampling rates from 10 Hz to 1 kHz in the
automatic power-down mode. The conditions are 2.7 V supply,
25°C, serial clock frequency of 8.33 MHz, and the data was
read after conversion.

200

f

= 8.33MHz

SCLK

160

120

80

POWER (␮W)

40

0

10

100

SAMPLING RATE IN

Hz

1000

Figure 13. Power vs. Sample Rate in Auto Power­Down Mode

REV. C–12–

1

4

85

0.310 (7.87)

0.220 (5.59)

PIN 1

0.005 (0.13)
MIN

0.055 (1.40)
MAX

0.100 (2.54) BSC

15

0

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

SEATING
PLANE

0.200 (5.08)
MAX

0.405 (10.29) MAX

0.150 (3.81)
MIN

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

0.070 (1.78)

0.030 (0.76)

0.060 (1.52)

0.015 (0.38)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

OUTLINE DIMENSIONS

AD7896

8-Lead Plastic Dual In-Line Package [PDIP]

(N-8)

Dimensions shown in inches and (millimeters)

0.375 (9.53)

0.365 (9.27)

0.355 (9.02)

8

1

0.100 (2.54)

0.180
(4.57)

MAX

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-095AA

BSC

5

4

0.295 (7.49)

0.285 (7.24)

0.275 (6.98)

0.015
(0.38)
MIN

SEATING
PLANE

0.060 (1.52)

0.050 (1.27)

0.045 (1.14)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

8-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-8)

Dimensions shown in inches and (millimeters)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

REV. C

8-Lead Standard Small Outline Package [SOIC]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8ⴗ
0ⴗ

1.27 (0.0500)

0.40 (0.0157)

ⴛ 45ⴗ

–13–

AD7896

Revision History

Location Page

7/03—Data Sheet changed from REV. B to REV. C.

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Added ESD Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

REV. C–14–

–15–

C01363–0–7/03(C)

–16–