Datasheet AD7885, AD7884 Datasheet (Analog Devices)

LC2MOS

±5V F

±5V S

±3V F ±3V S

16-BIT

ACCURATE

DAC

AD7884

TIMER

CONTROL

DGND

CS
RD

BUSY

DB15

V S

REF+

REF+

V F

V

REF–

AGNDS AGNDF

AV

DD

V

SS

GND

DB0

V

INV

CONVST

IN

V

DD

AV

SS

R7

2kΩ

R8

2kΩ

9

9

9

16 16

V

REF–

5kΩ

3kΩ

3kΩ

4kΩ

4kΩ

R1

R2

R3

R4

C1

SW1

R5

SW2

SW3

2kΩ

R6

A1

A2

9-BIT

ADC

LATCH

+

ALU

O
U
T
P
U
T

D
R

I
V
E
R
S

IN

IN IN

±5V F

±5V S

16-BIT

ACCURATE

DAC

AD7885

TIMER

CONTROL

DGND

CS
RD

BUSY

DB7

V S

REF+

V F

REF+

V

REF–

AGNDS AGNDF

AV

DD

V

SS

GND

DB0

V

INV

CONVST

IN

V

DD

AV

SS

R7

2kΩ

R8

2kΩ

9

9

9

16

8

V

REF–

5kΩ

3kΩ

2kΩ

4kΩ

4kΩ

R1

R2

3kΩR3

R4

C1

SW1

R5

SW2

SW3

R6

A1

A2

9-BIT

ADC

LATCH

+

ALU

O
U
T
P
U
T

D
R

I

V
E
R
S

IN

IN

±3V

HBEN

a

16-Bit, High Speed Sampling ADCs

FEATURES
Monolithic Construction
Fast Conversion: 5.3 ms
High Throughput: 166 kSPS
Low Power: 250 mW

APPLICATIONS
Automatic Test Equipment
Medical Instrumentation
Industrial Control
Data Acquisition Systems
Robotics

GENERAL DESCRIPTION

The AD7884/AD7885 is a 16-bit monolithic analog-to-digital
converter with internal sample-and-hold and a conversion time
of 5.3 µs. The maximum throughput rate is 166 kSPS. It uses a
two pass flash architecture to achieve this speed. Two input
ranges are available: ±5 V and ±3 V. Conversion is initiated by
the

CONVST signal. The result can be read into a microproces-

sor using the

CS and RD inputs on the device. The AD7884 has
a 16-bit parallel reading structure while the AD7885 has a byte
reading structure. The conversion result is in 2s complement
code.

The AD7884/AD7885 has its own internal oscillator which con­trols conversion. It runs from ± 5 V supplies and needs a V

REF+

of +3 V.
The AD7884 is available in a 40-pin plastic DIP package and in

a 44-pin PLCC package.
The AD7885 is available in a 28-pin plastic DIP package and

the AD7885A is available in a 44-pin PLCC package.

AD7884/AD7885

FUNCTIONAL BLOCK DIAGRAMS

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

© Analog Devices, Inc., 1995

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD7884/AD7885/AD7885A–SPECIFICATIONS

= +3 V; AGND = DGND = GND = 0 V; f

Parameter Version

= 166 kHz. All specifications T

SAMPLE

AB

1, 2, 3

Versions

to T

MIN

1, 2, 3

Units Test Conditions/Comments

, unless otherwise noted.)

MAX

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, V

REF

+S

DC ACCURACY

Resolution 16 16 Bits
Minimum Resolution for Which

No Missing Codes Are Guaranteed 16 16 Bits
Integral Nonlinearity ±0.0075 % FSR max Typically 0.003% FSR
Positive Gain Error ±0.03 ±0.03 % FSR typ AD7885AN/BN: 0.1% typ
Positive Gain Error ±0.05 % FSR max AD7885BN: 0.2% max

Gain TC

4

±2 ±2 ppm FSR/°C typ
Bipolar Zero Error ±0.05 ±0.05 % FSR typ
Bipolar Zero Error ±0.15 % FSR max
Bipolar Zero TC

4

±8 ±8 ppm FSR/°C typ
Negative Gain Error ±0.03 ±0.03 % FSR typ AD7885AN/BN: 0.1% typ
Negative Gain Error ±0.05 % FSR max AD7885BN: 0.2% max

Offset TC

4

±2 ±2 ppm FSR/°C typ
Noise 120 120 µV rms typ 78 µV rms typical in ±3 V Input Range

DYNAMIC PERFORMANCE

Signal to (Noise + Distortion) Ratio 84 84 dB min Input Signal: ±5 V, 1 kHz Sine Wave, Typically 86 dB

82 82 dB typ Input Signal: ±5 V, 12 kHz Sine Wave
Total Harmonic Distortion –88 –88 dB max Input Signal: ±5 V, 1 kHz Sine Wave

–84 –84 dB typ Input Signal: ±5 V, 12 kHz Sine Wave
Peak Harmonic or Spurious Noise –88 –88 dB max Input Signal: ±5 V, 1 kHz Sine Wave
Intermodulation Distortion (IMD)

2nd Order Terms –84 –84 dB typ f

= 11.5 kHz, fB = 12 kHz, f

A

3rd Order Terms –84 –84 dB typ fA = 11.5 kHz, fB = 12 kHz, f

SAMPLE
SAMPLE

= 166 kHz
= 166 kHz

CONVERSION TIME

Conversion Time 5.3 5.3 µs max
Acquisition Time 2.5 2.5 µs max
Throughput Rate 166 166 kSPS max There is an overlap between conversion and acquisition.

ANALOG INPUT

Voltage Range ±5 ±5 Volts

±3 ±3 Volts
Input Current ±4 ±4 mA max

REFERENCE INPUT

Reference Input Current ±5 ±5 mA max V

+ S = +3 V

REF

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

IN

IN

INH

INL

4

2.4 2.4 V min VDD = 5 V ± 5%

0.8 0.8 V max VDD = 5 V ± 5%

±10 ±10 µA max Input Level = 0 V to V

10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

4.0 4.0 V min I

0.4 0.4 V max I

SOURCE

= 1.6 mA

SINK

= 40 µA

DB15–DB0

Floating-State Leakage Current 10 10 µA max
Floating-State Output Capacitance415 15 pF max

POWER REQUIREMENTS

V

DD

V

SS

I

DD

I

SS

+5 +5 V nom ±5% for Specified Performance

–5 –5 V nom ±5% for Specified Performance

35 35 mA max Typically 25 mA

30 30 mA max Typically 25 mA
Power Supply Rejection Ratio

∆Gain/∆V
∆Gain/∆V

DD
SS

86 86 dB typ

86 86 dB typ
Power Dissipation 325 325 mW max Typically 250 mW

NOTES

1

Temperature ranges are as follows: A, B Versions: –40 °C to +85°C.

2

VIN = ±5 V.

3

The AD7885AAP has the same specs as the AD7884AP. The AD7885ABP has the same specs as the AD7884BP.

4

Sample tested to ensure compliance.

Specifications subject to change without notice.

–2–

DD

REV. C

TIMING CHARACTERISTICS

AD7884/AD7885

1, 2

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4 and 5.)

Limit at +258C Limit at T

MIN

, T

MAX

Parameter (All Versions) (A, B Versions) Units Conditions/Comments

t

1

t

2

t

3

t

4

t

5

2

t

6

3

t

7

50 50 ns min CONVST Pulse Width
100 100 ns max CONVST to BUSY Low Delay
0 0 ns min CS to RD Setup Time
60 60 ns min RD Pulse Width
0 0 ns min CS to RD Hold Time
57 57 ns max Data Access Time after RD
5 5 ns min Bus Relinquish Time after RD
50 50 ns max

t

8

t

9

t

10

t

11

t

12

t

13

t

14

NOTES

1

Timing specifications in bold print are 100% production tested. All other times are sample tested at +5°C to ensure compliance. All input signals are specified
with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

3

t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrap­olated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
bus relinquish time of the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

40 40 ns min New Data Valid before Rising Edge of BUSY
10 80 ns min HBEN to RD Setup Time
25 25 ns min HBEN to RD Hold Time
60 60 ns min HBEN Low Pulse Duration
60 60 ns min HBEN High Pulse Duration
55 70 ns max Propagation Delay from HBEN Falling to Data Valid
55 70 ns max Propagation Delay from HBEN Rising to Data Valid

, quoted in the Timing Characteristics is the true

7

ORDERING GUIDE

Linearity
Temperature Error SNR Package
Range (% FSR) (dB) Option

2

Model

1

AD7884AN –40°C to +85°C 84 N-40A
AD7884BN –40°C to +85°C ±0.0075 84 N-40A
AD7884AP –40°C to +85°C 84 P-44A
AD7884BP –40°C to +85°C ±0.0075 84 P-44A
AD7885AN –40°C to +85°C 84 N-28A
AD7885BN –40°C to +85°C ±0.0075 84 N-28A
AD7885AAP –40°C to +85°C 84 P-44A
AD7885ABP –40°C to +85°C ± 0.0075 84 P-44A

NOTES

1

Analog Devices reserves the right to ship cerdip (Q) packages in lieu of plastic

DIP (N) packages.

2

N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC).

TO OUTPUT PIN

C

L

100pF

1.6mA

200µA

I

OL

+2.1V

I

OH

Figure 1. Load Circuit for Access Time and Bus Relinquish
Time

REV. C

–3–

AD7884/AD7885

DATA

OLD DATA VALID NEW DATA VALID

BUSY

CONVST

t

1

t

2

t

8

t

CONVERT

t

CS

RD

1

t

2

CONVST

HBEN

BUSY

DATA

RD

t

3

t

CONVERT

Hi-Z

t

1

CS

t

2

t

CONVERT

Hi-Z Hi-Z

CONVST

BUSY

DATA

Figure 2. AD7884 Timing Diagram, Using

CS

t

6

t

4

DATA
VALID

and

RD

t

5

t

7

Hi-Z

Figure 3. AD7884 Timing Diagram, with CS and

RD

Permanently Low

t

9

t

3

t

6

t

4

DATA

VALID

DB0–DB7 DB8–DB15

t

10

t

5

t

7

DATA
VALID

Hi-Z

Figure 4. AD7885 Timing Diagram, Using CS and

t

CONVST

HBEN

BUSY

DATA

1

t

2

OLD DATA VALID

(DB8 – DB15)

Figure 5. AD7885 Timing Diagram, with CS and RD Permanently Low

RD

t

11

t

CONVERT

t

8

NEW DATA VALID

(DB8 – DB15)

–4–

t

13

NEW DATA VALID

(DB0 – DB7)

t

t

14

NEW DATA VALID

12

(DB8 – DB15)

NEW DATA VALID

(DB0 – DB7)

REV. C

AD7884/AD7885

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

SS

AV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to –7 V

SS

AGND Pins to DGND . . . . . . . . . . . . –0.3 V to V

AV

DD

AV

to V

SS

to V

2

. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

2

. . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

SS

GND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V

V

S, VINF to AGND . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V

IN

V

to AGND . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V

REF+

V

to AGND . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V

REF–

V

to AGND . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V

INV

Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V

Digital Outputs to DGND . . . . . . . . . . –0.3 V to V

1

Operating Temperature Range

Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C

Industrial Cerdip (A, B Versions) . . . . . . . . –40°C to +85°C

Extended Cerdip (T Versions) . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

+ 0.3 V

DD

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . 1000 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

1

Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

If the AD7884/AD7885 is being powered from separate analog and digital supplies,
AVSS should always come up before VSS. See Figure 12 for a recommended
protection circuit using Schottky diodes.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATIONS

DIP

F

S

S

IN

IN

IN

±5V

±3V

V

INV

V

REF–

±3V S

IN

±3V F

IN

±5V S

IN

±5V F

IN

AGNDS

AGNDF

AV

AV

GND

GND

V
V

V

CONVST

CS

RD

V

BUSY

DD

SS

SS

SS

DD

SS

1

2
3

4

5

6

7

8
9

10

11
12

13
14

15

16

17

18
19

20

AD7884

TOP VIEW

(Not to Scale)

V

40

V S

REF+

V F

39

REF+

38

DB15

37

DB14

DB13

36

DB12

35

34

DB11

DB10

33
32

DB9

DB8

31

DGND

30

V

DB7
DB6

DB5

DB4

DB3

DB2
DB1

DB0

CONVST

DD

29

28
27

26

25

24

23
22

21

REF–

±3V

±5V S

IN

±5V F

IN

AGNDS

AGNDF

AV

AV

GND

V

V

CS
RD

DD

SS

SS

DD

IN

1

2
3

4

5

6

7

8
9

10

11

12

13
14

AD7885

TOP VIEW

(Not to Scale)

V

28

INV

27

V S

REF+

26

V F

REF+

DB7

25

24

DB6

DB5

23

DB4

22

DGND

21
20

DB3

DB2

19

DB1

18

DB0

17

16

BUSY
HBEN

15

±5VINF
AGNDS
AGNDF

AV

AV

GND
GND

±5VINF

AGNDS
AGNDF

AV
AV

GND
GND

7
8
9

10

DD

11

SS

12

NC

13
14

V

15

SS

V

16

SS

V

17

DD

7
8
9

10

DD

SS

11

NC

12
13
14

V

15

SS

V

16

SS

V

17

DD

±3V

18 19 20 21 22 23 24 25 26 27 28

CONVST

S

±5V

18 19 20 21 22 23 24

CS

F

IN

±3V

CS

CONVST

SS

RD

V

S

IN

IN

±3V

RD

HBEN

PLCC

INVVREF

NC

V

21443456 42 41 4043

AD7884

TOP VIEW

(Not to Scale)

NC

BUSY

INVVREF

NC

V

21443456 42 41 4043

AD7885A

TOP VIEW

(Not to Scale)

NC

BUSY

S

F

REF+

REF+

V

V

DB1

DB0

NC = NO CONNECT

S

F

REF+

REF+

V

V

25 26 27 28

NCNCNC

NC = NO CONNECT

DB15

DB2

DB14

DB3

NC

DB13

DB4

NCNCNC

DB0

DB12

39

DB11

38
37

DB10

36

DB9

35

DB8
NC

34

DGND

33

V

DD

32

DB7

31

DB6

30

DB5

29

DB7

39

DB6

38

NC

37
36

DB5

35

DB4

34

NC

33

DGND
V

32

DD

DB3

31

DB2

30

DB1

29

REV. C

–5–

AD7884/AD7885

PIN FUNCTION DESCRIPTION

AD7884 AD7885 AD7885A Description

V

INV

V

INV

V

INV

This pin is connected to the inverting terminal of an op amp, as in Figure 6, and allows
the inversion of the supplied +3 V reference.

V

REF–

V

REF–

V

REF–

This is the negative reference input, and it can be obtained by using an external amplifier
to invert the positive reference input. In this case, the amplifier output is connected to
V

See Figure 6.

REF–.

S_ ±3 VINS This is the analog input sense pin for the ±3 volt analog input range on the AD7884 and

±3 V

IN

AD7885A.

±3 V

F_ ±3 VINF This is the analog input force pin for the ±3 volt analog input range on the AD7884 and

IN

AD7885A. When using this input range, the ± 5 V

F and ±5 VINS pins should be tied to

IN

AGND.

– ±3 V

±5 V

S ±5 VINS ± 5 VINS This is the analog input sense pin for the ±5 volt analog input range on both the AD7884,

IN

IN

– This is the analog input pin for the ±3 volt analog input range on the AD7885. When us-

ing this input range, the ±5 V

F and ±5 VINS pins should be tied to AGND.

IN

AD7885 and AD7885A.

±5 V

F ±5 VINF ±5 VINF This is the analog input force pin for the ±5 volt analog input range on both the AD7884,

IN

AD7885 and AD7885A. When using this input range, the ±3 V

F and ±3 VINS pins

IN

should be tied to AGND.
AGNDS AGNDS AGNDS This is the ground return sense pin for the 9-bit ADC and the on-chip residue amplifier.
AGNDF AGNDF AGNDF This is the ground return force pin for the 9-bit ADC and the on-chip residue amplifier.
AV
AV

DD
SS

AV
AV

DD
SS

AV
AV

DD
SS

Positive analog power rail for the sample-and-hold amplifier and the residue amplifier.

Negative analog power rail for the sample-and-hold amplifier and the residue amplifier.
GND GND GND This is the ground return for sample-and-hold section.
V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

Negative supply for the 9-bit ADC.

Positive supply for the 9-bit ADC and all device logic.

CONVST CONVST CONVST This asynchronous control input starts conversion.
CS CS CS Chip Select control input.
RD RD RD Read control input. This is used in conjunction with CS to read the conversion result

from the device output latch.
– HBEN HBEN High Byte Enable. Active high control input for the AD7885. It selects either the high or

the low byte of the conversion for reading.
BUSY BUSY BUSY Busy output. The Busy output goes low when conversion begins and stays low until it is

completed, at which time it goes high.
DB0–DB15 – – Sixteen-bit parallel data word output on the AD7884.
– DB0–DB7 DB0–DB7 Eight-bit parallel data byte output on the AD7885.
DGND DGND DGND Ground return for all device logic.
V

FV

REF+

V

SV

REF+

FV

REF+

SV

REF+

F Reference force input.

REF+

S Reference sense input. The device operates from a +3 V reference.

REF+

–6–

REV. C

AD7884/AD7885

±3VIN F

±5V

IN

F

–5V

+5V

AD817
AD711

AD817

AGNDS

AGNDF

AD7884
AD7885

A1

A3

A4

AD845, AD817 OR

EQUIVALENT

NOTE: POWER SUPPLY DECOUPLING NOT SHOWN

A2

GND

DGND

VDD = +5V

DATA

OUTPUTS

CONTROL

INPUTS

V

INV

V

REF+

S

V

REF+

F

V

REF–

±3VIN S

±5V

IN

S

AV

SS

V

DD

AV

DD

V

SS

V

IN

AD845, AD817 OR

EQUIVALENT

AD780

2

6

8

4

10µF

TERMINOLOGY
Integral Nonlinearity

This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Bipolar Zero Error

This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal (AGND).

Positive Gain Error

This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (+V

S – 1 LSB), after Bipolar

REF+

Zero Error has been adjusted out.

Negative Gain Error

This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–V

S + 1 LSB), after Bipolar

REF+

Zero Error has been adjusted out.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f

/2), excluding dc.

S

The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan­tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Thus for an ideal 16-bit converter, this is 98 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7884/AD7885, it is
defined as:

2

2

2

2

+V

+V

V

THD(dB)=20 log

2

where V1 is the rms amplitude of the fundamental and V2, V3,
V

, V5 and V6 are the rms amplitudes of the second through the

4

+V

3

4

V

1

2

+V

5

6

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
fundamental. Normally, the value of this specification is deter­mined by the largest harmonic in the spectrum, but for parts

/2 and excluding dc) to the rms value of the

S

where the harmonics are buried in the noise floor, it will be a
noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m or n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

REV. C

The AD7884/AD7885 is tested using the CCIFF standard
where two input frequencies near the top end of the input band­width are used. In this case, the second and third order terms
are of different significance. The second order terms are usually
distanced in frequency from the original sine waves while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second and third order terms are
specified separately. The calculation of the intermodulation dis­tortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms am­plitude of the fundamental expressed in dBs.

Power Supply Rejection Ratio

This is the ratio, in dBs, of the change in positive gain error to
the change in V

or VSS. It is a dc measurement.

DD

OPERATIONAL DIAGRAM

An operational diagram for the AD7884/AD7885 is shown in
Figure 6. It is set up for an analog input range of ±5 V. If a

±3 V input range is required, A1 should drive ±3 V
±3 V

F with ±5 VINS, ±5 VINF being tied to system AGND.

IN

S and

IN

Figure 6. AD7884/AD7885 Operational Diagram

The chosen input buffer amplifier (A1) should have low noise
and distortion and fast settling time for high bandwidth applica­tions. Both the AD711 and the AD845 are suitable amplifiers.

A2 is the force, sense amplifier for AGND. The AGNDS pin
should be at zero potential. Therefore, the amplifier must have a
low input offset voltage and good noise performance. It must
also have the ability to deal with fast current transients on the
AGNDS pin. The AD817 has the required performance and is
the recommended amplifier.

If AGNDS and AGNDF are simply tied together to Star
Ground instead of buffering, the SNR and THD are not signifi­cantly degraded. However, dc specifications like INL, Bipolar
Zero and Gain Error will be degraded.

–7–

AD7884/AD7885

The required +3 V reference is derived from the AD780 and
buffered by the high-speed amplifier A3 (AD845, AD817 or
equivalent). A4 is a unity gain inverter which provides the –3 V
negative reference. The gain setting resistors are on-chip and
are factory trimmed to ensure precise tracking of V

REF+

. Figure
6 shows A3 and A4 as AD845s or AD817s. These have the ability
to respond to the rapidly changing reference input impedance.

CIRCUIT DESCRIPTION
Analog Input Section

The analog input section of the AD7884/AD7885 is shown in
Figure 7. It contains both the input signal conditioning and
sample-and-hold amplifier. Note that the analog input is truly
benign. When SW1a goes open circuit to put the SHA into the
hold mode, SW1b is closed. This means that the input resis­tors, R1 and R2 are always connected to either virtual ground
or true ground.

R3 3kΩ

±3V F

IN

±3V S

IN

±5V F

IN

±5V S

IN

R1 3kΩ

SW1a

R2 5kΩ

SW1b

C1

A1

TO RESIDUE

AMPLIFIER A2

R4 4kΩ

R6 2kΩ

V

REF–

R5 4kΩ

TO
9-BIT
ADC

Figure 7. AD7884/AD7885 Analog Input Section

When the ±3 VINS and ±3 VINF inputs are tied to 0 V, the in­put section has a gain of –0.6 and transforms an input signal
of ±5 volts to the required ±3 volts. When the ±5 V
±5 V

F inputs are grounded, the input section has a gain of

IN

S and

IN

–1 and so the analog input range is now ± 3 volts. Resistors R4
and R5, at the amplifier output, further condition the ± 3 volts
signal to be 0 to –3 volts. This is the required input for the 9-bit
A/D converter section.

With SW1a closed, the output of A1 follows the input (the
sample-and-hold is in the track mode). On the rising edge of
the

CONVST pulse, SW1a goes open circuit, and capacitor C1
holds the voltage on the output of A1. The sample-and­hold is now in the hold mode. The aperture delay time for the
sample-and-hold is nominally 50 ns.

A/D Converter Section

The AD7884/AD7885 uses a two-pass flash technique in order
to achieve the required speed and resolution. When the

CONVST

control input goes from low to high, the sample-and-hold ampli­fier goes into the hold mode and a 0 V to –3 V signal is pre­sented to the input of the 9-bit ADC. The first phase of
conversion generates the 9 MSBs of the 16-bit result and trans­fers these to the latch and ALU combination. They are also fed
back to the 9 MSBs of the 16-bit DAC. The 7 LSBs of the
DAC are permanently loaded with 0s. The DAC output is sub­tracted from the analog input with the result being amplified
and offset in the Residue Amplifier Section. The signal at the
output of A2 is proportional to the error between the first phase
result and the actual analog input signal and is digitized in the
second conversion phase. This second phase begins when the
16-bit DAC and the Residue Error Amplifier have both settled.
First, SW2 is turned off and SW3 is turned on. Then, the SHA
section of the Residue Amplifier goes into hold mode. Next
SW2 is turned off and SW3 is turned on. The 9-bit result is
transferred to the output latch and ALU. An error correction al­gorithm now compensates for the offset inserted in the Residue
Amplifier Section and errors introduced in the first pass conver­sion and combines both results to give the 16-bit answer.

±3V SIGNAL

FROM INPUT

SHA

R6

2kΩ

R4

RESIDUE AMP

V F

REF+

4kΩ

R5

4kΩ

A2

+

SHA

ACCURATE

+3V –3V

V S

REF+

0 TO –3V

V

REF–

16-BIT

DAC

R7

2kΩ

9-BIT
ADC

SW2

SW3

9

R8

2kΩ

V

V

REF–

INV

9

9

LATCH

+

ALU

16

Figure 8. A/D Converter Section

–8–

REV. C

Timing and Control Section

A1

V

INV

±3V S

IN

IN

±3V F

±5V S

IN

IN

±5V F

±3V S

IN

IN

±3V F

±5V S

IN
IN

±5V F

A1

V

INV

Figure 9 shows the timing and control sequence for the
AD7884/AD7885. When the part receives a

CONVST pulse,
the conversion begins. The input sample-and-hold goes into the
hold mode 50 ns after the rising edge of

CONVST and BUSY
goes low. This is the first phase of conversion and takes 3.35 µs
to complete. The second phase of conversion begins when SW2
is turned off and SW3 turned on. The Residue Amplifier and
SHA section (A2 in Figure 8) goes into hold mode at this point
and allows the input sample-and-hold to go back into sample
mode. Thus, while the second phase of conversion is ongoing,
the input sample-and-hold is also acquiring the input signal for
the next conversion. This overlap between conversion and ac­quisition allows throughput rates of 166 kSPS to be achieved.

AD7884/AD7885

Figure 10. ±5 V Input Range Connection

CONVST

BUSY

HOLDINPUT

SHA

SAMPLE

FIRST PHASE OF CONVERSION
1ST 9-BIT CONVERSION
DAC SETTLING TIME
RESIDUE AMPLIFIER
SETTLING TIME

FIRST PHASE

3.5µs

SECOND PHASE OF CONVERSION
2ND 9-BIT CONVERSION
ERROR CORRECTION
OUTPUT LATCH UPDATE

SECOND

PHASE

1.8µs

TACQ

2.5µs

Figure 9. Timing and Control Sequence

USING THE AD7884/AD7885 ANALOG INPUT RANGES

The AD7884/AD7885 can be set up to have either a ± 3 volts
analog input range or a ±5 volts analog input range. Figures 10
and 11 show the necessary corrections for each of these. The
output code is 2s complement and the ideal code table for both
input ranges is shown in Table I.

Reference Considerations

The AD7884/AD7885 operates from a ± 3 volt reference. This
can be derived simply using the AD780 as shown in Figure 6.

Table I. Ideal Output Code Table for the AD7884/AD7885

In Terms of FSR263 V Range

Analog Input

3

65 V Range

Figure 11. ±3 V Input Range Connections

The critical performance specification for a reference in a 16-bit
application is noise. The reference pk-pk noise should be insig­nificant in comparison to the ADC noise. The AD7884/
AD7885 has a typical rms noise of 120 µV. For example a rea-
sonable target would be to keep the total rms noise less than
125 µV. To do this the reference noise needs to be less than
35 µV rms. In the 100 kHz band, the AD780 noise is less than
30 µV rms, making it a very suitable reference.

The buffer amplifier used to drive the device V

should have

REF+

low enough noise performance so as not to affect the overall
system noise requirement. The AD845 and AD817 achieve
this.

4

Digital Output
Code Transition

l

+FSR/2 – 1 LSB 2.999908 4.999847 011 . . . 111 to 111 . . . 110
+FSR/2 – 2 LSBs 2.999817 4.999695 011 . . . 110 to 011 . . . 101
+FSR/2 – 3 LSBs 2.999726 4.999543 011 . . . 101 to 011 . . . 100

AGND + 1 LSB 0.000092 0.000153 000 . . . 001 to 000 . . . 000
AGND 0.000000 0.000000 000 . . . 000 to 111 . . . 111
AGND – 1 LSB –0.000092 –0.000153 111 . . . 111 to 111 . . . 110

–(FSR/2 – 3 LSBs) –2.999726 –4.999543 100 . . . 011 to 100 . . . 010
–(FSR/2 – 2 LSBs) –2.999817 –4.999695 100 . . . 010 to 100 . . . 001
–(FSR/2 – 1 LSB) –2.999908 –4.999847 100 . . . 001 to 100 . . . 000

NOTES

1

This table applies for V

2

FSR (Full-Scale Range) is 6 volts for the ±3 V input range and 10 volts for the ±5 V input range.

3

REV. C

1 LSB on the ±3 V range is FSR/216 and is equal to 91.5 µV.

4

1 LSB on the ±5 V range is FSR/216 and is equal to 152.6 µV.

S = +3 V.

REF+

–9–

AD7884/AD7885

3000

0

2000

1000

CODE FREQUENCY

(X – 2) (X – 1) (X) (X + 1) (X + 2) (X + 3)

CODE

Decoupling and Grounding

The AD7884 and AD7885A have one AVDD pin and two V

DD

pins. They also have one AVSS pin and three VSS pins. The
AD7885 has one AV
V

pin. Figure 6 shows how a common +5 V supply should be

SS

pin, one VDD pin, one AVSS pin and one

DD

used for the positive supply pins and a common –5 V supply for
the negative supply pins.

For decoupling purposes, the critical pins on both devices are
the AV

and AVSS pins. Each of these should be decoupled to

DD

system AGND with 10 µF tantalum and 0.1 µF ceramic capaci-
tors right at the pins. With the V

and VSS pins, it is sufficient

DD

to decouple each of these with ceramic 1 µF capacitors.
AGNDS, AGNDF are the ground return points for the on-chip

9-bit ADC. They should be driven by a buffer amplifier as
shown in Figure 6. If they are tied directly together and then
to ground, there will he a marginal degradation in linearity
performance.

The GND pin is the analog ground return for the on-chip linear
circuitry. It should he connected to system analog ground.

The DGND pin is the ground return for the on-chip digital
circuitry. It should be connected to the ground terminal of the
V

and VSS supplies. If a common analog supply is used for

DD

AV

and VDD then DGND should be connected to the com-

DD

mon ground point.

Power Supply Sequencing

AVDD and VDD are connected to a common substrate and there
is typically 17 Ω resistance between them. If they are powered
by separate +5 V supplies, then these should come up simulta­neously. Otherwise, the one that comes up first will have to
drive +5 V into a 17 Ω load for a short period of time. However,
the standard short-circuit protection on regulators like the 7800
series will ensure that there is no possibility of damage to the
driving device.

AV

should always come up either before or at the same time

SS

as V

. If this cannot be guaranteed, Schottky diodes should be

SS

used to ensure that V

never exceeds AVSS by more than 0.3 V.

SS

Arranging the power supplies as in Figure 6 and using the recom­mended decoupling ensures that there are no power supply
sequencing issues as well as giving the specified noise performance.

+5V +5V –5V –5V

AVDDV

AV

DD

SSVSS

HP5082-2810

OR

EQUIVALENT

AD7884/AD7885 PERFORMANCE
Linearity

The linearity of the AD7884/AD7885 is determined by the
on-chip 16-bit D/A converter. This is a segmented DAC which
is laser trimmed for 16-bit DNL performance to ensure that
there are no missing codes in the ADC transfer function. Figure
13 shows a typical INL plot for the AD7884/AD7885.

2.0

1.5

1.0

0.5

LINEARITY ERROR – LSBs

0

0

16384 32768 49152

OUTPUT CODE

V = +5V

DD

V = –5V

SS

T = +25°C

A

65535

Figure 13. AD7884/AD7885 Typical Linearity Performance

Noise

In an A/D converter, noise exhibits itself as code uncertainty in
dc applications and as the noise floor (in an FFT, for example)
in ac applications.

In a sampling A/D converter like the AD7884/AD7885, all in­formation about the analog input appears in the baseband from
dc to 1/2 the sampling frequency. An antialiasing filter will re­move unwanted signals above f

/2 in the input signal but the

S

converter wideband noise will alias into the baseband. In the
AD7884/AD7885, this noise is made up of sample-and-hold
noise and A/D converter noise. The sample-and-hold section
contributes 51 µV rms and the ADC section contributes 59 µV
rms. These add up to a total rms noise of 78 µV. This is the in-
put referred noise in the ±3 V analog input range. When operat­ing in the ±5 V input range, the input gain is reduced to –0.6.
This means that the input referred noise is now increased by a
factor of 1.66 to 120 µV rms.

Figure 14 shows a histogram plot for 5000 conversions of a dc
input using the AD7884/AD7885 in the ± 5 V input range. The
analog input was set as close as possible to the center of a code
transition. All codes other than the center code are due to the
ADC noise. In this case, the spread is six codes.

Incorrect Power Supply Sequencing

Figure 12. Schottky Diodes Used to Protect Against

AD7884/AD7885

Figure 14. Histogram of 5000 Conversions of a DC Input

–10–

REV. C

AD7884/AD7885

MC68000

AD7884

ADDRESS

DECODE LOGIC

CONVST

CS

RD

DB15 – DB0

R/W

DATA BUS

ADDRESS BUS

A23 – A1

D15 – D0

DTACK

AS

CSA

CSB

If the noise in the converter is too high for an application, it can
be reduced by oversampling and digital filtering. This involves
sampling the input at higher than the required word rate and
then averaging to arrive at the final result. The very fast conver­sion time of the AD7884/AD7885 makes it very suitable for
oversampling. For example, if the required input bandwidth is
40 kHz, the AD7884/AD7885 could be oversampled by a factor
of 2. This yields a 3 dB improvement in the effective SNR per­formance. The noise performance in the ± 5 volt input range is
now effectively 85 µV rms and the resultant spread of codes for
2500 conversions will be four. This is shown in Figure 15.

1500

1000

500

CODE FREQUENCY

0

(X – 1) (X) (X + 1) (X + 2)

CODE

Figure 15. Histogram of 2500 Conversions of a DC Input
Using a

×

2 Oversampling Ratio

Dynamic Performance

With a combined conversion and acquisition time of 6 µs, the
AD7884/AD7885 is ideal for wide bandwidth signal processing
applications. Signal to (Noise + Distortion), Total Harmonic
Distortion, Peak Harmonic or Spurious Noise and Intermodula­tion Distortion are all specified. Figure 16 shows a typical
FFT plot of a 1.8 kHz, ± 5 V input after being digitized by the
AD7884/AD7885.

0

f = 1.8kHz, ± 5V SINE WAVE

IN

f = 163kHz

SAMPLE

–30

SNR = 87dB
THD = –95dB

16

15

14

13

12

EFFECTIVE NUMBER OF BITS

11

10

0

20

FREQUENCY – kHz

6040

80

Figure 17. Effective Number of Bits vs. Frequency

The effective number of bits for a device can be calculated from
its measured SNR. Figure 17 shows a typical plot of effective
number of bits versus frequency for the AD7884. The sampling
frequency is 166 kHz.

MICROPROCESSOR INTERFACING

The AD7884/AD7885 is designed on a high speed process
which results in very fast interfacing timing (Data Access Time
of 57 ns max). The AD7884 has a full 16-bit parallel bus, and
the AD7885 has an 8-bit wide bus. The AD7884, with its paral­lel interface, is suited to 16-bit parallel machines whereas the
AD7885, with its byte interface, is suited to 8-bit machines.
Some examples of typical interface configurations follow.

AD7884 to MC68000 Interface

Figure 18 shows a general interface diagram for the MC68000,
16-bit microprocessor to the AD7884. In Figure 18, conversion
is initiated by bringing

CSA low (i.e., writing to the appropriate
address). This allows the processor to maintain control over the
complete conversion process. In some cases it may be more
desirable to control conversion independent from the processor.
This can be done by using an external sampling timer.

–60

dB

–90

–120

–150

Figure 16. AD7884/AD7885 FFT Plot

Effective Number of Bits

The formula for SNR (see Terminology section) is related to
the resolution or number of bits in the converter. Rewriting the
formula, below, gives a measure of performance expressed in
effective number of bits (N).

2048 POINT FFT

N = (SNR – 1.76)/6.02

REV. C

Figure 18. AD7884 to MC68000 Interface

Once conversion has been started, the processor must wait until
it is completed before reading the result. There are two ways of
ensuring this. The first way is to simply use a software delay to
wait for 6.5 µs before bringing

CS and RD low to read the data.

–11–

AD7884/AD7885

The second way is to use the BUSY output of the AD7884 to
generate an interrupt in the MC68000. Because of the nature of
its interrupts, the MC68000 requires additional logic (not
shown in Figure 18) to allow it to be interrupted correctly. For
full information on this, consult the MC68000 User’s Manual.

AD7884 to 80286 Interface

The 80286 is an advanced high performance processor with spe­cial capabilities aimed at multiuser and multitasking systems.

MRDC

82288 BUS

CONTROLLER

CLK

82284 CLOCK

GENERATOR

CLK

CLK

A – A

80286

CPU

D – D

15 0

23 0

Figure 19 shows an interface configuration for the AD7884 to
such a system. Note that only signals relevant to the AD7884
are shown. For the full 80286 configuration refer to the iAPX
286 data sheet (Basic System Configuration).

In Figure 19 conversion is started by writing to a selected ad­dress and causing it
plete,

BUSY goes high and initiates an interrupt. The processor

CS2 to go low. When conversion is com-

can then read the conversion result.

MEMORY READ

CS1

CS2

DECODE

CIRCUITRY

AD7884

RD

CS

8282 OR

8283

LATCH

8259A

INTERRUPT

CONTROLLER

IR – IR

07

CONVST
DB15

DB0

BUSY

8286 OR 8287

TRANSCEIVER

Figure 19. AD7884 Interfacing to Basic iAPX 286 System

–12–

REV. C

AD7884/AD7885

TIMER

AD7884

CONVST

CS
RD

DB15 – DB8

BUSY

HBEN

A0

74HC574

74HC574

CLK

CLK

DB7 – DB0

AD7885 to 8088 Interface

The AD7885, with its byte (8 + 8) data format, is ideal for use
with the 8088 microprocessor. Figure 20 is the interface dia­gram. Conversion is started by enabling

CSA. At the end of
conversion, data is read into the processor. The read instruc­tions are:

MOV AX, C001 Read 8 MSBs of data
MOV AX, C000 Read 8 LSBs of data

STB

8282

+5 V

ADDRESS BUS

ADDRESS

DECODE LOGIC

CSB

DATA BUS

CSA

A0

HBEN

CONVST
CS

RD

AD7885

DB7 – DB0

MN/MX

A15 – A8

IO/M

8088

RD

ALE

AD7 – AD0

Figure 20. AD7885 to 8088 Interface

AD7884 to ADSP-2101 Interface

Figure 21 shows an intcrface between the AD7884 and the
ADSP-2101. Conversion is initiated using a timer which allows
very accurate control of the sampling instant. The AD7884
BUSY line provides an interrupt to the ADSP-2101 when con­version is completed. The

RD pulse width of the processor can
be programmed using the Data Memory Wait State Control
Register. The result can then be read from the ADC using the
following instruction:

MR0 = DM (ADC)

where MR0 is the ADSP-2101 MR0 register, and

where ADC is the AD7884 address.

Stand-Alone Operation

If CS and RD are tied permanently low on the AD7884, then,
when a conversion is completed, output data will be valid on the
rising edge of

BUSY. This makes the device very suitable for
stand-alone operation. All that is required to run the device is an
external

CONVST pulse which can be supplied by a sample
timer. Figure 22 shows the AD7884 set up in this mode with the
BUSY signal providing the clock for the 74HC574 3-state
latches.

Figure 22. Stand-Alone Operation

Digital Feedthrough from an Active Bus

It is very important when using the AD7884/AD7885 in a
microprocessor-based system to isolate the ADC data bus from
the active processor bus while a conversion is being executed.
This will yield the best noise performance from the ADC.
Latches like the 74HC574 can be used to do this. If the device
is connected directly to an active bus then the converter noise
will typically increase by a factor of 30%.

REV. C

TIMER

DMA13 – DMA0

ADSP-2101

DMS

IRQn

RD

DMD15 – DMD0

Figure 21. AD7884 to ADSP-2101 Interface

ADDRESS BUS

ADDRESS

DECODE LOGIC

EN

DATA BUS

CONVST
CS

BUSY
RD

DB15 – DB0

AD7884

–13–

AD7884/AD7885

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Pin Plastic DIP (N-28A)

1.450 (36.83)

1.440 (35.576)

28

1

0.200

(5.080)

MAX

SEATING

PLANE

0.020 (0.508)

0.015 (0.381)

LEADS ARE SOLDER DIPPED OR TIN-PLATED ALLOY 42 OR COPPER.

0.06 (1.52)

0.05 (1.27)

0.105 (2.67)

0.095 (2.41)

15

0.550 (13.97)

0.530 (13.462)

14

0.175 (4.45)

0.120 (3.05)

40-Pin Plastic DIP (N-40A)

0.606 (15.39)

0.594 (15.09)

15°

0°

0.160 (4.06)

0.140 (3.56)

0.012 (0.305)

0.008 (0.203)

0.005 (0.13) MIN

PIN 1

0.200
(5.08)

MAX

0.175 (4.45)

0.120 (3.05)

0.025 (0.64)

0.015 (0.38)

2.08 (52.83) MAX

0.100 (2.54)
BSC

0.060 (1.52)

0.040 (1.02)

0.110 (2.79) MAX

2140

0.55 (13.97)

0.53 (13.46)

201

0.060 (1.52)

0.015 (0.38)

SEATING
PLANE

0.140
(3.56)
MIN

0˚-15

0.620 (15.75)

0.580 (14.73)

˚

0.015 (0.38)

0.008 (0.20)

–14–

REV. C

44-Pin PLCC (P-44A)

AD7884/AD7885

0.045

(1.143)

TYP

0.045 (1.143) TYP

TOP VIEW

0.656 (16.662)

0.650 (16.510)

0.695 (17.65)

0.685 (17.40)

PIN 1

IDENTIFIER

SQ

SQ

R.020 (0.508) MAX

3 PLCS

0.045

(1.143)

TYP

0.180 (4.57)

0.165 (4.20)

0.045 (1.143) TYP

0.050 ± 0.005
(1.27 ± 0.13)

0.021 (0.533)

0.013 (0.331)

0.032 (0.812)

0.026 (0.661)

0.020 (0.508) MIN

0.120 (3.04)

0.090 (2.29)

0.630 (16.00)

0.590 (14.99)

REV. C

–15–

C1620b–5–3/95

–16–

PRINTED IN U.S.A.