Page 1
LC2MOS Complete,
V
V
FEATURES
Complete monolithic 12-bit ADCs with
2 μs track-and-hold amplifier
8 μs ADC
On-chip reference
Laser-trimmed clock
Parallel, byte, and serial digital interface
72 dB SNR at 10 kHz input frequency
(AD7870, AD7875)
57 ns data access time
Low power: −60 mW typical
Variety of input ranges
±3 V for AD7870
0 V to +5 V for AD7875
±10 V for AD7876
12-Bit, 100 kHz, Sampling ADCs
AD7870/AD7875/AD7876
FUNCTIONAL BLOCK DIAGRAM
3V
CLOCK
REF OUT
Figure 1.
IN
INPUT
SCALING
12-BIT
DAC
PARALLEL
AND SERIAL
INTERFACE
DB11 DB0CS RD BUSY/INT
DD
AD7870/AD7875/
AD7876
TRACK-AND-HOLD
COMP
SAR +
COUNTER
DGND
V
SS
07730-001
CLK
12/8/CLK
CONVST
AGND
REFERENCE
CONTROL LO GIC
GENERAL DESCRIPTION
The AD7870/AD7875/AD7876 are fast, complete, 12-bit
analog-to-digital converters (ADCs). These converters consist
of a track-and-hold amplifier, an 8 μs successive approximation
ADC, a 3 V buried Zener reference, and versatile interface logic.
The ADCs feature a self-contained internal clock which is laser
trimmed to guarantee accurate control of conversion time. No
external clock timing components are required; the on-chip
clock may be overridden by an external clock if required.
The parts offer a choice of three data output formats: a single,
parallel, 12-bit word; two 8-bit bytes or serial data. Fast bus
access times and standard control inputs ensure easy interfacing
to modern microprocessors and digital signal processors.
All parts operate from ±5 V power supplies. The AD7870 and
AD7876 accept input signal ranges of ±3 V and ±10 V, respectively, while the AD7875 accepts a unipolar 0 V to +5 V input
range. The parts can convert full power signals up to 50 kHz.
The AD7870/AD7875/AD7876 feature dc accuracy specifications, such as linearity, full-scale and offset error. In addition,
the AD7870 and AD7875 are fully specified for dynamic
performance parameters including distortion and signal-tonoise ratio.
The parts are available in a 24-pin, 0.3 inch-wide, plastic or
hermetic dual-in-line package (DIP). The AD7870 and AD7875
are available in a 28-pin plastic leaded chip carrier (PLCC),
while the AD7876 is available and in a 24-pin small outline
(SOIC) package.
PRODUCT HIGHLIGHTS
1. Complete 12-bit ADC on a chip.
The AD7870/AD7875/AD7876 provide all the functions
necessary for analog-to-digital conversion and combine a
12-bit ADC with internal clock, track-and-hold amplifier
and reference on a single chip.
2. Dynamic specifications for DSP users.
The AD7870 and AD7875 are fully specified and tested for
ac parameters, including signal-to-noise ratio, harmonic
distortion and intermodulation distortion.
3. Fast microprocessor interface.
Data access times of 57 ns make the parts compatible with
modern 8-bit and 16-bit microprocessors and digital signal
processors. Key digital timing parameters are tested and
guaranteed over the full operating temperature range.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1997–2009 Analog Devices, Inc. All rights reserved.
Page 2
AD7870/AD7875/AD7876
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AD7870 Specifications ................................................................. 3
AD7875/AD7876 Specifications ................................................. 4
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Load Circuits ................................................................................... 10
Converter Details ............................................................................ 11
Internal Reference ...................................................................... 11
Track-and-Hold Amplifier ........................................................ 11
Analog Input ............................................................................... 11
Offset And Full-Scale Adjustment—AD7870 ........................ 12
Offset And Full-Scale Adjustment—AD7876 ........................ 13
Offset And Full-Scale Adjustment—AD7875 ........................ 13
Timing and Control ....................................................................... 14
Data Output Formats ................................................................. 14
Mode 1 Interface ......................................................................... 14
Mode 2 Interface ......................................................................... 15
Dynamic Specifications ............................................................. 16
Microprocessor Interface ............................................................... 19
Parallel Read Interfacing ........................................................... 19
Two-Byte Read Interfacing ....................................................... 19
Serial Interfacing ........................................................................ 20
Standalone Operation ................................................................ 21
Applications Information .............................................................. 22
Layout Hints ................................................................................ 22
Noise ............................................................................................ 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 25
REVISION HISTORY
2/09—Rev. B to Rev. C
Updated Format .................................................................. Universal
Reorganized Layout ............................................................ Universal
Deleted S Version ................................................................ Universal
Changes to Internal Clock Parameter, Table 1 and
Added Endnote to Table 1 ............................................................... 4
Changes to Internal Clock Parameter, Table 2 .............................. 5
Changes to Mode 1 Interface Section .......................................... 14
Deleted Data Acquisition Board and Interface Connections
Sections and Figure 26 ................................................................... 15
Deleted Figure 27 and Power Supply Connections, Shorting
Plug Options and Components List Sections ............................. 16
Deleted Figure 28 and Figure 29 ................................................... 17
Deleted Figure 30 and Figure 31 ................................................... 18
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 25
Rev. C | Page 2 of 28
Page 3
AD7870/AD7875/AD7876
SPECIFICATIONS
VDD = +5 V ± 5%, VSS = −5 V ± 5%, AGND = DGND = 0 V, f
T
, unless otherwise noted.
max
AD7870 SPECIFICATIONS
= 2.5 MHz external, unless otherwise stated. All Specifications T
CLK
min
to
Table 1.
ADN7870
1
Parameter J, A K, B L, C T Units Test Conditions/Comments
DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio3 (SNR)
@ +25°C 70 70 72 69 dB min VIN = 10 kHz sine wave, f
T
to T
MIN
Total Harmonic Distortion (THD) −80 −80 −80 −78 dB max
70 70 71 69 dB min Typically 71.5 dB for 0 < VIN < 50 kHz
MAX
= 10 kHz sine wave, f
V
IN
Typically −86 dB for 0 < V
Peak Harmonic or Spurious Noise −80 −80 −80 −78 dB max
= 10 kHz, f
V
IN
SAMPLE
Typically −86 dB for 0 < V
SAMPLE
SAMPLE
< 50 kHz
IN
= 100 kHz
< 50 kHz
IN
Intermodulation Distortion (IMD)
Second Order Terms −80 −80 −80 −78 dB max fa = 9 kHz, fb = 9.5 kHz, f
Third Order Terms −80 −80 −80 −78 dB max fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
SAMPLE
Track-and-Hold Acquisition Time 2 2 2 2 μs max
DC ACCURACY
Resolution 12 12 12 12 Bits
Minimum Resolution for which No Missing Codes
12 12 12 12 Bits
are Guaranteed
Integral Nonlinearity ±1/2 ±1/2 ±1/4 ±1/2 LSB typ
Integral Nonlinearity ±1 ±1/2 ±1 LSB max
Differential Nonlinearity ±1 ±1 ±1 LSB max
Bipolar Zero Error ±5 ±5 ±5 ±5 LSB max
Positive Full-Scale Error4 ±5 ±5 ±5 ±5 LSB max
Negative Full-Scale Error4 ±5 ±5 ±5 ±5 LSB max
ANALOG INPUT
Input Voltage Range ±3 ±3 ±3 ±3 V
Input Current ±500 ±500 ±500 ±500 μA max
REFERENCE OUTPUT
REF OUT @ +25°C 2.99 2.99 2.99 2.99 V min
3.01 3.01 3.01 3.01 V max
REF OUT Tempco ±60 ±60 ±35 ±35
ppm/°C
max
Reference Load Sensitivity
(ΔREF OUT/ΔI)
±1 ±1 ±1 ±1 mV max
Reference load current change (0 μA to
500 μA). Reference load should not be
changed during conversion.
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
2.4 2.4 2.4 2.4 V min VDD = 5 V ± 5%
INH
0.8 0.8 0.8 0.8 V max VDD = 5 V ± 5%
INL
Input Current, IIN ±10 ±10 ±10 ±10 μA max VIN = 0 V to VDD
Input Current (12/8/CLK Input Only)
Input Capacitance, C
5
IN
±10 ±10 ±10 ±10 μA max V
10 10 10 10 pF max
= VSS to VDD
IN
LOGIC OUTPUTS
Output High Voltage, VOH 4.0 4.0 4.0 4.0 V min I
Output Low Voltage, VOL 0.4 0.4 0.4 0.4 V max I
= 40 μA
SOURCE
= 1.6 mA
SINK
DB11 to DB0
Floating-State Leakage Current ±10 ±10 ±10 ±10 μA max
Floating-State Output Capacitance
5
15 15 15 15 pF max
= 100 kHz
= 100 kHz
= 50 kHz
= 50 kHz
Rev. C | Page 3 of 28
Page 4
AD7870/AD7875/AD7876
ADN7870
1
Parameter J, A K, B L, C T Units Test Conditions/Comments
CONVERSION TIME
External Clock (f
Internal Clock
= 2.5 MHz) 8 8 8 8 μs max
CLK
6
6.5/9 6.5/9 6.5/9 6.5/9
μs min/
μs max
POWER REQUIREMENTS
VDD +5 +5 +5 +5 V nom ±5% for specified performance
VSS −5 −5 −5 −5 V nom ±5% for specified performance
IDD 13 13 13 13 mA max Typically 8 mA
ISS 6 6 6 6 mA max Typically 4 mA
Power Dissipation 95 95 95 95 mW max Typically 60 mW
1
The temperature range for the J, K, and L versions is from 0°C to +70°C; for the A, B, and C versions is−40°C to +85°C; and for the T version is −55°C to +125°C.
2
VIN (p-p) = ±3 V.
3
SNR calculation includes distortion and noise components.
4
Measured with respect to internal reference and includes bipolar offset error.
5
Sample tested @ +25°C to ensure compliance.
6
Conversion time specification for the AD7870A device with internal clock used is 8 μs/10 μs minimum/maximum.
AD7875/AD7876 SPECIFICATIONS
Table 2.
AD7875/AD7876
Parameter
1
Units Test Conditions/Comments K, B L, C T
DC ACCURACY
Resolution 12 12 12 Bits
Min Resolution for which No Missing
12 12 12 Bits
Codes Are Guaranteed
Integral Nonlinearity @ +25°C ±1 ±1/2 ±1 LSB max
T
to T
MIN
T
MIN
(AD7875 Only) ±1 ±1 ±1 LSB max
MAX
to T
(AD7876 Only) ±1 ±1/2 ±1 LSB max
MAX
Differential Nonlinearity ±1 ±1 ±1.5/−1.0 LSB max
Unipolar Offset Error (AD7875 Only) ±5 ±5 ±5 LSB max
Bipolar Zero Error (AD7876 Only) ±6 ±2 ±6 LSB max
Full-Scale Error at +25°C2 ±8 ±8 ±8 LSB max Typical full-scale error is ±1 LSB
Full-Scale TC2 ±60 ±35 ±60 ppm/°C max Typical TC is ±20 ppm/°C
Track-and-Hold Acquisition Time 2 2 2 μs max
DYNAMIC PERFORMANCE3 (AD7875
ONLY)
Signal-to-Noise Ratio4 (SNR)
@ +25°C 70 72 69 dB min VIN = 10 kHz sine wave, f
T
to T
MIN
Total Harmonic Distortion (THD) −80 −80 −78 dB max
70 71 69 dB min Typically 71.5 dB for 0 < VIN < 50 kHz
MAX
= 10 kHz sine wave, f
V
IN
Typically −86 dB for 0 < V
Peak Harmonic or Spurious Noise −80 −80 −78 dB max
= 10 kHz, f
V
IN
SAMPLE
Typically −86 dB for 0 < V
SAMPLE
SAMPLE
IN
= 100 kHz
IN
Intermodulation Distortion (IMD)
Second Order Terms −80 −80 −78 dB max fa = 9 kHz, fb = 9.5 kHz, f
Third Order Terms −80 −80 −78 dB max fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
SAMPLE
= 100 kHz
= 100 kHz
< 50 kHz
< 50 kHz
= 50 kHz
= 50 kHz
Rev. C | Page 4 of 28
Page 5
AD7870/AD7875/AD7876
AD7875/AD7876
Parameter
1
Units Test Conditions/Comments K, B L, C T
ANALOG INPUT
AD7875 Input Voltage Range 0 to +5 0 to +5 0 to +5 V
AD7875 Input Current 500 500 500 μA max
AD7876 Input Voltage Range ±10 ±10 ±10 V
AD7876 Input Current
±600 ±600 ±600 μA max
REFERENCE OUTPUT
REF OUT @ +25°C 2.99 2.99 2.99 V min
3.01 3.01 3.01 V max
REF OUT Tempco ±60 ±35 ±60 ppm/°C max Typical tempco Is ±20 ppm/°C
Reference Load Sensitivity
(ΔREF OUT/ΔI)
−1 −1 −1 mV max
Reference load current change (0 μA to 500 μA).
Reference load should not be changed during
conversion.
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
2.4 2.4 2.4 V min VDD = 5 V ± 5%
INH
0.8 0.8 0.8 V max VDD = 5 V ± 5%
INL
Input Current, IIN ±10 ±10 ±10 μA max VIN = 0 V to VDD
Input Current (12/8/CLK Input Only)
Input Capacitance, C
5
IN
±10 ±10 ±10 μA max V
10 10 10 pF max
= VSS to VDD
IN
LOGIC OUTPUTS
Output High Voltage, VOH 4.0 4.0 4.0 V min I
Output Low Voltage, VOL 0.4 0.4 0.4 V max I
= 40 mA
SOURCE
= 1.6 mA
SINK
DB11–DB0
Floating-State Leakage Current 10 10 10 μA max
Floating-State Output
Capacitance
5
15 15 15 pF max
CONVERSION TIME
External Clock (f
Internal Clock 6.5/9 6.5/9 6.5/9
= 2.5 MHz) 8 8 8 μs max
CLK
μs min/μs
max
POWER REQUIREMENTS As per AD7870
1
For the AD7875, the temperature range for the K and L versions is from 0°C to +70°C; for the B and C versions is−40°C to +85°C; and for the T version is −55°C to
+125°C. For the AD7876, the temperature range for the B and C versions is from −40°C to +85°C and for the T version is−55°C to +125°C.
2
Includes internal reference error and is calculated after unipolar offset error (AD7875) or bipolar zero error (AD7876) has been adjusted out. Full-scale error refers to
both positive and negative full-scale error for the AD7876.
3
Dynamic performance parameters are not tested on the AD7876, but these are typically the same as for the AD7875.
4
SNR calculation includes distortion and noise components.
5
Sample tested @ +25°C to ensure compliance.
Refer to the power requirements in Table 1.
Rev. C | Page 5 of 28
Page 6
AD7870/AD7875/AD7876
TIMING CHARACTERISTICS
VDD = +5 V ± 5%, VSS = −5 V ± 5%, AGND = DGND = 0 V. See Figure 14, Figure 15, Figure 16, and Figure 17. Timing specifications are
sample tested at 25°C to ensure compliance, unless otherwise noted. All input signals are specified with t
and timed from a voltage level of 1.6 V.
Table 3.
Parameter
t1
t2
2
t
3
t4
t5
2, 3
t
6
4
t
72,
t8
t9
t10
5
t
11
6
t
12
t13
1
Limit at T
(J, K, L, A, B, C Versions)
50 50 ns min
0 0 ns min
60 75 ns min
0 0 ns min
70 70
57 70 ns max
5 5 ns min
50 50
0 0 ns min
0 0 ns min
100 100 ns min
370 370 ns min SCLK cycle time
135 150 ns max SCLK to valid data delay. CL = 35 pF
20 20 ns min
MIN
, T
MAX
Limit at T
MIN
, T
MAX
(T Version) Units Conditions/Comments
CONVST
to RD setup time (Mode 1)
CS
pulse width
RD
to RD hold time (Mode 1)
CS
to INT delay
ns max
RD
Data access time after RD
Bus relinquish time after RD
ns max
HBEN to RD setup time
HBEN to RD
to SCLK falling edge setup time
SSTRB
SCLK rising edge to SSTRB
100 100 ns max
t14 10 10 ns min Bus relinquish time after SCLK
100 100 ns max
to RD setup time (Mode 2)
t15
t16
t17
t18
t19
t20
1
Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and
2
Timing specifications for t3, t6, and for the maximum limit at t7 are 100% production tested.
3
t6 is measured with the load circuits of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 5.
5
SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
6
SDATA will drive higher capacitive loads but this will add to t12 since it increases the external RC time constant (4.7 kΩ||CL) and thus the time to reach 2.4 V.
60 60 ns min
120 120
ns max
200 200 ns min
0 0 ns min
0 0 ns min
0 0 ns min
SSTRB
and a 2 kΩ pull-up on SCLK. The capacitance on all three outputs is 35 pF.
CS
CS
to BUSY propagation delay
Data setup time prior to BUSY
to RD hold time (Mode 2)
CS
HBEN to CS
HBEN to CS
= tf = 5 ns (10% to 90% of 5 V)
r
pulse width
hold time
setup time
hold time
Rev. C | Page 6 of 28
Page 7
AD7870/AD7875/AD7876
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
VDD to AGND −0.3 V to +7 V
VSS to AGND +0.3 V to −7 V
AGND to DGND −0.3 V to VDD +0.3 V
VIN to AGND −15 V to +15 V
REF OUT to AGND 0 V to VDD
Digital Inputs to DGND −0.3 V to VDD +0.3 V
Digital Outputs to DGND −0.3 V to VDD +0.3 V
Operating Temperature Range
Commercial (J, K, L Versions–AD7870) 0°C to +70°C
Commercial (K, L Versions–AD7875) 0°C to +70°C
Industrial (A, B, C Versions–AD7870) −25°C to +85°C
Industrial (B, C Versions–AD7875/
AD7876)
Extended (T Version) −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) +300°C
Power Dissipation (Any Package) to +75°C 450 mW
Derates above +75°C by 10 mW/°C
−40°C to +85°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. C | Page 7 of 28
Page 8
AD7870/AD7875/AD7876
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RD
1
CLK
DGND
2
AD7870/
3
AD7875/
4
AD7876
5
6
TOP VIEW
7
(Not to Scale)
8
9
10
11
12
BUSY/INT
DB11/HBEN
DB10/SSTRB
DB9/SCLK
DB8/SDATA
DB7/LOW
DB6/LOW
DB5/LOW
DB4/LOW
Figure 2. DIP and SOIC Pin Configuration
Table 5. Pin Function Descriptions
DIP and SOIC
Pin No.
N/A 1, 8, 15,
1 2
2 3
3 4 CLK
4 5 DB11/HBEN
5 6
6 7 DB9/SCLK
7 9 DB8/SDATA
8 to11 10 to 13 DB7/LOW–
12 14 DGND Digital Ground. Ground reference for digital circuitry.
13 to 16 16 to 19 DB3/DB11–
17 20 VDD Positive Supply, +5 V ± 5%.
PLCC
Pin No. Mnemonic Function
NC No Connect.
22
RD
Read. Active low logic input. This input is used in conjunction with CS low to enable the data outputs.
BUSY
INT
/
SSTRB
DB10/
DB4/LOW
DB0/DB8
CS
24
23
CONVST
12/8/CLK
22
V
21
20
V
REF OUT
19
AGND
18
17
V
DB0/DB8
16
DB1/DB9
15
14
DB2/DB10
DB3/DB11
13
SS
IN
DD
07730-004
DB11/HBEN
DB10/SSTRB
DB9/SCLK
NC
DB8/SDATA
DB7/LO W
DB6/LO W
CLK
BUSY/INTRDNCCSCONVST
5
6
7
8
9
10
11
PIN 1
INDENTFIER
AD7870/AD7875/
AD7876
TOP VIEW
(Not to Scale)
12 13 14 15 16 17 18
DGND
DB5/LOW
DB4/LOW
NC = NO CONNECT
1282726234
NC
12/8/CLK
25
V
24
V
23
REF OUT
22
NC
21
AGND
20
V
DB0/DB8
19
DB1/DB9
DB3/DB 11
DB2/DB10
Figure 3. PLCC Pin Configuration
Busy/Interrupt. Active low logic output indicating converter status. See Figure 14, Figure 15, Figure 16,
and Figure 17.
Clock Input. An external TTL-compatible clock may be applied to this input pin. Alternatively, tying this
pin to V
enables the internal laser-trimmed clock oscillator.
SS
Data Bit 11 (MSB)/High Byte Enable. The function of this pin is dependent on the state of the 12/
input. When 12-bit parallel data is selected, this pin provides the DB11 output. When byte data is
selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit bus interfacing. When HBEN is
low, DB7/LOW to DB0/DB8 become DB7 to DB0. With HBEN high, DB7/LOW to DB0/DB8 are used for
the upper byte of data (see ). Table 6
Data Bit 10/Serial Strobe. When 12-bit parallel data is selected, this pin provides the DB10 output.
SSTRB
is an active low open-drain output that provides a strobe or framing pulse for serial data. An
external 4.7 kΩ pull-up resistor is required on
SSTRB
.
Data Bit 9/Serial Clock. When 12-bit parallel data is selected, this pin provides the DB9 output. SCLK is
the gated serial clock output derived from the internal or external ADC clock. If the 12/
−5 V, then SCLK runs continuously. If 12/
8
/CLK is at 0 V, then SCLK is gated off after serial transmission is
8
complete. SCLK is an open-drain output and requires an external 2 kΩ pull-up resistor.
Data Bit 8/Serial Data. When 12-bit parallel data is selected, this pin provides the DB8 output. SDATA is
SSTRB
an open-drain serial data output which is used with SCLK and
is valid on the falling edge of SCLK while
SSTRB
is low. An external 4.7 kΩ pull-up resistor is required on
for serial data transfer. Serial data
SDATA.
Three-state data outputs controlled by
inputs. With 12/
8
/CLK high, they are always DB7–DB4. With 12/8/CLK low or −5 V, their function is
CS
and RD. Their function depends on the 12/8/CLK and HBEN
controlled by HBEN (see ). Table 6
Three-state data outputs which are controlled by
and HBEN inputs. With 12/
8
/CLK high, they are always DB3–DB0. With 12/8/CLK low or −5 V, their
CS
and RD. Their function depends on the 12/8/CLK
function is controlled by HBEN (see ). Table 6
SS
IN
DD
07730-005
8
/CLK
/CLK input is at
Rev. C | Page 8 of 28
Page 9
AD7870/AD7875/AD7876
DIP and SOIC
Pin No.
18 21 AGND Analog Ground. Ground reference for track-and-hold, reference and DAC.
19 23 REF OUT Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load capability is
20 24 VIN Analog Input. The analog input range is ±3 V for the AD7870, ±10 V for the AD7876, and 0 V to +5 V for the
21 25 VSS Negative Supply, −5 V ± 5%.
22 26
23 27
24 28
Table 6. Output Data for Byte Interfacing
HBEN DB7/Low DB6/Low DB5/Low DB4/Low DB3/DB11 DB2/DB10 DB1/DB9 DB0/DB8
High Low Low Low Low DB11(MSB) DB10 DB9 DB8
Low DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB)
PLCC
Pin No. Mnemonic Function
500 μA.
AD7875.
8
12/
/CLK
CONVST
CS
Chip Select. Active low logic input. The device is selected when this input is active. With
Three Function Input. Defines the data format and serial clock format. With this pin at +5 V, the output
data for-mat is 12-bit parallel only. With this pin at 0 V, either byte or serial data is available and SCLK is
not continuous. With this pin at −5 V, either byte or serial data is again available but SCLK is now
continuous.
Convert Start. A low to high transition on this input puts the track-and-hold into its hold mode and
starts conversion. This input is asynchronous to the CLK input.
low, a new conversion is initiated when
CS
goes low.
CONVST
tied
Rev. C | Page 9 of 28
Page 10
AD7870/AD7875/AD7876
V
LOAD CIRCUITS
DBN
5
DGND
3kΩ
10pF
07730-003
5V
56kΩ
DBN
56kΩ
DGND
HIGH-Z TO V
50pF
OH
Figure 4. Load Circuits for Access Time
DBN
HIGH-Z TO V
DGND
50pF
OL
07730-002
DBN
3kΩ
DGND
V
OH
10pF
TO HIGH-Z VOLTO HIGH-Z
Figure 5. Load Circuits for Output Float Delay
Rev. C | Page 10 of 28
Page 11
AD7870/AD7875/AD7876
CONVERTER DETAILS
The AD7870/AD7875/AD7876 is a complete 12-bit ADC,
requiring no external components apart from power supply
decoupling capacitors. It is comprised of a 12-bit successive
approximation ADC based on a fast settling voltage output
DAC, a high speed comparator and SAR, a track-and-hold
amplifier, a 3 V buried Zener reference, a clock oscillator,
and control logic.
INTERNAL REFERENCE
The AD7870/AD7875/AD7876 have on-chip temperature
compensated buried Zener reference that is factory trimmed
to 3 V ± 10 mV. Internally it provides both the DAC reference
and the dc bias required for bipolar operation (AD7870 and
AD7876). The reference output is available (REF OUT) and
capable of providing up to 500 μA to an external load.
The maximum recommended capacitance on REF OUT for
normal operation is 50 pF. If the reference is required for use
external to the ADC, it should be decoupled with a 200 Ω
resistor in series with a parallel combination of a 10 μF
tantalum capacitor and a 0.1 μF ceramic capacitor. These
decoupling components are required to remove voltage
spikes caused by the ADC’s internal operation.
V
DD
V
SS
The reference output voltage is 3 V. For applications using the
AD7875 or AD7876, a 5 V or 10 V reference may be required.
Figure 7 shows how to scale the 3 V REF OUT voltage to
provide either a 5 V or 10 V external reference.
AD7870/AD7875/AD7876
INTERNAL 3V
REFERENCE
Figure 7. Generating a 5 V or 10 V Reference
AD7870/AD7875/AD7876
TEMPERATURE
COMPENSATION
Figure 6. Reference Circuit
REF OUT
15kΩ
(3.9kΩ)
REF OUT
10kΩ
(9.1kΩ)
V
OUT
07730-006
= 5V (10V)
07730-007
TRACK-AND-HOLD AMPLIFIER
The track-and-hold amplifier on the analog input of the
AD7870/AD7875/AD7876 allows the ADC to accurately
convert input frequencies to 12-bit accuracy. The input
bandwidth of the track-and-hold amplifier is much greater
than the Nyquist rate of the ADC even when the ADC is
operated at its maximum throughput rate. The 0.1 dB cutoff
frequency occurs typically at 500 kHz. The track-and-hold
amplifier acquires an input signal to 12-bit accuracy in less than
2 μs. The overall throughput rate is equal to the conversion time
plus the track-and-hold amplifier acquisition time. For a 2.5 MHz
input clock the throughput rate is 10 μs max.
The operation of the track-and-hold is essentially transparent
to the user. The track-and-hold amplifier goes from its tracking
mode to its hold mode at the start of conversion.
CONVST
If the
to hold transition occurs on the rising edge of
starts conversion, this transition occurs on the falling edge of
input is used to start conversion then the track
CONVST
. If CS
CS
.
ANALOG INPUT
The three parts differ from each other in the analog input
voltage range that they can handle. The AD7870 accepts ±3 V
input signals, the AD7876 accepts a ±10 V input range, while
the input range for the AD7875 is 0 V to +5 V.
Figure 8 shows the AD7870 analog input. The analog input
range is ±3 V into an input resistance of typically 15 kΩ. The
designed code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . .
FS–3/2 LSBs). The output code is twos complement binary with
1 LSB = FS/4096 = 6 V/4096 = 1.46 mV. The ideal input/output
transfer function is shown in Figure 11.
AD7870
TRACK-AND-HOLD
R
The AD7876 analog input structure is shown in Figure 9. The
analog input range is ±10 V into an input resistance of typically
33 kΩ. As before, the designed code transitions occur midway
between successive integer LSB values. The output code is twos
complement with 1 LSB = FS/4096 = 20 V/4096 = 4.88 mV. The
ideal input/output transfer function is shown in Figure 11.
AMPLIFI ER
R
TO INTERNAL
3V REFERENCE
Figure 8. AD7970 Analog Input
TO INTERNAL
COMPARATOR
07730-008
Rev. C | Page 11 of 28
Page 12
AD7870/AD7875/AD7876
AD7876
TRACK-AND-HOLD
AMPLI FIER
TO INTERNAL
REFERENCE
TO INTERNAL AGND
TO INTERNAL
COMPARATOR
07730-009
V
REF OUT
AGND
7R
IN
2.1R
3R
Figure 9. AD7876 Analog Input
Figure 10 shows the analog input for the AD7875. The input
range is 0 V to +5 V into an input resistance of typically 25 kΩ.
Once again, the designed code transitions occur midway
between successive integer LSB values. The output code is
straight binary with 1 LSB = FS/4096 = 5 V/4096 = 1.22 mV.
The ideal input/output transfer function is shown in Figure 12.
AD7875
TRACK-AND-HOLD
AMPLI FIER
TO INTERNAL AGND
TO INTERNAL
COMPARATOR
07730-010
V
AGND
2R
IN
3R
Figure 10. AD7875 Analog Input
OUTPUT
CODE
011…111
011…110
000…010
000…001
000…000
111…111
111…110
100…001
100…000
AD7870 (AD7876)
–FS
2
V
– INPUT VOLTAGE
IN
0V
+FS
– 1LSB
2
FS = 6V (20V)
FS
1LSB =
4096
07730-011
Figure 11. AD7870/AD7876 Transfer Function
OUTPUT
CODE
111…111
111…110
111…101
111…100
000…011
000…010
000…001
000…000
V
– INPUT VOLTAGE
IN
FS = 5V
1LSB =
FS
4096
+FS – 1LSB0V
07730-012
Figure 12. AD7875 Transfer Function
OFFSET AND FULL-SCALE ADJUSTMENT— AD7870
In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain
by ac coupling. Full-scale error effect is linear and does not
cause problems as long as the input signal is within the full
dynamic range of the ADC. Some applications will require
that the input signal span the full analog input dynamic range.
In such applications, offset and full-scale error have to be
adjusted to zero.
Where adjustment is required, offset error must be adjusted
before full-scale error. This is achieved by trimming the offset
of the op amp driving the analog input of the AD7870 while the
input voltage is 1/2 LSB below ground. The trim procedure is as
follows: apply a voltage of −0.73 mV(−1/2 LSB) at V
and adjust the op amp offset voltage until the ADC output code
flickers between 1111 1111 1111 and 0000 0000 0000. Gain
error can be adjusted at either the first code transition (ADC
negative full-scale) or the last code transition (ADC positive full
scale). The trim procedures for both cases are as follows (see
Figure 13).
in Figure 13
1
Rev. C | Page 12 of 28
Page 13
AD7870/AD7875/AD7876
R1
10kΩ
V
1
R2
500Ω
R4
10kΩ
R3
10kΩ
1
ADDITIONAL PI NS OMIT TED FOR CL ARITY.
Figure 13. Offset and Full-Scale Adjust Circuit
R5
10kΩ
V
IN
AD7870/
AD7875/
AD7876
AGND
1
07730-013
Positive Full-Scale Adjust
Apply a voltage of 2.9978 V (FS/2 − 3/2 LSBs) at V1. Adjust R2
until the ADC output code flickers between 0111 1111 1110 and
0111 1111 1111.
Negative Full-Scale Adjust
Apply a voltage of −2.9993 V (−FS/2 + 1/2 LSB) at V1 and adjust
R2 until the ADC output code flickers between 1000 0000 0000
and 1000 0000 0001.
OFFSET AND FULL-SCALE ADJUSTMENT— AD7876
The offset and full-scale adjustment for the AD7876 is similar
to that just outlined for the AD7870. The trim procedure, for
those applications that do require adjustment, is as follows:
apply a voltage of −2.44 mV (−1/2 LSB) at V
amp offset voltage until the ADC output code flickers between
1111 1111 1111 and 0000 0000 0000. Full-scale error can be
adjusted at either the first code transition (ADC negative full
scale) or the last code transition (ADC positive full scale). The
trim procedure for both case is as described in the following
sections (see Figure 13).
and adjust the op
1
Positive Full-Scale Adjust
Apply a voltage of 9.9927 V (FS/2 − 3/2 LSBs) at V1. Adjust R2
until the ADC output code flickers between 0111 1111 1110 and
0111 1111 1111.
Negative Full-Scale Adjust
Apply a voltage of −9.9976 V (FS/2 + 1/2 LSB) at V1 and adjust
R2 until the ADC output code flickers between 1000 0000 0000
and 1000 0000 0001.
OFFSET AND FULL-SCALE ADJUSTMENT— AD7875
Similar to the AD7870, most of the DSP applications in which
the AD7875 is used do not require offset and full-scale
adjustment. For applications that do require adjustment, offset
error must be adjusted before full-scale (gain) error. This is
achieved by applying an input voltage of 0.61 mV (1/2 LSB) to
V
in Figure 13 and adjusting the op amp offset voltage until
1
the ADC output code flickers between 0000 0000 0000 and
0000 0000 0001. For full-scale adjustment, apply an input
voltage of 4.9982 V (FS − 3/2 LSBs) to V
the ADC output code flickers between 1111 1111 1110 and
1111 1111 1111.
and adjust R2 until
1
Rev. C | Page 13 of 28
Page 14
AD7870/AD7875/AD7876
TIMING AND CONTROL
The AD7870/AD7875/AD7876 is capable of two basic operating modes. In the first mode (Mode 1), the
used to start conversion and drive the track-and-hold into its
hold mode. At the end of conversion, the track-and-hold returns
to its tracking mode. It is intended principally for digital signal
processing and other applications where precise sampling in
time is required. In these applications, it is important that the
signal sampling occur at exactly equal intervals to minimize
errors due to sampling uncertainty or jitter. For these cases, the
CONVST
The second mode is achieved by hardwiring the
low. This mode (Mode 2) is intended for use in systems where
the microprocessor has total control of the ADC, both initiating
the conversion and reading the data.
the microprocessor is normally driven into a WAIT state for the
duration of conversion by
line is driven by a timer or some precise clock source.
BUSY
INT
/
CONVST
CS
starts conversion and
.
line is
CONVST
line
DATA OUTPUT FORMATS
In addition to the two operating modes, the AD7870/AD7875/
AD7876 also offers a choice of three data output formats, one
serial and two parallel. The parallel data formats are a single,
12-bit parallel word for 16-bit data buses and a two-byte format
for 8-bit data buses. The data format is controlled by the 12/
CLK input. A logic high on this pin selects the 12-bit parallel
output format only. A logic low or −5 V applied to this pin
allows the user access to either serial or byte formatted data.
Three of the pins previously assigned to the four MSBs in
parallel form are now used for serial communications while
the fourth pin becomes a control input for the byte-formatted
data. The three possible data output formats can be selected
in either of the modes of operation.
Parallel Output Format
The two parallel formats available on the part are a 12-bit wide
data word and a two-byte data word. In the first format, all
12 bits of data are available at the same time on DB11 (MSB)
through DB0 (LSB). In the second, two reads are required to
access the data. When this data format is selected, the DB11/
HBEN pin assumes the HBEN function. HBEN selects which
byte of data is to be read from the ADC. When HBEN is low,
the lower eight bits of data are placed on the data bus during a
read operation; with HBEN high, the upper four bits of the 12bit word are placed on the data bus. These four bits are right
justified and thereby occupy the lower nibble of data while the
upper nibble contains four zeros.
Serial Output Format
Serial data is available on the AD7870/AD7875/AD7876 when
8
the 12/
SSTRB
functions. Serial data is available during conversion with a
word length of 16 bits; four leading zeros, followed by the 12-bit
conversion result starting with the MSB. The data is synchro-
/CLK input is at 0 V or −5 V and in this case the DB10/
, DB9/SCLK and DB8/SDATA pins assume their serial
8
/
Rev. C | Page 14 of 28
nized to the serial clock output (SCLK) and framed by the serial
SSTRB
strobe (
of the serial clock and is valid on the falling edge of this clock
while the
clock cycles after
leading zero) is valid on the first falling edge of SCLK. All three
serial lines are open-drain outputs and require external pull-up
resistors.
The serial clock out is derived from the ADC clock source,
which may be internal or external. Normally, SCLK is required
during the serial transmission only. In these cases, it can be shut
down at the end of conversion to allow multiple ADCs to share
a common serial bus. However, some serial systems (such as the
TMS32020) require a serial clock that runs continuously. Both
options are available on the AD7870/AD7875/AD7876 using
the 12/
(SCLK) runs continuously; when 12/
turned off at the end of transmission.
). Data is clocked out on a low to high transition
SSTRB
output is low.
CONVST
8
/CLK input. With this input at −5 V, the serial clock
SSTRB
goes low within three
, and the first serial data bit (the first
8
/CLK is at 0 V, SCLK is
MODE 1 INTERFACE
Conversion is initiated by a low going pulse on the
input. The rising edge of this
and drives the track-and-hold amplifier into its hold mode
(AD7870/AD7875/AD7876). The falling edge of the
pulse starts conversion and drives the track-and-hold amplifier
into its hold mode (AD7870A). Conversion is not initiated if
CS
the
is low. The
function in this mode.
end of conversion. This
microprocessor. A read operation to the ADC accesses the data
and the
The
low for the ADC to operate correctly in this mode. The
RD
cannot be read from the part during conversion because the on-
chip latches are disabled when conversion is in progress. In
applications where precise sampling is not critical, the
CONVST
line OR-gated with a decoded address. In some applications,
depending on power supply turn-on time, the
AD7870/AD7875/AD7876 may perform a conversion on
power-up. In this case, the
dummy read to the AD7870/AD7875/AD7876 is required to
reset the
Figure 18 shows the Mode 1 timing diagram for a 12-bit parallel
data output format (12/
the end of conversion accesses all 12 bits of data at the same
time. Serial data is not available for this data output format.
INT
CONVST
input should not be hardwired low in this mode. Data
pulse can be generated from a microprocessor WR
INT
BUSY/INT
line is reset high on the falling edge of CS and RD.
input must be high when CS and RD are brought
line before starting conversion.
CONVST
status output assumes its
INT
is normally high and goes low at the
INT
line can be used to interrupt the
INT
line powers-up low and a
8
/CLK = +5 V). A read to the ADC at
pulse starts conversion
CONVST
CONVST
INT
CS
or
Page 15
AD7870/AD7875/AD7876
t
1
CONVST
CS
RD
INT
DATA
TRACK-AND-HOLD
GOES INTO HOLD
TRACK-AND-HOLD RET URNS
TO TRACK AND
ACQUISITI ON TIME BEGINS
t
CONVERT
THREE-STATE
Figure 14. Mode 1 Timing Diagram, 12-Bit Parallel Read
t
1
CONVST
1
HBEN
CS
RD
INT
DATA
2
SSTRB
3
SCLK
2
SDATA
1
TIMES
t
,
t
,
t
,
t
2
3
4
2
EXTERNAL 4. 7kΩ PULL-UP RESISTOR.
3
EXTERNAL 2kΩ PULL-UP RESISTOR;
CONTINUOUS SCLK (DASHED LINE) WHEN 12/8/CLK = –5V;
NONCONTINUO US WHEN 12/8/ CLK = 0V.
8
TRACK-AND-HOLD GO ES INTO HOLD
TRACK-AND-HOLD RET URNS TO TRACK
AND ACQUISITI ON TIME BEGINS
t
CONVERT
THREE-STATE
t
10
, AND
t
ARE THE SAME FO R A HIGH BYTE READ AS FOR A LOW BYTE READ.
9
LEADING
ZEROS
t
11
t
12
DB11 DB10
SERIAL DATA
Figure 15. Mode 1 Timing Diagram, Byte or Serial Read
The Mode 1 timing diagram for byte and serial data is shown
INT
in Figure 15.
high by the first falling edge of
goes low at the end of conversion and is reset
CS
and RD. This first read at the
end of conversion can either access the low byte or high byte of
data depending on the status of HBEN ( shows low
Figure 15
byte only for example). The diagram shows both a noncontinuously and a continuously running clock (dashed line).
MODE 2 INTERFACE
The second interface mode is achieved by hard wiring
CONVST
while HBEN is low. The track-and-hold amplifier goes into the
hold mode on the falling edge of
INT
/
low and conversion is initiated by taking CS low
CS
. In this mode, the
pin assumes its
BUSY
function.
BUSY
goes low at the start
BUSY
Rev. C | Page 15 of 28
t
2
t
5
t
4
DB11 TO DB0
t
8
t
2
t
3
t
5
t
6
VAL ID
DATA
DB7 TO DB0
t
13
t
14
DB0
t
3
VAL ID
DATA
t
9
t
7
t
4
t
7
07730-014
t
4
VAL ID
DATA
DB11 TO DB8
of conversion, stays low during the conversion and returns high
when the conversion is complete. It is normally used in parallel
interfaces to drive the microprocessor into a WAIT state for the
duration of conversion. Mode 2 is not relevant for the AD7870A
device.
Figure 16 shows the Mode 2 timing diagram for the 12-bit
parallel data output format (12/
8
/CLK = +5 V). In this case, the
ADC behaves like slow memory. The major advantage of this
interface is that it allows the microprocessor to start conversion,
WAIT and then read data with a single READ instruction. The
user does not have to worry about servicing interrupts or
ensuring that software delays are long enough to avoid reading
during conversion.
07730-015
Page 16
AD7870/AD7875/AD7876
CS
RD
BUSY
DATA
t
15
TRACK-AND-HOLD
GOES INTO HOLD
t
16
THREE-STATE
TRACK-AND-HOLD RET URNS TO TRACK
AND ACQUISITI ON TIME BE GINS
Figure 16. Mode 2 Timing Diagram, 12-Bit Parallel Read
1
HBEN
t
19
CS
t
15
RD
BUSY
DATA
2
SSTRB
3
SCLK
2
SDATA
1
TIMES
t
,
t
15
2
EXTERNAL 4.7kΩ PULL-UP RESISTOR.
3
EXTERNAL 2kΩ PULL-UP RESISTOR;
CONTINUOUS SCLK (DASHED LI NE) WHEN 12/8/ CLK = –5V;
NONCONTINUO US WHEN 12/8/ CLK = 0V.
16
TRACK-AND-HOLD
GOES INTO HOLD
t
t
16
THREE-STATE
t
10
, AND
t
ARE THE SAME FO R A HIGH BYTE READ AS FOR A LOW BYTE READ.
20
TRACK-AND-HOLD RET URNS TO TRACK
t
11
LEADING
ZEROS
CONVERT
AND ACQUISITION TIME BEGINS
t
12
DB11 DB10
SERIAL DATA
Figure 17. Mode 2 Timing Diagram, Byte or Serial Read
The Mode 2 timing diagram for byte and serial data is shown in
Figure 17. For a two-byte data read, the lower byte (DB0 – DB7)
has to be accessed first since HBEN must be low to start conversion. The ADC behaves like slow memory for this first read,
but the second read to access the upper byte of data is a normal
read. Operation of the serial functions is identical between
Mode 1 and Mode 2. The timing diagram of Figure 17 shows
both a noncontinuously and a continuously running SCLK
(dashed line).
DYNAMIC SPECIFICATIONS
The AD7870 and AD7875 are specified and 100% tested for
dynamic performance specifications as well as traditional dc
specifications such as integral and differential nonlinearity.
Although the AD7876 is not production tested for ac
parameters, its dynamic performance is similar to the AD7870
and AD7875. The ac specifications are required for signal
processing applications such as speech recognition, spectrum
analysis and high speed modems. These applications require
information on the ADC’s effect on the spectral content of the
Rev. C | Page 16 of 28
t
CONVERT
t
18
t
t
2
DB0
t
8
t
17
VAL ID
DATA
DB7 TO DB0
t
13
t
14
t
17
DB11 TO DB0
t
7
t
18
VAL ID
DATA
t
20
7
07730-016
t
6
t
6
VAL ID
DATA
DB11 TO DB8
t
7
07730-017
input signal. Thus, the parameters for which the AD7870 and
AD7875 are specified include SNR, harmonic distortion,
intermodulation distortion and peak harmonics. These terms
are discussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up
to half the sampling frequency (FS/2) excluding dc. SNR is
dependent upon the number of quantization levels used in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal-to-noise ratio for
a sine wave input is given by
SNR = (6.02N + 1.76) dB (1)
where N is the number of bits. Thus for an ideal 12-bit
converter, SNR = 74 dB.
Note that a sine wave signal is of very low distortion to the V
input which is sampled at a 100 kHz sampling rate. A fast
IN
Page 17
AD7870/AD7875/AD7876
Fourier transform (FFT) plot is generated from which the SNR
data can be obtained. Figure 18 shows a typical 2048 point FFT
plot of the AD7870KN/AD7875KN with an input signal of 25 kHz
and a sampling frequency of 100 kHz. The SNR obtained from
this graph is 72.6 dB. It should be noted that the harmonics are
taken into account when calculating the SNR.
0
INPUT FREQUENCY = 25kHz
SAMPLE FREQUENCY = 100kHz
SNR = 72.6dB
T
= 25°C
A
–30
–60
–90
SIGNAL AMPL ITUDE (dB)
–120
–140
0
Figure 18. FFT Plot
25
FREQUENCY (kHz)
07730-018
50
Effective Number of Bits
The formula given in Equation 1 relates SNR to the number of
bits. Rewriting the formula, as in Equation 2, it is possible to get
a measure of performance expressed in effective number of
bits (N).
SNR
=
N
76.1−
(2)
02.6
The effective number of bits for a device can be calculated
directly from its measured SNR.
Figure 19 shows a typical plot of effective number of bits vs.
frequency for an AD7870KN/AD7875KN with a sampling
frequency of 100 kHz. The effective number of bits typically
falls between 11.7 and 11.85 corresponding to SNR figures of
72.2 and 73.1 dB.
12.0
11.5
11.0
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the rms
value of the fundamental. For the AD7870/AD7875, THD is
defined as
2
THD
=
where V
V
is the rms amplitude of the fundamental and V2, V3,
1
, V5 and V6 are the rms amplitudes of the second through the
4
2
log20
4
3
V
1
VVVVV
++++
6
5
2
2
2
2
sixth harmonic. The THD is also derived from the FFT plot of
the ADC output spectrum.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation terms are those
for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa − fb), while the
third order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and
(fa − 2fb).
Using the CCIF standard, where two input frequencies near the
top end of the input bandwidth are used, the second and third
order terms are of different significance. The second order
terms are usually distanced in frequency from the original sine
waves while the third order terms are usually at a frequency
close to the input frequencies. As a result, the second and third
order terms are specified separately. The calculation of the
intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual distortion
products to the rms amplitude of the fundamental expressed in
dBs. In this case, the input consists of two, equal amplitude, low
distortion sine waves. Figure 20 shows a typical IMD plot for
the AD7870/AD7875.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to FS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor the peak is a
noise peak.
10.5
EFFECTI VE NUMBER OF BI TS
SAMPLE FREQUENCY = 100kHz
T
= 25°C
A
10.0
0 12.5 18.756.25 25.0 31.25 37.5 43.75 50.0
Figure 19. Effective Number of Bits vs. Frequency
INPUT FREQUENCY (kHz)
07730-019
Rev. C | Page 17 of 28
Page 18
AD7870/AD7875/AD7876
0
–30
–60
–90
SIGNAL AMPL ITUDE (dB)
–120
05
INPUT FREQUENCIES
F1 = 9.05kHz
F2 = 9.55kHz
SAMPLING FREQUENCY = 100kHz
T
= 25°C
A
IMD
ALL TERMS = 90.06dB
SECOND ORDER TERMS = 92.73dB
THIRD ORDER T ERSM = 93.45d B
FREQUENCY (kHz)
Figure 20. IMD Plot
07730-020
0
AC Linearity Plot
When a sine wave of specified frequency is applied to the VIN
input of the AD7870/AD7875 and several million samples are
taken, a histogram showing the frequency of occurrence of each
of the 4096 ADC codes can be generated. From this histogram
data it is possible to generate an ac integral linearity plot as
shown in Figure 21. This shows very good integral linearity
performance from the AD7870/AD7875 at an input frequency
of 25 kHz. The absence of large spikes in the plot shows good
differential linearity. Simplified versions of the formulae used
are outlined below.
V(i), the estimated code transition point, is derived as follows:
()
[ ]
π
CosAiV
×−=
()
icum
×
N
where:
A is the peak signal amplitude.
N is the number of histogram samples.
cum(i) =
–0.25
AC RELATIVE ACCURACY (LSB)
–0.50
∑
0.5
0.25
0
0 511 1023 1535 2047 2559 3071 3583 4095
()
=innV0
occurrences.
INPUT FREQ UENCY = 25kHz
SAMPLE FREQUENCY = 100kHz
T
= 25°C
A
CODE
Figure 21. AC INL Plot
07730-021
⎡
()
()
oViV
⎢
⎢
⎣
−
()
−
()
oVfsV
()
iINL −
= 4096
⎤
×
i
⎥
⎥
⎦
where:
INL(i) is the integral linearity at code i.
V(fs) and V(o) are the estimated full-scale and offset transitions.
V(i) is the estimated transition for the i
th
code.
Rev. C | Page 18 of 28
Page 19
AD7870/AD7875/AD7876
MICROPROCESSOR INTERFACE
The AD7870/AD7875/AD7876 have a wide variety of
interfacing options. They offer two operating modes and
three data-output formats. Fast data access times allow
direct interfacing to most microprocessors including the
DSP processors.
PARALLEL READ INTERFACING
Figure 22, Figure 23, and Figure 24 show interfaces to the
ADSP-2100, TMS32010 and the TMS32020 DSP processors.
The ADC is operating in Mode 1, parallel read for all three
interfaces. An external timer controls conversion start asynchronously to the microprocessor. At the end of each conversion
BUSY
the ADC
conversion result is read from the ADC with the following
instruction:
ADSP-2100: MR0 = DM(ADC)
TMS32010: IN D,ADC
TMS32020: IN D,ADC
MR0 = ADSP-2100 MR0 Register
D = Data Memory Address
ADC = AD7870/AD7875/AD7876 Address
Some applications may require that conversions be initiated by
the microprocessor rather than an external timer. One option
is to decode the
write operation to the ADC starts a conversion. Data is read at
the end of conversion as described earlier. Note: a read
operation must not be attempted during conversion.
1
ADDITIONAL PI NS OMIT TED FOR CL ARITY.
INT
/
interrupts the microprocessor. The
CONVST
DMA13
DMA0
ADSP-2100
IRQn
DMRD
DMD15
DMD0
signal from the address bus so that a
ADDRESS BUS
ADDR
DECODE
ENDMS
DATA BUS
Figure 22. ADSP-2100 Parallel Interface
TIMER
5V
AD7870/
AD7875/
AD7876
CONVST
CS
12/8/CLK
BUSY/INT
RD
DB11
DB0
1
07730-022
PA2
ADDRESS BUS
PA0
TMS32010
ADDR
DECODE
ENMEN
INT
DEN
D15
D0
1
ADDITIONAL PI NS OMIT TED FOR CL ARITY.
Figure 23. TMS32010 Parallel Interface
A15
ADDRESS BUS
A0
TMS32020
ADDR
DECODE
ENIS
INTn
STRB
R/W
D15
D0
1
ADDITIONAL PI NS OMIT TED FOR CL ARITY.
Figure 24. TMS32020 Parallel Interface
TWO-BYTE READ INTERFACING
68008 Interface
Figure 25 shows an 8-bit bus interface for the MC68008 microprocessor. For this interface, the 12/
and the DB11/HBEN pin is driven from the microprocessor
least significant address bit. Conversion start control is provided
by the microprocessor. In this interface example, a Move instruction from the ADC address both starts a conversion and reads
the conversion result.
MOVEW ADC,DO
ADC = AD7870/AD7875/AD7876 address
D0 = 68008 D0 register
TIMER
AD7870/
AD7875/
AD7876
CONVST
CS
5V
12/8/CLK
BUSY/INT
RD
DB11
DB0
DATA BUS
TIMER
AD7870/
AD7875/
AD7876
CONVST
CS
5V
12/8/CLK
BUSY/INT
RD
DB11
DB0
DATA BUS
8
/CLK input is tied to 0 V
1
07730-023
1
07730-024
Rev. C | Page 19 of 28
Page 20
AD7870/AD7875/AD7876
This is a two-byte read instruction. During the first read
operation
BUSY
, in conjunction with CS, forces the microprocessor to WAIT for the ADC conversion. At the end of
conversion the ADC low byte (DB7 – DB0) is loaded into
D15 – D8 of the D0 register and the ADC high byte (DB15 –
DB7) is loaded into Bits D7 – D0 of the D0 register.
The following rotate instruction to the D0 register swaps the
high and low bytes to the correct format.
R0L = 8, D0.
Note that while executing the two-byte read instruction above,
WAIT states are inserted during the first read operation only
and not for the second.
A15
A0
MC68008
DTACK
AS
STRB
R/W
D15
D0
1
ADDITIONAL PI NS OMIT TED FOR CL ARITY.
2
RESISTOR AND CAPACITOR REQUIRED TO G UARANTEE
ADDRESS BUS
A0
HBEN
ADDR
DECODE
EN
2
R
C
DATA BUS
Figure 25. MC68008 Byte Interface
AD7870/
AD7875/
CS
AD7876
BUSY/INT
RD
12/8/CLK
CONVST
DB7
DB0
t
15
1
.
07730-025
SERIAL INTERFACING
Figure 26, Figure 27, Figure 28, and Figure 29 show the
AD7870/AD7875/AD7876 configured for serial interfacing. In
all four interfaces, the ADC is configured for Mode 1 operation.
The interfaces show a timer driving the
this could be generated from a decoded address if required. The
SCLK, SDAT and
SSTRB
are open-drain outputs. If these are
required to drive capacitive loads in excess 35 pF, buffering is
recommended.
DSP56000 Serial Interface
Figure 26 shows a serial interface between the AD7870/AD7875/
AD7876, and the DSP56000. The interface arrangement is
two-wire with the ADC configured for noncontinuous clock
operation (12/
8
/CLK = 0 V). The DSP56000 is configured
for normal mode asynchronous operation with gated clock.
It is also set up for a 16-bit word with SCK and SC1 as inputs
and the FSL control bit set to a 0. In this configuration, the
DSP56000 assumes valid data on the first falling edge of SCK.
Since the ADC provides valid data on this first edge, there is
no need for a strobe or framing pulse for the data. SCLK and
SDATA are gated off when the ADC is not performing a
CONVST
input, but
Rev. C | Page 20 of 28
conversion. During conversion, data is valid on the SDATA
output of the ADC and is clocked into the receive data shift
register of the DSP56000. When this register has received
16 bits of data, it generates an internal interrupt on the
DSP56000 to read the data from the register.
AD7870/
AD7875/
1
AD7876
TIMER
5V
DSP56000
1
ADDITIONAL P INS OMIT TED FOR CL ARITY.
4.7kΩ
SCK
SRD
2kΩ
CONVST
12/8/CLK
SCLK
SDATA
07730-026
Figure 26. DSP56000 Serial Interface
The DSP56000 and AD7870/AD7875/AD7876 can also be
configured for continuous clock operation (12/
8
/CLK = −5 V).
In this case, a strobe pulse is required by the DSP56000 to
indicate when data is valid. The
SSTRB
output of the ADC
is inverted and applied to the SC1 input of the DSP56000 to
provide this strobe pulse. All other conditions and connections
are the same as for gated clock operation.
NEC7720/77230 Serial Interface
A serial interface between the AD7870/AD7875/AD7876 and
the NEC7720 is shown in Figure 27. In the interface shown, the
ADC is configured for continuous clock operation. This can be
changed to a noncontinuous clock by simply tying the 12/
8
/CLK
input of the ADC to 0 V with all other connections remaining
the same. The NEC7720 expects valid data on the rising edge of
its SCK input and therefore an inverter is required on the SCLK
output of the ADC. The NEC7720 is configured for a 16-bit
data word. Once the 16 bits of data have been received by the SI
register of the NEC7720, an internal interrupt is generated to
read the contents of the SI register.
The NEC77230 interface is similar to that just outlined for the
NEC7720. However, the clock input of the NEC77230 is SICLK.
Additionally, no inverter is required between the ADC SCLK
output and this SICLK input since the NEC77230 assumes data
is valid on the falling edge of SICLK.
AD7870/
AD7875/
1
AD7876
TIMER
+5V
µPD7720
1
ADDITIONAL PINS OMIT TED FOR CL ARITY.
4.7kΩ 4.7kΩ
SIEN
SCLK
SI
Figure 27. NEC7720 Serial Interface
2kΩ
CONVST
12/8/CLK
–5V
SSTRB
SCLK
SDATA
07730-027
Page 21
AD7870/AD7875/AD7876
TMS32020 Serial Interface
Figure 28 shows a serial interface between the AD7870/
AD7875/AD7876 and the TMS32020. The AD7870/AD7875/
AD7876 is configured for continuous clock operation. Note
that the ADC will not interface correctly to the TMS32020 if the
ADC is configured for a noncontinuous clock. Data is clocked
into the data receive register (DRR) of the TMS32020 during
conversion. As with the previous interfaces, when a 16-bit word
is received by the TMS32020 it generates an internal interrupt
to read the data from the DRR.
AD7870/
AD7875/
1
AD7876
TIMER
5V
TMS32020
FSR
CLKR
DR
1
ADDITIONAL PINS OMIT TED FOR CL ARITY.
2kΩ
4.7kΩ 4.7kΩ
CONVST
12/8/CLK
–5V
SSTRB
SCLK
SDATA
07730-028
Figure 28. TMS32020 Serial Interface
ADSP-2101/ADSP-2102 Serial Interface
Figure 29 shows a serial interface between the AD7870/
AD7875/AD7876 and the ADSP-2101/ADSP-2102. The ADC
is configured for continuous clock operation. Data is clocked
into the serial port register of the ADSP-2101/ADSP-2102
during conversion. As with the previous interfaces, when a 16bit data word is received by the ADSP-2101/ADSP-2102 an
internal microprocessor interrupt is generated and the data is
read from the serial port register.
TIMER
+5V
ADSP-2101/
ADSP-2102
FSR
CLKR
DR
1
ADDITIONAL PINS OMIT TED FOR CL ARITY.
2kΩ
4.7kΩ 4. 7kΩ
Figure 29. ADSP-2101/ADSP-2102 Serial Interface
STANDALONE OPERATION
The AD7870/AD7875/AD7876 can be used in its Mode 2,
parallel interface mode for standalone operation. In this case,
conversion is initiated with a pulse to the ADC
pulse must be longer than the conversion time of the ADC. The
BUSY
output is used to drive the RD input. Data is latched from
the ADC DB0–DB11 outputs to an external latch on the rising
BUSY
edge of
.
1
t
CS
CS
EN
LATCH
1
t
>
t
+
t
CS
16
2
ADDITIONAL PINS OMITTED FO R CLARITY.
CONVERT
Figure 30. Stand-Alone Operation
BUSY
RD
DB11
DB0
.
CONVST
12/8/CLK
–5V
SSTRB
SCLK
SDATA
AD7870/
AD7875/
AD7876
AD7870/
AD7875/
AD7876
CS
input. This
2
07730-030
1
07730-029
Rev. C | Page 21 of 28
Page 22
AD7870/AD7875/AD7876
APPLICATIONS INFORMATION
Good printed circuit board (PCB) layout is as important as
the overall circuit design itself in achieving high speed analogto-digital performance. The designer has to be conscious of
noise both in the ADC itself and in the preceding analog
circuitry. Switching mode power supplies are not recommended
because the switching spikes feed through to the comparator
causing noisy code transitions. Other causes of concern are
ground loops and digital feedthrough from microprocessors.
These are factors which influence any ADC, and a proper
PCB layout which minimizes these effects is essential for best
performance.
LAYOUT HINTS
Ensure that the layout for the printed circuit board has the
digital and analog signal lines separated as much as possible.
Take care not to run any digital track alongside an analog signal
track. Guard (screen) the analog input with AGND.
Establish a single point analog ground (star ground) separate
from the logic system ground at the AGND pin or as close
as possible to the ADC. Connect all other grounds and the
AD7870/AD7875/AD7876 DGND to this single analog
ground point. Do not connect any other digital grounds to
this analog ground point.
Low impedance analog and digital power supply common
returns are essential to low noise operation of the ADC, so
make the foil width for these tracks as wide as possible. The
use of ground planes minimizes impedance paths and also
guards the analog circuitry from digital noise. The circuit
layout has both analog and digital ground planes which are
kept separated and only joined together at the AD7870/
AD7875/AD7876 AGND pin.
NOISE
Keep the input signal leads to VIN and signal return leads from
AGND as short as possible to minimize input noise coupling.
In applications where this is not possible, use a shielded cable
between the source and the ADC. Reduce the ground circuit
impedance as much as possible since any potential difference
in grounds between the signal source and the ADC appears as
an error voltage in series with the input signal.
Rev. C | Page 22 of 28
Page 23
AD7870/AD7875/AD7876
OUTLINE DIMENSIONS
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
0.210 (5.33)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
MAX
24
1
0.100 (2.54)
BSC
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
13
12
0.280 (7. 11)
0.250 (6.35)
0.240 (6.10)
0.015
(0.38)
MIN
SEATING
PLANE
0.005 (0.13)
MIN
0.060 (1.52)
MAX
0.015 (0.38)
GAUGE
PLANE
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.430 (10.92)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
CONTROLL ING DIMENS IONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF INCH EQ UIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.
CORNER LEADS M AY BE CONFIGURED AS WHOLE O R HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001
071006-A
Figure 31. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
0.005 (0.13)
PIN 1
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
MIN
24
112
CONTROLL ING DIMENS IONS ARE IN I NCHES; MILL IMETER DI MENSIONS
(IN PARENTHESES ) ARE ROUNDED-OF F INCH EQUI VALENTS FOR
REFERENCE ONLY AND ARE NOT APPRO PRIATE FO R USE IN DESIGN.
Figure 32. 24-Lead Ceramic Dual In-Line Package [CERDIP]
0.098 (2.49)
1.280 (32.51) MAX
0.100
(2.54)
BSC
MAX
0.070 (1.78)
0.030 (0.76)
13
0.310 (7.87)
0.220 (5.59)
0.060 (1.52)
0.015 (0.38)
0.150 (3.81)
MIN
SEATING
PLANE
Narrow Body
(Q-24-1)
Dimensions shown in inches and (millimeters)
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
100808-A
Rev. C | Page 23 of 28
Page 24
AD7870/AD7875/AD7876
0.048 (1.22)
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
4
5
11
12
0.456 (11.582)
0.450 (11.430)
0.495 (12.57)
0.485 (12.32)
PIN 1
IDENTIFIER
TOP VIEW
(PINS DOWN)
CONTROLL ING DIMENS IONS ARE IN I NCHES; MILL IMETER DI MENSIONS
(IN PARENTHESES ) ARE ROUNDED-OF F INCH EQUI VALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FO R USE IN DESIGN.
0.056 (1.42)
0.042 (1.07)
26
25
0.050
(1.27)
BSC
19
18
SQ
SQ
COMPLIANT TO JEDEC ST ANDARDS MO-047-AB
0.120 (3.04)
0.090 (2.29)
0.180 (4.57)
0.165 (4.19)
0.020 (0.51)
MIN
0.021 (0.53)
0.013 (0.33)
0.032 (0.81)
0.026 (0.66)
0.045 (1.14)
0.025 (0.64)
0.430 (10.92)
0.390 (9.91)
R
BOTTOM
VIEW
(PINS UP)
042508-A
Figure 33. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28)
Dimensions shown in inches and (millimeters)
15.60 (0.6142)
15.20 (0.5984)
24
1
13
7.60 (0.2992)
7.40 (0.2913)
12
10.65 (0.4193)
10.00 (0.3937)
0.30 (0.0 118)
0.10 (0.0039)
COPLANARIT Y
0.10
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
CONTROLL ING DIMENS IONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.51 (0.0201)
0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
SEATING
PLANE
8°
0°
0.33 (0.0130)
0.20 (0.0079)
Figure 34. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
0
0
.
7
5
.
2
(
0
.
5
(
0
.
0
2
9
5
)
45°
0
9
8
)
0
1.27 (0.0500)
0.40 (0.0157)
060706-A
Rev. C | Page 24 of 28
Page 25
AD7870/AD7875/AD7876
ORDERING GUIDE
Table 7.
V
Voltage Range
Model Temperature Range
IN
(V)
AD7870JN 0°C to +70°C ±3 70 min ±1/2 typ 24-Lead PDIP N-24-1
AD7870JNZ1 0°C to +70°C ±3 70 min ±1/2 typ 24-Lead PDIP N-24-1
AD7870KN 0°C to +70°C ±3 70 min ±1 max 24-Lead PDIP N-24-1
AD7870KNZ
1
0°C to +70°C ±3 70 min ±1 max 24-Lead PDIP N-24-1
AD7870LN 0°C to +70°C ±3 72 min ±1/2 max 24-Lead PDIP N-24-1
AD7870LNZ
1
0°C to +70°C ±3 72 min ±1/2 max 24-Lead PDIP N-24-1
AD7870JP 0°C to +70°C ±3 70 min ±1/2 typ 28-Lead PLCC P-28
AD7870JP-REEL 0°C to +70°C ±3 70 min ±1/2 typ 28-Lead PLCC P-28
AD7870JPZ1 0°C to +70°C ±3 70 min ±1/2 typ 28-Lead PLCC P-28
AD7870JPZ-REEL
1
0°C to +70°C ±3 70 min ±1/2 typ 28-Lead PLCC P-28
AD7870KP 0°C to +70°C ±3 70 min ±1 max 28-Lead PLCC P-28
AD7870KP-REEL 0°C to +70°C ±3 70 min ±1 max 28-Lead PLCC P-28
AD7870KPZ1 0°C to +70°C ±3 70 min ±1 max 28-Lead PLCC P-28
AD7870KPZ-REEL
1
0°C to +70°C ±3 70 min ±1 max 28-Lead PLCC P-28
AD7870LP 0°C to +70°C ±3 72 min ±1/2 max 28-Lead PLCC P-28
AD7870LP-REEL 0°C to +70°C ±3 72 min ±1/2 max 28-Lead PLCC P-28
AD7870LPZ1 0°C to +70°C ±3 72 min ±1/2 max 28-Lead PLCC P-28
AD7870AQ −25°C to +85°C ±3 70 min ±1/2 typ 24-Lead CERDIP Q-24-1
AD7870BQ −25°C to +85°C ±3 70 min ±1 max 24-Lead CERDIP Q-24-1
AD7870CQ −25°C to +85°C ±3 72 min ±1/2 max 24-Lead CERDIP Q-24-1
AD7870TQ −55°C to +125°C ±3 70 min ±1 max 24-Lead CERDIP Q-24-1
AD7875KN 0°C to +70°C 0 to +5 70 min ±1 max 24-Lead PDIP N-24-1
AD7875KNZ1 0°C to +70°C 0 to +5 70 min ±1 max 24-Lead PDIP N-24-1
AD7875LN 0°C to +70°C 0 to +5 72 min ±1/2 max 24-Lead PDIP N-24-1
AD7875LNZ1 0°C to +70°C 0 to +5 72 min ±1/2 max 24-Lead PDIP N-24-1
AD7875KP 0°C to +70°C 0 to +5 70 min ±1 max 28-Lead PLCC P-28
AD7875KPZ1 0°C to +70°C 0 to +5 70 min ±1 max 28-Lead PLCC P-28
AD7875KPZ-REEL1 0°C to +70°C 0 to +5 70 min ±1 max 28-Lead PLCC P-28
AD7875LP-REEL 0°C to +70°C 0 to +5 72 min ±1/2 max 28-Lead PLCC P-28
AD7875LPZ
AD7875LPZ-REEL
1
0°C to +70°C 0 to +5 72 min ±1/2 max 28-Lead PLCC P-28
1
0°C to +70°C 0 to +5 72 min ±1/2 max 28-Lead PLCC P-28
AD7875BQ −40°C to +85°C 0 to +5 70 min ±1 max 24-Lead CERDIP Q-24-1
AD7875CQ −40°C to +85°C 0 to +5 72 min ±1/2 max 24-Lead CERDIP Q-24-1
AD7875TQ −55°C to +125°C 0 to +5 70 min ±1 max 24-Lead CERDIP Q-24-1
AD7876BN −40°C to +85°C ±10 ±1 max 24-Lead PDIP N-24-1
AD7876BNZ1 −40°C to +85°C ±10 ±1 max 24-Lead PDIP N-24-1
AD7876CN −40°C to +85°C ±10 ±1/2 max 24-Lead PDIP N-24-1
AD7876CNZ1 −40°C to +85°C ±10 ±1/2 max 24-Lead PDIP N-24-1
AD7876BR −40°C to +85°C ±10 ±1 max 24-Lead SOIC_W RW-24
AD7876BR-REEL −40°C to +85°C ±10 ±1 max 24-Lead SOIC_W RW-24
AD7876BR-REEL7 −40°C to +85°C ±10 ±1 max 24-Lead SOIC_W RW-24
AD7876BRZ
AD7876BRZ-REEL
AD7876BRZ-REEL7
1
−40°C to +85°C ±10 ±1 max 24-Lead SOIC_W RW-24
1
−40°C to +85°C ±10 ±1 max 24-Lead SOIC_W RW-24
1
−40°C to +85°C ±10 ±1 max 24-Lead SOIC_W RW-24
AD7876CR −40°C to +85°C ±10 ±1/2 max 24-Lead SOIC_W RW-24
AD7876CR-REEL −40°C to +85°C ±10 ±1/2 max 24-Lead SOIC_W RW-24
AD7876CRZ
1
−40°C to +85°C ±10 ±1/2 max 24-Lead SOIC_W RW-24
AD7876BQ −40°C to +85°C ±10 ±1 max 24-Lead CERDIP Q-24-1
AD7876TQ −55°C to +125°C ±10 ±1 max 24-Lead CERDIP Q-24-1
1
Z = RoHS Compliant Part.
SNR
(dBs)
Rev. C | Page 25 of 28
Integral
Nonlinearity (LSB)
Package Description
Package
Option
Page 26
AD7870/AD7875/AD7876
NOTES
Rev. C | Page 26 of 28
Page 27
AD7870/AD7875/AD7876
NOTES
Rev. C | Page 27 of 28
Page 28
AD7870/AD7875/AD7876
NOTES
©1997–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07730-0-2/09( C)
Rev. C | Page 28 of 28
Loading...