Datasheet AD7866 Datasheet (Analog Devices)

Dual 1 MSPS, 12-Bit, 2-Channel

SAR ADC with Serial Interface

AD7866

FEATURES
Dual 12-Bit, 2-Channel ADC
Fast Throughput Rate: 1 MSPS
Specified for V

of 2.7 V to 5.25 V

DD

Low Power

11.4 mW Max at 1 MSPS with 3 V Supplies
24 mW Max at 1 MSPS with 5 V Supplies

Wide Input Bandwidth

70 dB SNR at 300 kHz Input Frequency
On-Board Reference 2.5 V
–40ⴗC to +125ⴗC Operation
Flexible Power/Throughput Rate Management
Simultaneous Conversion/Read
No Pipeline Delays
High Speed Serial Interface SPI

MICROWIRE

TM

/DSP Compatible

TM

/QSPITM/

Shutdown Mode: 1 ␮A Max
20-Lead TSSOP Package

GENERAL DESCRIPTION

The AD7866 is a dual 12-bit high speed, low power, successive
approximation ADC. The part operates from a single 2.7 V to

5.25 V power supply and features throughput rates up to 1 MSPS.
The device contains two ADCs, each preceded by a low noise,
wide bandwidth track-and-hold amplifier that can handle
input frequencies in excess of 10 MHz.

The conversion process and data acquisition are controlled
using standard control inputs, allowing easy interfacing to
microprocessors or DSPs. The input signal is sampled on the
falling edge of CS; conversion is also initiated at this point.
The conversion time is determined by the SCLK frequency.
There are no pipelined delays associated with the part.

The AD7866 uses advanced design techniques to achieve
very low power dissipation at high throughput rates. With 3 V
supplies and 1 MSPS throughput rate, the part consumes a
maximum of 3.8 mA. With 5 V supplies and 1 MSPS, the
current consumption is a maximum of 4.8 mA. The part also
offers flexible power/throughput rate management when
operating in sleep mode.

The analog input range for the part can be selected to be a 0 V
to V

range or a 2 ⫻ V

REF

range with either straight binary or

REF

twos complement output coding. The AD7866 has an on-chip

2.5 V reference that can be overdriven if an external reference
is preferred. Each on-board ADC can also be supplied with a
separate individual external reference.

The AD7866 is available in a 20-lead thin shrink small outline
(TSSOP) package.

FUNCTIONAL BLOCK DIAGRAM

BUF

T/H

T/H

BUF

D

AAV

CAP

REF SELECT

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

D

B

CAP

AD7866

DGND

DDDVDD

OUTPUT

DRIVERS

OUTPUT

DRIVERS

D

OUT

A0
RANGE
SCLK

CS

V

DRIVE

D

OUT

A

B

V

A1

V

A2

V

B1

V

B2

V

REF

2.5V
REF

MUX

MUX

AGND AGND

PRODUCT HIGHLIGHTS

1. The AD7866 features two complete ADC functions, allowing
simultaneous sampling and conversion of two channels. Each
ADC has a 2-channel input multiplexer. The conversion result
of both channels is available simultaneously on separate data
lines, or may be taken on one data line if only one serial port
is available.

2. High Throughput with Low Power Consumption—The
AD7866 offers a 1 MSPS throughput rate with 11.4 mW
maximum power consumption when operating at 3 V.

3. Flexible Power/Throughput Rate Management—The conver­sion rate is determined by the serial clock, allowing the power
consumption to be reduced as the conversion time is reduced
through a SCLK frequency increase. Power efficiency can be
maximized at lower throughput rates if the part enters sleep
during conversions.

4. No Pipeline Delay—The part features two standard successive
approximation ADCs with accurate control of the sampling
instant via a CS input and once off conversion control.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD7866–SPECIFICATIONS

(TA = T
External on D

MIN

to T

, VDD = 2.7 V to 5.25 V, V

MAX

A and D

CAP

CAP

= 2.7 V to 5.25 V, Reference = 2.5 V

B, f

SCLK

DRIVE

= 20 MHz, unless otherwise noted.)

Parameter A Version1B Version1Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to Noise + Distortion (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)

2

2

2

68 68 dB min fIN = 300 kHz Sine Wave, fS = 1 MSPS
–75 –75 dB max f

2

–76 –76 dB max fIN = 300 kHz Sine Wave, fS = 1 MSPS

= 300 kHz Sine Wave, fS = 1 MSPS

IN

Second Order Terms –88 –88 dB typ
Third Order Terms –88 –88 dB typ
Channel-to-Channel Isolation –88 –88 dB typ

SAMPLE AND HOLD

Aperture Delay
Aperture Jitter
Aperture Delay Matching

3

3

3

10 10 ns max
50 50 ps typ
200 200 ps max

Full Power Bandwidth 12 12 MHz typ @ 3 dB

22MHz typ @ 0.1 dB

DC ACCURACY

Resolution 12 12 Bits
Integral Nonlinearity ± 1.5 ± 1 LSB max B Grade, 0 V to V

± 1.5 LSB max 0 V to 2  V

Range Only; ±0.5 LSB typ

REF

Range; ± 0.5 LSB typ

REF

Differential Nonlinearity –0.95/+1.25 –0.95/+1.25 LSB max Guaranteed No Missed Codes to 12 Bits
0 V to V

Input Range Straight Binary Output Coding

REF

Offset Error ± 8 ± 8 LSB max
Offset Error Match ± 1.2 ± 1.2 LSB typ
Gain Error ± 2.5 ± 2.5 LSB max
Gain Error Match ± 0.2 ± 0.2 LSB typ

2  V

Input Range –V

REF

REF

to +V

Biased about V

REF

REF

with
Positive Gain Error ± 2.5 ± 2.5 LSB max Twos Complement Output Coding
Zero Code Error ± 8 ± 8 LSB max
Zero Code Error Match ± 0.2 ± 0.2 LSB typ
Negative Gain Error ± 2.5 ± 2.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

REF

0 to 2  V

DC Leakage Current ± 500 ± 500 nA max T

REF

0 to V

REF

0 to 2  V

V RANGE Pin Low upon CS Falling Edge
V RANGE Pin High upon CS Falling Edge

REF

= –40C to +85C

A

11µA max 85C < TA ≤ 125C

Input Capacitance 30 30 pF typ When in Track

10 10 pF typ When in Hold

REFERENCE INPUT/OUTPUT

Reference Input Voltage 2.5 2.5 V ± 1% for Specified Performance
Reference Input Voltage Range
DC Leakage Current ± 30 ±30 µA max V

Input Capacitance 20 20 pF typ
Reference Output Voltage
V

Output Impedance

REF

4

5

6

2/3 2/3 V min/V max REF SELECT Pin Tied High

Pin

± 160 ± 160 µA max D

REF

CAP

A, D

CAP

B Pins

2.45/2.55 2.45/2.55 V min/V max
25 25 Ω typ VDD = 5 V

45 45 Ω typ VDD = 3 V
Reference Temperature Coefficient 50 50 ppm/°C typ
REF OUT Error (T

MIN

to T

) ± 15 ±15 mV typ

MAX

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

3

0.7 V

0.3 V

DRIVE

DRIVE

0.7 V

0.3 V

DRIVE

DRIVE

V min

V max
± 1 ± 1 µA max Typically 15 nA, V
10 10 pF max

= 0 V or V

IN

DRIVE

LOGIC OUTPUTS

V

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ± 1 ± 1 µA max V
Floating-State Output Capacitance

OH

OL

3

– 0.2 V

DRIVE

0.4 0.4 V max I

10 10 pF max

– 0.2 V min I

DRIVE

= 200 µA

SOURCE

= 200 µA

SINK

= 2.7 V to 5.25 V

DD

Output Coding Straight (Natural) Binary Selectable with Either Input Range

Twos Complement

REV. A–2–

AD7866

Parameter A Version1B Version1Unit Test Conditions/Comments

CONVERSION RATE

Conversion Time 16 16 SCLK cycles 800 ns with SCLK = 20 MHz
Track/Hold Acquisition Time
Throughput Rate 1 1 MSPS max See Serial Interface Section

POWER REQUIREMENTS

V

DD

V

DRIVE

7

I

DD

Normal Mode (Static) 3.1 3.1 mA max VDD = 4.75 V to 5.25 V. Add 0.5 mA

Operational, f

= 1 MSPS 4.8 4.8 mA max VDD = 4.75 V to 5.25 V. Add 0.5 mA

S

Partial Power-Down Mode 1.6 1.6 mA max f

Partial Power-Down Mode 560 560 µA max (Static) Add 100 µA Typical if Using

Full Power-Down Mode 1 1 µA max SCLK On or Off. T

Power Dissipation

7

Normal Mode (Operational) 24 24 mW max VDD = 5 V

Partial Power-Down (Static) 2.8 2.8 mW max V

Full Power-Down (Static) 5 5 µW max V

NOTES

1

Temperature ranges as follows: A, B Versions: –40°C to +125°C.

2

See Terminology section.

3

Sample tested @ 25°C to ensure compliance.

4

External reference range that may be applied at V

5

Relates to pins V

6

See Reference section for D

7

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

REF

, D

CAP

A, or D

CAP

3

B.

CAP

A, D

B output impedances.

CAP

300 300 ns max

2.7/5.25 2.7/5.25 V min/max

2.7/5.25 2.7/5.25 V min/max
Digital I/Ps = 0 V or V

Typical if Using Internal Reference.

2.8 2.8 mA max V

= 2.7 V to 3.6 V. Add 0.35 mA

DD

Typical if Using Internal Reference.

Typical if Using Internal Reference.

3.8 3.8 mA max V

= 2.7 V to 3.6 V. Add 0.5 mA

DD

Typical if Using Internal Reference.

= 100 kSPS, f

S

SCLK

Add 0.2 mA Typ if Using Internal
Reference.

Internal Reference.

22 µA max SCLK On or Off. 85C < T

A

11.4 11.4 mW max V

1.68 1.68 mW max V

= 3 V

DD

= 5 V. SCLK On or Off.

DD

= 3 V. SCLK On or Off.

DD

= 5 V. SCLK On or Off.

DD

33 µW max VDD = 3 V. SCLK On or Off.

, D

REF

CAP

A, or D

CAP

B.

DRIVE

= 20 MHz

= –40C to +85C

≤ 125C

A

REV. A

–3–

AD7866

1

TIMING SPECIFICATIONS

(VDD = 2.7 V to 5.25 V, V

Limit at

Parameter T

2

f

SCLK

MIN

, T

MAX

Unit Description

10 kHz min

20 MHz max

t

CONVERT

t

QUIET

t

2

3

t

3

3

t

4

t

5

t

6

t

7

4

t

8

4

t

9

16  t

SCLK

800 ns max f

ns max t

SCLK

SCLK

50 ns max Minimum Time between End of Serial Read and Next Falling Edge of CS
10 ns min CS to SCLK Setup Time
25 ns max Delay from CS until D

40 ns max Data Access Time after SCLK Falling Edge. V

V

0.4 t

0.4 t

SCLK

SCLK

ns min SCLK Low Pulsewidth
ns min SCLK High Pulsewidth

DRIVE

10 ns min SCLK to Data Valid Hold Time
25 ns max CS Rising Edge to D
10 ns min SCLK Falling Edge to D
50 ns max SCLK Falling Edge to D

NOTES

1

Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of V

2

Mark/Space ratio for the CLK input is 40/60 to 60/40.

3

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.

4

t

are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-

8, t9

lated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times t8 and t9 quoted in the timing characteristics are the true
bus relinquish times of the part and are independent of the bus loading.

Specifications subject to change without notice.

= 2.7 V to 5.25 V, V

DRIVE

= 1/f

SCLK

= 20 MHz

< 3 V, CL = 25 pF

OUT

OUT

A, D

OUT

OUT

A and D

= 2.5 V; TA = T

REF

B Three-State Disabled

OUT

B, High Impedance

OUT

A, D
A, D

B, High Impedance

OUT

B, High Impedance

OUT

) and timed from a voltage level of 1.6 V.

DRIVE

to T

MIN

, unless otherwise noted.)

MAX

3 V, CL = 50 pF;

DRIVE

OUTPUT

PIN

TO

50pF

C

L

200␮AI

200␮A

OL

1.6V

I

OH

Figure 1. Load Circuit for Digital Output Timing Specifications

REV. A–4–

AD7866

ABSOLUTE MAXIMUM RATINGS

(TA = 25oC, unless otherwise noted.)

AV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

to DGND . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

V

DRIVE

to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

V

DRIVE

to DVDD . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

AV

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND . . . . . –0.3 V to AV

Digital Input Voltage to DGND . . . . . . . . . . . . –0.3 V to +7 V

to AGND . . . . . . . . . . . . . . . . . . –0.3 V to AV

V

REF

Digital Output Voltage to DGND . . . –0.3 V to V
Input Current to Any Pin Except Supplies
Operating Temperature Range

Commercial (A, B Versions) . . . . . . . . . . . . . –40C to +125C

1

2

DRIVE

. . . . . . . . . 10 mA

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

Storage Temperature Range . . . . . . . . . . . . –65C to +150C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C

TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW

Thermal Impedance (TSSOP) . . . . . . . . . . . . . 143C/W



JA

Thermal Impedance (TSSOP) . . . . . . . . . . . . . . 45C/W



JC

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kV

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch up.

ORDERING GUIDE

Resolution Package

Model Temperature Range (Bits) Package Description Option

AD7866ARU –40°C to +125°C12Thin Shrink SOC (TSSOP) RU-20
AD7866BRU –40°C to +125°C12Thin Shrink SOC (TSSOP) RU-20
EVAL-AD7866CB
EVAL-CONTROL BRD2

NOTES

1

This can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes.

2

This evaluation board controller is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB design ators.
To order a complete evaluation kit, the particular ADC evaluation board, e.g., EVAL-AD7866CB, the EVAL-CONTROL BRD2, and a 12 V transformer must be
ordered. See relevant Evaluation Board Technical note for more information.

1

2

Evaluation Board
Controller Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7866 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. A

–5–

AD7866

PIN CONFIGURATION

REF SELECT

D

CAP

AGND

V

V

V

V

AGND

D

CAP

V

REF

1

2

B

3

4

B2

5

B1

6

A2

7

A1

8

9

A

10

AD7866

TOP VIEW

(Not to Scale)

20

19

18

17

16

15

14

13

12

11

A0

CS

SCLK

V

DRIVE

D

OUT

D

OUT

DGND

DV

DD

AV

DD

RANGE

B

A

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 REF SELECT Internal/External Reference Selection. Logic input. If this pin is tied to GND, the on-chip 2.5 V reference

is used as the reference source for both ADC A and ADC B. In addition, pins V

REF

, D

A, and D

CAP

CAP

B
must be tied to decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external refer­ence can be supplied to the AD7866 through the V
required on D

A and D

CAP

B. However, if the V

CAP

pin, in which case decoupling capacitors are

REF

pin is tied to AGND while REF SELECT is tied to

REF

a logic low, an individual external reference can be applied to both ADC A and ADC B through pins

2, 9 D

CAP

B, D

A and D

D

CAP

A Decoupling capacitors are connected to these pins to decouple the reference buffer for each respective

CAP

B, respectively. See the Reference Configuration Options section.

CAP

ADC. The on-chip reference can be taken from these pins and applied externally to the rest of a system.
Depending on the polarity of the REF SELECT pin and the configuration of the V

pin, these

REF

pins can also be used to input a separate external reference to each ADC. The range of the external
reference is dependent on the analog input range selected. See the Reference Configuration
Options section.

3, 8 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7866. All analog input signals

and any external reference signal should be referred to this AGND voltage. Both of these pins should
connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the
same potential and must not be more than 0.3 V apart, even on a transient basis.

4, 5 V

6, 7 V

10 V

B2, VB1

A2, VA1

REF

Analog Inputs of ADC B. Single-ended analog input channels. The input range on each channel is 0 V
to V

or a 2  V

REF

range depending on the polarity of the RANGE pin upon the falling edge of CS .

REF

Analog Inputs of ADC A. Single-ended analog input channels. The input range on each channel is 0 V
to V

or a 2  V

REF

range depending on the polarity of the RANGE pin upon the falling edge of CS .

REF

Reference Decoupling and External Reference Selection. This pin is connected to the internal reference
and requires a decoupling capacitor. The nominal reference voltage is 2.5 V, which appears at the pin;
however, if the internal reference is to be used externally in a system, it must be taken from either the

A or D

D

CAP

applying an external ref

B pins. This pin is also used in conjunction with the REF SELECT pin when

CAP

erence to the AD7866. See the REF SELECT pin description.

REV. A–6–

AD7866

PIN FUNCTION DESCRIPTIONS (continued)

Pin No. Mnemonic Function

11 RANGE Analog Input Range and Output Coding Selection. Logic input. The polarity on this pin will

determine what input range the analog input channels on the AD7866 will have, and will also select
the type of output coding the ADC will use for the conversion result. On the falling edge of CS, the
polarity of this pin is checked to determine the analog input range of the next conversion. If this pin
is tied to a logic low, the analog input range is 0 V to V
be straight binary (for the next conversion). If this pin is tied to a logic high when CS goes low, the
analog input range is 2  V

and the output coding for the part will be twos complement. How-

REF

ever, if after the falling edge of CS the logic level of the RANGE pin has changed upon the eighth
SCLK falling edge, the output coding will change to the other option without any change in the
analog input range. (See the Analog Input and ADC Transfer Function sections.)

12 AV

DD

Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the
AD7866. The AV

and DV

DD

voltages ideally should be at the same potential and must not be

DD

more than 0.3 V apart even on a transient basis. This supply should be decoupled to AGND.

13 DV

DD

Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the
AD7866. The DV

and AV

DD

voltages should ideally be at the same potential and must not be

DD

more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND.

14 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7866. The

DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V
apart even on a transient basis.

15, 16 D

OUT

A, D

B Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are

OUT

clocked out on the falling edge of the SCLK input. The data appears on both pins simultaneously
from the simultaneous conversions of both ADCs. The data stream consists of one leading zero
followed by three STATUS bits, followed by the 12 bits of conversion data. The data is provided
MSB first. If CS is held low for another 16 SCLK cycles after the conversion data has been output
on either D

OUT

A or D

B, the data from the other ADC follows on the D

OUT

from a simultaneous conversion on both ADCs to be gathered in serial format on either D

B alone using only one serial port. See the Serial Interface section.

D

OUT

17 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
will operate. This pin should be decoupled to DGND.

18 SCLK Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the

AD7866. This clock is also used as the clock source for the conversion process.

19 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the AD7866 and frames the serial data transfer.

20 A0 Multiplexer Select. Logic input. This input is used to select the pair of channels to be converted

simultaneously, i.e., Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADC B.
The logic state of this pin is checked upon the falling edge of CS, and the multiplexer is set up for
the next conversion. If it is low, the following conversion will be performed on Channel 1 of each ADC;
if it is high, the following conversion will be performed on Channel 2 of each ADC.

and the output coding from the part will

REF

pin. This allows data

OUT

OUT

A or

REV. A

–7–

AD7866

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB above
the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Offset Error

This applies to Straight Binary output coding. It is the deviation
of the first code transition (00 . . . 000) to (00 . . . 001) from the
ideal, i.e., AGND + 1 LSB.

Offset Error Match

This is the difference in Offset Error between the two channels.

Gain Error

This applies to Straight Binary output coding. It is the deviation
of the last code transition (111 . . . 110) to (111 . . . 111) from
the ideal (i.e., V

– 1 LSB) after the offset error has been

REF

adjusted out.

Gain Error Match

This is the difference in Gain Error between the two channels.

Zero Code Error

This applies when using the twos complement output coding
option, in particular with the 2  V

biased about the V

+V

REF

point. It is the deviation of the

REF

midscale transition (all 1s to all 0s) from the ideal V
i.e., V

Zero Code Error Match

– 1 LSB.

REF

input range as –V

REF

REF

voltage,

IN

to

This refers to the difference in Zero Code Error between the
two channels.

Positive Gain Error

This applies when using the twos complement output coding
option, in particular with the 2  V

biased about the V

+V

REF

point. It is the deviation of the last

REF

input range as –V

REF

REF

to

code transition (011 . . . 110) to (011 . . . 111) from the ideal
(i.e., +V

– 1 LSB) after the Zero Code Error has been

REF

adjusted out.

Negative Gain Error

This applies when using the twos complement output coding
option, in particular with the 2  V

biased about the V

+V

REF

point. It is the deviation of the first

REF

input range as –V

REF

REF

to

code transition (100 . . . 000) to (100 . . . 001) from the ideal
(i.e., –V

+ 1 LSB) after the Zero Code Error has been

REF

adjusted out.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns into track mode after the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.

Signal-to-(Noise + Distortion) Ratio (SNDR)

This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the sum of all nonfundamental sig­nals up to half the sampling frequency (f

/2), excluding dc. The

S

ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza­tion noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion (THD)

Total harmonic distortion is the ratio of the rms sum of har­monics to the fundamental. For the AD7866, it is defined as:

2

THD db

()

VVVVV

++++

=

20

223242526

log

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,

V4, V5, and V6 are the rms amplitudes of the second through the

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic, or spurious noise, is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f

/2 and excluding dc) to the rms value of the

S

fundamental. Normally, the value of this specification is deter­mined by the largest harmonic in the spectrum. But for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities will create distortion products
at sum and difference frequencies of mfa ± nfb where m, n = 0,
1, 2, 3, and so on. Intermodulation distortion terms are those for
which neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).

The AD7866 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa­rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dB.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale
(2  V

), 455 kHz sine wave signal to all unselected input

REF

channels and determining how much that signal is attenuated in the
selected channel with a 10 kHz signal (0 V to V

). The figure

REF

given is the worst-case across all four channels for the AD7866.

PSR (Power Supply Rejection)

See the Performance Curves section.

REV. A–8–

AD7866

AVDD RIPPLE FREQUENCY – Hz

0

–100

1k

PSRR – dB

10k

–90

–80

–70

–60

–50

–40

–30

–20

–10

100k 1M

100mV p-p SINE WAVE ON AV

DD

2.5V EXT REFERENCE ON V

REF

TA = 25ⴗC

VDD = 2.7V

VDD = 5.25V

VDD = 4.75V

VDD = 3.6V

PERFORMANCE CURVES

TPC 1 shows a typical FFT plot for the AD7866 at 1 MHz
sample rate and 300 kHz input frequency. TPC 2 shows the
signal-to-(noise + distortion) ratio performance versus input
frequency for various supply voltages while sampling at 1 MSPS
with an SCLK of 20 MHz.

TPCs 3a to 4b show the power supply rejection ratio versus
AV

supply ripple frequency for the AD7866 under different

DD

conditions. The power supply rejection ratio (PSRR) is defined
as the ratio of the power in the ADC output at full-scale fre­quency f, to the power of a 100 mV sine wave applied to the
ADC AV

supply of frequency fS:

DD

PSRR dB Pf Pf

()=()

10 log

S

Typical Performance Characteristics

0

4098 POINT FFT

f

= 1MSPS

SAMPLE

–15

f

= 300kHz

IN

SNR = 70.31dB
THD = –85.47dB
SFDR = –86.64dB

–35

Pf = power at frequency f in ADC output, and PfS = power at
frequency f
peak-to-peak sine wave is coupled onto the AV

coupled onto the ADC AVDD supply. Here, a 100 mV

S

supply while the

DD

digital supply is left unaltered. TPCs 3a and 3b show the PSRR
of the AD7866 when there is no decoupling on the supply, while
TPCs 4a and 4b show the PSRR with decoupling capacitors
of 10 µF and 0.1 µF on the supply.

TPCs 5 and 6 show typical DNL and INL plots for the AD7866.

TPC 7 shows a graph of the total harmonic distortion versus
analog input frequency for various source impedances.

TPC 8 shows a graph of total harmonic distortion versus analog
input frequency for various supply voltages. See the Analog
Input section.

REV. A

–55

SNR – dB

–75

–95

–115

0 500100

50 150 250 350 450

TPC 1. Dynamic Performance

–61

TA = 25 C

–63

–65

–67

–69

SINAD – dB

–71

–73

–75

VDD = V

10k 1M100k

INPUT FREQUENCY – Hz

TPC 2. SINAD vs. Input Frequency

200 300 400

FREQUENCY – kHz

VDD = V

DRIVE

DRIVE

VDD = V

= 4.75V

DRIVE

VDD = V

= 3.6V

= 2.7V

DRIVE

= 5.25V

–9–

TPC 3a. PSRR vs. Supply Ripple Frequency,
without Supply Decoupling

0

100mV p-p SINE WAVE ON AV

–10

2.5V EXT REFERENCE ON D
T

= 25ⴗC

A

–20

–30

–40

–50

–60

–70

–80

–90

VDD = 2.7V

VDD = 4.75V

1k

PSRR – dB

–100

VDD = 5.25V

VDD = 3.6V

10k

AVDD RIPPLE FREQUENCY – Hz

DD

A, D

CAP

B

CAP

100k 1M

TPC 3b. PSRR vs. Supply Ripple Frequency,
without Supply Decoupling

AD7866

0

100mV p-p SINE WAVE ON AV

–10

2.5V EXT REFERENCE ON V
TA = 25ⴗC

–20

–30

–40

–50

PSRR – dB

–60

VDD = 2.7V

–70

–80

VDD = 3.6V

–90

–100

1k

10k

AVDD RIPPLE FREQUENCY – Hz

DD

REF

100k 1M

TPC 4a. PSRR vs. Supply Ripple Frequency,
with Supply Decoupling

0

100mV p-p SINE WAVE ON AV

–10

2.5V EXT REFERENCE ON D
T

= 25ⴗC

A

–20

–30

–40

–50

VDD = 2.7V

PSRR – dB

–60

–70

–80

–90

VDD = 4.75V

–100

1k

VDD = 3.6V

10k

AVDD RIPPLE FREQUENCY – Hz

DD

A, D

CAP

B

CAP

100k 1M

TPC 4b. PSRR vs. Supply Ripple Frequency,
with Supply Decoupling

1.0

0.8

0.6

0.4

0.2

0.0

INL – LSB

–0.2

–0.4

–0.6

–0.8

–1.0

0

500 1000 1500 2000 2500 3000 3500 4000

ADC – Code

TPC 6. DC INL Plot

–60

TA = 25ⴗC

= 4.75V

V

DD

–65

–70

–75

THD – dB

–80

–85

–90

10k

100k 1000k

INPUT FREQUENCY – Hz

TPC 7. THD vs. Analog Input Frequency
for Various Source Impedances

RIN = 100⍀

RIN = 50⍀

RIN = 10⍀

1.0

0.8

0.6

0.4

0.2

0

DNL – LSB

–0.2

–0.4

–0.6

–0.8

–1.0

0

500 1000 1500 2000 2500 3000 3500 4000

ADC – Code

TPC 5. DC DNL Plot

–70

–72

–74

–76

–78

–80

THD – dB

–82

–84

–86

–88

–90

10k

TA = 25ⴗC

VDD = V

= 4.75V

DRIVE

INPUT FREQUENCY – Hz

VDD = V

VDD = V

DRIVE

VDD = V

100k 1000k

DRIVE

= 3.6V

DRIVE

= 2.7V

= 5.25V

TPC 8. THD vs. Analog Input Frequency
for Various Supply Voltages

REV. A–10–

AD7866

CIRCUIT INFORMATION

The AD7866 is a fast, micropower, dual 12-bit, single supply,
A/D converter that operates from a 2.7 V to 5.25 V supply.
When operated from either a 5 V supply or a 3 V supply, the
AD7866 is capable of throughput rates of 1 MSPS when provided
with a 20 MHz clock.

The AD7866 contains two on-chip track-and-hold amplifiers,
two successive approximation A/D converters, and a serial inter­face with two separate data output pins, and is housed in a
20-lead TSSOP package, which offers the user considerable
space-saving advantages over alternative solutions. The serial
clock input accesses data from the part but also provides the
clock source for each successive approximation ADC. The ana­log input range for the part can be selected to be a 0 V to V
input or a 2  V

input with either straight binary or twos

REF

REF

complement output coding. The AD7866 has an on-chip 2.5 V
reference that can be overdriven if an external reference is pre­ferred. In addition, each ADC can be supplied with an individual
separate external reference.

The AD7866 also features power-down options to allow power
saving between conversions. The power-down feature is imple­mented across the standard serial interface, as described in the
Modes of Operation section.

CONVERTER OPERATION

The AD7866 has two successive approximation analog-to-digital
converters, each based around a capacitive DAC. Figures 2 and
3 show simplified schematics of one of these ADCs. The ADC
is comprised of control logic, a SAR, and a capacitive DAC, all
of which are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition. Figure 2 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in position A, the comparator
is held in a balanced condition, and the sampling capacitor
acquires the signal on V

A

V

IN

SW1

B

AGND

, for example.

A1

SW2

COMPARATOR

CAPACITIVE

DAC

CONTROL

LOGIC

Figure 2. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 3), SW2 will
open and SW1 will move to position B, causing the comparator
to become unbalanced. The Control Logic and the capacitive
DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the ADC
output code. Figures 10 and 11 show the ADC transfer functions.

CAPACITIVE

DAC

A

V

AGND

IN

SW1

B

SW2

COMPARATOR

CONTROL

LOGIC

Figure 3. ADC Conversion Phase

ANALOG INPUT

Figure 4 shows an equivalent circuit of the analog input structure
of the AD7866. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by more
than 300 mV. This will cause these diodes to become forward­biased and start conducting current into the substrate. 10 mA is
the maximum current these diodes can conduct without causing
irreversible damage to the part. The capacitor C1 in Figure 4 is
typically about 10 pF and can primarily be attributed to pin
capacitance. The resistor R1 is a lumped component made up
of the on resistance of a switch. This resistor is typically about
100 Ω. The capacitor C2 is the ADC sampling capacitor and
has a capacitance of 20 pF typically. For ac applications, removing
high frequency components from the analog input signal is
recommended by use of an RC low-pass filter on the relevant
analog input pin. In applications where harmonic distortion and
signal-to-noise ratio are critical, the analog input should be driven
from a low impedance source. Large source impedances will
significantly affect the ac performance of the ADC. This may
necessitate the use of an input buffer amplifier. The choice of the
op amp will be a function of the particular application.

V

DD

D1

V

IN

C1

D2

CONVERT PHASE – SWITCH OPEN
TRACK PHASE – SWITCH CLOSED

C2

R1

Figure 4. Equivalent Analog Input Circuit

When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of total harmonic
distortion (THD) that can be tolerated. The THD will increase
as the source impedance increases, and performance will degrade
(see TPC 7).

REV. A

–11–

AD7866

Analog Input Ranges

The analog input range for the AD7866 can be selected to be 0 V
to V

or 2  V

REF

with either straight binary or twos complement

REF

output coding. The RANGE pin is used to select both the analog
input range and the output coding, as shown in Figures 5 to 8.
On the falling edge of CS, point A, the logic level of the RANGE
pin is checked to determine the analog input range of the next
conversion. If this pin is tied to a logic low, the analog input
range will be 0 V to V

and the output coding from the part will

REF

be straight binary (for the next conversion). If this pin is at a logic
high when CS goes low, the analog input range will be 2  V

REF

and

the output coding for the part will be twos complement. How­ever, if after the falling edge of CS, the logic level of the
RANGE pin has changed upon the eighth falling SCLK edge,
point B, the output coding will change to the other option without
any change in the analog input range. So for the next conversion,
twos complement output coding could be selected with a 0 V to

input range, for example, if the RANGE pin is low upon

V

REF

the falling edge of CS and high upon the eighth falling SCLK
edge, as shown in Figure 7. Figures 5 to 8 show examples of
timing diagrams for selections of different analog input ranges
with various output coding formats. Table I summarizes the
required logic level of the RANGE pin for each selection. Note

Table I. Analog Input and Output Coding Selection

Range Level Range Level
@ Point A

1

@ Point B

2

Input Range

Low Low 0 V to V

High High V

Low High V

High Low 0 V to 2  V

NOTES

1

Point A = Falling edge of CS.

2

Point B = Eighth falling edge of SCLK.

3

Selected for next conversion.

AB

CS

1816 161

SCLK

that the analog input range selected must not exceed VDD. The
logic input A0 is used to select the pair of channels to be converted
simultaneously. The logic state of this pin is also checked upon
the falling edge of CS, and the multiplexers are set up for the
next conversion. If it is low, the following conversion will be
performed on Channel 1 of each ADC; if it is high, the following
conversion will be performed on Channel 2 of each ADC.

Handling Bipolar Input Signals

Figure 9 shows how useful the combination of the 2  V

REF

input range and the twos complement output coding scheme is
for handling bipolar input signals. If the bipolar input signal
is biased about V
selected, then V
negative full-scale, and +V
dynamic range of 2  V

and twos complement output coding is

REF

becomes the zero code point, –V

REF

becomes positive full-scale with a

REF

.

REF

REF

is

Transfer Functions

The designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is V

REF

/4096.
The ideal transfer characteristic for the AD7866 when straight
binary coding is selected is shown in Figure 10, and the ideal
transfer characteristic for the AD7866 when twos complement
coding is selected is shown in Figure 11.

REF

REF

REF

± V

/2 ± V

0V TO V

INPUT RANGE

3

Output Coding

Straight Binary

REF

REF

REF

Twos Complement

/2 Twos Complement

Straight Binary

REF

3

RANGE

D

A

OUT

D

B

OUT

Figure 5. Selecting 0 V to V

AB

CS

1816 161

SCLK

RANGE

D

A

OUT

D

B

OUT

Figure 6. Selecting V

REF

± V

STRAIGHT BINARY

Input Range with Straight Binary Output Coding

REF

ⴞ V

V

REF

REF

INPUT RANGE

TWOS COMPLEMENT

Input Range with Twos Complement Output Coding

REF

REV. A–12–

AB

CS

1816 161

SCLK

RANGE

D

A

OUT

D

B

OUT

Figure 7. Selecting V

CS

SCLK

RANGE

D

A

OUT

D

B

OUT

/2 ± V

REF

AB

1816 161

Figure 8. Selecting 0 V to 2  V

/2 ⴞ V

V

REF

INPUT RANGE

/2 Input Range with Twos Complement Output Coding

REF

0V TO 2 ⴛ V

INPUT RANGE

Input Range with Straight Binary Output Coding

REF

REF

/2

TWOS COMPLEMENT

REF

STRAIGHT BINARY

AD7866

V

0V

V

R1 = R2 = R3 = R4

Figure 9. Handling Bipolar Signals with the AD7866

111...111

111...110

111...000

011...111

ADC CODE

000...010

000...001

000...000
1LSB

0V

ANALOG INPUT

1LSB = V

V

REF

Figure 10. Straight Binary Transfer
Characteristic with 0 V to V

Input Range

REF

REF

– 1LSB

R3

R2

/4096

100nF

R4

V

REF

REF SELECT

V

REF

D

A

CAP

470nF

R1

470nF

D

CAP

AD7866

V

IN

+V

REF

V

REF

–V

REF

V

DRIVE

B

TWOS

COMPLEMENT

D

OUT

(= 2 ⴛ V

(= 0V)

)

REF

011...111

011...110

000...001

000...000

111...111

ADC CODE

100...010

100...001

100...000

011

000

100

REF

V

V

DSP/␮P

111

000

000

1LSB = 2 ⴛ V

+ 1LSB

V

REF

ANALOG INPUT

DD

DD

REF

– 1LSB

/4096

+V

REF

– 1LSB–V

Figure 11. Twos Complement Transfer

± V

Characteristic with V

REF

Input Range

REF

REV. A

–13–

AD7866

D

CAP

B

D

CAP

A

V

REF

470nF

AD7866

470nF

100nF

D

CAP

B

D

CAP

A

V

REF

AD7866

V

REF

REF SELECT

D

CAP

B

D

CAP

A

V

REF

470nF

AD7866

470nF

V

REF

REF SELECT

V

DRIVE

Digital Inputs

The digital inputs applied to the AD7866 are not limited by the
maximum ratings that limit the analog inputs. Instead, the digital
inputs applied can go to 7 V and are not restricted by the V

0.3 V limit as on the analog inputs. See maximum ratings.

Another advantage of SCLK, RANGE, REF SELECT, A0, and
CS not being restricted by the V

+ 0.3 V limit is that power

DD

supply sequencing issues are avoided. If one of these digital inputs
is applied before V

, there is no risk of latch-up, as there

DD

would be on the analog inputs if a signal greater than 0.3 V were
applied prior to V

V

DRIVE

The AD7866 also has the V
voltage at which the serial interface operates. V

DD

.

feature, which controls the

DRIVE

DRIVE

allows the
ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7866 was operated with a V

pin could be powered from a 3 V supply, allowing a large

V

DRIVE

of 5 V, the

DD

dynamic range with low voltage digital processors. For example,
the AD7866 could be used with the 2  V

of 5 V while still being able to interface to 3 V digital parts.

V

DD

input range, with a

REF

REFERENCE CONFIGURATION OPTIONS

The AD7866 has various reference configuration options. The
REF SELECT pin allows the choice of using an internal 2.5 V
reference or applying an external reference, or even an individual
external reference for each on-chip ADC if desired. If the REF
SELECT pin is tied to AGND, then the on-chip 2.5 V reference
is used as the reference source for both ADC A and ADC B. In
addition, pins V

REF

A, and D

CAP

B must be tied to decoupling

CAP

, D
capacitors (100 nF, 470 nF, and 470 nF recommended,
respectively). If the REF SELECT pin is tied to a logic high, an
external reference can be supplied to the AD7866 through the

pin to overdrive the on-chip reference, in which case

V

REF

decoupling capacitors are required on D
However, if the V

pin is tied to AGND while REF SELECT

REF

A and D

CAP

CAP

is tied to a logic low, an individual external reference can be
applied to both ADC A and ADC B through pins D

B, respectively. Table II summarizes these reference options.

D

CAP

CAP

For specified performance, the last configuration was used with
the same reference voltage applied to both D

A and D

CAP

The connections for the relevant reference pins are shown in the
typical connection diagrams. If the internal reference is being
used, the V
AGND very close to the V

pin should have a 100 nF capacitor connected to

REF

pin. These connections are shown

REF

in Figure 12.

Table II. Reference Selection

Reference Option REF SELECT V

Internal Low Decoupling Capacitor Decoupling Capacitor
Externally through V

High External Reference Decoupling Capacitor

REF

Externally through

A and/or D

D

CAP

NOTES

1

Recommended value of decoupling capacitor = 100 nF.

2

Recommended value of decoupling capacitor = 470 nF.

B Low AGND External Reference A and/or

CAP

DD

B again.

A and

B.

CAP

+

REF

Figure 12. Relevant Connections when Using an
Internal Reference

Figure 13. Relevant Connections when Applying
an External Reference at D

A and/or D

CAP

CAP

B

Figure 14. Relevant Connections when Applying
an External Reference at V

REF

Figure 13 shows the connections required when an external
reference is applied to D

A and D

CAP

B. In this example, the

CAP

same reference voltage is applied at each pin; however, a different
voltage may be applied at each of these pins for each on-chip
ADC. An external reference applied at these pins may have a
range from 2 V to 3 V, but for specified performance it must be
within ± 1% of 2.5 V. Figure 14 shows the third option, which is
to overdrive the internal reference through the V
possible due to the series resistance from the V

pin. This is

REF

pin to the

REF

internal reference. This external reference can have a range from
2 V to 3 V; but again, to get as close as possible to the specified
performance, a 2.5 V reference is desirable. D

A and D

CAP

CAP

B

decouple each on-chip reference buffer, as shown in Figure 15.

1

D

A and D

CAP

CAP

2

B

Reference B

REV. A–14–

AD7866

EXT REF

100nF

2.5V
REF

REF

D

BUF A

BUF B

D

AV

CAP

B

CAP

EXT REF

EXT REF

470nF

ADC A

ADC B

470nF

Figure 15. Reference Circuit

If the on-chip 2.5 V reference is being used, and is to be applied
externally to the rest of the system, it may be taken from either
the V

pin or one of the D

REF

from the V

pin, it must be buffered before being applied

REF

CAP

A or D

B pins. If it is taken

CAP

elsewhere as it will not be capable of sourcing more than a few
microamps. If the reference voltage is taken from either the
D

CAP

A pin or D

B pin, a buffer is not strictly necessary. Either

CAP

pin is capable of sourcing current in the region of 100 µA; how-
ever, the larger the source current requirement, the greater the
voltage drop seen at the pin. The output impedance of each of
these pins is typically 50 Ω. In addition, this point represents
the actual voltage applied to the ADC internally so any voltage
drop due to the current load or disturbance due to a dynamic
load will directly affect the ADC conversion. For this reason, if a
large current source is necessary or a dynamic load is present, it
is recommended to use a buffer on the output to drive a device.

Examples of suitable external reference devices that may be ap­plied at pins V

REF

CAP

A, or D

B are the AD780, REF192,

CAP

, D

REF43, and AD1582.

MODES OF OPERATION

The mode of operation of the AD7866 is selected by controlling
the (logic) state of the CS signal during a conversion. There
are three possible modes of operation: normal mode, partial
power-down mode, and full power-down mode. The point at
which CS is pulled high after the conversion has been initiated
will determine which power-down mode, if any, the device will
enter. Similarly, if already in a power-down mode, CS can
control whether the device will return to normal operation or
remain in power-down. These modes of operation are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for differing application requirements.

Normal Mode

This mode is intended for fastest throughput rate performance
since the user does not have to worry about any power-up times
with the AD7866 remaining fully powered all the time. Figure 16
shows the general diagram of the operation of the AD7866 in
this mode.

The conversion is initiated on the falling edge of CS, as described
in the Serial Interface section. To ensure that the part remains
fully powered up at all times, CS must remain low until at least
10 SCLK falling edges have elapsed after the falling edge of CS.
If CS is brought high any time after the 10th SCLK falling edge,
but before the 16th SCLK falling edge, the part will remain
powered up but the conversion will be terminated and D
and D

B will go back into three-state. Sixteen serial clock

OUT

OUT

A

cycles are required to complete the conversion and access the
conversion result. The D

line will not return to three-state

OUT

after 16 SCLK cycles have elapsed, but instead when CS is
brought high again. If CS is left low for another 16 SCLK cycles,
the result from the other ADC on board will also be accessed on
the same D

line, as shown in Figure 22 (see also the Serial

OUT

Interface section). The STATUS bits provided prior to each
conversion result will identify which ADC the following result
will be from. Once 32 SCLK cycles have elapsed, the D

OUT

line

will return to three-state on the 32nd SCLK falling edge. If CS is
brought high prior to this, the D

line will return to three-state

OUT

at that point. Thus, CS may idle low after 32 SCLK cycles, until
it is brought high again sometime prior to the next conversion
(effectively idling CS low), if so desired, since the bus will still
return to three-state upon completion of the dual result read.

Once a data transfer is complete and D

A and D

OUT

OUT

B have
returned to three-state, another conversion can be initiated after
the quiet time, t

, has elapsed by bringing CS low again.

QUIET

Partial Power-Down Mode

This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then powered
down for a relatively long duration between these bursts of several
conversions. When the AD7866 is in partial power-down, all
analog circuitry is powered down except for the on-chip reference
and reference buffer.

To enter partial power-down, the conversion process must be
interrupted by bringing CS high anywhere after the second
falling edge of SCLK and before the tenth falling edge of SCLK
as shown in Figure 17. Once CS has been brought high in this
window of SCLKs, the part will enter partial power-down, the
conversion that was initiated by the falling edge of CS will be

REV. A

SCLK

D

OUT

D

OUT

CS

1

A

B

STATUS BITS AND CONVERSION RESULT

10

16

Figure 16. Normal Mode Operation

–15–

AD7866

terminated, and D

A and D

OUT

B will go back into three-

OUT

state. If CS is brought high before the second SCLK falling
edge, the part will remain in normal mode and will not power
down. This will avoid accidental power-down due to glitches on
the CS line.

To exit this mode of operation and power up the AD7866 again,
a dummy conversion is performed. On the falling edge of CS,
the device will begin to power up, and will continue to power up
as long as CS is held low until after the falling edge of the tenth
SCLK. In the case of an external reference, the device will be
fully powered up once 16 SCLKs have elapsed, and valid data
will result from the next conversion, as shown in Figure 18. If
CS is brought high before the second falling edge of SCLK, the
AD7866 will again go into partial power-down. This avoids
accidental power-up due to glitches on the CS line; although the
device may begin to power up on the falling edge of CS, it will
power down again on the rising edge of CS. If the AD7866 is
already in partial power-down mode and CS is brought high
between the second and tenth falling edges of SCLK, the device
will enter full power-down mode. For more information on the
power-up times associated with partial power-down in various
configurations, see the Power-Up Times section.

Full Power-Down Mode

This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are required,
as power-up from a full power-down takes substantially longer
than that from partial power-down. This mode is more suited to
applications where a series of conversions performed at a rela­tively high throughput rate would be followed by a long period
of inactivity and thus power-down. When the AD7866 is in full
power-down, all analog circuitry is powered down. Full power­down is entered in a similar way as partial power-down, except
the timing sequence shown in Figure 17 must be executed twice.
The conversion process must be interrupted in a similar fashion
by bringing CS high anywhere after the second falling edge of
SCLK and before the tenth falling edge of SCLK. The device
will enter partial power-down at this point. To reach full
power-down, the next conversion cycle must be interrupted in
the same way, as shown in Figure 19. Once CS has been
brought high in this window of SCLKs, the part will power
down completely.

Note that it is not necessary to complete the 16 SCLKs once
CS has been brought high to enter a power-down mode.

To exit full power-down and power the AD7866 up again, a
dummy conversion is performed, as when powering up from
partial power-down. On the falling edge of CS, the device will
begin to power up and will continue to power up as long as CS
is held low until after the falling edge of the tenth SCLK. The
power-up time required must elapse before a conversion can be
initiated, as shown in Figure 20. See the Power-Up Times sec­tion for the power-up times associated with the AD7866.

POWER-UP TIMES

The AD7866 has two power-down modes, partial power-down
and full power-down, which are described in detail in the Modes
of Operation section. This section deals with the power-up time
required when coming out of either of these modes. It should be
noted that the power-up times quoted apply with the recommended

, D

capacitors on the V

REF

A, and D

CAP

B pins in place.

CAP

To power up from full power-down, approximately 4 ms should
be allowed from the falling edge of CS, shown in Figure 20 as
t

POWER UP

. Powering up from partial power-down requires much
less time. If the internal reference is being used, the power-up
time is typically 4 µs; but if an external reference is being used,
the power-up time is typically 1 µs. This means that with any
frequency of SCLK up to 20 MHz, one dummy cycle will always
be sufficient to allow the device to power up from partial power­down when using an external reference (see Figure 18). Once
the dummy cycle is complete, the ADC will be fully powered up
and the input signal will be acquired properly. A dummy cycle
may well be sufficient to power up the part when using an internal
reference also, provided the SCLK is slow enough to allow the
required power-up time to elapse before a valid conversion is
requested. In addition, it should be ensured that the quiet time,

, has still been allowed from the point where the bus goes

t

QUIET

back into three-state after the dummy conversion to the next
falling edge of CS. Alternatively, instead of slowing the SCLK to
make the dummy cycle long enough, the CS high time could
just be extended to include the required power-up time (as in
Figure 20) when powering up from full power-down.

Different power-up time is needed when coming out of partial
power-down for two cases where an internal or external refer­ence is being used, primarily because of the on-chip reference
buffers. They power down in partial power-down mode and must
be powered up again if the internal reference is being used,
but they do not need to be powered up again if an external
reference is being used. The time needed to power up these
buffers is not just their own power-up time but also the time
required to charge up the decoupling capacitors present on pins

, D

V

REF

A, and D

CAP

CAP

B.

It should also be noted that during power-up from partial
power-down, the track-and-hold, which was in hold mode while
the part was powered down, returns to track mode after the first
SCLK edge the part receives after the falling edge of CS. This is
shown as point A in Figure 18.

When power supplies are first applied to the AD7866, the ADC
may power up in either of the power-down modes or the normal
mode. Because of this, it is best to allow a dummy cycle to elapse
to ensure that the part is fully powered up before attempting a
valid conversion. Likewise, if the part is to be kept in the partial
power-down mode immediately after the supplies are applied,
two dummy cycles must be initiated. The first dummy cycle must
hold CS low until after the tenth SCLK falling edge (see Figure 16);
in the second cycle, CS must be brought high before the tenth
SCLK edge but after the second SCLK falling edge (see Figure 17).
Alternatively, if the part is to be placed in full power-down
mode when the supplies have been applied, three dummy cycles
must be initiated. The first dummy cycle must hold CS low
until after the tenth SCLK falling edge (see Figure 16); the sec­ond and third dummy cycles place the part in full power-down
(see Figure 19). See also the Modes of Operation section.

Once supplies are applied to the AD7866, enough time must be
allowed for any external reference to power up and charge any
reference capacitor to its final value, or enough time must be
allowed for the internal reference buffer to charge the various
reference buffer decoupling capacitors to their final values.

REV. A–16–

AD7866

Then, to place the AD7866 in normal mode, a dummy cycle
(1 µs to 4 µs approximately) should be initiated. If the first valid
conversion is performed directly after the dummy conversion,
care must be taken to ensure that adequate acquisition time has
been allowed. As mentioned earlier, when powering up from the
power-down mode, the part will return to track upon the first
SCLK edge applied after the falling edge of CS. However when
the ADC initially powers up after supplies are applied, the
track-and-hold will already be in track. This means that (assuming

CS

1

SCLK

D

A

OUT

B

D

OUT

Figure 17. Entering Partial Power-Down Mode

THE PART MAY BE FULLY

THE PART BEGINS

CS

TO POWER UP

POWERED UP; SEE POWER-UP

TIMES SECTION

one has the facility to monitor the ADC supply current and thus
determine which mode the AD7866 is in) if the ADC powers up
in the desired mode of operation and thus a dummy cycle is not
required to change mode, then neither is a dummy cycle required
to place the track-and-hold into track. If no current monitoring
facility is available, the relevant dummy cycle(s) should be
performed to ensure the part is in the required mode.

102

THREE-STATE

16

SCLK

D

D

SCLK

D

OUT

D

OUT

OUT

OUT

CS

A

B

A

B

CS

1

A

INVALID DATA VALID DATA

10

16

116

Figure 18. Exiting Partial Power-Down Mode

THE PART ENTERS

PARTIAL POWER-DOWN

116

2

INVALID DATA INVALID DATA

10

THREE-STATE THREE-STATE

THE PART BEGINS

TO POWER UP

116

2

THE PART ENTERS

FULL POWER-DOWN

Figure 19. Entering Full Power-Down Mode

THE PART BEGINS

TO POWER UP

t

POWER UP

THE PART IS

FULLY POWERED UP

10

SCLK

D

OUT

D

OUT

REV. A

1

A

B

INVALID DATA VALID DATA

10

16

116

Figure 20. Exiting Full Power-Down Mode

–17–

AD7866

POWER VS. THROUGHPUT RATE

When the AD7866 is in partial power-down mode and not
converting, the average power consumption of the ADC decreases
at lower throughput rates. Figure 21 shows that as the through­put rate is reduced, the part remains in its partial power-down
state longer, and the average power consumption over time
drops accordingly.

100

VDD = 5V

10

1

POWER – mW

0.1

0.01
0

SCLK = 20MHz

50 100

VDD = 3V

SCLK = 20MHz

150 200 250 300 350

THROUGHPUT – kSPS

Figure 21. Power vs. Throughput for Partial Power-Down

For example, if the AD7866 is operated in a continuous sampling
mode with a throughput rate of 100 kSPS and an SCLK of
20 MHz (V

= 5 V), and the device is placed in partial power-

DD

down mode between conversions, the power consumption is
calculated as follows. The maximum power dissipation during
normal operation is 24 mW (V

= 5 V). If the power-up time

DD

allowed from partial power-down is one dummy cycle, i.e., 1 µs,
(assuming use of an external reference) and the remaining
conversion time is another cycle, i.e., 1 µs, then the AD7866

can be said to dissipate 24 mW for 2 µs during each conversion
cycle. For the remainder of the conversion cycle, 8 µs, the part
remains in partial power-down mode. The AD7866 can be said to
dissipate 2.8 mW for the remaining 8 µs of the conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10 µs and the
average power dissipated during each cycle is (2/10)  (24 mW) +
(8/10)  (2.8 mW) = 7.04 mW. If V

= 3 V, SCLK = 20 MHz,

DD

and the device is again in partial power-down mode between
conversions, the power dissipated during normal operation is

11.4 mW. The AD7866 can be said to dissipate 11.4 mW for 2 µs
during each conversion cycle and 1.68 mW for the remaining 8 µs
when the part is in partial power-down. With a throughput rate of
100 kSPS, the average power dissipated during each conversion
cycle is (2/10)  (11.4 mW) + (8/10)  (1.68 mW) = 3.624 mW.
Figure 21 shows the maximum power versus throughput rate
when using the partial power-down mode between conversions
with both 5 V and 3 V supplies for the AD7866.

SERIAL INTERFACE

Figure 22 shows the detailed timing diagram for serial interfacing
to the AD7866. The serial clock provides the conversion clock
and controls the transfer of information from the AD7866
during conversion.

The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and
requires 16 SCLK cycles to complete. Once 13 SCLK falling
edges have elapsed, the track-and-hold will go back into track
on the next SCLK rising edge, as shown in Figure 22 at point
B. On the rising edge of CS, the conversion will be terminated
and D

OUT

A and D

B will go back into three-state. If CS is

OUT

not brought high but is instead held low for a further 16 SCLK
cycles on D

A, the data from conversion B will be output on

OUT

SCLK

D

OUT

SCLK

D

D

CS

OUT

OUT

A

CS

A

B

THREE-

STATE

t

2

12345 13141516

t

3

0 RANGE A0 A/B DB11 DB2 DB1 DB0

THREE­STATE

1 LEADING ZERO
3 STATUS BITS

t

6

t

4

DB10

t

B

7

t

Figure 22. Serial Interface Timing Diagram

t

2

2 3 4

1

t

3

0 RANGE DB11

1 LEADING ZERO
3 STATUS BITS

A0/A0 ZERO DB1ADB0AZERO RANGE A0/ A0 ONE DB11

t

6

5 14 15 16

t

5

t

4

A

t

7

17

1 LEADING ZERO
3 STATUS BITS

Figure 23. Reading Data from Both ADCs on One D

5

OUT

t

Line

8

B

THREE-

STATE

DB1

t

B

QUIET

DB0

32

t

9

B

THREE-

STATE

REV. A–18–

AD7866

Table III. STATUS Bit Description

Bit Bit Name Comment

15 ZERO Leading Zero. This bit will always be a zero output.
14 RANGE The polarity of this bit reflects the analog input range that has been selected with the RANGE pin.

If it is a 0, it means that in the previous transfer upon the falling edge of the CS, the range pin was
at a logic low, providing an analog input range from 0 V to V
means that in the previous transfer upon the falling edge of CS, the RANGE pin was at a logic high,
resulting in an analog input range of 2  V

selected for this conversion. See Analog Input section.

REF

13 A0 This bit indicates on which channel the conversion is being performed, Channel 1 or Channel 2 of

the ADC in question. If this bit is a 0, the conversion result will be from Channel 1 of the ADC;
if it is a 1, the result will be from Channel 2 of the ADC in question.

12 A/B This bit indicates from which ADC the conversion result comes. If this bit is a 0, the result is from ADC A;

if it is a 1, the result is from ADC B. This is especially useful if only one serial port is available for
use and one D

line is used, as shown in Figure 23.

OUT

for this conversion. If it is a 1, it

REF

D

A. Likewise, if CS is held low for a further 16 SCLK cycles

OUT

on D
This is illustrated in Figure 23 where the case for D
Note that in this case, the D

B, the data from conversion A will be output on D

OUT

line in use will go back into

OUT

OUT

B.

OUT

A is shown.

three-state on the 32nd SCLK rising edge or the rising edge of CS,
whichever occurs first.

Sixteen serial clock cycles are required to perform the conversion
process and to access data from one conversion on either data
line of the AD7866. CS going low provides the leading zero to
be read in by the microcontroller or DSP. The remaining data is
then clocked out by subsequent SCLK falling edges, beginning
with the first of three data STATUS bits. Thus the first falling
clock edge on the serial clock has the leading zero provided and
also clocks out the first of three STATUS bits. The final bit in
the data transfer is valid on the sixteenth falling edge, having
being clocked out on the previous (fifteenth) falling edge. In
applications with a slower SCLK, it is possible to read in data on
each SCLK rising edge, i.e., the first rising edge of SCLK after
the CS falling edge would have the leading zero provided and
the fifteenth rising SCLK edge would have DB0 provided. The
three STATUS bits that follow the leading zero provide infor­mation with respect to the conversion result that follows them
on the D

line in use. Table III shows how these identifica-

OUT

tion bits can be interpreted.

MICROPROCESSOR INTERFACING

The serial interface on the AD7866 allows the parts to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7866 with some of the
more common microcontroller and DSP serial interface protocols.

AD7866 to ADSP-218x

The ADSP-218x family of DSPs is directly interfaced to the
AD7866 without any glue logic required. The V

DRIVE

pin of the
AD7866 takes the same supply voltage as that of the ADSP-218x.
This allows the ADC to operate at a higher supply voltage than
the serial interface, i.e., ADSP-218x, if necessary. This example
shows both D

OUT

A and D

B of the AD7866 connected to

OUT

both serial ports of the ADSP-218x.

The SPORT0 control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1

The SPORT1 control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 0, External Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1

To implement the power-down modes on the AD7866, SLEN
should be set to 1001 to issue an 8-bit SCLK burst. The
connection diagram is shown in Figure 24. The ADSP-218x has
the TFS0 and RFS0 of the SPORT0 and the RFS1 of SPORT1
tied together, with TFS0 set as an output and both RFS0 and RFS1
set as inputs. The DSP operates in alternate framing mode and
the SPORT control register is set up as described. The frame
synchronization signal generated on the TFS is tied to CS and,
as with all signal processing applications, equidistant sampling is
necessary. However, in this example, the timer interrupt is used to
control the sampling rate of the ADC and under certain conditions,
equidistant sampling may not be achieved.

The timer and other registers are loaded with a value that will
provide an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and there­fore the reading of data. The frequency of the serial clock is set
in the SCLKDIV register. When the instruction to transmit with
TFS is given (i.e., AX0 = TX0), the state of the SCLK is
checked. The DSP will wait until the SCLK has gone high, low,
and high before transmission will start. If the timer and SCLK
values are chosen such that the instruction to transmit occurs on
or near the rising edge of SCLK, the data may be transmitted or
it may wait until the next clock edge.

REV. A

–19–

AD7866

For example, if the ADSP-2189 had a 20 MHz crystal such that it
had a master clock frequency of 40 MHz, then the master cycle
time would be 25 ns. If the SCLKDIV register is loaded with the
value 3, an SCLK of 5 MHz is obtained and eight master clock
periods will elapse for every 1 SCLK period. Depending on the
throughput rate selected, if the timer register were loaded with the
value, 803, (803 + 1 = 804), for example, 100.5 SCLKs would
occur between interrupts and subsequently between transmit
instructions. This situation would result in nonequidistant
sampling as the transmit instruction is occurring on an SCLK
edge. If the number of SCLKs between interrupts were a whole
integer figure of N, equidistant sampling would be implemented
by the DSP.

AD7866*

SCLK

CS

D

A

OUT

D

B

OUT

V

DRIVE

*ADDITIONAL PINS OMITTED
FOR CLARITY

ADSP-218x*

SCLK0

SCLK1

TFS0

RFS0

RSF1

DR0

DR1

V

DD

Figure 24. Interfacing the AD7866 to the ADSP-218x

AD7866*

SCLK

D

A

OUT

B

D

OUT

CS

V

DRIVE

*ADDITIONAL PINS OMITTED
FOR CLARITY

TMS320C541*

CLKX0

CLKR0

CLKX1

CLKR1

DR0

DR1

FSX0

FSR0

FSR1

V

DD

Figure 25. Interfacing the AD7866 to the TMS320C541

AD7866 to TMS320C541

The serial interface on the TMS320C541 uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7866. The
CS input allows easy interfacing between the TMS320C541 and
the AD7866 with no glue logic required. The serial ports of
the TMS320C541 are set up to operate in burst mode with internal
CLKX (Tx serial clock on serial port 0) and FSX0 (Tx frame sync
from serial port 0). The serial port control (SPC) registers must have
the following setup:

SPC0: FO = 0, FSM = 1, MCM = 1 and TxM = 1
SPC1: FO = 0, FSM = 1, MCM = 0 and TxM = 0

The format bit, FO, may be set to 1 to set the word length to
eight bits, in order to implement the power-down modes on the AD7866.

The connection diagram is shown in Figure 25. It should be noted
that for signal processing applications, it is imperative that the
frame synchronization signal from the TMS320C541 will provide
equidistant sampling. The V

pin of the AD7866 takes the

DRIVE

same supply voltage as that of the TMS320C541. This allows the
ADC to operate at a higher voltage than the serial interface, i.e.,
TMS320C541, if necessary.

AD7866 to DSP-563xx

The connection diagram in Figure 26 shows how the AD7866
can be connected to the ESSI (synchronous serial interface) of
the DSP-563xx family of DSPs from Motorola. Each ESSI
(there are two on-board) is operated in synchronous mode
(bit SYN = 1 in CRB register) with internally generated word
length frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 = 0
in CRB). Normal operation of the ESSI is selected by making
MOD = 0 in the CRB. Set the word length to 16 by setting bits
WL1 = 1 and WL0 = 0 in CRA. To implement the power-down
modes on the AD7866, the word length can be changed to eight
bits by setting bits WL1 = 0 and WL0 = 0 in CRA. The FSP bit
in the CRB should be set to 1 to make the frame sync negative.
It should be noted that for signal processing applications, it is
imperative that the frame synchronization signal from the
DSP-563xx provide equidistant sampling.

In the example shown in Figure 26, the serial clock is taken from
the ESSI0, so the SCK0 pin must be set as an output, SCKD = 1,
while the SCK1 pin is set up as an input, SCKD = 0. The frame
sync signal is taken from SC02 on ESSI0, so SCD2 = 1, while
on ESSI1, SCD2 = 0, so SC12 is configured as an input. The

pin of the AD7866 takes the same supply voltage as that

V

DRIVE

of the DSP-563xx. This allows the ADC to operate at a higher
voltage than the serial interface, i.e., DSP-563xx, if necessary.

AD7866*

SCLK

D

A

OUT

D

B

OUT

CS

V

DRIVE

*ADDITIONAL PINS OMITTED
FOR CLARITY

DSP-563xx*

SCK0

SCK1

SRD0

SRD1

SC02

SC12

V

DD

Figure 26. Interfacing to the DSP-563xx

APPLICATION HINTS
Grounding and Layout

The analog and digital supplies to the AD7866 are independent
and separately pinned out to minimize coupling between the analog
and digital sections of the device. The AD7866 has very good
immunity to noise on the power supplies as can be shown by the
PSRR vs. Supply Ripple Frequency plots, TPC 3a to TPC 4b.
However, care should be taken with regard to grounding and
layout.

The printed circuit board that houses the AD7866 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum

REV. A–20–

AD7866

etch technique is generally best for ground planes because it gives
the best shielding. Both AGND pins of the AD7866 should be
sunk in the AGND plane. Digital and analog ground planes
should be joined at only one place. If the AD7866 is in a system
where multiple devices require an AGND to DGND connec­tion, the connection should still be made at one point only,
a star ground point that should be established as close as
possible to the AD7866.

Avoid running digital lines under the device since these will
couple noise onto the die. The analog ground plane should be
allowed to run under the AD7866 to avoid noise coupling.
The power supply lines to the AD7866 should use the largest
trace possible to provide low impedance paths and to reduce the
effects of glitches on the power supply line. Fast switching signals
like clocks should be shielded with digital ground to avoid
radiating noise to other sections of the board, and clock signals
should never be run near the analog inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This will reduce the
effects of feedthrough through the board. A microstrip technique
is by far the best but is not always possible with a double-sided
board. For this technique, the component side of the board is
dedicated to ground planes while signals are placed on the
solder side.

Good decoupling is also important. All analog supplies should be
decoupled with 10 µF tantalum in parallel with 0.1 µF capacitors
to AGND. All digital supplies should have at least a 0.1 µF disk
ceramic capacitor to DGND. V

should have a 0.1 µF ceramic

DRIVE

capacitor to DGND. To achieve the best results from these
decoupling components, place them as close as possible to the
device, ideally right up against it. The 0.1 µF capacitors should

be common ceramic or surface-mount types, which have low
Effective Series Resistance (ESR) and Effective Series Inductance
(ESI), and provide a low impedance path to ground at high
frequencies for handling transient currents due to internal logic
switching. Figure 27 shows the recommended supply decoupling
scheme. For information on the decoupling requirements of each
reference configuration, see the Reference Configuration
Options section.

AD7866

DV

DGND

V

DRIVE

DD

0.1␮F10␮F

0.1␮F

AV

0.1␮F10␮F

DD

AGND
AGND

Figure 27. Recommended Supply Decoupling Scheme

Evaluating the AD7866 Performance

The recommended layout for the AD7866 is outlined in the
evaluation board for the AD7866. The evaluation board package
includes a fully assembled and tested evaluation board, documen­tation, and software for controlling the board from the PC via the
eval-controller board. The eval-controller board can be used in
conjunction with the AD7866 evaluation board, as well as many
other Analog Devices evaluation boards ending in the CB desig­nator, to demonstrate/evaluate the ac and dc performance of the
AD7866.

The software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the AD7866.

REV. A

–21–

AD7866

OUTLINE DIMENSIONS

20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

6.60

6.50

6.40

PIN 1

0.15

0.05

COPLANARITY

0.10

20

1

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AC

0.65
BSC

11

10

1.20

MAX

SEATING

PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09
8ⴗ

0ⴗ

0.75

0.60

0.45

REV. A–22–

AD7866

Revision History

Location Page

2/03—Data Sheet changed from REV. 0 to REV. A.

Addition to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Addition to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Added text to Analog Input Ranges section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Changes to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Changes to POWER VS. THROUGHPUT RATE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Replaced Figure 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

REV. A

–23–

C02672–0–2/03(A)

–24–

PRINTED IN U.S.A.