Datasheet AD7836 Datasheet (Analog Devices)

LC2MOS

a

FEATURES
Four 14-Bit DACs in One Package
Voltage Outputs
Separate Offset Adjust for Each Output
Reference Range of 5 V
Maximum Output Voltage Range of 10 V
Clear Function to User-Defined Code
44-Pin MQFP Package

APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation

Quad 14-Bit DAC

AD7836

GENERAL DESCRIPTION

The AD7836 contains four 14-bit DACs on one monolithic
chip. It has output voltages with a full-scale range of ±10 V
from reference voltages of ±5 V.

The AD7836 accepts 14-bit parallel loaded data from the exter­nal bus into one of the input latches under the control of the
WR, CS and DAC channel address pins, A0–A2.

The DAC outputs are updated individually, on reception of new
data. In addition, the SEL input can be used to apply the user
programmed value in DAC Register E to all DACs, thus setting
all DAC output voltages to the same level. The contents of the
DAC data registers are not affected by the SEL input.

Each DAC output is buffered with a gain of two amplifier into
which an external DAC offset voltage can be inserted via the
DUTGNDx pins.

The AD7836 is available in a 44-lead MQFP package.

FUNCTIONAL BLOCK DIAGRAM

DB13

DB0

WR

(+)A

REF

X1 X1

DAC A

DAC D

X1 X1

(+)D V

REF

V

REF

REF

(–)A V

(–)D V

(+)B V

REF

X1

DAC B

DAC B

X1 X1

(+)C V

REF

REF

REF

(–)B

V

A

X1

(–)C

CLR

R

R

R

R

R

R

R

R

OUT

DUTGND A

V

B

OUT

DUTGND B

C

V

OUT

DUTGND C

V

D

OUT

DUTGND D

MUX

MUX

MUX

MUX

SELAGNDDGND

V

V

V

CCVSSVDD

AD7836

14

INPUT

BUFFER

CS

A0

A1

A2

ADDRESS

DECODE

14 14

DATA

14

DATA

DATA

DATA

DATA

REG

A

REG

B

REG

C

REG

D

REG

E

14

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

(VCC = +5 V  5%; VDD = +15 V  5%; VSS = –15 V  5%; AGND = DGND = DUTGND

AD7836–SPECIFICATIONS

= 0 V; RL = 5 k and CL = 50 pF to GND, T

Parameter A Units Test Conditions/Comments

ACCURACY

Resolution 14 Bits
Relative Accuracy ±2 LSB max
Differential Nonlinearity ±0.9 LSB max Guaranteed Monotonic Over Temperature
Full-Scale Error ±8 LSB max V
Zero-Scale Error ±8 LSB max V
Gain Error ±2 mV typ V
Gain Temperature Coefficient

DC Crosstalk

2

2

20 ppm FSR/°C typ
40 ppm FSR/°C max
50 µV max See Terminology. RL = 5 kΩ

(+) = +5 V, V

REF

(+) = +5 V, V

REF

(+) = +5 V, V

REF

REFERENCE INPUTS

DC Input Resistance 100 MΩ typ
Input Current ±1 µA max Per Input. Typically ±20 nA

(+) Range 0/+5 V min/max

V

REF

V

(–) Range –5/0 V min/max

REF

[V

REF

(+) – V

(–)] 2/10 V min/max For Specified Performance. Can Go as Low as 0 V,

REF

but Performance Not Guaranteed

OUTPUT CHARACTERISTICS

Output Voltage Swing ±10 V min 2 × (V

REF

(–)+[V

Short Circuit Current 25 mA max
Resistive Load 5 kΩ min To 0 V
Capacitive Load 50 pF max To 0 V

DIGITAL INPUTS

, Input High Voltage 2.4 V min

V

INH

, Input Low Voltage 0.8 V max

V

INL

, Input Current ±10 µA max Total for All Pins

I

INH

CIN, Input Capacitance 10 pF max

POWER REQUIREMENTS

V

CC

V

DD

V

SS

5.0 V nom ±5% for Specified Performance

15.0 V nom ±5% for Specified Performance
–15.0 V nom ±5% for Specified Performance

Power Supply Sensitivity

∆Full Scale/∆V
∆Full Scale/∆V

I

CC

I

DD

I

SS

DD

SS

110 dB typ
100 dB typ

0.5 mA max V
8 mA max V

= VCC, V

INH

= 2.4 V min, V

INH

14 mA max Outputs Unloaded. Typically 7 mA
14 mA max Outputs Unloaded. Typically 7 mA

1

= T

to T

A

MIN

(–) = –5 V. Typically within ±1 LSB

REF

(–) = –5 V. Typically within ±1 LSB

REF

(–) = –5 V

REF

(+)-V

REF

INL

REF

= DGND. Dynamic Current

= 0.8 V max

INL

, unless otherwise noted)

MAX

(–)]•D) – V

DUTDGN

(These characteristics are included for Design Guidance and are not

AC PERFORMANCE CHARACTERISTICS

Parameter A Units Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 16 µs typ Full-Scale Change to ±1/2 LSB. DAC Latch Contents Alternately

Digital-to-Analog Glitch Impulse 150 nV-s typ Measured with V

DC Output Impedance 0.3 Ω max See Terminology
Channel-to-Channel Isolation 115 dB typ See Terminology
DAC-to-DAC Crosstalk 10 nV-s typ See Terminology
Digital Crosstalk 10 nV-s typ Feedthrough to DAC Output Under Test Due to Change in Digital

Digital Feedthrough 0.2 nV-s typ Effect of Input Bus Activity on DAC Output Under Test
Output Noise Spectral Density

@ 1 kHz 40 nV/√Hz typ All 1s Loaded to DAC. V

NOTES

1

Temperature range for A Version: –40°C to +85°C

2

Guaranteed by design.

Specifications subject to change without notice.

subject to production testing.)

Loaded with All 0s and All 1s

REF

Alternately Loaded with 1FFF Hex and 2000 Hex. Not Dependent
on Load Conditions

Input Code to Another Converter

–2–

(+) = +5 V, V

(+) = V

REF

(–) = –5 V. DAC Latch

REF

(–) = 0 V

REF

REV. A

TIMING SPECIFICATIONS

1

(VCC = +5 V  5%; VDD = +15 V  5%; VSS = –15 V  5%; AGND = DGND = 0 V)

AD7836

Parameter Limit at T

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

NOTES

1

All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

Rise and fall times should be no longer than 50 ns.

Specifications subject to change without notice.

15 ns min A0, A1, A2 to WR Setup Time
0 ns min A0, A1, A2 to WR Hold Time
0 ns min CS to WR Setup Time
0 ns min WR to CS Hold Time
44 ns min WR Pulsewidth
15 ns min Data Setup Time

4.5 ns min Data Hold Time
44 ns min WR Pulse Interval
16 µs typ Settling Time
300 ns max CLR Pulse Activation Time

A0, A1, A2

CS

WR

DATA

MIN, TMAX

t

3

t

1

t

5

t

6

Units Description

t

2

t

4

t

8

t

7

t

9

V

OUT

t

CLR

V

OUT

10

Figure 1. Timing Diagram

REV. A

–3–

AD7836

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

VCC to DGND . . . . . . . . . . . . . . .–0.3 V, +7 V or V

1

+ 0.3 V

DD

(Whichever Is Lower)

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V

V

DD

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V

SS

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +0.3 V

Digital Inputs to DGND . . . . . . . . . . . . . –0.3 V, V

V

(+) to V

REF

V

(+) to AGND . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V

REF

(–) to AGND . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V

V

REF

DUTGND to AGND . . . . . . . . . . . V

V

(A–D) to AGND . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V

OUT

(–) . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V

REF

– 0.3 V, VDD + 0.3 V

SS

+ 0.3 V

CC

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

ORDERING GUIDE

Temperature Error DNL Package

Model Range (LSBs) (LSBs) Option*

AD7836AS –40°C to +85°C ±2 ±0.9 S-44

*S = Plastic Quad Flatpack (MQFP).

MQFP Package, Power Dissipation . . . . . . . . . . . . . . 480 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

Linearity

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7836 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. A

Pin Mnemonic Description

AD7836

PIN DESCRIPTION

V

CC

V

SS

V

DD

Logic Power Supply; +5 V ± 5%.
Negative Analog Power Supply; –15 V ± 5%.
Positive Analog Power Supply; +15 V ± 5%.

DGND Digital Ground.
AGND Analog Ground.
V
V
V
V
V

REF

REF

REF

REF

OUT

(+)A, V
(+)B, V
(+)C, V
(+)D, V

A...V

(–)A Reference Inputs for DAC A. These reference voltages are referred to AGND.

REF

(–)B Reference Inputs for DAC B. These reference voltages are referred to AGND.

REF

(–)C Reference Inputs for DAC C. These reference voltages are referred to AGND.

REF

(–)D Reference Inputs for DAC D. These reference voltages are referred to AGND.

REF

D DAC Outputs.

OUT

CS Level-Triggered Chip Select Input (active low). The device is selected when this input is low.
DB0 . . . DB13 Parallel Data Inputs. The AD7836 can accept a straight 14-bit parallel word on DB0 to DB13 where

DB13 is the MSB and DB0 is the LSB.
A0, A1, A2 Address inputs. A0, A1 and A2 are decoded to select one of the five input latches for a data transfer.
CLR Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog outputs are

switched to the externally set potential on the DUTGND pin. The contents of data registers A to E are

not affected when the CLR pin is taken low. When CLR is brought back high, the DAC outputs revert

back to their original outputs as determined by the data in their data registers.
WR Level-Triggered Write Input (active low), when active and used in conjunction with CS to write data to

the AD7836 input buffer. Data is latched into the selected data register on the rising edge of WR.
DUTGND A Device Sense Ground for DAC A. Vout A is referenced to the voltage applied to this pin.
DUTGND B Device Sense Ground for DAC B. Vout B is referenced to the voltage applied to this pin.
DUTGND C Device Sense Ground for DAC C. Vout C is referenced to the voltage applied to this pin.
DUTGND D Device Sense Ground for DAC D. Vout D is referenced to the voltage applied to this pin.
SEL Select pin, active high level triggered input. When the SEL input is high, the user programmed value in

DATAREG E will be loaded into all DAC registers and the DAC outputs updated accordingly. The con-

tents of the other DATA REGs (A–D) will not be affected by the SEL pin.

34

C

V

OUT

35

(–)C

V

REF

36

(+)C

V

REF

37

AGND

38

NC

39

V

DD

40

NC

41

V

SS

42

V

(+)A

REF

43

(–)A

V

REF

44

A

V

OUT

NC = NO CONNECT

PIN CONFIGURATION

D

(+)D

(–)D

OUT

REF

REF

V

V

DUTGND C

PIN 1
IDENTIFIER

234567891011

1

(–)B

(+)B

REF

REF

V

V

DUTGND A

DB13

V

DUTGND D

AD7836

TOP VIEW

(Not to Scale)

B

A2A1A0

OUT

V

DUTGND B

DB12

DB11

DB10

SEL

DB9

CS

DB8

2324252627282930313233

22

DB7

21

DB6

20

DB5

19

DB4

18

DB3

17

DB2

16

DB1

15

DB0

14

DGND

13

V

CC

CLR

12

WR

REV. A

–5–

AD7836

TERMINOLOGY
Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the max­imum deviation from a straight line passing through the endpoints
of the DAC transfer function. It is measured after adjusting for
zero error and full-scale error and is normally expressed in Least
Significant Bits or as a percentage of full-scale reading.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.

DC Crosstalk

Although the common input reference voltage signals are inter­nally buffered, small IR drops in the individual DAC reference
inputs across the die can mean that an update to one channel
can produce a dc output change in one or other of the channel
outputs.

The four DAC outputs are buffered by op amps that share com­mon V

and VSS power supplies. If the dc load current changes

DD

in one channel (due to an update), this can result in a further dc
change in one or other channel outputs. This effect is most ob­vious at high load currents and reduces as the load currents are
reduced. With high impedance loads the effect is virtually
unmeasurable.

Output Voltage Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.

Digital-to-Analog Glitch Impulse

This is the amount of charge injected into the analog output when
the inputs change state. It is specified as the area of the glitch in
nV-secs. It is measured with V

(+) = +5 V and V

REF

(–) = –5 V

REF

and the digital inputs toggled between 1FFFHEX and 8000H.

Channel-to-Channel Isolation

Channel-to-channel isolation refers to the proportion of input
signal from one DACs reference input that appears at the output
of the other DAC. It is expressed in dBs.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is defined as the glitch impulse that ap­pears at the output of one converter due to both the digital
change and subsequent analog O/P change at another converter.
It is specified in nV-s.

Digital Crosstalk

The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the digital crosstalk and is specified in nV-s.

Digital Feedthrough

When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the V

OUT

pins. This noise is digital feedthrough.

DC Output Impedance

This is the effective output source resistance. It is dominated by
package lead resistance.

Full-Scale Error

This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s
loaded into the DAC latch, should be 2 V

(+) – 1 LSB. Full-

REF

scale error does not include zero-scale error.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC latch. Ideally the output voltage,
with all 0s in the DAC latch should be equal to 2 V

(–). Zero-

REF

scale error is mainly due to offsets in the output amplifier.

Gain Error

Gain Error is defined as (Full-Scale Error) – (Zero-Scale Error).

GENERAL DESCRIPTION
DAC Architecture—General

Each channel consists of a segmented 14-bit R-2R voltage-mode
DAC. The full-scale output voltage range is equal to twice the
reference span of V
straight binary; all 0s produces an output of 2 V
produces an output of 2 V

REF

(+) – V

REF

(–). The DAC coding is

REF

REF

(+) – 1 LSB.

(–); all 1s

The analog output voltage of each DAC channel reflects the
contents of its own DAC latch. Data is transferred from the ex­ternal bus to the input register of each DAC latch on a per
channel basis. The AD7836 has a feature whereby using the A2
pin, data can be transferred from the input data bus to all four
input registers simultaneously.

Bringing the CLR line low switches all the signal outputs,
V

OUT

A to V

D, to the voltage level on the DUTGND pin.

OUT

When CLR signal is brought back high the output voltages from
the DACs will reflect the data stored in the relevant DAC
registers.

Data Loading to the AD7836

Data is loaded into the AD7836 in straight parallel 14-bit wide
words.

The DAC output voltages, V

OUT

A–V

D are updated to

OUT

reflect new data in the DAC input registers.

The actual DAC input register that is being written to is deter­mined by the logic levels present on the devices address lines, as
shown in Table I.

Table I. Address Line Truth Table

A2 A1 A0 DAC Selected

0 0 0 DATA REG A (DAC A)
0 0 1 DATA REG B (DAC B)
0 1 0 DATA REG C (DAC C)
0 1 1 DATA REG D (DAC D)
1 0 0 DATA REG E
1 1 1 DATA REG A–D

–6–

REV. A

Typical Performance Characteristics–AD7836

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

–0.4

INL ERROR – LSBs

–0.6

–0.8

–1.0

024681012

INPUT CODE/1000

14 16

Figure 2. Typical INL Plot

1.0

0.5

0

DNL ERROR – LSB

–0.5

–1.0

–40 90–20 0 20 40 60 80

TEMPERATURE – °C

VDD = 15V
V

= –15V

SS

V

(+) = +5V

REF

V

(–) = –5V

REF

Figure 5. Typical DNL Error vs.
Temperature

0.9

0.6

0.4

0.2

0.0

–0.2

–0.4

DNL ERROR – LSBs

–0.6

–0.9

02

4681012

INPUT CODE/1000

14 16

Figure 3. Typical DNL Plot

2

VDD = 15V
V

= –15V

SS

V

(+) = +5V

REF

1

V

(–) = –5V

REF

FULL-SCALE ERROR

0

ERROR – LSB

–1

–2

–40 90–20 0 20 40 60 80

OFFSET ERROR

TEMPERATURE – °C

Figure 6. Offset and Full-Scale Error
vs. Temperature

2

1

0

INL ERROR – LSB

–1

–2

–20 0 20 40 60 80

–40 90

TEMPERATURE – °C

VDD = 15V
V

= –15V

SS

V

(+) = +5V

REF

V

(–) = –5V

REF

Figure 4. Typical INL Error vs.
Temperature

6

DIGITAL INPUTS @ THRESHOLDS

5

4

VCC = 5V
V

= 15V

DD

3

V

= –15V

SS

– mA

2

CC

I

1

DIGITAL INPUTS @ SUPPLIES

0

–1

–40 90–20 0 20406080

TEMPERATURE – °C

Figure 7. ICC vs. Temperature

0.7

VERT = 100mV/DIV

0.6
HORIZ = 1s/DIV

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

Figure 8. Typical Digital/Analog
Glitch Impulse

10.2

10.0

9.8

– V

OUT

V

9.6

9.4

9.2
11 14

12 13

SETTLING TIME – s

Figure 9. Settling Time (+)

8

7

VDD = 15V
V

= –15V

SS

– mA

6

V

SS

/I

DD

I

Figure 10. IDD/I

(+) = +5V

REF

V

(–) = –5V

REF

5

4

–40 90–20 0 20 40 60 80

TEMPERATURE – °C

vs. Temperature

SS

REV. A

–7–

AD7836

Unipolar Configuration

Figure 11 shows the AD7836 in the unipolar binary circuit con­figuration. The V
AD586, a +5 V reference. V

(+) input of the DAC is driven by the

REF

(–) is tied to ground. Table II

REF

gives the code table for unipolar operation of the AD7836.
Other suitable references include the REF02, a precision 5 V
reference, and the REF195, a low dropout, micropower preci­sion +5 V reference.

+15V +5V

C1

1nF

2

8

6

AD586

5

4

SIGNAL

GND

*ADDITIONAL PINS OMITTED FOR CLARITY

R1
10k

V

REF

V

REF

V

DD

(+)

AD7836*

(–)

V

–15V

V

CC

V

DUTGND

AGND

DGND

SS

OUT

V
(0 TO +10V)

SIGNAL

GND

OUT

Figure 11. Unipolar +5 V Operation

Offset and gain may be adjusted in Figure 2 as follows: To ad­just offset, disconnect the V
with all 0s and adjust the V

(–) input from 0 V, load the DAC

REF

(–) voltage until V

REF

= 0 V. For

OUT

gain adjustment, the AD7836 should be loaded with all 1s and
R1 adjusted until V

= 10 V(16383/16384) = 9.999389.

OUT

Many circuits will not require these offset and gain adjustments. In
these circuits R1 can be omitted. Pin 5 of the AD586 may be left
open circuit and Pin 2 (V

(–)) of the AD7836 tied to 0 V.

REF

Table II. Code Table for Unipolar Operation

Binary Number in DAC Latch Analog Output
MSB LSB (V

11 1111 1111 1111 2 V
10 0000 0000 0000 2 V
01 1111 1111 1111 2 V
00 0000 0000 0001 2 V

)

OUT

(16383/16384) V

REF

(8192/16384) V

REF

(8191/16384) V

REF

(1/16384) V

REF

00 0000 0000 0000 0 V

NOTE
V

= V

(+); V

REF

REF

For V

(+) = +5 V, 1 LSB = +10 V/214 = +10 V/16384 = 610 µV.

REF

(–) = 0 V for unipolar operation.

REF

Bipolar Configuration

Figure 12 shows the AD7836 set up for ±10 V operation. The
AD588 provides precision ±5 V tracking outputs that are fed to
the V

(+) and V

REF

(–) inputs of the AD7836. The code table

REF

for bipolar operation of the AD7836 is shown in Table III.

In Figure 12, full-scale and bipolar zero adjustments are pro­vided by varying the gain and balance on the AD588. R2 varies
the gain on the AD588 while R3 adjusts the offset of both the
+5 V and –5 V outputs together with respect to ground.

For bipolar-zero adjustment, the DAC is loaded with
1000 . . . 0000 and R3 is adjusted until V

= 0 V. Full scale

OUT

is adjusted by loading the DAC with all 1s and adjusting R2 un­til V

= 10(8191/8192) V = 9.998779 V.

OUT

When bipolar-zero and full-scale adjustment are not needed,
R2 and R3 can be omitted. Pin 12 on the AD588 should be
connected to Pin 11 and Pin 5 should be left floating.

+15V +5V

R1
39k

6

100k

4

7

C1

1F

9

AD588

R2

100k

5

10

11

R3

12 8

*ADDITIONAL PINS OMITTED FOR CLARITY

2

3

V

1

14

15

16

13

REF

V

REF

V

DD

(+)

AD7836

(–)

DUTGND

V

SS

–15V

V

CC

V

*

AGND

DGND

OUT

V

OUT

(–10V TO +10V)

SIGNAL

GND

Figure 12. Bipolar ±5 V Operation

Table III. Code Table for Bipolar Operation

Binary Number in DAC Latch Analog Output
MSB LSB (V

11 1111 1111 1111 2[V
10 0000 0000 0001 2[V
10 0000 0000 0000 2[V
01 1111 1111 1111 2[V
00 0000 0000 0001 2[V
00 0000 0000 0000 2[V

NOTE
V

= (V

REF

For V

= 20 V/16384 = 1220 µV.

(+) – V

REF

(+) = +5 V, and V

REF

REF

(–)).

REF

(–) = –5 V, V

)

OUT

(–) + V

REF

(–) + V

REF

(–) + V

REF

(–) + V

REF

(–) + V

REF

(–)] V

REF

=10 V, 1 LSB = 2 VREF V/2

REF

(16383/16384)] V

REF

(8193/16384)] V

REF

(8192/16384)] V

REF

(8191/16384)] V

REF

(1/16384)] V

REF

14

CONTROLLED POWER-ON OF THE OUTPUT STAGE

A block diagram of the output stage of the AD7836 is shown in
Figure 13. It is capable of driving a load of 5 kΩ in parallel
with 50 pF. G
control the power on voltage present at V

to G6 are transmission gates that are used to

1

. On power up G

OUT

1

and G2 are also used in conjunction with the CLR input to set
V

to the user defined voltage present at the DUTGND pin.

OUT

When CLR is taken back high the DAC outputs reflect the data
in the DAC registers.

G

DAC

1

G

G

G

R

4

G

DUTGND

R = 13.5k

2

G

6

3

5

6k

V

OUT

Figure 13. Block Diagram of AD7836 Output Stage

–8–

REV. A

AD7836

Power-On with CLR Low

The output stage of the AD7836 has been designed to allow
output stability during power-on. If CLR is kept low during
power-on, then just after power is applied to the AD7836, the
situation is as depicted in Figure 14. G
while G

, G3 and G5 are closed.

2

G

DAC

1

G

G

2

4

R

DUTGND

G

G

, G4 and G6 are open

1

G

6

3

R

5

6k

V

OUT

Figure 14. Output Stage with VDD < 10 V

V

is kept within a few hundred millivolts of DUTGND via

OUT

and a 6kΩ resistor. This thin-film resistor is connected in

G

5

parallel with the gain resistors of the output amplifier. The out­put amplifier is connected as a unity gain buffer via G
DUTGND voltage is applied to the buffer input via G

, and the

3

. The

2

amplifier’s output is thus at the same voltage as the DUTGND
pin. The output stage remains configured as in Figure 14 until
the voltage at V

and VSS reaches approximately ±10 V. By

DD

now the output amplifier has enough headroom to handle sig­nals at its input and has also had time to settle. The internal
power-on circuitry opens G

and G5 and closes G4 and G6. This

3

situation is shown in Figure 15. Now the output amplifier is
configured in its noise gain configuration via G

and G6. The

4

DUTGND voltage is still connected to the noninverting input
via G2 and this voltage appears at V

G

DAC

1

G

R

G

4

G

DUTGND

R

G

2

Figure 15. Output Stage with VDD > 10 V and

V

has been disconnected from the DUTGND pin by the

OUT

opening of G

but will track the voltage present at DUTGND

5

.

OUT

G

6

3

5

6k

V

OUT

CLR

Low

via the configuration shown in Figure 15.

When CLR is taken back high, the output stage is configured as
shown in Figure 16. The internal control logic closes G
opens G

. The output amplifier is connected in a noninverting

2

and

1

gain of two configuration. The voltage that appears on the Vout
pins is determined by the data present in the DAC registers. To
set all output voltages to the same known state, a write to
DATA REG E with the SEL pin high allows all DAC registers
to be updated with the same data.

G

DAC

1

G

G

G

R

4

G

DUTGND

R

2

Figure 16. Output Stage After

G

6

3

5

6k

CLR

Is Taken High

V

OUT

Power-On with CLR High

If CLR is high on the application of power to the device, the
output stages of the AD7836 are configured as in Figure 17
while V

are less than ±10 V. G1 is closed and G2 is open

DD/VSS

thereby connecting the output of the DAC to the input of its
output amplifier. G

and G5 are closed while G4 and G6 are

3

open thus connecting the output amplifier as a unity gain
buffer. V
resistor until V

Figure 17. Output Stage Powering Up with
While V

is connected to DUTGND via G5 through a 6 kΩ

OUT

DAC

DD/VSS

and VSS reach approximately ±10 V.

DD

G

1

G

G

G

R

4

G

DUTGND

R

2

G

6

3

5

6k

CLR

< ±10 V

V

High

OUT

When the supplies reach ±10 V, the internal power on circuitry
opens G

and G5 and closes G4 and G6 configuring the output

3

stage as shown in Figure 18.

G

DAC

1

G

G

G

R

4

G

DUTGND

R

2

Figure 18. Output Stage Powering Up with
When V

DD/VSS

> ±10 V

G

6

3

5

6k

CLR

V

OUT

High

REV. A

–9–

AD7836

DUTGND Voltage Range

During power-on, the V
to the relevant DUTGND pins via G

pins of the AD7836 are connected

OUT

and the 6 kΩ thin-film

6

resistor. The DUTGND potential must obey the max ratings at
all times. Thus, the voltage at DUTGND must always be
within the range V
that the voltages at the V

– 0.3 V, VDD + 0.3 V. However, in order

SS

pins of the AD7836 stay within

OUT

±2 V of the relevant DUTGND potential during power-on, the
voltage applied to DUTGND should also be kept within the
range AGND – 2 V, AGND + 2 V.

Once the AD7836 has powered on and the on-chip amplifiers
have settled, any voltage that is now applied to the DUTGND
pin is subtracted from the DAC output which has been gained
up by a factor of two. Thus, for specified operation, the maxi­mum voltage that can be applied to the DUTGND pin increases
to the maximum allowable 2 × V

(+) voltage, and the mini-

REF

mum voltage that can be applied to DUTGND is the minimum
2 × V

(–) voltage. After the AD7836 has fully powered on,

REF

the outputs can track any DUTGND voltage within this
minimum/maximum range.

MICROPROCESSOR INTERFACING
Interfacing the AD7836—16-Bit Interface

The AD7836 can be interfaced to a variety of 16-bit micro­controllers or DSP processors. Figure 19 shows the AD7836
interfaced to a generic 16-bit microcontroller/DSP processor.
The lower address lines from the processor are connected to
A0, A1 and A2 on the AD7836 as shown. The upper address
lines are decoded to provide a chip select signal for the
AD7836. They are also decoded (in conjunction with the lower
address lines if need be) to provide a SEL signal. The fast inter­face timing of the AD7836 allows direct interface to a wide vari­ety of microcontrollers and DSPs as shown in Figure 19.

CONTROLLER/

DSP

PROCESSOR*

DATA

BUS

UPPER BITS OF

ADDRESS BUS

*ADDITIONAL PINS OMITTED FOR CLARITY

D13

D0

A2
A1
A0

R/W

AD7836

•

•

•

ADDRESS

DECODE

D13

D0

CS

A2

A1
A0

WR

•

•

•

*

Figure 19. AD7836 Parallel Interface

APPLICATIONS
Power Supply Bypassing and Grounding

In any circuit where accuracy is important, careful consider­ation of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD7836 is mounted should be designed such that
the analog and digital sections are separated and confined to
certain areas of the board. This facilitates the use of ground
planes that can be separated easily. A minimum etch tech­nique is generally best for ground planes as it gives the best
shielding. Digital and analog ground planes should only be
joined at one place. If the AD7836 is the only device requiring
an AGND to DGND connection, then the ground planes
should be connected at the AGND and DGND pins of the
AD7836. If the AD7836 is in a system where multiple devices
require an AGND to DGND connection, the connection
should still be made at one point only, a star ground point
which should be established as close as possible to the
AD7836.

Digital lines running under the device should be avoided as
these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7836 to avoid noise
coupling. The power supply lines of the AD7836 should use
as large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line. Fast
switching signals like clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board and
should never be run near the analog inputs.

Avoid crossover of digital and analog signals. Traces on oppo­site sides of the board should run at right angles to each other.
This reduces the effects of feedthrough through the board. A
microstrip technique is by far the best but not always possible
with a double sided board. In this technique, the component
side of the board is dedicated to ground plane while signal
traces are placed on the solder side.

The AD7836 should have ample supply bypassing located as
close to the package as possible, ideally right up against the
device. Figure 20 shows the recommended capacitor values of
10 µF in parallel with 0.1 µF on each of the supplies. The 10 µF
capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low Effective Series Resistance (ESR) and Effec­tive Series Inductance (ESI), such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.

V

V

CC

DD

10F 0.1F10F0.1F

AD7836

V

SS

10F 0.1F

Figure 20. Recommended Decoupling Scheme
for AD7836

–10–

REV. A

AD7836

Automated Test Equipment

The AD7836 is particularly suited for use in an automated test
environment. Figure 21 shows the AD7836 providing the nec­essary voltages for the pin driver and the window comparator in
a typical ATE pin electronics configuration. AD588s are used
to provide reference voltages for the AD7836. In the configu­ration shown, the AD588s are configured so that the voltage at
Pin 1 is 5 V greater than the voltage at Pin 9 and the voltage at
Pin 15 is 5 V less than the voltage at Pin 9.

V

OFFSET

162

3

1

15
14

9

0.1F

V

(+)A/B

REF

V

(–)A/B

REF

DUTGND A/B

V

OUT

V

OUT

AD7836*

DUTGND C/D

162

3

1

15
14

8

DEVICE
GND

*

ADDITIONAL PINS OMITTED FOR CLARITY

V

(+)C/D

REF

V

(–)C/D

REF

AGND

V

OUT

V

OUT

WINDOW

COMPARATOR

+15V

A

PIN

DRIVER

B

–15V

V

DEVICE
GND

C

D

TO TESTER

OUT

DEVICE
GND

1F

+15V –15V

4

6
8

13

7

+15V –15V

4
6

8
13

10
11
12

1F

AD588

10 11 12

AD588

7

Figure 21. ATE Application

One of the AD588s is used as a reference for DACs 1 and 2.
These DACs are used to provide high and low levels for the pin
driver. The pin driver may have an associated offset. This can
be nulled by applying an offset voltage to Pin 9 of the AD588.
First, the code 1000 . . . 0000 is loaded into the DACA latch
and the pin driver output is set to the DACA output. The
V
driver output and DUT GND. This causes both V
V
to V

voltage is adjusted until 0 V appears between the pin

OFFSET

(–) to be offset with respect to AGND by an amount equal

REF

. However, the output of the pin driver will vary

OFFSET

(+) and

REF

from –10 V to +10 V with respect to DUT GND as the DAC
input code varies from 000 . . . 000 to 111 . . . 111. The
V

voltage is also applied to the DUTGND pins. When a

OFFSET

clear is performed on the AD7836, the output of the pin driver
will be 0 V with respect to Device GND.

The other AD588 is used to provide a reference voltage for
DACs C and D. These provide the reference voltages for the
window comparator shown in the diagram. Note that Pin 9 of
this AD588 is connected to Device GND. This causes
V

(+)C & D and V

REF

(–)C & D to be referenced to Device

REF

GND. As DAC 3 and DAC 4 input codes vary from
000 . . . 000 to 111 . . . 111, V

OUT

3 and V

4 vary from –10 V

OUT

to +10 V with respect to Device GND. Device GND is also
connected to DUTGND. When the AD7836 is cleared,
V

OUT

C and V

D are cleared to 0 V with respect to DEVICE

OUT

GND.

TrimDAC is a registered trademark of Analog Devices, Inc.

Programmable Reference Generation for the AD7836 in an
ATE Application

The AD7836 is particularly suited for use in an automated test
environment. The reference input for the AD7836 quad 14-bit
DAC requires two references for each DAC. Programmable
references may be a requirement in some ATE applications as
the offset and gain errors at the output of each DAC can be ad­justed by varying the voltages on the reference pins of the DAC.
To trim offset errors, the DAC is loaded with the digital code
000 . . . 000 and the voltage on the V

(–) pin is adjusted until

REF

the desired negative output voltage is obtained. To trim out
gain errors, first the offset error is trimmed. Then the DAC is
loaded with the code 111 . . . 111 and the voltage on the
V

(+) pin is adjusted until the desired full scale voltage

REF

minus one LSB is obtained.

It is not uncommon in ATE design, to have other circuitry at
the output of the AD7836 that can have offset and gain errors
of up to say ±300 mV. These offset and gain errors can be eas­ily removed by adjusting the reference voltages of the AD7836.
The AD7836 uses nominal reference values of ±5 V to achieve
an output span of ±10 V. Since the AD7836 has a gain of two
from the reference inputs to the DAC output, adjusting the ref­erence voltages by ±150 mV will adjust the DAC offset and
gain by ±300 mV.

There are a number of suitable 8- and 10-bit DACs available
that would be suitable to drive the reference inputs of the
AD7836, such as the AD7804 which is a quad 10-bit digital-to­analog converter with serial load capabilities. The voltage out­put from this DAC is in the form of V

BIAS

± V

SWING

and rail to
rail operation is achievable. The voltage reference for this DAC
can be internally generated or provided externally. This DAC
also contains an 8-bit SUB DAC which can be used to shift the
complete transfer function of each DAC around the V

BIAS

point. This can be used as a fine trim on the output voltage. In
this Application two AD7804s are required to provide program­mable reference capability for all four DACs. One AD7804 is
used to drive the V
drive the V

(–) pins.

REF

Another suitable DAC for providing programmable reference
capability is the AD8803. This is an octal 8-bit trimDAC

(+) pins and the second package used to

REF

®

and
provides independent control of both the top and bottom ends
of the trimDAC. This is helpful in maximizing the resolution of
devices with a limited allowable voltage control range.

The AD8803 has an output voltage range of GND to V
+5 V). To trim the V
on the AD8803 DAC can be set using the V

(+) input, the appropriate trim range

REF

REFL

DD

and V

(0 V to

REFH

pins allowing 8 bits of resolution between the two points. This
will allow the V

To trim the V

(+) pin to be adjusted to remove gain errors.

REF

(–) voltage, some method of providing a trim

REF

voltage in the required negative voltage range is required. Nei­ther the AD7804 or the AD8803 can provide this range in nor­mal operation as their output range is 0 V to +5 V. There are
two methods of producing this negative voltage. One method is
to provide a positive output voltage and then to level shift that
analog voltage to the required negative range. Alternatively

REV. A

–11–

AD7836

these DACs can be operated with supplies of 0 V and a –5 V,
with the V

pin connected to 0 V and the GND pin connected

DD

to –5 V. Now these can be used to provide the negative refer­ence voltages for the V

(–) inputs on the AD7836. However,

REF

ADDR BUS

ADDR

DECODER

FSIN/CS

SDATA

SCLK

CONTROLLER

DATA BUS

LOGIC LEVEL

SHIFT

*

DIN

SCLK

FSIN/CS

DIN

SCLK

ADDITIONAL PINS OMITTED FOR CLARITY

8/10-BIT

DAC

8/10-BIT

DAC

the digital signals driving the DACs need to be level shifted
from the 0 V to +5 V range to the –5 V to 0 V range. Figure 22
shows a typical application circuit to provide programmable ref­erence capabilities for the AD7836.

+5V

V

DD

A0,A1,A2

V

(+)A

REF

AD7836

(–) A

V

REF

DATA BUS

AGND

V

OUT

V

A

OUT

*

GND

V

GND

–5V

0V to 5V

DD

0V to -5V

C2163a–0–9/99

Figure 22. Programmable Reference Generation for the AD7836

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

44-Lead MQFP (S-44)

0.548 (13.925)

0.037 (0.94)

0.025 (0.64)

SEATING

PLANE

0.040 (1.02)

0.032 (0.81)

0.096 (2.44)
MAX

0.083 (2.11)

0.077 (1.96)

8

0.8

0.040 (1.02)

0.032 (0.81)

34

44

33

1

0.033 (0.84)

0.029 (0.74)

0.546 (13.875)

0.398 (10.11)

0.390 (9.91)

TOP VIEW

(PINS DOWN)

0.016 (0.41)

0.012 (0.30)

23

22

12

11

PRINTED IN U.S.A.

–12–

REV. A