Datasheet AD7834 Datasheet (Analog Devices)

LC2MOS

a

FEATURES
Four 14-Bit DACs in One Package

AD7834—Serial Loading

AD7835—Parallel 8-/14-Bit Loading
Voltage Outputs
Power-On Reset Function
Max/Min Output Voltage Range of 8.192 V
Maximum Output Voltage Span of 14 V
Common Voltage Reference Inputs
User Assigned Device Addressing
Clear Function to User-Defined Voltage
Surface-Mount Packages

AD7834—28-Lead SOIC and PDIP

AD7835—44-Lead MQFP and PLCC

APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation

GENERAL DESCRIPTION

The AD7834 and AD7835 contain four 14-bit DACs on one
monolithic chip. The AD7834 and AD7835 have output
voltages in the range of ±8.192 V with a maximum span
of 14 V.

Quad 14-Bit DACs

AD7834/AD7835

The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after two leading 0s,
into one via DIN, SCLK and FSYNC. The AD7834 has five
dedicated package address pins, PA0–PA4, that can be wired to
AGND or V
addressed in a multipackage application.

The AD7835 can accept either 14-bit parallel loading or double­byte loading, where right-justified data is loaded in one 8-bit and
one 6-bit byte. Data is loaded from the external bus into one of
the input latches under the control of the WR, CS, BYSHF,
and DAC channel address pins, A0–A2.

With either device, the LDAC signal can be used to update either
all four DAC outputs simultaneously or individually on reception
of new data. In addition, for either device, the asynchronous
CLR input can be used to set all signal outputs, V
to the user-defined voltage level on the Device Sense Ground pin,
DSG. On power-on, before the power supplies have stabilized,
internal circuitry holds the DAC output voltage levels to within
±2 V of the DSG potential. As the supplies stabilize, the DAC
output levels move to the exact DSG potential (assuming
CLR is exercised).

The AD7834 is available in 28-lead 0.3" SOIC and 0.6" PDIP
packages, and the AD7835 is available in a 44-lead MQFP
package and a 44-lead PLCC package.

to permit up to 32 AD7834s to be individually

CC

1–V

OUT

OUT

(continued on page 10)

4,

AD7834 FUNCTIONAL BLOCK DIAGRAM

PAEN

PA0

PA1

PA2

PA3

PA4

FSYNC

DIN

SCLK

AD7834

CONTROL

LOGIC

&

ADDRESS

DECODE

SERIAL-TO-

PARALLEL

CONVERTER

V

CC

AGND

VDDV

INPUT

REGISTER

1

INPUT

REGISTER

2

INPUT

REGISTER

3

INPUT

REGISTER

4

DGND

SS

DAC 1

LATCH

DAC 2

LATCH

DAC 3

LATCH

DAC 4

LATCH

LDAC

V

(–)

(+)

V

REF

REF

DAC 1

DAC 2

DAC 3

DAC 4

DSG

X1

V

1

OUT

X1

V

2

OUT

V

OUT

V

OUT

CLR

3

4

X1

X1

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

AD7835 FUNCTIONAL BLOCK DIAGRAM

V

VDDV

CC

BYSHF

DB13

DB0

WR

CS

AD7835

INPUT

BUFFER

A0

ADDRESS

A1

DECODE

A2

14

AGND

INPUT

REGISTER

1

INPUT

REGISTER

2

INPUT

REGISTER

3

INPUT

REGISTER

4

DGND

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

SS

DAC 1

LATCH

DAC 2

LATCH

DAC 3

LATCH

DAC 4

LATCH

LDAC

V

(–)A

(+)A

V

V

REF

REF

DAC 1

DAC 2

DAC 3

DAC 4

(–)B

DSG A

REF

X1

V

1

OUT

X1

V

2

OUT

X1

X1

DSG B

V

(+)B

REF

V

V

CLR

OUT

OUT

3

4

(VCC = +5 V  5%; VDD = +15 V  5%; VSS = –15 V  5%;

AD7834/AD7835

AD7834/AD7835–SPECIFICATIONS

P

arameter A B S Unit Test Conditions/Comments

AGND = DGND = 0 V; T

ACCURACY

Resolution 14 14 14 Bits
Relative Accuracy ±2 ±1 ±2 LSB max
Differential Nonlinearity ±0.9 ±0.9 ±0.9 LSB max Guaranteed Monotonic over Temperature
Full-Scale Error V

to T

T

MIN

MAX

±5 ±5 ±8 mV max
Zero-Scale Error ±4 ±4 ±5 mV max V
Gain Error ±0.5 ±0.5 ±0.5 mV typ V
Gain Temperature Coefficient

DC Crosstalk

2

2

444ppm FSR/∞C typ

20 20 20 ppm FSR/∞C max

50 50 50 mV max See Terminology. RL = 10 kW

REFERENCE INPUTS

DC Input Resistance 30 30 30 MW typ
Input Current ±1 ±1 ±1 mA max Per Input

(+) Range 0/+8.192 0/+8.192 0/+8.192 V min/max

V

REF

(–) Range –8.192/0 –8.192/0 –8.192/0 V min/max

V

REF

[V

REF

(+) – V

(–)] +5/+14 +7/+14 +5/+14 V min/max For Specified Performance. Can go as low as

REF

DEVICE SENSE GROUND INPUTS

Input Current ±2 ±2 ±2 mA max Per Input. V

DIGITAL INPUTS

, Input High Voltage 2.4 2.4 2.4 V min

V

INH

V

, Input Low Voltage 0.8 0.8 0.8 V max

INL

, Input Current ±10 ±10 ±10 mA max

I

INH

CIN, Input Capacitance 10 10 10 pF max

POWER REQUIREMENTS

V

CC

V

DD

V

SS

+5.0 +5.0 +5.0 V nom ±5% for Specified Performance

+15.0 +15.0 +15.0 V nom ±5% for Specified Performance

–15.0 –15.0 –15.0 V nom ±5% for Specified Performance
Power Supply Sensitivity

DFull Scale/DV
DFull Scale/DV

I

CC

DD

SS

110 110 110 dB typ

100 100 100 dB typ

0.2 0.2 0.5 mA max V

333mA max AD7834: V

666mA max AD7835: V
I

DD

13 13 15 mA max AD7834: Outputs Unloaded

15 15 15 mA max AD7835: Outputs Unloaded
I

SS

NOTES

1

Temperature range is as follows: A Version: –40∞C to +85∞C; B Version: –40∞C to +85∞ C.

2

Guaranteed by design.

Specifications subject to change without notice.

13 13 15 mA max Outputs Unloaded

1

= T

to T

A

MIN

(+) = +7 V, V

REF

(+) = +7 V, V

REF

(+) = +7 V, V

REF

, unless otherwise noted.)

MAX

(–) = –7 V

REF

(–) = –7 V

REF

(–) = –7 V

REF

0 V, but performance not guaranteed.

= –2 V to +2 V

DSG

= VCC, V

INH

= DGND

INL

= 2.4 V min, V

INH

= 2.4 V min, V

INH

= 0.8 V max

INL

= 0.8 V max

INL

(These characteristics are included for design guidance and are not

AC PERFORMANCE CHARACTERISTICS

P

arameter A B S Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 10 10 10 ms typ Full-Scale Change to ± 1/2 LSB. DAC latch contents

Digital-to-Analog Glitch Impulse 120 120 120 nV-s typ Measured with V

DC Output Impedance 0.5 0.5 0.5 W typ See Terminology
Channel-to-Channel Isolation 100 100 100 dB typ See Terminology; applies to the AD7835 only
DAC to DAC Crosstalk 25 25 25 nV-s typ See Terminology
Digital Crosstalk 3 3 3 nV-s typ Feedthrough to DAC Output under test due to

Digital Feedthrough – AD7834 0.2 0.2 0.2 nV-s typ Effect of Input Bus Activity on DAC Output Under Test
Digital Feedthrough – AD7835 1.0 1.0 1.0 nV-s typ
Output Noise Spectral Density
@ 1 kHz 40 40 40 nV/÷Hz typ All 1s Loaded to DAC. V

subject to production testing. )

alternately loaded with all 0s and all 1s

alternately loaded with all 0s and all 1s

change in digital input code to another converter.

–2–

REF

(+) = V

REF

(–) = 0 V. DAC latch

REF

(+) = V

(–) = 0 V

REF

REV. B

AD7834/AD7835

(VCC = +5 V  5%; VDD = +12 V  5%; VSS = –12 V  5%;

SPECIFICATIONS

P

arameter A B S Unit Test Conditions/Comments

AGND = DGND = 0 V; T

ACCURACY

Resolution 14 14 14 Bits
Relative Accuracy ±2 ± 1 ±2 LSB max
Differential Nonlinearity ±0.9 ± 0.9 ± 0.9 LSB max Guaranteed Monotonic over Temperature
Full-Scale Error V

to T

T

MIN

MAX

±5 ± 5 ±8 mV max
Zero-Scale Error ± 4 ± 4 ± 5 mV max V
Gain Error ±0.5 ± 0.5 ±0.5 mV typ V
Gain Temperature Coefficient

DC Crosstalk

2

2

444ppm FSR/∞C typ

20 20 20 ppm FSR/∞C max

50 50 50 mV max See Terminology. RL = 10 kW

REFERENCE INPUTS

DC Input Resistance 30 30 30 MW typ
Input Current ±1 ± 1 ±1 mA max Per Input

(+) Range 0/+8.192 0/+8.192 0/+8.192 V min/max

V

REF

(–) Range –5/0 –5/0 –5/0 V min/max

V

REF

[V

REF

(+) – V

(–)] +5/+13.192 +7/+13.192 +5/+13.192 V min/max For Specified Performance. Can Go as Low

REF

DEVICE SENSE GROUND INPUTS

Input Current ±2 ± 2 ±2 mA max Per Input. V

DIGITAL INPUTS

V

, Input High Voltage 2.4 2.4 2.4 V min

INH

, Input Low Voltage 0.8 0.8 0.8 V max

V

INL

, Input Current ±10 ±10 ± 10 mA max

I

INH

CIN, Input Capacitance 10 10 10 pF max

POWER REQUIREMENTS

V

CC

V

DD

V

SS

+5.0 +5.0 +5.0 V nom ±5% for Specified Performance

+15.0 +15.0 +15.0 V nom ± 5% for Specified Performance

–15.0 –15.0 –15.0 V nom ±5% for Specified Performance
Power Supply Sensitivity

DFull Scale/DV
DFull Scale/DV

I

CC

DD

SS

110 110 110 dB typ

100 100 100 dB typ

0.2 0.2 0.5 mA max V

333mA max AD7834: V

666mA max AD7835: V
I

DD

13 13 15 mA max AD7834: Outputs Unloaded

15 15 15 mA max AD7835: Outputs Unloaded
I

SS

NOTES

1

Temperature range is as follows: A Version: –40∞C to +85∞C; B Version: –40∞C to +85∞ C.

2

Guaranteed by design.

Specifications subject to change without notice.

13 13 15 mA max Outputs Unloaded

A

1

= T

MIN

to T

, unless otherwise noted.)

MAX

(+) = +5 V, V

REF

(+) = +5 V, V

REF

(+) = +5 V, V

REF

(–) = –5 V

REF

(–) = –5 V

REF

(–) = –5 V

REF

as 0 V, but Performance Not Guaranteed

= –2 V to +2 V

DSG

= VCC, V

INH

= DGND

INL

= 2.4 V min, V

INH

= 2.4 V min, V

INH

= 0.8 V max

INL

= 0.8 V max

INL

REV. B

–3–

AD7834/AD7835

)

TIMING SPECIFICATIONS

Parameter Limit at T

AD7834 Specific

2

t

1

2

t

2

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

21

1

(VCC = +5 V  5%; VDD = +11.4 V to +15.75 V; VSS = –11.4 V to –15.75 V; AGND = DGND = 0 V)

MIN, TMAX

Unit Description

100 ns min SCLK Cycle Time
50 ns min SCLK Low
30 ns min SCLK High Time
30 ns min FSYNC, PAEN Setup Time
40 ns min FSYNC, PAEN Hold Time
30 ns min Data Setup Time
10 ns min Data Hold Time
0 ns min LDAC to FSYNC Setup Time
40 ns min LDAC to FSYNC Hold Time
20 ns min Delay Between Write Operations

AD7835 Specific

t

11

t

12

t

13

t

14

t

15

t

16

t

17

t

18

t

19

t

20

15 ns min A0, A1, A2, BYSHF to CS Setup Time
15 ns min A0, A1, A2, BYSHF to CS Hold Time
0 ns min CS to WR Setup Time
0 ns min CS to WR Hold Time
40 ns min WR Pulsewidth
40 ns min Data Setup Time
10 ns min Data Hold Time
0 ns min LDAC to CS Setup Time
0 ns min CS to LDAC Setup Time
0 ns min LDAC to CS Hold Time

General

t

10

NOTES

1

All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

Rise and fall times should be no longer than 50 ns.

Specifications subject to change without notice.

40 ns min LDAC, CLR Pulsewidth

SCLK

FSYNC

DIN

(SIMULTANEOUS

LDAC

UPDATE)

LDAC

(PER-CHANNEL

UPDATE

1ST

2ND

CLK

CLK

t

4

t

7

MSB LSB

D23 D22

t

8

t

2

t

6

24TH

t

1

CLK

D1

t

D0

t

3

Figure 1. AD7834 Timing Diagram

A0 A1 A2

BYSHF

t

11

CS

t

13

5

t

21

t

10

t

9

(SIMULTANEOUS

(PER-CHANNEL

WR

DATA

LDAC

UPDATE)

LDAC

UPDATE)

t

t

15

t

16

18

t

12

t

14

t

17

t

10

t

19

t

20

Figure 2. AD7835 Timing Diagram

–4–

REV. B

AD7834/AD7835

ABSOLUTE MAXIMUM RATINGS

(TA = 25∞C unless otherwise noted.)

VCC to DGND3 . . . . . . . . . . . . . . –0.3 V, +7 V or V

1, 2

+ 0.3 V

DD

(Whichever Is Lower)

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V

V

DD

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V

SS

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +0.3 V

Digital Inputs to DGND . . . . . . . . . . . . . . –0.3 V, V

(+) to V

V

REF

V

(+) to AGND . . . . . . . . . . . . . . . V

REF

(–) to AGND . . . . . . . . . . . . . . . V

V

REF

DSG to AGND . . . . . . . . . . . . . . . . . V

V

(1–4) to AGND . . . . . . . . . . . . V

OUT

(–) . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V

REF

– 0.3 V, VDD + 0.3 V

SS

– 0.3 V, VDD + 0.3 V

SS

– 0.3 V, VDD + 0.3 V

SS

– 0.3 V, VDD + 0.3 V

SS

+ 0.3 V

CC

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . . . .–40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C

Plastic Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75∞C/W

␪

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 260∞C

SOIC Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75∞C/W

␪

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215∞C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

MQFP Package

␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 95∞C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215∞C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

PLCC Package

Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . 55∞C/W

␪

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215∞C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

Power Dissipation (Any Package) . . . . . . . . . . . . . . . . 480 mW

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch up.

3

VCC must not exceed VDD by more than 0.3 V. If it is possible for this to happen
during power supply sequencing, the following diode protection scheme will
ensure protection.

V

V

DD

CC

IN4148

SD103C

V

V

DD

CC

AD7834/

AD7835

ORDERING GUIDE

Temperature Linearity DNL Package

Model Range Error (LSBs) (LSBs) Option

AD7834AR –40∞C to +85∞C ± 2 ± 0.9 R-28
AD7834AR-REEL –40∞C to +85∞C ± 2 ± 0.9 R-28
AD7834BR –40∞C to +85∞C ± 1 ± 0.9 R-28
AD7834BR-REEL –40∞C to +85∞C ± 1 ± 0.9 R-28
AD7834AN –40∞C to +85∞C ± 2 ± 0.9 N-28
AD7834BN –40∞C to +85∞C ± 1 ± 0.9 N-28
AD7835AP
AD7835AP-REEL
AD7835AS
AD7835AS-REEL

NOTES

1

R = SOIC; N = Plastic DIP; S = Plastic Quad Flatpack (MQFP); P = Plastic Leaded Chip Carrier (PLCC).

2

Contact Sales Office for availability.

2

2

2

2

–40∞C to +85∞C ± 2 ± 0.9 P-44A
–40∞C to +85∞C ± 2 ± 0.9 P-44A
–40∞C to +85∞C ± 2 ± 0.9 S-44
–40∞C to +85∞C ± 2 ± 0.9 S-44

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7834/AD7835 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

1

WARNING!

ESD SENSITIVE DEVICE

REV. B

–5–

AD7834/AD7835

AD7834 PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

V

CC

V

SS

V

DD

DGND Digital Ground

AGND Analog Ground

V

(+) Positive Reference Input. The positive reference voltage is referred to AGND.

REF

V

(–)Negative Reference Input. The negative reference voltage is referred to AGND.

REF

V

1 to V

OUT

OUT

DSG Device Sense Ground Input. Used in conjunction with the CLR input for power-on protection of the DACs.

DIN Serial Data Input

SCLK Clock Input for writing data to the device. Data is clocked into the input register on the falling edge of SCLK.
FSYNC Frame Sync Input. Active low logic input used, in conjunction with DIN and SCLK, to write data to the device

PA0 to PA4 Package Address Inputs. These inputs are hardwired high (V

PAEN Package Address Enable Input. When low, this input allows normal operation of the device. When it is high, the

LDAC Load DAC Input (level sensitive). This input signal, in conjunction with the FSYNC input signal, determines

CLR Asynchronous Clear Input (level sensitive, active low). When this input is brought low, all analog outputs are

Logic Power Supply; +5 V ± 5%
Negative Analog Power Supply; –15 V ± 5% or –12 V ± 5%
Positive Analog Power Supply; +15 V ± 5% or +12 V ± 5%

4 DAC Outputs

When CLR is low, the DAC outputs are forced to the potential on the DSG pin.

with serial data expected after the falling edge of this signal. The contents of the 24-bit serial-to-parallel input
register are transferred on the rising edge of this signal.

) or low (DGND) to assign dedicated package

CC

addresses in a multipackage environment.

device ignores the package address (but not the channel address) in the serial data stream and loads the serial
data into the input registers. This feature is useful in a multipackage application where it can be used to load the
same data into the same channel in each package.

how the analog outputs are updated. If LDAC is maintained high while new data is being loaded into the
device’s input registers, no change occurs on the analog outputs. Subsequently, when LDAC is brought low, the
contents of all four input registers are transferred into their respective DAC latches, updating the analog outputs.

Alternatively, if LDAC is kept low while new data is shifted into the device, then the addressed DAC latch (and
corresponding analog output) is updated immediately on the rising edge of FSYNC.

switched to the externally set potential on the DSG pin. When CLR is brought high, the signal outputs remain at
the DSG potential until LDAC is brought low. When LDAC is brought low, the analog outputs are switched
back to reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are ignored
and the signal outputs remain switched to the potential on the DSG pin.

PIN CONFIGURATIONS

PDIP AND SOIC

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AGND

NC

NC

NC

NC

V

DD

V

OUT

V

OUT

CLR

LDAC

FSYNC

PAEN

PA4

PA3

1

3

V

REF

V

REF

V

V

DGND

V

DSG

NC

OUT

OUT

V

SCLK

DIN

PA0

PA1

PA2

SS

(–)

(+)

2

4

CC

1

2

3

4

5

AD7834

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

13

14

NC = NO CONNECT

–6–

REV. B

AD7834/AD7835

AD7835 PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

V

CC

V

SS

V

DD

DGND Digital Ground

AGND Analog Ground

V

V

V

REF

REF

OUT

(+)A, V

(+)B, V

1 to V

(–)A Reference Inputs for DACs 1 and 2. These reference voltages are referred to AGND.

REF

(–)B Reference Inputs for DACs 3 and 4. These reference voltages are referred to AGND.

REF

4 DAC Outputs

OUT

CS Level-Triggered Chip Select Input (active low). The device is selected when this input is low.

DB0 to DB13 Parallel Data Inputs. The AD7835 can accept a straight 14-bit parallel word on DB0 to DB13, where

BYSHF Byte Shift Input. When low, it shifts the data on DB0–DB7 into the DB8–DB13 half of the input register.

A0, A1, A2 Address Inputs. A0 and A1 are decoded to select one of the four input latches for a data transfer. A2 is

LDAC Load DAC Input (level sensitive). This input signal, in conjunction with the WR and CS input signals,

CLR Asynchronous Clear Input (level sensitive, active low). When this input is brought low, all analog outputs

WR Level-Triggered Write Input (active low). When active, it is used in conjunction with CS to write data

DSGA Device Sense Ground A Input. Used in conjunction with the CLR input for power-on protection of the

DSGB Device Sense Ground B Input. Used in conjunction with the CLR input for power-on protection of the

Logic Power Supply; +5 V ± 5%.
Negative Analog Power Supply; –15 V ± 5% or –12 V ± 5%
Positive Analog Power Supply; +15 V ±5 % or +12 V ± 5%

DB13 is the MSB and the BYSHF input is hardwired to a logic high. Alternatively for byte loading, the
bottom eight data inputs, DB0–DB7, are used for data loading, while the top six data inputs, DB8–DB13,
should be hardwired to a logic low. The BYSHF control input selects whether 8 LSBs or 6 MSBs of data
are being loaded into the device.

used to select all four DACs simultaneously.

determines how the analog outputs are updated. If LDAC is maintained high while new data is being
loaded into the device’s input registers, no change occurs on the analog outputs. Subsequently, when
LDAC is brought low, the contents of all four input registers are transferred into their respective DAC
latches, updating the analog outputs simultaneously.

Alternatively, if LDAC is brought low while new data is being entered, then the addressed DAC latch
(and corresponding analog output) is updated immediately on the rising edge of WR.

are switched to the externally set potentials on the DSG pins (V
V

OUT

3 and V

4 follow DSGB). When CLR is brought high, the signal outputs remain at the DSG

OUT

OUT

1 and V

2 follow DSGA while

OUT

potentials until LDAC is brought low. When LDAC is brought low, the analog outputs are switched back
to reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are ignored
and the signal outputs remain switched to the potential on the DSG pins.

over the input databus.

DACs. When CLR is low, DAC outputs V

DACs. When CLR is low, DAC outputs V

OUT

OUT

1 and V

3 and V

2 are forced to the potential on the DSGA pin.

OUT

4 are forced to the potential on the DSGB pin.

OUT

REV. B

–7–

AD7834/AD7835

NC

1

DSGA

2

V

1

3

OUT

V

2

4

OUT

NC

5

A2

6

A1

7

8

A0

CLR

9

LDAC

10

11

BYSHF

12 13 14 15 16 17 18 192021 22

NC = NO CONNECT

(–)A

REF

NC

V

PIN 1
IDENTIFIER

CS

WR

PIN CONFIGURATIONS

MQFP PLCC

(+)B

(+)A

REF

V

NC

40 39 3841424344 36 35 3437

AD7835

TOP VIEW

(Not to Scale)

CC

V

DGND

SS

V

DB0

DD

V

DB1

AGND

DB2

NC

DB3

REF

V

DB4

(–)B

REF

V

DB5

NC

DB6

NC

33

32

DSGB

V

3

31

OUT

V

4

30

OUT

DB13

29

DB12

28

27

DB11

DB10

26

25

DB9

24

DB8

23

DB7

NC

7

DSGA

8

V

1

9

OUT

V

10

2

OUT

NC

11

A2

12

13

A1

14

A0

CLR

15

LDAC

16

BYSHF

17

NC = NO CONNECT

(–)A

(+)A

REF

REF

V

NC

181920 21 22 23 24 252627 28

CS

WR

NC

V

(Not to Scale)

CC

V

DGND

SS

DD

V

AGND

V

2144345642414043

PIN 1
IDENTIFIER

AD7835

TOP VIEW

DB1

DB0

DB2

NC

DB3

(+)B

REF

V

DB4

(–)B

REF

V

DB5

NC

DB6

NC

39

DSGB

38

V

3

37

OUT

V

4

36

OUT

DB13

35

34

DB12

33

DB11

DB10

32

31

DB9

DB8

30

29

DB7

TERMINOLOGY
Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the maximum
deviation from a straight line passing through the endpoints of
the DAC transfer function. It is measured after adjusting for
zero error and full-scale error and is normally expressed in least
significant bits or as a percentage of full-scale reading.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.

DC Crosstalk

Although the common input reference voltage signals are inter­nally buffered, small IR drops in the individual DAC reference
inputs across the die can mean that an update to one channel
can produce a dc output change in one or other channel outputs.

The four DAC outputs are buffered by op amps that share com­mon V

and VSS power supplies. If the dc load current changes

DD

in one channel (due to an update), this can result in a further
dc change in one or channel outputs. This effect is most obvious
at high load currents and reduces as the load currents are reduced.
With high impedance loads the effect is virtually unmeasurable.

Output Voltage Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.

Digital-to-Analog Glitch Impulse

This is the amount of charge injected into the analog output when
the inputs change state. It is specified as the area of the glitch in
nV-secs. It is measured with the reference inputs connected to 0 V
and the digital inputs toggled between all 1s and all 0s.

Channel-to-Channel Isolation

Channel-to-channel isolation refers to the proportion of input
signal from one DACs reference input which appears at the
output of the other DAC. It is expressed in dBs.

The AD7834 has no specification for channel-to-channel isolation
because it has one reference for all DACs. Channel-to-channel
isolation is specified for the AD7835.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is defined as the glitch impulse that appears
at the output of one converter due to both the digital change and
subsequent analog O/P change at another converter. It is specified
in nV-s.

Digital Crosstalk

The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the digital crosstalk and is specified in nV-s.

Digital Feedthrough

When the device is not selected, high frequency logic activity on
its digital inputs can be capacitively coupled both across and
through the device to show up as noise on the V

pins. This

OUT

noise is digital feedthrough.

DC Output Impedance

This is the effective output source resistance. It is dominated by
package lead resistance.

Full-Scale Error

This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally, the output voltage, with all 1s
loaded into the DAC latch, should be V

(+) – 1 LSB. Full-scale

REF

error does not include zero-scale error.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC latch. Ideally, the output voltage,
with all 0s in the DAC latch, should be equal to V

REF

(–).

Zero-scale error is mainly due to offsets in the output amplifier.

Gain Error

Gain error is defined as (full-scale error) – (zero-scale error).

–8–

REV. B

Typical Performance Characteristics–

AD7834/AD7835

1.0

0.8

0.6

0.4

0.2

0.0

INL – LSB

–0.2

–0.4

–0.6

–0.8

–1.0

0216468101214

CODE/1000

TPC 1. Typical INL Plot

0.50

0.45

0.40

0.35

DAC 3

0.30

0.25
DAC 2

0.20

INL – LSB

0.15

0.10

0.05

TEMP = 25C
ALL DACs FROM 1 DEVICE

0

0 2.5 5.0

DAC 1

DAC 4

V

(+) – V

REF

TPC 4. Typical INL vs. V
(V

(+) – V

REF

(–) = 5 V)

REF

REF

(+)

8.0

0.5

0.4

0.3

0.2

0.1

0.0

–0.1

DNL – LSB

–0.2

–0.3

–0.4

–0.5

0216468101214

CODE/1000

TPC 2. Typical DNL Plot

0.8

0.7

0.6

DAC 3

0.5

0.4

INL – LSB

0.3

0.2
ALL DACs FROM ONE DEVICE

0.1

0
–40 +85+25

TEMPERATURE –



C

DAC 1

DAC 4

DAC 2

TPC 5. Typical INL vs. Temperature

0.9

0.8

0.7

0.6

0.5

0.4

INL – LSB

0.3

0.2

0.1

0

V

(+) – V

REF

TPC 3. Typical INL vs. V

(–) = –6 V)

(V

REF

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

DAC – LSB

–0.4

–0.6

–0.8

–1.0

0216468101214

CODE/1000

REF

801234 567

(+)

TPC 6. Typical DAC-to-DAC Matching

0.7

VERT = 100mV/DIV

0.6
HORIZ = 1s/DIV

0.5

0.4

0.3

0.2

VOLTS

0.1

0

–0.1

–0.2

TPC 7. Typical Digital/Analog
Glitch Impulse

8

6

4

2

VOLTS

0

–2

–4

VERT = 2V/DIV

HORIZ = 1.2s/DIV

V

(+) = +7V

REF

(–) = –3V

V

REF

VERT = 25mV/DIV

HORIZ = 2.5s/DIV

TPC 8. Settling Time (+)

7.250

7.225

7.200

7.175

7.150

7.125

7.100

VOLTS

8

6

4

V

(+) = +7V

REF

2

(–) = –3V

V

REF

VOLTS

0

–2

VERT = 2V/DIV
HORIZ = 1s/DIV

–4

0

TPC 9. Settling Time (–)

VERT = 10mV/DIV
HORIZ = 1s/DIV

–2.985

–3.005

–3.025

–3.045

–3.065

–3.085

–3.105

0

VOLTS

REV. B

–9–

AD7834/AD7835

(continued from page 1)

GENERAL DESCRIPTION
DAC Architecture—General

Each channel consists of a segmented 14-bit R-2R voltage-mode
DAC. The full-scale output voltage range is equal to the entire
reference span of V

REF

(+) – V
binary; all 0s produce an output of V
output of V

(+) – 1 LSB.

REF

(–). The DAC coding is straight

REF

(–); all 1s produce an

REF

The analog output voltage of each DAC channel reflects the con­tents of its own DAC latch. Data is transferred from the external
bus to the input register of each DAC latch on a per channel basis.
The AD7835 has a feature whereby using the A2 pin data can
be transferred from the input databus to all four input registers,
simultaneously.

Bringing the CLR line low switches all the signal outputs, V

4, to the voltage level on the DSG pin. The signal outputs

to V

OUT

OUT

1

are held at this level after the removal of the CLR signal and will
not switch back to the DAC outputs until the LDAC signal is
exercised.

Data Loading—AD7834, Serial Input Device

A write operation transfers 24 bits of data to the AD7834. The
first 8 bits are control data and the remaining 16 bits are DAC
data (see Figure 3). The control data identifies the DAC channel
to be updated with new data and which of 32 possible packages
the DAC resides in. In any communication with the device, the
first 8 bits must always be control data.

Note that the DAC output voltages, V

OUT

1 to V

OUT

4, can be

updated to reflect new data in the DAC input registers in one of
two ways. The first method normally keeps LDAC high and only
pulses LDAC low momentarily to update all DAC latches simul­taneously with the contents of their respective input registers. The
second method ties LDAC low and channel updating occurs on a
per channel basis after new data has been clocked into the AD7834.
With LDAC low, the rising edge of FSYNC transfers the new data
directly into the DAC latch, updating the analog output voltage.

Data being shifted into the AD7834 enters a 24-bit long shift
register. If more than 24 bits are clocked in before FSYNC goes
high, the last 24 bits transmitted are used as the control data
and DAC data.

Individual bit functions are discussed below.

D23: Determines whether the following 23 bits of address and
data should be used or should be ignored. This is effectively a

software chip select bit. D23 is the first bit to be transmitted in
the 24-bit long word.

Table I. D23 Control

D23 Control Function

0 Ignore following 23 bits of information.
1 Use following 23 bits of address and data as normal.

D22 and D21: Decoded to select one of the four DAC channels
within a device. The truth table for D22 and D21 is as shown
below in Table II.

Table II. D22, D21 Control

D22 D21 Control Function

00Select Channel 1
01Select Channel 2
10Select Channel 3
11Select Channel 4

D20–D16: Determines the package address. The five address bits
allow up to 32 separate packages to be individually decoded.
Successful decoding is accomplished when these five bits match
up with the five hardwired pins on the physical package.

D15–D0: DAC data to be loaded into the identified DAC input
register. This data must have two leading 0s followed by 14 bits
of data, MSB first. The MSB is in location D13 of the 24-bit
data stream.

Data Loading—AD7835, Parallel Loading Device

Data can be loaded into the AD7835 in either straight 14-bit
wide words or in two 8-bit bytes.

In systems that can transfer 14-bit wide data, the BYSHF input
should be hardwired to V

. This sets up the AD7835 as a

CC

straight 14-bit parallel-loading DAC.

In 8-bit bus systems where it is required to transfer data in
two bytes, it is necessary to have the BYSHF input under logic
control. In such a system, the top six pins of the device databus,
DB8–DB13, must be hardwired to DGND. New low byte data
is loaded into the lower eight places of the selected input register
by carrying out a write operation while holding BYSHF high.
A second write operation is subsequently executed with BYSHF
low and the 6 MSBs on the DB0–DB5 inputs (DB5 = MSB).

CONTROL BIT TO USE/IGNORE

FOLLOWING 23 BITS OF INFORMATION

CHANNEL ADDRESS MSB, D1

CHANNEL ADDRESS LSB, D2

PACKAGE ADDRESS MSB, PA4

PACKAGE ADDRESS, PA3

PACKAGE ADDRESS, PA2

PACKAGE ADDRESS, PA1

PACKAGE ADDRESS LSB, PA0

NOTE: D23 IS THE FIRST BIT TRANSMITTED IN THE SERIAL WORD.

D23 D22 D21

D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D20 D19

DB6

DB7

DB8

DB9

DB10

THIRD MSB, DB11

SECOND MSB, DB12

MSB, DB13

SECOND LEADING ZERO

FIRST LEADING ZERO

Figure 3. Bit Assignments for 24-Bit Data Stream of AD7834

–10–

DB5

DB4

THIRD LSB, DB2

DB3

LSB, DB0

SECOND LSB, DB1

REV. B

AD7834/AD7835

When 14-bit transfers are being used, the DAC output voltages,
V

OUT

1–V

4, can be updated to reflect new data in the DAC

OUT

input registers in one of two ways. The first method normally
keeps LDAC high and only pulses LDAC low momentarily to
update all DAC latches simultaneously with the contents of
their respective input registers. The second method ties LDAC
low and channel updating occurs on a per channel basis after
new data is loaded to an input register.

To avoid the DAC output going to an intermediate value during a
2-byte transfer, LDAC should not be tied low permanently but
should be held high until the two bytes are written to the input
register. When the selected input register has been loaded with the
two bytes, LDAC should then be pulsed low to update the DAC
latch and, hence, perform the digital-to-analog conversion.

In many applications, it may be acceptable to allow the DAC
output to go to an intermediate value during a 2-byte transfer.
In such applications, LDAC can be tied low, thus using one less
control line.

The actual DAC input register that is being written to is deter­mined by the logic levels present on the devices address lines, as
shown in Table III.

Table III. AD7835—Address Line Truth Table

A2 A1 A0 DAC Selected

00 0DAC 1
00 1DAC 2
01 0DAC 3
01 1DAC 4
1XXAll DACs Selected

Unipolar Configuration

Figure 4 shows the AD7834/AD7835 in the unipolar binary
circuit configuration. The V
the AD586, a 5 V reference. V

(+) input of the DAC is driven by

REF

(–) is tied to ground. Table IV

REF

gives the code table for unipolar operation of the AD7834/AD7835.

+15V +5V

2

AD586

4

SIGNAL

GND

6

5

8

C1

1nF

*

ADDITIONAL PINS OMITTED FOR CLARITY

R1
10k

V

REF

V

REF

V

DD

(+)

AD7834/
AD7835

(–)

V

–15V

SS

V

CC

V

*

AGND

DGND

OUT

V

(0 TO 5V)

SIGNAL

GND

OUT

Figure 4. Unipolar 5 V Operation

Offset and gain may be adjusted in Figure 4 as follows. To adjust
offset, disconnect the V
with all 0s, and adjust the V

(–) input from 0 V, load the DAC

REF

(–) voltage until V

REF

= 0 V. For

OUT

gain adjustment, the AD7834/AD7835 should be loaded with all
1s and R1 adjusted until V

= 5 V(16383 / 16384) = 4.999695.

OUT

Many circuits will not require these offset and gain adjustments.
In these circuits, R1 can be omitted. Pin 5 of the AD586 may
be left open circuit and Pin 2 (V

(–)) of the AD7834/AD7835

REF

tied to 0 V.

Table IV. Code Table for Unipolar Operation

Binary Number in DAC Latch Analog Output
MSB LSB (V

11 1111 1111 1111 V
10 0000 0000 0000 V
01 1111 1111 1111 V
00 0000 0000 0001 V

)

OUT

(16383 / 16384) V

REF

(8192 / 16384) V

REF

(8191 / 16384) V

REF

(1 / 16384) V

REF

00 0000 0000 0000 0 V

NOTE
V

= V

(+); V

REF

REF

For V

(+) = +5 V, 1 LSB = +5 V / 214 = +5 V / 16384 = 305 mV.

REF

(–) = 0 V for unipolar operation.

REF

Bipolar Configuration

Figure 5 shows the AD7834/AD7835 set up for ±5 V operation.
The AD588 provides precision ±5 V tracking outputs that are
fed to the V

(+) and V

REF

(–) inputs of the AD7834/AD7835.

REF

The code table for bipolar operation of the AD7834/AD7835 is
shown in Table V.

+15V

+5V

R1
39k

6

4

7

C1

1µF

9

AD588

R2

100k

100k

*

ADDITIONAL PINS OMITTED FOR CLARITY

5

10

11

12 8

R3

13

2

3

V

1

14

15

16

REF

V

REF

V

DD

(+)

AD7834/
AD7835

(–)

V

–15V

V

CC

V

V

OUT

*

AGND

DGND

SS

(–5 TO +5V)

SIGNAL

GND

OUT

Figure 5. Bipolar ±5 V Operation

Table V. Code Table for Bipolar Operation

Binary Number in DAC Latch Analog Output
MSB LSB (V

11 1111 1111 1111 V
10 0000 0000 0001 V
10 0000 0000 0000 V
01 1111 1111 1111 V
00 0000 0000 0001 V
00 0000 0000 0000 V

NOTE
V

= (V

REF

For V

REF

(+) – V

REF

(+) = +5 V and V

(–)).

REF

(–) = –5 V, 1 LSB = 10 V / 214 = 10 V / 16384 = 610 mV.

REF

OUT

REF

REF

REF

REF

REF

REF

)

(–) + V

(–) + V
(–) + V
(–) + V
(–) + V
(–) V

(16383 / 16384) V

REF

(8193 / 16384) V

REF

(8192 / 16384) V

REF

(8191 / 16384) V

REF

(1 / 16384) V

REF

In Figure 5, full-scale and bipolar zero adjustments are provided
by varying the gain and balance on the AD588. R2 varies the
gain on the AD588 while R3 adjusts the offset of both the +5 V
and –5 V outputs together with respect to ground.

For bipolar-zero adjustment, the DAC is loaded with 1000 . . . 0000
and R3 is adjusted until V

= 0 V. Full scale is adjusted

OUT

by loading the DAC with all 1s and adjusting R2 until

= 5(8191 / 8192) V = 4.99939 V.

V

OUT

When bipolar zero and full-scale adjustment are not needed,
R2 and R3 can be omitted. Pin 12 on the AD588 should be
connected to Pin 11, and Pin 5 should be left floating.

REV. B

–11–

AD7834/AD7835

CONTROLLED POWER-ON OF THE OUTPUT STAGE

A block diagram of the output stage of the AD7834/AD7835 is
shown in Figure 6. It is capable of driving a load of 10 kW in
parallel with 200 pF. G
used to control the power-on voltage present at V

are also used in conjunction with the CLR input to set V

G

2

to the user defined voltage present at the DSG pin.

DAC

Figure 6. Block Diagram of AD7834/AD7835 Output Stage

Power-On with CLR Low, LDAC High

The output stage of the AD7834/AD7835 has been designed to
allow output stability during power-on. If CLR is kept low during
power-on, then just after power is applied to the part, the situa­tion is as depicted in Figure 7. G

, G3, and G5 are closed.

G

2

DAC

Figure 7. Output Stage with VDD < 10 V

V

is kept within a few hundred millivolts of DSG via G5 and R.

OUT

R is a thin-film resistor between DSG and V
amplifier is connected as a unity gain buffer via G
voltage is applied to the buffer input via G
is thus at the same voltage as the DSG pin. The output stage
remains configured as in Figure 7 until the voltage at V

reaches approximately ±10 V. By now the output amplifier

V

SS

has enough headroom to handle signals at its input and has also
had time to settle. The internal power-on circuitry opens G

and closes G4 and G6. This situation is shown in Figure 8.

G

5

Now the output amplifier is connected in unity gain mode via

and G6. The DSG voltage is still applied to the noninverting

G

4

input via G

. This voltage appears at V

2

DAC

Figure 8. Output Stage with VDD > 10 V and

to G6 are transmission gates that are

1

G

1

G

3

G

2

DSG

G

1

G

2

DSG

G

1

G

2

DSG

G

5

G

3

G

5

G

3

G

5

G

6

G

4

R

, G4, and G6 are open while

1

G

6

G

4

R

. The output

OUT

. The amplifier’s output

2

.

OUT

G

6

G

4

R

. G1 and

OUT

OUT

V

OUT

V

OUT

and the DSG

3

and

DD

and

3

V

OUT

CLR

Low

V

has been disconnected from the DSG pin by the opening

OUT

of G

but will track the voltage present at DSG via the unity

5

gain buffer.

Power-On with LDAC Low, CLR High

In many applications of the AD7834/AD7835, LDAC will be
kept continuously low, updating the DAC after each valid data
transfer. If LDAC is low when power is applied, then G

is open, connecting the output of the DAC to the input

and G

2

of the output amplifier. G

and G5 will be closed and G4 and G

3

is closed

1

6

open, connecting the amplifier as a unity gain buffer, as before.

is connected to DSG via G5 and R (a thin-film resistance

V

OUT

between DSG and V

) until VDD and VSS reach approximately

OUT

±10 V. Then, the internal power-on circuitry opens G3 and G5 and
closes G

and G6. This is the situation shown in Figure 9. V

4

OUT

is

now at the same voltage as the DAC output.

G

DAC

1

G

3

G

2

DSG

G

5

Figure 9. Output Stage with

G

6

G

4

R

LDAC

Low

V

OUT

Loading the DAC and Using the CLR Input

When LDAC goes low, it closes G1 and opens G2 as in Figure 9.
The voltage at V

now follows the voltage present at the output

OUT

of the DAC. The output stage remains connected in this manner
until a CLR signal is applied. Then the situation reverts to that
shown in Figure 8. Once again V

remains at the same voltage

OUT

as DSG until LDAC goes low. This reconnects the DAC output
to the unity gain buffer.

DSG Voltage Range

During power-on, the V
connected to the relevant DSG pins via G

pins of the AD7834/AD7835 are

OUT

and the thin-film

6

resistor, R. The DSG potential must obey the max ratings at all
times. Thus, the voltage at DSG must always be within the
range V
the V

– 0.3 V, VDD + 0.3 V. However, to keep the voltages at

SS

pins of the AD7834/AD7835 within ±2 V of the relevant

OUT

DSG potential during power-on, the voltage applied to DSG
should also be kept within the range AGND – 2 V, AGND + 2 V.

Once the AD7834/AD7835 has powered on and the on-chip
amplifiers have settled, the situation is as shown as in Figure 8.
Any voltage that is now applied to the DSG pin is buffered by
the same amplifier that buffers the DAC output voltage in normal
operation. Thus, for specified operations, the maximum voltage
that can be applied to the DSG pin increases to the maximum
allowable V
applied to DSG is the minimum V

(+) voltage, and the minimum voltage that can be

REF

(–) voltage. After the

REF

AD7834/AD7835 has fully powered on, the outputs can track
any DSG voltage within this minimum/maximum range.

POWER-ON OF THE AD7834/AD7835

Power should normally be applied to the AD7834/AD7835 in
the following sequence: first V
V

REF

(+) and V

REF

(–).

and VSS, then VCC, and then

DD

–12–

REV. B

AD7834/AD7835

The V
applied to the part. (V
below V
below V
V

CC

pins should never be allowed to float when power is

REF

(–) – 0.3 V. V

REF

– 0.3 V. VDD should never be allowed to go below

SS

(+) should never be allowed to go

REF

(–) should never be allowed to go

REF

– 0.3 V.

In some systems, it may be necessary to introduce one or more
Schottky diodes between pins to prevent the above situations
arising at power-on. These diodes are shown in Figure 10.
However in most systems, with careful consideration given to
power supply sequencing, the above rules will be adhered to and
protection diodes won’t be necessary.

V

(+)

REF

*

AD7834

V

(–)

REF

*

ADDITIONAL PINS OMITTED FOR CLARITY

SD103C
1N5711
1N5712

Figure 10. Power-On Protection

MICROPROCESSOR INTERFACING
AD7834 to 80C51 Interface

A serial interface between the AD7834 and the 80C51 micro­controller is shown in Figure 11. TXD of the 80C51 drives SCLK
of the AD7834, while RXD drives the serial data line of the part.

The 80C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. The AD7834 expects the MSB of the
24-bit write first. Therefore, the user will have to ensure that the
data in the SBUF register is arranged correctly so that this is taken
into account. When data is to be transmitted to the part, P3.3 is
taken low. Data on RXD is valid on the falling edge of TXD.
The 80C51 transmits its data in 8-bit bytes with only 8 falling
clock edges occurring in the transmit cycle. To load data to the
AD7834, P3.3 is left low after the first 8 bits are transferred.
A second byte is then transferred, with P3.3 still kept low. After
the third byte has been transferred, the P3.3 line is taken high.

*

80C51

P3.5

P3.4

P3.3

TXD

RXD

*

ADDITIONAL PINS OMITTED FOR CLARITY

CLR

LDAC

FSYNC

SCLK

DIN

AD7834

*

Figure 11. AD7834 to 80C51 Interface

LDAC and CLR on the AD7834 are also controlled by 80C51
port outputs. The user can bring LDAC low after every 3 bytes
have been transmitted to update the DAC which has been
programmed. Alternatively, it is possible to wait until all the
input registers have been loaded (12 byte transmits) and then
update the DAC outputs.

AD7834 to 68HC11 Interface

Figure 12 shows a serial interface between the AD7834 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7834, while the MOSI output drives the serial data line,
DIN, of the AD7834. The FSYNC signal is derived from port
line PC7 in this example.

For correct operation of this interface, the 68HC11 should be
configured so that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transferred to the part, PC7 is taken low. When
the 68HC11 is configured like this, data on MOSI is valid on
the falling edge of SCK. The 68HC11 transmits its serial data in
8-bit bytes, MSB first. The AD7834 expects the MSB of the 24-bit
write first also. Eight falling clock edges occur in the transmit
cycle. To load data to the AD7834, PC7 is left low after the first
8 bits are transferred. A second byte of data is then transmitted
serially to the AD7834. Then a third byte is transmitted, and
when this transfer is complete, the PC7 line is taken high.

*

68HC11

PC5

PC6

PC7

SCK

MOSI

*

ADDITIONAL PINS OMITTED FOR CLARITY

CLR

LDAC

FSYNC

SCLK

DIN

AD7834

*

Figure 12. AD7834 to 68HC11 Interface

In Figure 12, LDAC and CLR are controlled by the PC6 and
PC5 port outputs. As with the 80C51, each DAC of the AD7834
can be updated after each 3 byte transfer or else all DACs can
be simultaneously updated after 12 bytes have been transferred.

AD7834 to ADSP-2101 Interface

An interface between the AD7834 and the ADSP-2101 is shown
in Figure 13. In the interface shown, SPORT0 is used to transfer
data to the part. SPORT1 is configured for alternate functions.
FO, the flag output on SPORT0, is connected to LDAC and is
used to load the DAC latches. In this way data can be transferred
from the ADSP-2101 to all the input registers in the DAC, and
the DAC latches can be updated simultaneously. In the application
shown, the CLR pin on the AD7834 is controlled by circuitry
that monitors the power in the system.

POWER

MONITOR

ADSP-2101

*

ADDITIONAL PINS OMITTED FOR CLARITY

*

FO

TFS

SCK

DT

CLR

LDAC

FSYNC

SCLK

DIN

AD7834

*

Figure 13. AD7834 to ADSP-2101 Interface

The AD7834 requires 24 bits of serial data framed by a single
FSYNC pulse. It is necessary that this FSYNC pulse stays low
until all the data has been transferred. This can be provided by the
ADSP-2101 in one of two ways. Both require setting the serial
word length of the SPORT to 12 bits, with the following condi­tions: internal SCLK, alternate framing mode and active low
framing signal. Data can be transferred using the autobuffering
feature of the ADSP-2101, sending two 12-bit words directly after
each other. This ensures a continuous TFS pulse. Alternatively,

REV. B

–13–

AD7834/AD7835

ADDITIONAL PINS OMITTED FOR CLARITY

*

ADDRESS

DECODE

D7

D0

A2

A1

A0

R/W

DATABUS

UPPER BITS OF

ADDRESS BUS

CONTROLLER/

DSP

PROCESSOR

*

A3

AD7835

*

D7

D0

CS

LDAC

A2
A1

A0

BYSHF

D13

D8

DGND

WR

the first data word can be loaded to the serial port, the subsequent
interrupt that is generated can be trapped, and then the second
data word can be sent immediately after the first. Again, this
produces a continuous TFS pulse that frames the 24 data bits.

AD7834 to DSP56000/DSP56001 Interface

Figure 14 shows a serial interface between the AD7834 and the
DSP56000/DSP56001. The serial port is configured for a word
length of 24 bits, gated clock and with FSL0 and FSL1 control
bits each set to 0. Normal mode synchronous operation is selected
which allows the use of SC0 and SC1 as outputs controlling
CLR and LDAC. The framing signal on SC2 has to be inverted
before being applied to FSYNC. SCK is internally generated on
the DSP56000/DSP56001 and is applied to SCLK on the
AD7834. Data from the DSP56000/DSP56001 is valid on the
falling edge of SCK.

DSP56000/
DSP56001

*

ADDITIONAL PINS OMITTED FOR CLARITY

*

SC0

SC1

SC2

SCK

STD

CLR

LDAC

FSYNC

SCLK

DIN

AD7834

*

Figure 14. AD7834 to DSP56000/DSP56001 Interface

AD7834 to TMS32020/TMS320C25 Interface

A serial interface between the AD7834 and the TMS32020/
TMS320C25 DSP processor is shown in Figure 15. The CLKX
and FSX signals for the TMS32020/TMS32025 should be
generated using an external clock/timer circuit. The CLKX and
FSX pins should be configured as inputs. The TMS32020/
TMS320C25 should be set up for an 8-bit serial data length.
Data can then be written to the AD7834 by writing 3 bytes to the
serial port of the TMS32020/TMS320C25. In the configuration
shown in Figure 15, the CLR input on the AD7834 is controlled
by the XF output on the TMS32020/TMS320C25. The
clock/timer circuit controls the LDAC input on the AD7834.
Alternatively, LDAC could also be tied to ground to allow automatic
update of the DAC latches after each transfer.

address lines from the processor are connected to A0, A1, and
A2 on the AD7835 as shown. The upper address lines are decoded
to provide a chip select signal for the AD7835. They are also
decoded (in conjunction with the lower address lines if need be)
to provide a LDAC signal. Alternatively, LDAC could be driven
by an external timing circuit or just tied low. The data lines of
the processor are connected to the data lines of the AD7835.
The selection of the DACs is as given in Table III.

CONTROLLER/

DSP

PROCESSOR

DATABUS

UPPER BITS OF

ADDRESS BUS

*

ADDITIONAL PINS OMITTED FOR CLARITY

*

D13

D0

R/W

ADDRESS

DECODE

A2
A1
A0

V

CC

BYSHF

D13

D0

CS

LDAC

A2
A1

A0

WR

AD7835

*

Figure 16. AD7835 16-Bit Interface

8-Bit Interface

Figure 17 shows an 8-bit interface between the AD7835 and a
generic 8-bit microcontroller/DSP processor. Pins D13 to D8 of
the AD7835 are tied to DGND. Pins D7 to D0 of the processor
are connected to pins D7 to D0 of the AD7835. BYSHF is
driven by the A0 line of the processor. This maps the DAC
upper bits and lower bits into adjacent bytes in the processor’s
address space. Table VI shows the truth table for addressing the
DACs in the AD7835. If, for example, the base address for the
DACs in the processor address space is decoded by the upper
address bits to location HC000, then the first DAC’s upper and
lower bits are at locations HC000 and HC001, respectively.

CLOCK/

TIMER

in this interface. The lower

CC

TMS32020/

TMS320C25

*

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 15. AD7834 to TMS32020/TMS320C25 Interface

Interfacing the AD7835—16-Bit Interface

The AD7835 can be interfaced to a variety of microcontrollers or
DSP processors, both 8-bit and 16-bit. Figure 16 shows the
AD7835 interfaced to a generic 16-bit microcontroller/DSP
processor. BYSHF is tied to V

*

XF

FSX

CLKX

DX

AD7834

LDAC

CLR

FSYNC

SCLK

DIN

*

Figure 17. AD7835 8-Bit Interface

When writing to the DACs, the lower eight bits must be written
first, followed by the upper six bits. The upper six bits should be
output on data lines D0 to D5. Once again, the upper address
lines of the processor are decoded to provide a CS signal. They
are also decoded in conjunction with lines A3 to A0 to provide a

–14–

REV. B

LDAC signal. Alternatively, LDAC can be driven by an external

ADDITIONAL PINS
OMITTED FOR CLARITY

*

AD7834

DEVICE 0

PAEN
LDAC
FSYNC

SCLK

DIN

PA0

PA1
PA2

PA3

PA4

V

CC

V

CC

CONTROLLER

CONTROL OUT

CONTROL OUT

SYNC OUT

SERIAL CLOCK OUT

SERIAL DATA OUT

AD7834

DEVICE 1

PAEN
LDAC
FSYNC

SCLK

DIN

PA0

PA1
PA2

PA3

PA4

AD7834

DEVICE 9

PAEN
LDAC
FSYNC

SCLK

DIN

PA0

PA1
PA2

PA3

PA4

*

*

*

timing circuit or, if it’s acceptable to allow the DAC output to
go to an intermediate value between 8-bit writes, LDAC can be
tied low.

Processor Address Lines
A3 A2 A1 A0 DAC Selected

1 XX0 Upper 6 Bits of All DACs
1 XX1 Lower 8 Bits of All DACs
0000 Upper 6 Bits, DAC 1
0001 Lower 8 Bits, DAC 1
0010 Upper 6 Bits, DAC 2
0011 Lower 8 Bits, DAC 2
0100 Upper 6 Bits, DAC 3
0101 Lower 8 Bits, DAC 3
0110 Upper 6 Bits, DAC 4
0111 Lower 8-Bits, DAC 4

APPLICATIONS

Serial Interface to Multiple AD7834s

Figure 18 shows how the package address pins of the AD7834
are used to address multiple AD7834s. The figure shows only
10 devices, but up to 32 AD7834s can each be assigned a unique
address by hardwiring each of the package address pins to V
or DGND. Normal operation of the device occurs when PAEN
is low. When serial data is being written to the AD7834s, only the
device with the same package address as the package address
contained in the serial data will accept data into the input regis­ters. If, on the other hand, PAEN is high, the package address is
ignored and the data is loaded into the same channel on each
package.

The main limitation with multiple packages is the output update
rate. For example, if an output update rate of 10 kHz is required,
then there are 100 ms to load all DACs. Assuming a serial clock
frequency of 10 MHz, it takes 2.5 ms to load data to one DAC.
Thus 40 DACs or 10 packages can be updated in this time. As
the update rate requirement decreases, the number of possible
packages increases.

Table VI. DAC Selection, 8-Bit Interface

CC

AD7834/AD7835

Figure 18. Serial Interface to Multiple AD7834s

Opto-Isolated Interface

In many process control applications it is necessary to provide an
isolation barrier between the controller and the unit being con­trolled. Opto-isolators can provide voltage isolation in excess of
3kV. The serial loading structure of the AD7834 makes it ideal
for opto-isolated interfaces as the number of interface lines is
kept to a minimum. Figure 19 shows a 5-channel isolated inter­face to the AD7834. Multiple devices are connected to the
outputs of the opto-coupler and controlled as explained above.
To reduce the number of opto-isolators, the PAEN line doesn’t
need to be controlled if it is not used. If the PAEN line is not
controlled by the microcontroller, then it should be tied low at
each device. If simultaneous updating of the DACs is not required,
then LDAC pin on each part can be tied permanently low and
a further opto-isolator is not needed.

V

CC

CONTROLLER

CONTROL OUT

CONTROL OUT

SYNC OUT

SERIAL CLOCK OUT

SERIAL DATA OUT

OPTO-COUPLER

Figure 19. Opto-Isolated Interface

TO PAENs

TO LDACs

TO FSYNCs

TO SCLKs

TO DINs

REV. B

–15–

AD7834/AD7835

Automated Test Equipment

The AD7834/AD7835 is particularly suited for use in an auto­mated test environment. Figure 20 shows the AD7835 providing
the necessary voltages for the pin driver and the window
comparator in a typical ATE pin electronics configuration. Two
AD588s are used to provide reference voltages for the AD7835.
In the configuration shown, the AD588s are configured so that
the voltage at Pin 1 is 5 V greater than the voltage at Pin 9, and
the voltage at Pin 15 is 5 V less than the voltage at Pin 9.

One of the AD588s is used as a reference for DACs 1 and 2. These
DACs are used to provide high and low levels for the pin driver.
The pin driver may have an associated offset. This can be nulled
by applying an offset voltage to Pin 9 of the AD588. First, the
code 1000 . . . 0000 is loaded into the DAC 1 latch and the pin
driver output is set to the DAC 1 output. The V

OFFSET

voltage is
adjusted until 0 V appears between the pin driver output and
DUT GND. This causes both V

(+)A and V

REF

with respect to AGND by an amount equal to V

(–)A to be offset

REF

OFFSET

. However,
the output of the pin driver will vary from –5 V to +5 V
with respect to DUT GND as the DAC input code varies from
000 . . . 000 to 111 . . . 111. The V

voltage is also applied

OFFSET

to the DSG A pin. When a clear is performed on the AD7835,
the output of the pin driver will be 0 V with respect to DUT GND.

+15V

4
6
8

AD588

13

7

1F

10 11 12

+15V

–15V

4

6

8

13

AD588

10

11

12

7

1F

*

ADDITIONAL PINS OMITTED FOR CLARITY

162

162

8

DUT
GND

OFFSET

3

1

15
14

9

3
1

15
14

0.1F

V

REF

V

REF

DSG A

V

REF

V

REF

(+)A

(–)A

AD7835

(+)B

(–)B

AGND

COMPARATOR

V

OUT

V

OUT

*

DSG B

V

OUT

V

OUT

WINDOW

+15V

1

PIN

DRIVER

2

–15V

DUT

GND

V

DUT

DUT
GND

3

4

TO TESTER

V

–15V

Figure 20. ATE Application

The other AD588 provides a reference voltage for DACs 3 and 4.
These provide the reference voltages for the window comparator
shown in the diagram. Note that Pin 9 of this AD588 is con­nected to DUT GND. This causes V

REF

(+)B and V

REF

(–)B to
be referenced to DUT GND. As DAC 3 and DAC 4 input codes
vary from 000 ...000 to 111 . . . 111, V

OUT

3 and V

OUT

4 vary
from –5V to +5 V with respect to DUT GND. DUT GND is
also connected to DSG B. When the AD7835 is cleared, V
and V

4 are cleared to 0 V with respect to DUT GND.

OUT

OUT

3

Care must be taken to ensure that the maximum and minimum
voltage specs for the AD7835 reference voltages are not broken
in the above configuration.

Power Supply Bypassing and Grounding

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD7834/AD7835 is mounted should be designed such that the
analog and digital sections are separated and confined to certain
areas of the board. This facilitates the use of ground planes that
can be separated easily. A minimum etch technique is generally
best for ground planes since it gives the best shielding. Digital
and analog ground planes should only be joined at one place. If
the AD7834/AD7835 is the only device requiring an AGND to
DGND connection, then the ground planes should be connected
at the AGND and DGND pins of the AD7834/AD7835. If the
AD7834/AD7835 is in a system where multiple devices require
an AGND to DGND connection, the connection should still be
made at one point only, a star ground point, which should be
established as close as possible to the AD7834/AD7835.

Digital lines running under the device should be avoided as these
will couple noise onto the die. The analog ground plane should be
allowed to run under the AD7834/AD7835 to avoid noise cou­pling. The power supply lines of the AD7834/AD7835 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching signals, such as clocks, should be shielded with digital
ground to avoid radiating noise to other parts of the board and
should never be run near the analog inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects
of feedthrough through the board. A microstrip technique is by
far the best but not always possible with a double sided board.
In this technique, the component side of the board is dedicated
to ground plane while signal traces are placed on the solder side.

The AD7834/AD7835 should have ample supply bypassing
located as close to the package as possible, ideally right up against
the device. Figure 21 shows the recommended capacitor values of
10 mF in parallel with 0.1 mF on each of the supplies. The 10 mF
capacitors are the tantalum bead type. The 0.1 mF capacitor
should have low Effective Series Resistance (ESR) and Effective
Series Inductance (ESI), such as the common ceramic types,
which provide a low impedance path to ground at high frequen­cies to handle transient currents due to internal logic switching.

V

V

CC

DGND

10F

0.1F

*

ADDITIONAL PINS OMITTED FOR CLARITY

AD7834/

AD7835

DD

0.1F

10F

*

V

SS

0.1F

AGND

10F

Figure 21. Power Supply Decoupling

–16–

REV. B

OUTLINE DIMENSIONS

28-Lead Standard Small Outline Package [SOIC]

Wide Body

(R-28)

Dimensions shown in millimeters and (inches)

18.10 (0.7126)

17.70 (0.6969)

AD7834/AD7835

0.048 (1.22)

0.042 (1.07)

0.048 (1.22)

0.042 (1.07)

6

7

17

18

28 15

1

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

1.27 (0.0500)

COMPLIANT TO JEDEC STANDARDS MS-013AE

BSC

0.51 (0.0201)

0.33 (0.0130)

14

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

7.60 (0.2992)

7.40 (0.2913)

0.32 (0.0126)

0.23 (0.0091)

44-Lead Plastic Leaded Chip Carrier [PLCC]

(P-44A)

Dimensions shown in inches and (millimeters)

0.180 (4.57)

0.165 (4.19)

0.056 (1.42)

0.042 (1.07)

40

PIN 1

IDENTIFIER

TOP VIEW

(PINS DOWN)

0.656 (16.66)

0.650 (16.51)

0.695 (17.65)

0.685 (17.40)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

39

0.050
(1.27)
BSC

29

28

SQ

SQ

COMPLIANT TO JEDEC STANDARDS MO-047AC

0.120 (3.05)

0.090 (2.29)

0.020 (0.51)
MIN

0.021 (0.53)

0.013 (0.33)

0.032 (0.81)

0.026 (0.66)

0.040 (1.02)

0.025 (0.64)

10.65 (0.4193)

10.00 (0.3937)

0.75 (0.0295)

0.25 (0.0098)

8
0

0.630 (16.00)

0.590 (14.99)

 45

1.27 (0.0500)

0.40 (0.0157)

BOTTOM VIEW

(PINS UP)

REV. B

–17–

AD7834/AD7835

OUTLINE DIMENSIONS

28-Lead Plastic Dual In-Line Package [PDIP]

(N-28)

Dimensions shown in inches and (millimeters)

1.565 (39.7)

1.380 (35.1)

28

1

15

0.580 (14.73)

0.485 (12.32)

14

0.250 (6.35)
MAX

0.200 (5.05)

0.115 (2.93)

0.100 (2.54)
BSC

0.022 (0.558)

0.014 (0.356)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-011AB

0.015 (0.39)
MIN

0.70 (1.77)

0.30 (0.77)

SEATING
PLANE

0.625 (15.87)

0.600 (15.24)

0.015 (0.381)

0.008 (0.204)

44-Lead Metric Quad Flat Package [MQFP]

(S-44)

Dimensions shown in millimeters

33

13.20 BSC SQ

10.00 BSC SQ

TOP VIEW

(PINS DOWN)

23

1.03

0.88

0.73

SEATING

PLANE

COPLANARITY

0.10

2.45
MAX

0.8

8

34

22

0.195 (4.95)

0.125 (3.18)

PIN 1

44

2.20

0.25 MAX

COMPLIANT TO JEDEC STANDARDS MS-022-AB

2.00

1.80

1

0.80
BSC

–18–

12

11

0.45

0.29

REV. B

AD7834/AD7835

Revision History

Location Page

7/03—Data Sheet changed from REV. A to REV. B.

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to AC PERFORMANCE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Update ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Changes to AD7834 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to AD7835 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Changed Figures to TPCs per Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Updated Figure Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–16

Removed 28-Leaded CERDIP (Q-28) Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

REV. B

–19–

AD7834/AD7835

C01006–0–7/03(B)

–20–

REV. B