Datasheet AD7829-1 Datasheet (ANALOG DEVICES)

V

V

V

V

V

V

V

V

V

FEATURES

8-bit half-flash ADC with 420 ns conversion time
Eight single-ended analog input channels

Available with input offset adjust
On-chip track-and-hold
SNR performance given for input frequencies

up to10 MHz
On-chip reference (2.5 V)
Automatic power-down at the end of conversion
Wide operating supply range

3 V ± 10% and 5 V ± 10%
Input ranges

0 V to 2 V p-p, V

0 V to 2.5 V p-p, V

Flexible parallel interface with

stand-alone operation

APPLICATIONS

Data acquisition systems, DSP front ends
Disk drives
Mobile communication systems, subsampling

applications

GENERAL DESCRIPTION

= 3 V ± 10%

DD

= 5 V ± 10%

DD

EOC

pulse to allow

3 V/5 V, 2 MSPS, 8-Bit, 8-Channel ADC

AD7829-1

FUNCTIONAL BLOCK DIAGRAM

COMP

BUF

PARALLEL

PORT

RD

CS

DD

2.5V
REF

V

REF IN/OUT

DB7
DB0

06179-001

CONVST

EOC

A0 A1 A2

CONTROL

LOGIC

IN1
IN2
IN3

INPUT

IN4
IN5
IN6
IN7
IN8

MUX

T/H

V

MID

AGND

8-BIT
HALF

FLASH

ADC

Figure 1.

DGND

The AD7829-1 is a high speed 8-channel, microprocessor­compatible, 8-bit analog-to-digital converter with a maximum
throughput of 2 MSPS. The AD7829-1 contains an on-chip
reference of 2.5 V (2% tolerance); a track-and-hold amplifier;
a 420 ns, 8-bit half-flash ADC; and a high speed parallel
interface. The converter can operate from a single 3 V ± 10%
and 5 V ± 10% supply.

The AD7829-1 combines the convert start and power-down
functions at one pin, that is, the

CONVST

pin. This allows a
unique automatic power-down at the end of a conversion to be
implemented. The logic level on the
after the end of a conversion when an

CONVST

EOC

pin is sampled

(end of conversion)
signal goes high, and if it is logic low at that point, the ADC is
powered down. The parallel interface is designed to allow easy
interfacing to microprocessors and DSPs. Using only address
decoding logic, the parts are easily mapped into the microprocessor
address space.

EOC

The

pulse allows the ADCs to be used in a stand-alone

manner (see the Parallel Interface section).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The AD7829-1 is available in a 28-lead, wide body, small outline
IC (SOIC_W) and a 28-lead thin shrink small outline package
(TSSOP).

PRODUCT HIGHLIGHTS

1. Fast Conversion Time. The AD7829-1 has a conversion

time of 420 ns. Faster conversion times maximize the DSP
processing time in a real-time system.

2. Analog Input Span Adjustment. The V

user to offset the input span. This feature can reduce the
requirements of single-supply op amps and take into
account any system offsets.

3. FPBW (Full Power Bandwidth) of Track-and-Hold. The

track-and-hold amplifier has excellent high frequency
performance. The AD7829-1 is capable of converting full­scale input signals up to a frequency of 10 MHz, making
the parts ideally suited to subsampling applications.

4. Channel Selection. Channel selection is made without the

necessity of writing to the part.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

pin allows the

MID

AD7829-1

TABLE OF CONTENTS

Features.............................................................................................. 1

Typical Connection Diagram ................................................... 10

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Timing Diagram........................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Terminology ...................................................................................... 8

Circuit Information........................................................................ 10

Circuit Description..................................................................... 10

ADC Transfer Function............................................................. 11

Analog Input............................................................................... 11

Power-Up Times......................................................................... 14

Power vs. Throughput................................................................ 14

Operating Modes........................................................................ 15

Parallel Interface......................................................................... 17

Microprocessor Interfacing........................................................... 18

AD7829-1 to 8051 ...................................................................... 18

AD7829-1 to PIC16C6x/PIC16C7x......................................... 18

AD7829-1 to ADSP-21xx.......................................................... 18

Interfacing Multiplexer Address Inputs .................................. 18

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

7/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD7829-1

SPECIFICATIONS

VDD = 3 V ± 10%, VDD = 5 V ± 10%, GND = 0 V, V

REF IN/OUT

Table 1.

Parameter Version B Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 30 kHz, f

Signal to (Noise + Distortion) Ratio
Total Harmonic Distortion

1

Peak Harmonic or Spurious Noise
Intermodulation Distortion

1

1

1

2nd Order Terms −65 dB typ
3rd Order Terms −65 dB typ

Channel-to-Channel Isolation

1

DC ACCURACY

Resolution 8 Bits
Minimum Resolution for Which

No Missing Codes Are Guaranteed
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Gain Error
Gain Error Match
Offset Error

1

1

1

Offset Error Match

ANALOG INPUTS

2

1

1

1

VDD = 5 V ± 10% Input voltage span = 2.5 V

V

to V

IN1

Input Voltage VDD V max

IN8

0 V min
V

Input Voltage VDD − 1.25 V max Default V

MID

1.25 V min

VDD = 3 V ± 10% Input voltage span = 2 V

V

to V

IN1

Input Voltage VDD V max

IN8

0 V min
V

Input Voltage VDD − 1 V max Default V

MID

1 V min
VIN Input Leakage Current ±1 µA max
VIN Input Capacitance 15 pF max
V

Input Impedance 6 kΩ typ

MID

REFERENCE INPUT

V

Input Voltage Range 2.55 V max 2.5 V + 2%

REF IN/OUT

2.45 V min 2.5 V − 2%
Input Current 1 A typ
100 A max

ON-CHIP REFERENCE Nominal 2.5 V

Reference Error ±50 mV max
Temperature Coefficient 50 ppm/°C typ

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input High Voltage, V
Input Low Voltage, V

2.4 V min VDD = 5 V ± 10%

INH

0.8 V max VDD = 5 V ± 10%

INL

2 V min VDD = 3 V ± 10%

INH

0.4 V max VDD = 3 V ± 10%

INL

Input Current, IIN ±1 A max Typically 10 nA, VIN = 0 V to VDD
Input Capacitance, CIN 10 pF max

= 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.

= 2 MHz

SAMPLE

48 dB min

−55 dB max

−55 dB max
fa = 27.3 kHz, fb = 28.3 kHz

−70 dB typ fIN = 20 kHz

8 Bits

±0.75 LSB max
±0.75 LSB max
±2 LSB max
±0.1 LSB typ
±1 LSB max
±0.1 LSB typ
See Analog Input section

= 1.25 V

MID

= 1 V

MID

Rev. 0 | Page 3 of 20

AD7829-1

Parameter Version B Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, VOH I
4 V min VDD = 5 V ± 10%

2.4 V min VDD = 3 V ± 10%
Output Low Voltage, VOL I

0.4 V max VDD = 5 V ± 10%

0.2 V max VDD = 3 V ± 10%
High Impedance Leakage Current ±1 A max
High Impedance Capacitance 10 pF max

CONVERSION RATE

Track/Hold Acquisition Time 200 ns max See Circuit Description section
Conversion Time 420 ns max

POWER SUPPLY REJECTION

VDD ± 10% ±1 LSB max

POWER REQUIREMENTS

VDD 4.5 V min 5 V ± 10%; for specified performance

5.5 V max
VDD 2.7 V min 3 V ± 10%; for specified performance

3.3 V max
IDD

Normal Operation 12 mA max 8 mA typically
Power-Down 5 A max Logic inputs = 0 V or VDD

0.2 A typ
Power Dissipation VDD = 3 V

Normal Operation 36 mW max Typically 24 mW
Power-Down

200 kSPS 9.58 mW typ
500 kSPS 23.94 mW typ

1

See the Terminology section of this data sheet.

2

Refer to the Analog Input section for an explanation of the analog input(s).

= 200 A

SOURCE

= 200 A

SINK

Rev. 0 | Page 4 of 20

AD7829-1

TIMING CHARACTERISTICS

V

Table 2.

Parameter

t1 420 420 ns max Conversion time
t2 20 20 ns min
t3 30 30 ns min

t4 110 110 ns max
70 70 ns min

t5 10 10 ns max
t6 0 0 ns min
t7 0 0 ns min
t8 30 30 ns min

3

t

9

t

10

20 20 ns max
t11 10 10 ns min
t12 15 15 ns min

t13 200 200 ns min Minimum time between new channel selection and convert start
t

POWER UP

t

POWER UP

1

Sample tested to ensure compliance.

2

See Figure 21, Figure 22, and Figure 23.

3

Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V with VDD = 5 V ± 10%, and the time required for an

output to cross 0.4 V or 2.0 V with VDD = 3 V ± 10%.

4

Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time
of the part and, as such, is independent of external bus loading capacitances.

= 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.

REF IN/OUT

1, 2

5 V ± 10% 3 V ± 10% Unit Description

Minimum CONVST
Minimum time between the rising edge of RD

pulse width

EOC

rising edge to EOC pulse high

RD

to RD setup time

CS

to RD hold time

CS
Minimum RD

10 20 ns max

4

5 5 ns min

Data access time after RD
Bus relinquish time after RD

Address setup time before the falling edge of RD
Address hold time after the falling edge of RD

25 25 μs typ
1 1 μs max

Power-up time from the rising edge of CONVST
Power-up time from the rising edge of CONVST

pulse width

and the next falling edge of convert start

pulse width

low

high

using on-chip reference
using external 2.5 V reference

TIMING DIAGRAM

200µA I

TO OUTPUT

PIN

C

L

50pF

200µA I

Figure 2. Load Circuit for Access Time and Bus Relinquish Time

OL

2.1V

OH

06179-002

Rev. 0 | Page 5 of 20

AD7829-1

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

V

to AGND −0.3 V to +7 V

DD

V

to DGND −0.3 V to +7 V

DD

Analog Input Voltage to AGND

V

to V

IN1

−0.3 V to V

IN8

−0.3 V to V

V

Input Voltage to AGND −0.3 V to VDD + 0.3 V

MID

−0.3 V to V

−0.3 V to V

+ 0.3 V

DD

+ 0.3 V Reference Input Voltage to AGND

DD

+ 0.3 V Digital Input Voltage to DGND

DD

+ 0.3 V Digital Output Voltage to DGND

DD

Operating Temperature Range

−40°C to +85°C Industrial (B Version)

−65°C to +150°C Storage Temperature Range
150°C Junction Temperature

SOIC Package, Power Dissipation 450 mW

θ

Thermal Impedance 75°C/W

JA

Lead Temperature, Soldering

215°C Vapor Phase (60 sec)
220°C Infrared (15 sec)

TSSOP Package, Power Dissipation 450 mW

θ

Thermal Impedance 128°C/W

JA

Lead Temperature, Soldering

215°C Vapor Phase (60 sec)
220°C Infrared (15 sec)

ESD 1 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 20

AD7829-1

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DB2 1

2

DB1

DB0 3

CONVST 4

5

CS

AD7829-1

RD 6 AGND23

DGND 7 V

EOC

V

V

V

TOP VIEW

(Not to Scale)

8

A2 9 V

A1 10 V

11

A0

12

IN8

13

IN7

14

IN6

27

24

22

21

20

19

18

17

16

15

DB328

DB4

DB526

DB625

DB7

DD

V

REF IN/OUT

MID

IN1

V

IN2

V

IN3

V

IN4

V

IN5

06179-003

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

12 to 19 V

IN8

to V

IN1

Analog Input Channels. The AD7829-1 has eight analog input channels. The inputs have an input span of 2.5 V
and 2 V, depending on the supply voltage (V
using the V
(V

= 5 V ± 10%). See the Analog Input section of the data sheet for more information.

DD

pin. The default input range (V

MID

). This span can be centered anywhere in the range AGND to VDD

DD

unconnected) is AGND to 2 V (VDD = 3 V ± 10%) or AGND to 2.5 V

MID

22 VDD Positive Supply Voltage, 3 V ± 10% and 5 V ± 10%.
23 AGND Analog Ground. Ground reference for track/hold, comparators, reference circuit, and multiplexer.
7 DGND Digital Ground. Ground reference for digital circuitry.
4

CONVST Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge

of this signal. The falling edge of this signal places the track/hold in hold mode. The track/hold goes into track
mode again 120 ns after the start of a conversion. The state of the

CONVST signal is checked at the end of a

conversion. If it is logic low, the AD7829-1 powers down (see the Operating Modes section).

8

EOC Logic Output. The end of conversion signal indicates when a conversion has finished. The signal can be used

to interrupt a microcontroller when a conversion has finished or latch data into a gate array (see the
Interface

5

CS Logic Input Signal. The chip select signal is used to enable the parallel port of the AD7829. This is necessary

section).

if the ADC is sharing a common data bus with another device.

6

RD Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and drive

data onto the data bus. The signal is internally gated with the CS signal. Both

RD and CS must be logic low to

enable the data bus.

9 to 11 A2 to A0

1 to 3,
24 to 28

21 V

DB2 to DB0,
DB7 to DB3

REF IN/OUT

Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when

RD signal goes low.

the
Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when

both

RD and CS go active low.

Analog Input and Output. An external reference can be connected to the AD7829-1 at this pin. The on-chip
reference is also available at this pin. When using the internal reference, this pin can be left unconnected or,
in some cases, it can be decoupled to AGND with a 0.1 µF capacitor.

20 V

MID

The V
(see the

pin, if connected, is used to center the analog input span anywhere in the range of AGND to VDD

MID

Analog Input section).

Parallel

Rev. 0 | Page 7 of 20

AD7829-1

TERMINOLOGY

Signal-to-(Noise + Distortion) Ratio

The measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f

/2), excluding dc.

S

The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal-to-(noise +
distortion) ratio for an ideal N-bit converter with a sine wave
input is given by

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Thus, for an 8-bit converter, this is 50 dB.

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental.
For the AD7829-1 it is defined as

22222

++++

VVVVV

54

THD

log20)dB(

=

32

V

1

6

where V1 is the rms amplitude of the fundamental, and V2, V3,

, V5, and V6 are the rms amplitudes of the second through the

V

4

sixth harmonics.

As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the fundamental expressed in decibels (dB).

Channel-to-Channel Isolation

A measure of the level of crosstalk between channels. It is
measured by applying a full-scale 20 kHz sine wave signal to
one input channel and determining how much that signal is
attenuated in each of the other channels. The figure given is
the worst case across all eight channels of the AD7829-1.

Relative Accuracy or Endpoint Nonlinearity

The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Offset Error

The deviation of the 128th code transition (01111111) to
(10000000) from the ideal, that is, V

MID

.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the
ADC output spectrum (up to f

/2 and excluding dc) to the rms

S

value of the fundamental. Normally, the value of this specifica­tion is determined by the largest harmonic in the spectrum,
but for parts where the harmonics are buried in the noise floor,
it will be a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = 0, 1, 2, 3… . Intermodulation terms are those for which
neither m nor n is equal to zero. For example, the second order
terms include (fa + fb) and (fa − fb), while the third order terms
include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The
AD7829-1 is tested using the CCIF standard, where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second and third order terms are of different
significance. The second order terms are usually distanced in
frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.

Offset Error Match

The difference in offset error between any two channels.

Zero-Scale Error

The deviation of the first code transition (00000000) to
(00000001) from the ideal; that is, V
5 V ± 10%), or V

− 1.0 V + 1 LSB (VDD = 3 V ± 10%).

MID

− 1.25 V + 1 LSB (VDD =

MID

Full-Scale Error

The deviation of the last code transition (11111110) to
(11111111) from the ideal; that is, V
5 V ± 10%), or V

+ 1.0 V − 1 LSB (VDD = 3 V ± 10%).

MID

+ 1.25 V − 1 LSB (VDD =

MID

Gain Error

The deviation of the last code transition (1111 . . . 110) to
(1111 . . . 111) from the ideal; that is, V

− 1 LSB, after the

REF

offset error has been adjusted out.

Gain Error Match

The difference in gain error between any two channels.

Rev. 0 | Page 8 of 20

AD7829-1

Trac k / Hold Ac q u isiti o n Ti me

The time required for the output of the track/hold amplifier to
reach its final value, within ±1/2 LSB, after the point at which
the track/hold returns to track mode. This happens approxi­mately 120 ns after the falling edge of

CONVST

.

It also applies to situations where a change in the selected input
channel takes place or where there is a step input change on the
input voltage applied to the selected V

input of the AD7829-1.

IN

It means that the user must wait for the duration of the
track/hold acquisition time after a channel change/step input
change to V

before starting another conversion, to ensure that

IN

the part operates to specification.

PSR (Power Supply Rejection)

Variations in power supply affect the full-scale transition
but not the converter’s linearity. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.

Rev. 0 | Page 9 of 20

AD7829-1

CIRCUIT INFORMATION

CIRCUIT DESCRIPTION

The AD7829-1 consists of a track-and-hold amplifier followed
by a half-flash analog-to-digital converter. These devices use a
half-flash conversion technique where one 4-bit flash ADC is
used to achieve an 8-bit result. The 4-bit flash ADC contains a
sampling capacitor followed by 15 comparators that compare
the unknown input to a reference ladder to achieve a 4-bit result.
This first flash, that is, coarse conversion, provides the four
MSBs. For a full 8-bit reading to be realized, a second flash,
that is, a fine conversion, must be performed to provide the four
LSBs. The 8-bit word is then placed on the data output bus.

Figure 4 and Figure 5 show simplified schematics of the ADC.
When the ADC starts a conversion, the track-and-hold goes
into hold mode and holds the analog input for 120 ns. This is
the acquisition phase as shown in
Position A. At the point when the track-and-hold returns to its
track mode, this signal is sampled by the sampling capacitor as
Switch 2 moves into Position B. The first flash occurs at this
instant and is then followed by the second flash. Typically, the
first flash is complete after 100 ns, that is, at 220 ns, while the
end of the second flash and, hence, the 8-bit conversion result,
is available at 330 ns (minimum). The maximum conversion
time is 420 ns. As shown in
to track mode after 120 ns and starts the next acquisition before
the end of the current conversion.
transfer function.

REFERENCE

Figure 4, when Switch 2 is in

Figure 6, the track-and-hold returns

Figure 8 shows the ADC

T/H 1

V

IN

CONVST

EOC

CS

RD

DB0 TO DB7

REFERENCE

SW2

A

B

HOLD

TIMING AND

CONTROL

TRACK

R16

15

R15

R14

R13

14

LOGIC

DECODE

13

1

R1

OUTPUT

REGISTER

SAMPLING

CAPACITOR

LOGIC

Figure 5. ADC Conversion Phase

120ns

HOLD HOLD

t

2

t

1

TRACK

VALID
DATA

t

3

Figure 6. Track-and-Hold Timing

D7

D6

D5

D4

D3

OUTPUT

DRIVERS

D2

D1

D0

06179-006

06179-007

TYPICAL CONNECTION DIAGRAM

R16

15

SW2

A

T/H 1

V

IN

HOLD

B

TIMING AND

CONTROL

LOGIC

R15

SAMPLING

CAPACITOR

R14

R13

14

LOGIC

DECODE

13

1

R1

OUTPUT

REGISTER

D7

D6

D5

D4

D3

OUTPUT

DRIVERS

D2

D1

D0

06179-005

Figure 4. ADC Acquisition Phase

Rev. 0 | Page 10 of 20

Figure 7 shows a typical connection diagram for the AD7829-1.
The AGND and DGND are connected together at the device for
good noise suppression. The parallel interface is implemented
using an 8-bit data bus. The end of conversion signal (
high, the falling edge of

CONVST

the end of conversion the falling edge of

initiates a conversion, and at

EOC

EOC

) idles

is used to initiate
an interrupt service routine (ISR) on a microprocessor (see the
Parallel Interface section). V
voltage source, such as the AD780, while V
voltage source that can vary from 4.5 V to 5.5 V (see
the

Analog Input section). When VDD is first connected, the

REF IN/OUT

and V

are connected to a

MID

is connected to a

DD

Tabl e 5 in

AD7829-1 powers up in a low current mode, that is, power-down.
Ensure that the

CONVST

line is not floating when VDD is applied,

because this can put the AD7829-1 into an unknown state.

AD7829-1

4

V

A suggestion is to tie
pull-up or pull-down resistor. A rising edge on the
pin causes the AD7829-1 to fully power up. For applications

where power consumption is of concern, the automatic power­down at the end of a conversion should be used to improve
power performance (see the
If the AD7829-1 is operated outside normal V
example, a brown-out), it may take two conversions to reset the
part once the correct V

SUPPLY

.5V TO 5.5

10µF 0.1µF

1.25V TO

3.75V INPUT

ADC TRANSFER FUNCTION

The output coding of the AD7829-1 is straight binary. The
designed code transitions occur at successive integer LSB values
(that is, 1 LSB, 2 LSBs, and so on). The LSB size is equal to
V

/256 (VDD = 5 V), or the LSB size is equal to (0.8 V

REF

(V

= 3 V). The ideal transfer characteristic for the AD7829-1

DD

is shown in

Figure 8.

11111111

111...110

111...000

10000000

000...111

ADC CODE

000...010

000...001

00000000

(VDD = 5V) V
(V

CONVST

to VDD or DGND through a

Power vs. Throughput section).

has been established.

DD

2.5V

AD780

V

V

REF

DB0 TO DB7

CONVST

/256

(V

DD

1LSB = 0.8V

V

+ 1.25V – 1LS B

MID

+ 1V – 1LSB

V

MID

V

= 3V)

DD

V

IN1

V

IN2

AD7829-1

V

IN8

AGND

DGND

Figure 7. Typical Connection Diagram

= 5V)

(V

DD

1LSB = V

REF

1LSB

V

MID

– 1.25V

MID

DD

= 3V) V

– 1V

MID

ANALOG INPUT VOLTAG E

Figure 8. Transfer Characteristic

MID

EOC

REF

RD

CS

A0

A1

A2

/256

CONVST

limits (for

DD

PARALLEL
INTERFACE

6179-009

REF

µC/µP

)/256

ANALOG INPUT

06179-008

The AD7829-1 has eight input channels. Each input channel has
an input span of 2.5 V or 2.0 V, depending on the supply voltage
(V

). This input span is automatically set up by an on-chip

DD

“V

detector” circuit. A 5 V operation of the ADCs is detected

DD

when V
V

DD

exceeds 4.1 V, and a 3 V operation is detected when

DD

falls below 3.8 V. This circuit also possesses a degree of
glitch rejection; for example, a glitch from 5.5 V to 2.7 V up to
60 ns wide does not trip the V

The V
range of AGND to V

pin is used to center this input span anywhere in the

MID

. If no input voltage is applied to V

DD

the default input range is AGND to 2.0 V (V
that is, centered about 1.0 V; or AGND to 2.5 V (V

detector.

DD

= 3 V ± 10%),

DD

= 5 V ± 10%),

DD

MID

,

that is, centered about 1.25 V. When using the default input range,
the V

pin can be left unconnected; or, in some cases, it can be

MID

decoupled to AGND with a 0.1 µF capacitor.

If, however, an external V
is from V
V

MID

− 1.0 V to V

MID

− 1.25 V to V

MID

The range of values of V
value of V
be applied to V
V

− 1.25 V when VDD = 5 V ± 10%. Tabl e 5 shows the relevant

DD

ranges of V

. For VDD = 3 V ± 10%, the range of values that can

DD

is from 1.0 V to VDD − 1.0 V and is 1.25 V to

MID

and the input span for various values of VDD.

MID

is applied, the analog input range

MID

+ 1.0 V (VDD = 3 V ± 10%), or from

MID

+ 1.25 V (VDD = 5 V ± 10%).

that can be applied depends on the

MID

Figure 9 illustrates the input signal range available with various
values of V

MID

.

Table 5.

VDD

V

MID

Internal

V

Ext

MID

Maximum

V

Span

IN

V

Ext

MID

Minimum

V

Span

IN

5.5 1.25 4.25 3.0 to 5.5 1.25 0 to 2.5

5.0 1.25 3.75 2.5 to 5.0 1.25 0 to 2.5

4.5 1.25 3.25 2.0 to 4.5 1.25 0 to 2.5

3.3 1.00 2.3 1.3 to 3.3 1.00 0 to 2.0

3.0 1.00 2.0 1.0 to 3.0 1.00 0 to 2.0

2.7 1.00 1.7 0.7 to 2.7 1.00 0 to 2.0

Rev. 0 | Page 11 of 20

AD7829-1

3V

V

V

V

= 5V

DD

5V

4V

3V

V

= 2.5V

MID

2V

V

= N/C (1.25V)

MID

1V

V

= 3V

DD

2V

V

= 1.5V

MID

V

1V

= N/C (1V)

MID

Figure 9. Analog Input Span Variation with V

V

can be used to remove offsets in a system by applying the

MID

offset to the V

pin, as shown in

MID

to accommodate bipolar signals by applying V
circuit before V

, as shown in

IN

Figure 11. When V

V

= 3.75V

MID

INPUT SIG NAL RANGE

FOR VARIOUS V

V

= 2V

MID

INPUT SIG NAL RANGE

FOR VARIOUS V

MID

MID

MID

6179-010

Figure 10; or it can be used

to a level-shifting

MID

is being

MID

driven by an external source, the source can be directly tied to
the level-shifting circuitry (see
V

, that is, the default value, is being used as an output, it must

MID

Figure 11); however, if the internal

be buffered before applying it to the level-shifting circuitry, because
the V

pin has an impedance of approximately 6 kΩ (see

MID

Figure 12).

IN

V

MID

Figure 10. Removing Offsets Using V

V

IN

AD7829-1

V

MID

V

MID

MID

6179-011

V

0V

V

0

NOTE: Although there is a V
reference of 2.5 V can be sourced, or to which an external
reference can be applied, this does not provide an option of
varying the value of the voltage reference. As stated in the
specifications for the AD7829-1, the input voltage range at this
pin is 2.5 V ± 2%.

Analog Input Structure

Figure 13 shows an equivalent circuit of the analog input
structure of the AD7829-1. The two diodes, D1 and D2, provide
ESD protection for the analog inputs. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 200 mV. This causes these diodes to become
forward biased and start conducting current into the substrate.
20 mA is the maximum current these diodes can conduct
without causing irreversible damage to the part. However, it is
worth noting that a small amount of current (1 mA) conducted
into the substrate due to an overvoltage on an unselected channel
can cause inaccurate conversions on a selected channel.

2.5V

V

REF

V

R4

R3

R2

V

R1

V

2.5V

0V

MID

AD7829-1

V

IN

IN

Figure 11. Accommodating Bipolar Signals Using External V

EXTERNAL

2.5V

V

REF

V

R4

R3

R2

V

R1

V

V

MID

0V

MID

AD7829-1

V

IN

IN

Figure 12. Accommodating Bipolar Signals Using Internal V

pin from which a voltage

REF

MID

MID

06179-012

06179-013

Rev. 0 | Page 12 of 20

AD7829-1

V

V

Capacitor C2 in Figure 13 is typically about 4 pF and can be
primarily attributed to pin capacitance. The resistor, R1, is a
lumped component made up of the on resistance of several
components, including that of the multiplexer and the track­and-hold. This resistor is typically about 310 Ω. Capacitor C1
is the track-and-hold capacitor and has a capacitance of 0.5 pF.
Switch 1 is the track-and-hold switch, while Switch 2 is that of
the sampling capacitor, as shown in

DD

D1

R1

IN

C2

4pF

Figure 13. Equivalent Analog Input Circuit

310Ω

D2

Figure 4 and Figure 5.

C1

0.5pF

SW2

A

SW1

B

6179-014

When in track phase, Switch 1 is closed and Switch 2 is in
Position A; when in hold mode, Switch 1 opens, while Switch 2
remains in Position A. The track-and-hold remains in hold
mode for 120 ns (see the

Circuit Description section), after
which it returns to track mode and the ADC enters its
conversion phase. At this point, Switch 1 opens and Switch 2
moves to Position B. At the end of the conversion, Switch 2
moves back to Position A.

Analog Input Selection

On power-up, the default VIN selection is V
to normal operation from power-down, the V

. When returning

IN1

selected is the

IN

same one that was selected prior to power-down being initiated.
Tabl e 6 shows the multiplexer address corresponding to each
analog input from V

IN1

to V

for the AD7829-1.

IN8

Table 6.

A2 A1 A0 Analog Input Selected

0 0 0 V
0 0 1 V
0 1 0 V
0 1 1 V
1 0 0 V
1 0 1 V
1 1 0 V
1 1 1 V

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

Channel selection on the AD7829-1 is made without the
necessity of a write operation. The address of the next channel
to be converted is latched at the start of the current read
operation, that is, on the falling edge of
shown in

Figure 14. This allows for improved throughput rates

RD CS

while is low, as

in “channel hopping” applications.

120ns

TRACK CHx

CONVST

EOC

DB0 TO DB7

A0 TO A2

HOLD CHx

t

2

CS

RD

TRACK CHx

t

1

TRACK CHy

VALID
DATA

ADDRESS CHANNEL y

t

HOLD CHy

t

3

13

Figure 14. Channel Hopping Timing

There is a minimum time delay between the falling edge of RD
and the next falling edge of the

CONVST

signal, t13. This is the
minimum acquisition time required of the track-and-hold to
maintain 8-bit performance.

Figure 15 shows the typical
performance of the AD7829-1 when channel hopping for
various acquisition times. These results were obtained using an
external reference and internal V
between V

IN1

and V

with 0 V on Channel 4 and 0.5 V on

IN4

while channel hopping

MID

Channel 1.

8.5

8.0

7.5

7.0

ENOB

6.5

6.0

5.5

5.0
100 50 40 30 20 15

ACQUISITION TIME (ns)

10500 200

06179-016

Figure 15. Effective Number of Bits vs. Acquisition Time for the AD7829-1

The on-chip track-and-hold can accommodate input
frequencies to 10 MHz, making the AD7829-1 ideal for
subsampling applications. When the AD7829-1 is converting a
10 MHz input signal at a sampling rate of 2 MSPS, the effective
number of bits typically remains above seven, corresponding to
a signal-to-noise ratio of 42 dB, as shown in

Figure 16.

06179-015

Rev. 0 | Page 13 of 20

AD7829-1

50

f

48

46

44

SNR (dB)

42

40

38

Figure 16. SNR vs. Input Frequency on the AD7829-1

34568

INPUT FREQUENCY (MHz)

SAMPLE

= 2MHz

If the falling edge of
up time has elapsed, then it is upon this falling edge that a
conversion is initiated. When using the on-chip reference, it is
necessary to wait the required power-up time of approximately
25 µs before initiating a conversion. That is, a falling edge on
CONVST

must not occur before the required power-up time
has elapsed, when V
has been powered down using the
Figure 17.

POWER VS. THROUGHPUT

010.2 1

06179-017

Superior power performance can be achieved by using the
automatic power-down (Mode 2) at the end of a conversion
(see the

Operating Modes section).

CONVST

is first connected or after the AD7829-1

DD

occurs after the required power-

CONVST

pin, as shown in

POWER-UP TIMES

The AD7829-1 has a 1 µs power-up time when using an
external reference and a 25 s power-up time when using the
on-chip reference. When V
is in a low current mode of operation. Ensure that the
line is not floating when V
CONVST
before V

while VDD is rising, the part attempts to power up

has fully settled and may enter an unknown state.

DD

In order to carry out a conversion, the AD7829-1 must first be
powered up.

EXTERNAL REFERENCE

V

CONVST

V

CONVST

DD

DD

t

POWER-UP

1µs

t

POWER- UP

25µs

Figure 17. AD7829-1 Power-Up Time

The AD7829-1 is powered up by a rising edge on the
pin. A conversion is initiated on the falling edge of
Figure 17 shows how to power up the AD7829-1 when VDD is

first connected or after the AD7829-1 has been powered down
using the

CONVST

pin when using either the on-chip reference
or an external reference. When using an external reference, the
falling edge of

CONVST
up time has elapsed. However, the conversion is not initiated on
the falling edge of

CONVST

part has completely powered up, that is, after 1 µs.

is first connected, the AD7829-1

DD

CONVST

is applied. If there is a glitch on

DD

CONVERSI ON

INITIATED HERE

ON-CHIP REFERENCE

CONVERSI ON

INITIATED HERE

CONVST

CONVST

may occur before the required power-

but rather at the moment when the

.

Figure 18 shows how the automatic power-down is implemented
using the

CONVST

ance for the AD7829-1. The duration of the

signal to achieve the optimum power perform-

CONVST

pulse is
set to be equal to or less than the power-up time of the devices
(see the

Operating Modes section). As the throughput rate is
reduced, the device remains in its power-down state longer, and the
average power consumption over time drops accordingly.

t

CONVST

t

POWER-UP

CONVERT

1µs

330ns

Figure 18. Automatic Power-Down

POWER-DO WN

t

CYCLE

10µs @ 100kSPS

6179-019

For example, if the AD7829-1 is operated in a continuous
sampling mode, with a throughput rate of 100 kSPS and using
an external reference, the power consumption is calculated as
follows. The power dissipation during normal operation is
36 mW, V

= 3 V. If the power-up time is 1 s and the conversion

DD

time is 330 ns (@ +25°C), the AD7829-1 can be said to dissipate
36 mW (maximum) for 1.33 µs during each conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10 s and

06179-018

the average power dissipated during each cycle is (1.33/10) ×
(36 mW) = 4.79 mW. This calculation uses the minimum
conversion time, thus giving the best-case power dissipation at
this throughput rate. However, the actual power dissipated
during each conversion cycle may increase, depending on the
actual conversion time (up to a maximum of 420 ns).

Rev. 0 | Page 14 of 20

AD7829-1

Figure 19 shows the power vs. throughput rate for automatic,
full power-down.

100

OPERATING MODES

The AD7829-1 has two possible modes of operation, depending
on the state of the

CONVST

end of a conversion, that is, upon the rising edge of the

pulse approximately 100 ns after the

EOC

pulse.

10

1

POWER (mW)

0.1

0

50 150 250 350 450

200 300 400

THROUG HPUT ( kSPS)

Figure 19. AD7829-1 Power vs. Throughput

0

–10

–20

–30

–40

(dB)

–50

–60

–70

–80

0

85

28

57

227

283

425

113

170

255

142

198

481

312

368

510

453

340

396

FREQUENCY (kHz)

538

Figure 20. AD7829-1 SNR

566

595

623

2048 POINT FFT
SAMPLING
2MSPS

f

= 200kHz

IN

680

821

708

765

651

736

793

850

878

Mode 1 Operation (High-Speed Sampling)

When the AD7829-1 is operated in Mode 1, it is not powered
down between conversions. This mode of operation allows high
throughput rates to be achieved.
optimum throughput rate is achieved by bringing
high before the end of a conversion, that is, before the

Figure 21 shows how this

CONVST

EOC

pulses low. When operating in this mode, a new conversion
should not be initiated until 30 ns after the end of a read

0050100

06179-020

operation. This allows the track/hold to acquire the analog
signal to 0.5 LSB accuracy.

Mode 2 Operation (Automatic Power-Down)

When the AD7829-1 is operated in Mode 2 (see Figure 22), it
automatically powers down at the end of a conversion. The
CONVST

left logic low until after the
100 ns after the end of the conversion. The state of the

signal is brought low to initiate a conversion and is

EOC

goes high, that is, approximately

CONVST

signal is sampled at this point (that is, 530 ns maximum after
CONVST

as
edge of the

falling edge) and the AD7829-1 powers down as long

CONVST

is low. The ADC is powered up again on the rising

CONVST

signal. Superior power performance can
be achieved in this mode of operation by powering up the
AD7829-1 only to carry out a conversion. The parallel interface

906

963

935

991

06179-021

of the AD7829-1 is still fully operational while the ADCs are
powered down. A read can occur while the part is powered
down, and so it does not necessarily need to be placed within

EOC

the

pulse, as shown in Figure 22.

CONVST

EOC

DB0 TO DB7

CS

RD

TRACK

120ns

HOLD

t

2

t

1

TRACK

VALID
DATA

t

3

HOLD

06179-022

Figure 21. Mode 1 Operation

Rev. 0 | Page 15 of 20

AD7829-1

CONVST

EOC

CS

RD

DB0 TO DB7

t

POWER-UP

t

1

Figure 22. Mode 2 Operation

VALID

DATA

POWER

DOWN

HERE

06179-023

Rev. 0 | Page 16 of 20

AD7829-1

EOC

PARALLEL INTERFACE

The parallel interface of the AD7829-1 is eight bits wide. Figure 23
shows a timing diagram illustrating the operational sequence of
the AD7829-1 parallel interface. The multiplexer address is latched
into the AD7829-1 on the falling edge of the
chip track/hold goes into hold mode on the falling edge of
CONVST

. A conversion is also initiated at this point. When the
conversion is complete, the end of conversion line (
low to indicate that new data is available in the output register
of the AD7829-1. The

EOC

pulse stays logic low for a maximum

time of 110 ns.

t

CONVST

EOC

CS

RD

DB0 TO DB7

A0 TO A2

2

RD

t

1

input. The on-

EOC

) pulses

Figure 23. AD7829-1 Parallel Port Timing

However, the
RD EOC

. This line can be used to drive an edge-triggered
interrupt of a microprocessor.
the 8-bit conversion result. It is possible to tie
low and use only
part is interfaced to a gate array or ASIC, this
applied to the
AD7829-1 and into the gate array or ASIC. This means that the

gate array or ASIC does not need any conversion status
recognition logic, and it also eliminates the logic required in the
gate array or ASIC to generate the read signal for the AD7829-1.

t

4

t

6

t

t

9

t11t

12

NEXT
CHANNEL
ADDRESS

pulse can be reset high by a rising edge of

CS RD

and going low accesses

RD

to access the data. In systems where the

CS RD

and inputs to latch data out of the

t

5

t

7

8

VALID
DATA

t

3

t

10

t

13

CS

permanently

EOC

pulse can be

06179-024

Rev. 0 | Page 17 of 20

AD7829-1

MICROPROCESSOR INTERFACING

The parallel port on the AD7829-1 allows the ADCs to be
interfaced to a range of many different microcontrollers. This
section explains how to interface the AD7829-1 with some of
the more common microcontroller parallel interface protocols.

PIC16C6x/7x

PSP0 TO PSP7

1

AD7829-1

DB0 TO DB7

1

AD7829-1 TO 8051

Figure 24 shows a parallel interface between the AD7829-1 and

EOC

the 8051 microcontroller. The

signal on the AD7829-1
provides an interrupt request to the 8051 when a conversion
ends and data is ready. Port 0 of the 8051 can serve as an input
or output port, or, as in this case when used together with the
address latch enable (ALE) of the AD8051, it can be used as a
bidirectional low order address and data bus. The ALE output
of the 8051 is used to latch the low byte of the address during
accesses to the device, while the high order address byte is
supplied from Port 2. Port 2 latches remain stable when the
AD7829-1 is addressed, because they do not have to be turned
around (set to 1) for data input, as is the case for Port 0.

1

8051

AD0 TO AD7

LATCH

ALE

A8 TO A15

RD

INT

1

ADDITIONAL PINS O MITTED F OR CLARITY.

Figure 24. Interfacing to the 8051

DECODER

DB0 TO DB7

AD7829-1

CS

RD

EOC

1

AD7829-1 TO PIC16C6x/PIC16C7x

Figure 25 shows a parallel interface between the AD7829-1 and

EOC

the PIC16C64/PIC16C65/PIC16C74. The
AD7829-1 provides an interrupt request to the microcontroller
when a conversion begins. Of the PIC16C6x/PIC16C7x range of
microcontrollers, only the PIC16C64/PIC16C65/PIC16C74 can
provide the option of a parallel slave port. Port D of the micro­controller operates as an 8-bit wide parallel slave port when Control
Bit PSPMODE in the TRISE register is set. Setting PSPMODE
enables Port Pin RE0 to be the

RD CS

output and RE2 to be the
(chip select) output. For this functionality, the corresponding
data direction bits of the TRISE register must be configured as
outputs (reset to 0). See the PIC16C6x/PIC16C7x Microcontroller
User Manual for more information.

signal on the

CS

RD

INT

1

ADDITIO NAL PINS O MITT ED FOR CL ARITY.

CS

RD

EOC

06179-026

Figure 25. Interfacing to the PIC16C6x/PIC16C7x

AD7829-1 TO ADSP-21xx

Figure 26 shows a parallel interface between the AD7829-1 and

EOC

the ADSP-21xx series of DSPs. As before, the

signal on the
AD7829-1 provides an interrupt request to the DSP when a
conversion ends.

ADSP-21xx

06179-025

1

ADDITIO NAL PINS O MITT ED FOR CL ARITY.

1

D7 TO D0

A13 TO A0

DMS

RD

IRQ

ADDRESS

DECODE

LOGIC

EN

Figure 26. Interfacing to the ADSP-21xx

DB0 TO DB7

AD7829-1

CS

RD

EOC

1

06179-027

INTERFACING MULTIPLEXER ADDRESS INPUTS

Figure 27 shows a simplified interfacing scheme between the
AD7829-1 and any microprocessor or microcontroller that
facilitates easy channel selection on the ADCs. The multiplexer
address is latched on the falling edge of the
in the

Parallel Interface section, which allows the use of the three
LSBs of the address bus to select the channel address. As shown in
Figure 27, only Address Bit A3 to Address Bit A15 are address
decoded, allowing A0 to A2 to be changed according to desired
channel selection without affecting chip selection.

RD

signal, as outlined

Rev. 0 | Page 18 of 20

AD7829-1

MICROPROCESSOR READ CYCLE

ADC I/O ADDRESS

MUX ADDRESS

A/D RESULT

MUX ADDRESS

(CHANNEL SELECT ION A0 TO A2)

LATCHED

06179-028

A15 TO A3

SYSTEM BUS

ADDRESS

DECODE

AD7829-1

A0
A1

A2

CS

RD

DB7 TO DB0

1

CS

RD

A15 TO A3

A2 TO A0

DB0 TO DB7

Figure 27. AD7829-1 Simplified Microinterfacing Scheme

Rev. 0 | Page 19 of 20

AD7829-1

C

Y

OUTLINE DIMENSIONS

18.10 (0.7126)

17.70 (0.6969)

0.30 (0.0118)

0.10 (0.0039)

COPLANARIT Y

0.10

28

1

1.27 (0.0500)
BSC

CONTROLL ING DIMENSIONS ARE IN MILLI METERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LIMET ER EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013-AE

15

7.60 (0.2992)

7.40 (0.2913)

14

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

8°
0°

0.33 (0.0130)

0.20 (0.0079)

Figure 28. 28-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-28)

Dimensions shown in millimeters and (inches)

9.80

9.70

9.60

PIN 1

0.15

0.05

OPLANARIT

0.10

28

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AE

1.20 MAX

SEATING

PLANE

15

4.50

4.40

4.30

0.20

0.09

6.40 BSC

8°
0°

141

Figure 29. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

0.75

0.60

0.45

0
0

.

7

5

.

2

5

(

0

.

0

2

(

0

.

0

0

9

5

)

45°

9

8

)

1.27 (0.0500)

0.40 (0.0157)

060706-A

ORDERING GUIDE

Model Temperature Range Package Description Package Option Linearity Error

AD7829BRU-1 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 ±0.75 LSB
AD7829BRU-1REEL7 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 ±0.75 LSB
AD7829BRUZ-1 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 ±0.75 LSB
AD7829BRUZ-1REEL7 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 ±0.75 LSB
AD7829BRW-1 −40°C to +85°C 28-Lead Standard Small Outline Package [SOIC_W] RW-28 ±0.75 LSB
AD7829BRW-1RL7 −40°C to +85°C 28-Lead Standard Small Outline Package [SOIC_W] RW-28 ±0.75 LSB
AD7829BRWZ-1 −40°C to +85°C 28-Lead Standard Small Outline Package [SOIC_W] RW-28 ±0.75 LSB
AD7829BRWZ-1RL7 −40°C to +85°C 28-Lead Standard Small Outline Package [SOIC_W] RW-28 ±0.75 LSB

1

Z = Pb-free part.

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06179-0-7/06(0)

1

1

1

1

Rev. 0 | Page 20 of 20