Datasheet AD7794 Datasheet (Analog Devices)

Page 1

6-Channel, Low Noise, Low Power, 24-Bit

∑-Δ

FEATURES

Up to 22.5 effective bits RMS noise: 40 nV @ 4.17 Hz 85 nV @ 16.7 Hz Current: 400 µA typ Power-down: 1 µA max Low noise programmable gain instrumentation-amp Band gap reference with 4 ppm/°C drift typ Update rate: 4.17 Hz to 500 Hz Six differential analog inputs Internal clock oscillator Simultaneous 50 Hz/60 Hz rejection Reference detect Programmable current sources On-chip bias voltage generator Burnout currents Low-side power switch Power supply: 2.7 V to 5.25 V –40°C to +105°C temperature range Independent interface power supply 24-lead TSSOP package

INTERFACE

3-wire serial SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible Schmitt trigger on SCLK

APPLICATIONS

Temperature measurement Pressure measurement Weigh scales

FUNCTIONAL BLOCK DIAGRAM

GND AV

ADC with On-Chip In-Amp and Reference

AD7794

Strain gauge transducers Gas analysis Industrial process control Instrumentation Blood analysis Smart transmitters Liquid/gas chromotography 6-digit DVM

GENERAL DESCRIPTION

The AD7794 is a low power, low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit ∑-∆ ADC with six differential inputs. The on-chip low noise instrumentation amplifier means that signals of small amplitude can be interfaced directly to the ADC.

The device contains a precision low noise, low drift internal band gap reference and can also accept up to two external differential references. Other on-chip features include programmable excitation current sources, burnout currents and a bias voltage generator, this feature being used to set the common mode voltage of a channel to AV switch can be used to power down bridge sensors between conversions, minimizing the system’s power consumption. The device can be operated with the internal clock or, alternatively, an external clock can be used. The output data rate from the part can be varied from 4.17 Hz to 500 Hz.

The part operates with a power supply from 2.7 V to 5.25 V. It consumes a current of 400 µA typical and is housed in a 24-lead TSSOP package.

AIN4(+)/REFIN2(+) REFIN1(+) AIN4(–)/REFIN2(–) REFIN1(–)

/2. The low-side power

BIAS

MUX

GND

AIN1(+) AIN1(–) AIN2(+) AIN2(–) AIN3(+)

AIN3(–) AIN5(+)/IOUT2 AIN5(–)/IOUT1

AIN6(+)/P1 AIN6(+)/P2

PSW

GND

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

BAND GAP

REFERENCE

IN-AMPBUF

TEMP

SENSOR

Figure 1.

REFERENCE

DETECT

GND

SERIAL

CLK

INTERFACE

AND

LOGIC

CONTROL

AD7794

Σ-∆

ADC

INTERNAL

CLOCK

DOUT/RDY DIN SCLK CS

04854-001

Page 2

AD7794

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 7

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Output Noise and Resolution Specifications .............................. 12

Chopping Enabled...................................................................... 12

External Reference ................................................................. 12

Internal Reference.................................................................. 13

Chopping Disabled..................................................................... 14

Typical Performance Characteristics ...........................................15

On-Chip Registers.......................................................................... 16

Communications Register......................................................... 16

Status Register............................................................................. 17

Mode Register ............................................................................. 17

Single Conversion Mode....................................................... 26

Continuous Conversion Mode ............................................. 26

Continuous Read........................................................................ 27

Circuit Description......................................................................... 28

Analog Input Channel ............................................................... 28

Instrumentation Amplifier........................................................ 28

Bipolar/Unipolar Configuration .............................................. 28

Data Output Coding .................................................................. 28

Burnout Currents....................................................................... 29

Excitation Currents .................................................................... 29

Bias Voltage Generator .............................................................. 29

Reference ..................................................................................... 29

Reference Detect......................................................................... 30

Reset ............................................................................................. 30

Monitor ............................................................................. 30

Configuration Register ..............................................................19

Data Register............................................................................... 21

ID Register................................................................................... 21

IO Register................................................................................... 21

Offset Register............................................................................. 22

Full-Scale Register ...................................................................... 22

ADC Circuit Information.............................................................. 23

Overview...................................................................................... 23

Digital Interface.......................................................................... 25

REVISION HISTORY

10/04—Revision 0: Initial Version

Calibration................................................................................... 30

Grounding and Layout .............................................................. 31

Applications..................................................................................... 32

Flowmeter.................................................................................... 32

Outline Dimensions....................................................................... 33

Ordering Guide .......................................................................... 33

Rev. 0 | Page 2 of 36

Page 3

AD7794

SPECIFICATIONS

AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V; all specifications T

Table 1.

Parameter1 AD7794B Unit Test Conditions/Comments AD7794 (CHOP ENABLED)

Output Update Rate 4.17 – 500 Hz nom Settling Time = 2/Output Update Rate No Missing Codes2 24 Bits min f Resolution See Tables in ADC

Description

Output Noise and Update Rates See Tables in ADC

Description Integral Nonlinearity ±15 ppm of FSR max Offset Error3 ±1 µV typ Offset Error Drift vs. Temperature4 ±10 nV/°C typ Full-Scale Error

3, 5

Gain Drift vs. Temperature4

±10 µV typ

±1 ppm/°C typ Gain = 1 to 16, External Reference ±3 ppm/°C typ Gain = 32 to 128, External Reference Power Supply Rejection 100 dB min AIN = 1 V/Gain, Gain ≥ 4, External Reference ANALOG INPUTS

Differential Input Voltage Ranges ± V

Absolute AIN Voltage Limits2

/Gain V nom V

REF

Unbuffered Mode GND – 30 mV V min Gain = 1 or 2

AVDD + 30 mV V max

Buffered Mode GND + 100 mV V min Gain = 1 or 2

AVDD – 100 mV V max

In-Amp Active GND + 300 mV V min Gain = 4 to 128

AVDD – 1.1 V max

Common-Mode Voltage, VCM 0.5 V min VCM = (AIN(+) + AIN(–))/2, Gain = 4 to 128

Analog Input Current

Buffered Mode or In-Amp Active

Average Input Current2

±1 nA max Gain = 1 or 2, Update Rate < 100 Hz ±250 pA max Gain = 4 to 128, Update Rate < 100 Hz ±1 nA max AIN6(+)/AIN6(−)

Average Input Current Drift ±2 pA/°C typ

Unbuffered Mode Gain = 1 or 2

Average Input Current ±400 nA/V typ Input current varies with input voltage Average Input Current Drift ±50 pA/V/°C typ

Normal Mode Rejection2

Internal Clock

@ 50 Hz, 60 Hz 65 dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106 @ 50 Hz 80 dB min @ 60 Hz 90 dB min

External Clock

@ 50 Hz, 60 Hz 80 dB min @ 50 Hz 94 dB min @ 60 Hz 90 dB min

Common-Mode Rejection

@ DC 100 dB min AIN = 1 V/Gain, Gain ≥ 4 @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2

100 dB min

MIN

to T

, unless otherwise noted.

MAX

≤ 250 Hz

ADC

= REFIN(+) – REFIN(−) or Internal Reference,

REF

Gain = 1 to 128

90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000

90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010

100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000

50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106 50 ± 1 Hz (FS[3:0] = 10016), 60 ± 1 Hz (FS[3:0] = 10006)

Rev. 0 | Page 3 of 36

Page 4

AD7794

Parameter1 AD7794B Unit Test Conditions/Comments AD7794 (CHOP DISABLED)

Output Update Rate 4.17 - 500 Hz nom Settling Time = 1/Output Update Rate No Missing Codes2 Resolution See Tables in ADC

Output Noise and Update Rates See Tables in ADC

Integral Nonlinearity ±15 ppm of FSR max Offset Error3 Offset Error Drift vs. Temperature4 10 nV/°C typ Gain = 32 to 128 Full-Scale Error

3, 5

Gain Drift vs. Temperature4 ±3 ppm/°C typ Gain = 32 to 128, External Reference Power Supply Rejection 100 dB typ AIN = 1 V/Gain, Gain ≥ 4, External Reference ANALOG INPUTS

Differential Input Voltage Ranges ± V

Absolute AIN Voltage Limits2

Unbuffered Mode GND – 30 mV V min Gain = 1 or 2

AVDD + 30 mV V max

Buffered Mode GND + 100 mV V min Gain = 1 or 2

AVDD – 100 mV V max

In-Amp Active GND + 300 mV V min Gain = 4 to 128

AVDD – 1.1 V max

Common-Mode Voltage, VCM 0.2 + (Gain/2 x

AVDD – 0.2 – (Gain/2

Analog Input Current

Buffered Mode or In-Amp Active

Average Input Current2 ±250 pA max Gain = 4 to 128 ±1 nA max AIN6(+)/AIN6(−)

Average Input Current Drift ±2 pA/°C typ

Unbuffered Mode Gain = 1 or 2

Average Input Current ±400 nA/V typ Input current varies with input voltage.

Average Input Current Drift ±50 pA/V/°C typ

Normal Mode Rejection2

Internal Clock

@ 50 Hz, 60 Hz 60 dB min

@ 50 Hz 78 dB min

@ 60 Hz 86 dB min

External Clock

@ 50 Hz, 60 Hz 60 dB min

@ 50 Hz 94 dB min

@ 60 Hz 90 dB min

Common-Mode Rejection

@ DC 100 dB min AIN = 1 V/Gain with Gain = 4, AMP-CM Bit = 1

@ 50 Hz, 60 Hz2

24 Bits min f

≤125 Hz

ADC

Description

±100/Gain µV typ Without Calibration ±100/Gain nV/°C typ Gain = 1 to 16

±10 µV typ ±1 ppm/°C typ Gain = 1 to 16, External Reference

/Gain V nom V

REF

= REFIN(+)− REFIN(−) or Internal Reference,

REF

Gain = 1 to 128

V min AMP-CM = 1, VCM = (AIN(+) + AIN(–))/2, Gain = 4 to 128

(AIN(+) – AIN(-)))

V max

x (AIN(+) – AIN(-)))

±1 nA max Gain = 1 or 2

70 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000

70 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000

100 dB min 100 dB min

50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106 50 ± 1 Hz (FS[3:0] = 10016), 60 ± 1 Hz (FS[3:0] = 10006)

Rev. 0 | Page 4 of 36

Page 5

AD7794

Parameter1 AD7794B Unit Test Conditions/Comments AD7794 (CHOP ENABLED or DISABLED)

REFERENCE INPUT

Internal Reference

Internal Reference Initial Accuracy 1.17 ±0.01% V min/max Internal Reference Drift2

15 ppm/°C max

Power Supply Rejection 85 dB typ

External Reference

External REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–) Reference Voltage Range2

AVDD V max When V

Absolute REFIN Voltage Limits2

AVDD + 30 mV V max

Average Reference Input Current 400 nA/V typ Average Reference Input Current

Drift Normal Mode Rejection2

Common-Mode Rejection 100 Reference Detect Levels 0.3 V min

0.65 V max NOXREF Bit Active if V EXCITATION CURRENT SOURCES

(IEXC1 and IEXC2) Output Current 10/210/1000 µA nom Initial Tolerance at 25°C ±5 % typ Drift 200 ppm/°C typ Current Matching ±0.5 % typ Matching between IEXC1 and EXC2. V Drift Matching 50 ppm/°C typ Line Regulation (AVDD) 2 %/V typ AVDD = 5 V ± 5% Load Regulation 0.2 %/V typ

Output Compliance AVDD – 0.65 V max Current Sources Programmed to 10 µA or 210 µA AVDD – 1.1 V max Current Sources Programmed to 1 mA GND – 30 mV V min BIAS VOLTAGE GENERATOR

AVDD/2 V nom

BIAS

Generator Start-Up Time

BIAS

TEMPERATURE SENSOR

Accuracy

Sensitivity LOW SIDE POWER SWITCH

RON 7 Ω max AVDD = 5 V 9 Ω max AVDD = 3 V

Allowable Current2 DIGITAL OUTPUTS (P1 and P2)

VOH, Output High Voltage2

VOL, Output Low Voltage2

VOH, Output High Voltage2

VOL, Output Low Voltage2 INTERNAL/EXTERNAL CLOCK

Internal Clock

Frequency2 Duty Cycle 50:50 % typ

AVDD = 4 V, TA = 25°C

4 ppm/°C typ

0.1 V min = AVDD , the differential input must be limited to

REF

/Gain if the In-Amp is active

0.9×V

REF

GND – 30 mV V min

±0.03 nA/V/°C typ

Same as for Analog Inputs

See

± 2

0.81

Figure 11

dB typ

ms/nF typ Dependent on the Capacitance connected to AIN

°C typ Applies if User Calibrates the Temp Sensor mV/°C typ

30 mA max Continuous Current

− 0.6 V min AVDD = 3 V, I

0.4 V max AV

4 V min AV

0.4 V max AV

= 3 V, I

= 5 V, I

= 100 µA

SOURCE

= 100 µA

SINK

= 200 µA

SOURCE

= 800 µA

SINK

64 ± 3% kHz min/max

< 0.3 V

REF

OUT

= 0 V

Rev. 0 | Page 5 of 36

Page 6

AD7794

Parameter1 AD7794B Unit Test Conditions/Comments

External Clock

Frequency 64 kHz nom A 128 kHz external clock can be used if the divide by 2

Duty Cycle 45:55 to 55:45 % typ

LOGIC INPUTS

, Input Low Voltage 0.8 V max DVDD = 5 V

INL

0.4 V max DVDD = 3 V V

, Input High Voltage 2.0 V min DVDD = 3 V or 5 V

INH

SCLK, CLK and DIN (Schmitt-Triggered

Input)

VT(+) 1.4/2 V min/V max DVDD = 5 V VT(–) 0.8/1.7 V min/V max DVDD = 5 V VT(+) − VT(−)

0.1/0.17 V min/V max DV

VT(+) 0.9/2 V min/V max DVDD = 3 V VT(−) 0.4/1.35 V min/V max DVDD = 3 V VT(+)− VT(−) 0.06/0.13 V min/V max DVDD = 3 V

Input Currents ±10 µA max VIN = DVDD or GND Input Capacitance 10 pF typ All Digital Inputs

LOGIC OUTPUTS (Including CLK)

VOH, Output High Voltage2 VOL, Output Low Voltage2 VOH, Output High Voltage2 VOL, Output Low Voltage2

– 0.6 V min DVDD = 3 V, I

0.4 V max DV 4 V min DV

0.4 V max

Floating-State Leakage Current ±10 µA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset Binary

SYSTEM CALIBRATION2

Full-Scale Calibration Limit 1.05 × FS V max Zero-Scale Calibration Limit −1.05 × FS V min Input Span 0.8 × FS V min

2.1 × FS V max

POWER REQUIREMENTS7

Power Supply Voltage AVDD – GND 2.7/5.25 V min/max DVDD – GND 2.7/5.25 V min/max Power Supply Currents IDD Current 140 µA max

185 µA max

400 µA max

500 µA max

IDD (Power-Down Mode) 1 µA max

Temperature Range: −40°C to +105°C.

Specification is not production tested but is supported by characterization data at initial product release.

Following a calibration, this error will be in the order of the noise for the programmed gain and update rate selected.

Recalibration at any temperature will remove these errors.

Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V, gain = 1, TA = 25°C ).

FS[3:0] are the four bits used in the mode register to select the output word rate.

Digital inputs equal to DV

or GND with excitation currents and bias voltage generator disabled.

function is used (Bit CLK1 = CLK0 = 1) Applies for external 64 kHz clock.

have a less stringent duty cycle

= 5 V

= 100 µA

SOURCE

= 3 V, I

= 5 V, I

110 µA typ @ AV

= 100 µA

SINK

= 200 µA

SOURCE

= 1.6 mA (DOUT/

SINK

= 3 V, 125 µA typ @ AVDD = 5 V,

A 128 kHz clock can

RDY

)/800 µA (CLK)

Unbuffered Mode, Ext. Reference 130 µA typ @ AV

= 3 V, 165 µA typ @ AVDD = 5 V,

Buffered Mode, Gain = 1 or 2, Ext Ref 300 µA typ @ AV

= 3 V, 350 µA typ @ AVDD = 5 V,

Gain = 4 to 128, Ext. Ref 400 µA typ @ AV

= 3 V, 450 µA typ @ AVDD = 5 V,

Gain = 4 to 128, Int Ref

Rev. 0 | Page 6 of 36

Page 7

AD7794

TIMING CHARACTERISTICS

AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter

t4 100 ns min SCLK Low Pulse Width Read Operation

t1 0 ns min 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t

60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t

80 ns max t6 0 ns min t7 10 ns min

Write Operation

t8 0 ns min t9 30 ns min Data Valid to SCLK Edge Setup Time

t10 25 ns min Data Valid to SCLK Edge Hold Time t11 0 ns min

1, 2

Limit at T

MIN

, T

(B Version) Unit Conditions/Comments

MAX

100 ns min SCLK High Pulse Width

Falling Edge to DOUT/RDY Active Time

0 ns min SCLK Active Edge to Data Valid Delay4

5, 6

10 ns min

Bus Relinquish Time after CS

SCLK Inactive Edge to CS SCLK Inactive Edge to DOUT/RDY

Falling Edge to SCLK Active Edge Setup Time4

Rising Edge to SCLK Edge Hold Time

Inactive Edge

High

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

See Figure 3 and Figure 4.

These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

SCLK active edge is falling edge of SCLK.

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

RDY

returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.

RDY

is high,

(1.6mA WITH DVDD = 5V,

SINK

OUTPUT

50pF

100µA WITH DV

SOURCE

100µA WITH DV

= 3V)

1.6V

(200µA WITH DVDD = 5V,

= 3V)

04854-002

Figure 2. Load Circuit for Timing Characterization

Rev. 0 | Page 7 of 36

Page 8

AD7794

CS (I)

DOUT/RDY (O)

SCLK (I)

CS (I)

MSB LSB

I = INPUT, O = OUTPUT

Figure 3. Read Cycle Timing Diagram

04854-003

04854-004

CLK (I)

DIN (I)

I = INPUT, O = OUTPUT

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev. 0 | Page 8 of 36

Page 9

AD7794

ABSOLUTE MAXIMUM RATINGS

TA= 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND –0.3 V to +7 V DVDD to GND –0.3 V to +7 V Analog Input Voltage to GND –0.3 V to AVDD + 0.3 V Reference Input Voltage to GND –0.3 V to AVDD + 0.3 V Digital Input Voltage to GND –0.3 V to DVDD + 0.3 V Digital Output Voltage to GND –0.3 V to DVDD + 0.3 V AIN/Digital Input Current 10 mA Operating Temperature Range –40°C to +85°C Storage Temperature Range –65°C to +85°C Maximum Junction

Temperature TSSOP

θJA Thermal Impedance 97.9°C/W θJC Thermal Impedance 14°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 9 of 36

Page 10

AD7794

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK

1 2

CLK

CS NC

AIN1(+) AIN1(–) AIN2(+) AIN2(–) AIN3(+) AIN3(–)

4 5

AD7794

TOP VIEW

(Not to Scale)

9 10 11 12

NC = NO CONNECT

IN6(+)/P1 IN6(–)/P2

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 SCLK Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the interface

2 CLK Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can be disabled

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems

4 NC No Connect. 5 AIN6(+)/P1 Analog Input/Digital Output Pin. AIN6(+) is the positive terminal of the differential analog input pair AIN6(+)/AIN6(−).

6 AIN6(−)/P2

7 AIN1(+) Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(−). 8 AIN1(−) Analog Input. AIN1(−) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(−). 9 AIN2(+) Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(−). 10 AIN2(−) Analog Input. AIN2(−) is the negative terminal of the differential analog input pair AIN2(+)/AIN2(−). 11 AIN3(+) Analog Input. AIN3(+) is the positive terminal of the differential analog input pair AIN3(+)/AIN3(−). 12 AIN3(−) Analog Input. AIN3(−) is the negative terminal of the differential analog input pair AIN3(+)/AIN3(−). 13 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can lie

14 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between GND and AVDD − 0.1 V. 15 AIN5(+)/IOUT2 Analog Input/Output of Internal Excitation Current Source.

16 AIN5(−)/IOUT1 Analog Input/Output of Internal Excitation Current Source. AIN5(−) is the negative terminal of the differential analog

17 AIN4(+)/REFIN2(+) Analog Input/Positive Reference Input.

suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data.

and the ADC can be driven by an external clock. This allows several ADCs to be driven from a common clock, allowing simultaneous conversions to be performed.

with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device.

Alternatively, this pin can function as a general purpose output bit referenced between AV Analog Input/ Digital Output Pin. AIN6(−) is the negative terminal of the differential analog input pair AIN6(+)/AIN6(−).

Alternatively, this pin can function as a general purpose output bit referenced between AV

anywhere between AV

and GND + 0.1 V. The nominal reference voltage (REFIN1(+)− REFIN1(−)) is 2.5 V, but the part

functions with a reference from 0.1 V to AV

AIN5(+) is the positive terminal of the differential analog input pair AIN5(+)/AIN5(−). Alternatively, the internal excitation current source can be made available at this pin. The excitation current source is

programmable so that the current can be 10 µA, 210 µA or 1 mA. Either IEXC1 or IEXC2 can be switched to this output

input pair AIN5(+)/AIN5(−). Alternatively, the internal excitation current source can be made available at this pin. The excitation current source is

programmable so that the current can be 10 µA, 210 µA or 1 mA. Either IEXC1 or IEXC2 can be switched to this output.

AIN4(+) is the positive terminal of the differential analog input pair AIN4(+)/AIN4(−). This pin can also function as a reference input. REFIN2(+) can lie anywhere between AV

nominal reference voltage (REFIN2(+)− REFIN2(−)) is 2.5 V, but the part functions with a reference from 0.1 V to AV

DIN

24 23

DOUT/RDY

GND

PSW

AIN4(–)/REFIN2(–)

18 17

AIN4(+)/REFIN2(+)

AIN5(–)/IOUT1 AIN5(+)/IOUT2

REFIN1(–)

REFIN1(+)

04854-005

and GND.

and GND + 0.1 V. The

Rev. 0 | Page 10 of 36

Page 11

AD7794

Pin No. Mnemonic Description

18 AIN4(−)/REFIN2(−) Analog Input/Negative Reference Input.

19 PSW Low-Side Power Switch to GND. 20 GND Ground Reference Point. 21 AVDD Supply Voltage, 2.7 V to 5.25 V. 22 DVDD Serial Interface Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, the serial interface can be

24 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers

DOUT/

RDY

Serial Data Output/Data Ready Output. DOUT/

AIN4(−) is the negative terminal of the differential analog input pair AIN4(+)/AIN4(−). This pin also functions as the negative reference input for REFIN2. This reference input can lie anywhere between GND and AV

operated at 3 V with AV

access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/ conversion. If the data is not read after the conversion, the pin will go high before the next update occurs. The DOUT/ external serial clock, the data can be read using the DOUT/ placed on the DOUT/

within the ADC, the register selection bits of the communications register identifying the appropriate register.

RDY

falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an

at 5 V or vice versa.

RDY

serves a dual purpose. It functions as a serial data output pin to

RDY

operates as a data ready pin, going low to indicate the completion of a

RDY

pin. With CS low, the data/control word information is

RDY

pin on the SCLK falling edge and is valid on the SCLK rising edge.

− 0.1 V.

Rev. 0 | Page 11 of 36

Page 12

AD7794

OUTPUT NOISE AND RESOLUTION SPECIFICATIONS

The AD7794 can be operated with chopping enabled or chopping disabled, allowing the ADC to be optimized for switching time or optimized for drift performance. With chopping enabled, the settling time is two times the conversion time. However, the offset is continuously removed by the ADC leading to low offset and low offset drift. With chopping disabled, the allowable update rates are the same as in chop enable mode. However, the settling time now equals the conversion time. With chopping disabled, the offset is not removed by the ADC so periodic offset calibrations may be required to remove offset due to drift.

Table 5. Output RMS Noise (µV) vs. Gain and Output Update Rate Using an External 2.5 V Reference with Chop Enabled

Update Rate Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

4.17 Hz

8.33 Hz

16.7 Hz

33.3 Hz

62.5 Hz 125 Hz 250 Hz 500 Hz

0.64 0.6 0.29 0.22 0.1 0.065 0.039 0.041

1.04 0.96 0.38 0.26 0.13 0.078 0.057 0.055

1.55 1.45 0.54 0.36 0.18 0.11 0.087 0.086

2.3 2.13 0.74 0.5 0.23 0.17 0.124 0.118

2.95 2.85 0.92 0.58 0.29 0.2 0.153 0.144

4.89 4.74 1.49 1 0.48 0.32 0.265 0.283

11.76 9.5 4.02 1.96 0.88 0.45 0.379 0.397

11.33 9.44 3.07 1.79 0.99 0.63 0.568 0.593

Table 6. Typical Resolution (Bits) vs. Gain and Output Update Rate Using an External 2.5 V Reference with Chop Enabled

Update Rate Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

4.17 Hz

8.33 Hz

16.7 Hz

33.3 Hz

62.5 Hz 125 Hz 250 Hz 500 Hz

22.5 (20) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5)) 20.5 (18) 20.5 (18) 19.5 (17)

21.5 (19) 20.5 (18) 21 (18.5) 20.5 (18) 20.5 (18) 20.5 (18) 20 (17.5) 19 (16.5) 21 (18.5) 20 (17.5) 20.5 (18) 20 (17.5) 20.5 (18) 20 (17.5) 19.5 (17) 18.5 (16)

20.5 (18) 19.5 (17) 20 (17.5) 19.5 (17) 20 (17.5) 19.5 (17) 18.5 (16) 18 (15.5) 20 (17.5) 19 (16.5) 20 (17.5) 19.5 (17) 19.5 (17) 19 (16.5) 18.5 (16) 17.5 (15)

19.5 (17) 18.5 (16) 19 (16.5) 18.5 (16) 19 (16.5) 18.5 (16) 17.5 (15) 16.5 (14) 18 (15.5) 17.5 (15) 17.5 (15) 17.5 (15) 18 (15.5) 18 (15.5) 17 (14.5) 16 (13.5) 18 (15.5) 17.5 (15) 18 (15.5) 18 (15.5) 17.5 (15) 17.5 (15) 16.5 (14) 15.5 (13)

CHOPPING ENABLED

External Reference

Table 5 shows the AD7794’s output rms noise for some of the update rates and gain settings. The numbers given are for the bipolar input range with an external 2.5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. Table 6 shows the effective resolution while the output peak-to-peak (p-p) resolution is listed in brackets. It is important to note that the effective resolution is calculated using the rms noise while the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there will be no code flicker. These numbers are typical and are rounded to the nearest LSB.

Rev. 0 | Page 12 of 36

Page 13

AD7794

Internal Reference

Table 7 shows the AD7794’s output rms noise for some of the update rates and gain settings. The numbers given are for the bipolar input range with the internal 1.17 V reference. These numbers are typical and are generated with a differential input voltage of 0V. Table 8 shows the effective resolution while the output peak-to-peak (p-p) resolution is listed in brackets. It is important to note that the effective resolution is calculated

Table 7. Output RMS Noise (µV) vs. Gain and Output Update Rate (Internal Reference) with Chop Enabled

Update Rate Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

4.17 Hz

8.33 Hz

16.7 Hz

33.3 Hz

62.5 Hz 125 Hz 250 Hz 500 Hz

0.81 0.67 0.32 0.2 0.13 0.065 0.04 0.039

1.18 1.11 0.41 0.25 0.16 0.078 0.058 0.059

1.96 1.72 0.55 0.36 0.25 0.11 0.088 0.088

2.99 2.48 0.83 0.48 0.33 0.17 0.13 0.12

3.6 3.25 1.03 0.65 0.46 0.2 0.15 0.15

5.83 5.01 1.69 0.96 0.67 0.32 0.25 0.26

11.22 8.64 2.69 1.9 1.04 0.45 0.35 0.34

12.46 10.58 4.58 2 1.27 0.63 0.50 0.49

Table 8. Typical Resolution (Bits) vs. Gain and Output Update Rate (Internal Reference) with Chop Enabled

Update Rate Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

4.17 Hz

8.33 Hz

16.7 Hz

33.3 Hz

62.5 Hz 125 Hz 250 Hz 500 Hz

21 (18.5) 20 (17.5) 20.5 (18) 20 (17.5) 19.5 (17) 19.5 (17) 19.5 (17) 18.5 (16)

20.5 (18) 19.5 (17) 20 (17.5) 19.5 (17) 19.5 (17) 19.5 (17) 18.5 (16) 17.5 (15)

19.5 (17) 19 (16.5) 19.5 (17) 19 (16.5) 18.5 (16) 19 (16.5) 18 (15.5) 17 (14.5) 19 (16.5) 18.5 (16) 19 (16.5) 18.5 (16) 18 (15.5) 18 (15.5) 17.5 (15) 16.5 (14)

18.5 (16) 18 (15.5) 18.5 (16) 18.5 (16) 18 (15.5) 18 (15.5) 17.5 (15) 16.5 (14) 18 (15.5) 17.5 (15) 18 (15.5) 17.5 (15) 17 (14.5) 17.5 (15) 16.5 (14) 15.5 (13) 17 (14.5) 16.5 (14) 17 (14.5) 16.5 (14) 16.5 (14) 17 (14.5) 16 (13.5) 15 (12.5) 17 (14.5) 16.5 (14) 16.5 (14) 16.5 (14) 16.5 (14) 16.5 (14) 15.5 (13) 14.5 (12)

using the rms noise while the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there will be no code flicker. These numbers are typical and are rounded to the nearest LSB.

Rev. 0 | Page 13 of 36

Page 14

AD7794

CHOPPING DISABLED

With chopping disabled, the switching time or settling time is reduced by a factor of 2. However, periodic offset calibrations may now be required to remove offset and offset drift. When chopping is disabled, the AMP-CM bit in the mode register should be set to 1. This limits the allowable common-mode voltage that can be used. However, the common-mode rejection will degrade if the bit is not set.

Table 9 shows the AD7794’s output rms noise for some of the update rates and gain settings with chopping disabled. The

Table 9. Output RMS Noise (µV) vs. Gain and Output Update Rate Using the Internal Reference with Chop Disabled

Update Rate Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

4.17 Hz

8.33 Hz

16.7 Hz

33.3 Hz

62.5 Hz 125 Hz 250 Hz 500 Hz

1.22 0.98 0.33 0.18 0.13 0.062 0.053 0.051

1.74 1.53 0.49 0.29 0.21 0.1 0.079 0.07

2.64 2.44 0.79 0.48 0.33 0.16 0.13 0.12

4.55 3.52 1.11 0.66 0.46 0.21 0.17 0.16

5.03 4.45 1.47 0.81 0.58 0.27 0.2 0.22

8.13 7.24 2.27 1.33 0.96 0.48 0.36 0.37

15.12 13.18 3.77 2.09 1.45 0.64 0.5 0.47

17.18 14.63 8.86 2.96 1.92 0.89 0.69 0.7

Table 10. Typical Resolution (Bits) vs. Gain and Output Update Rate Using the Internal Reference with Chop Disabled

Update Rate Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

4.17 Hz

8.33 Hz

16.7 Hz

33.3 Hz

62.5 Hz 125 Hz 250 Hz 500 Hz

20.5 (18) 19.5 (17) 20 (17.5) 20 (17.5) 19.5 (17) 19.5 (17) 19 (16.5) 18 (15.5) 20 (17.5) 19 (16.5) 19.5 (17) 19.5 (17) 19 (16.5) 19 (16.5) 18.5 (16) 17.5 (15) 19 (16.5) 18.5 (16) 19 (16.5) 18.5 (16) 18 (15.5) 18.5 (16) 17.5 (15) 16.5 (14)

18.5 (16) 18 (15.5) 18.5 (16) 18 (15.5) 18 (15.5) 18 (15.5) 17.5 (15) 16.5 (14)

18.5 (16) 17.5 (15) 18 (15.5) 18 (15.5) 17.5 (15) 17.5 (15) 17 (14.5) 16 (13.5)

17.5 (15) 17 (14.5) 17.5 (15) 17 (14.5) 16.5 (14) 16.5 (14) 16 (13.5) 15 (12.5)

16.5 (14) 16 (13.5) 16.5 (14) 16.5 (14) 16 (13.5) 16.5 (14) 15.5 (13) 14.5 (12)

16.5 (14) 16 (13.5) 15.5 (13) 16 (13.5) 15.5 (13) 15.5 (13) 15 (12.5) 14 (11.5)

numbers given are for the bipolar input range with the internal

1.17 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. Table 10 shows the effective resolution while the output peak-to-peak (p-p) resolution is listed in brackets. It is important to note that the effective resolution is calculated using the rms noise, while the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there will be no code flicker. These numbers are typical and are rounded to the nearest LSB.

Rev. 0 | Page 14 of 36

Page 15

AD7794

TYPICAL PERFORMANCE CHARACTERISTICS

8388800

8388750

8388700

8388650

8388600

CODE READ

8388550

8388500

8388450

0 1000800600400200

READING NUMBER

Figure 6. Typical Noise Plot (Internal Reference, Gain = 64,

Update Rate = 16.7 Hz, Chop Enabled)

OCCURANCE

04854-006

OCCURANCE

8388068 8388396838835083883008388250838820083881508388100

CODE

04854-009

Figure 9. Noise Distribution Histogram (Internal Reference, Gain = 64,

Update Rate = 16.7 Hz, Chop Disabled, AMP-CM = 1)

(%)

8388482 8388750838872083886808388640838860083885608388520

04854-007

Figure 7. Noise Distribution Histogram (Internal Reference, Gain = 64,

Update Rate = 16.7 Hz, Chop Enabled)

8388450

8388400

8388350

8388300

8388250

CODE READ

8388200

8388150

8388100

8388050

0 1000800600400200

READING NUMBER

Figure 8. Typical Noise Plot when Gain = 64 and Internal Reference Selected

(Chop Disabled, AMP-CM = 1)

04854-008

–2.0 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0

MATCHING (%)

04854-010

Figure 10. Excitation Current Matching (210 µA) at Ambient Temperature

POWER-UP TIME (ms)

0 200 400 600 800 1000

LOAD CAPACITANCE (nF)

04854-011

Figure 11. Bias Voltage Generator Power Up Time vs. Load Capacitance

Rev. 0 | Page 15 of 36

Page 16

AD7794

ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.

COMMUNICATIONS REGISTER

(RS2, RS1, RS0 = 0, 0, 0)

The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 11 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

WEN(0) R/W(0)

Table 11. Communications Register Bit Designations

Bit Location Bit Name Description

CR7

CR6

CR5–CR3 RS2–RS0

CR2 CREAD

CR1–CR0 0 These bits must be programmed to logic 0 for correct operation.

Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually

WEN

A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this

R/W

Table 12. Register Selection

RS2 RS1 RS0 Register Register Size

0 0 0 Communications Register during a Write Operation 8-Bit 0 0 0 Status Register during a Read Operation 8-Bit 0 0 1 Mode Register 16-Bit 0 1 0 Configuration Register 16-Bit 0 1 1 Data Register 24-Bit 1 0 0 ID Register 8-Bit 1 0 1 IO Register 8-Bit 1 1 0 Offset Register 24-Bit 1 1 1 Full-Scale Register 24-Bit

RS2(0) RS1(0) RS0(0) CREAD(0) 0(0) 0(0)

occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN loaded to the communications register.

position indicates that the next operation will be a read from the designated register. Register Address Bits. These address bits are used to select which of the ADC’s registers are being selected

during this serial interface communication. See Table 12. Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial

interface is configured so that the data register can be continuously read, i.e., the contents of the data register are placed on the DOUT pin automatically when the SCLK pulses are applied after the RDY goes low to indicate that a conversion is complete. The communications register does not have to be written to for data reads. To enable continuous read mode, the instruction 01011100 must be written to the communications register. To exit the continuous read mode, the instruction 01011000 must be written to the communications register while the RDY monitors activity on the DIN line so that it can receive the instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device.

pin is low. While in continuous read mode, the ADC

bit, the next seven bits will be

Rev. 0 | Page 16 of 36

Page 17

AD7794

STATUS REGISTER

(RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x88)

The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load bits RS2, RS1, and RS0 with 0. Table 13 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

RDY(1)

Table 13. Status Register Bit Designations

Bit Location Bit Name Description

SR7

SR6 ERR

SR5 NOREF

SR4 0 This bit is automatically cleared. SR3 1 This bit is automatically set. SR2–SR0 CH2–CH0 These bits indicate which channel is being converted by the ADC.

ERR(0) NOREF(0) 0(0) 1(1) CH2(0) CH1(0) CH0(0)

Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically

RDY

after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is also indicated by the DOUT/RDY be used as an alternative to the status register for monitoring the ADC for conversion data.

ADC Error Bit. This bit is written to at the same time as the RDY the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange, or the absence of a reference voltage. Cleared by a write operation to start a conversion.

No External Reference Bit. Set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is below a specified threshold. When set, conversion results are clamped to all ones. Cleared to indicate that a valid reference is applied to the selected reference pins. The NOXREF bit is enabled by setting the REF_DET bit in the configuration register to 1. The ERR bit is also set if the voltage applied to the selected reference input is invalid.

bit. Set to indicate that the result written to

pin. This pin can

MODE REGISTER

(RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A)

The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the update rate and the clock source. Table 14 outlines the bit designations for the mode register. MR0 through MR15 indicate the bit locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the RDY

bit.

MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8

MD2(0) MD1(0) MD0(0) PSW(0) 0(0) 0(0) AMP-CM(0) 0(0)

MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0

CLK1(0) CLK0(0) 0(0) CHOP-DIS(0) FS3(1) FS2(0) FS1(1) FS0(0)

Table 14. Mode Register Bit Designations

Bit Location Bit Name Description MR15–MR13 MD2–MD0 Mode Select Bits. These bits select the operational mode of the AD7794 (see Table 15). MR12 PSW

MR11–MR10 0 These bits must be programmed with a Logic 0 for correct operation. MR9 AMP-CM

Power Switch Control Bit. sink up to 30 mA. Cleared by user to open the power switch. When the ADC is placed in power-down mode, the power switch is opened.

Instrumentation Amplifier Common-Mode Bit. It is used in conjunction with the CHOP-DIS bit. When chopping is disabled, the user can operate with a wider range of common mode voltages when AMP-CM is cleared. However, the dc common-mode rejection will degrade.

Set by user to close the power switch PSW to GND. The power switch can

Rev. 0 | Page 17 of 36

Page 18

AD7794

Bit Location Bit Name Description

With AMP-CM set, the span for the common-mode voltage is reduced (see Specifications section). However, the dc common-mode rejection is significantly better. MR8 0 This bit must be programmed with a Logic 0 for correct operation. MR7–MR6 CLK1–CLK0

0 0 Internal 64 kHz clock. Internal clock is not available at the CLK pin 0 1 Internal 64 kHz clock. This clock is made available at the CLK pin 1 0

1 1 External clock used. The external clock is divided by 2 within the AD7794. MR5 0 This bit must be programmed with a Logic 0 for correct operation. MR4 CHOP–DIS

MR3–MR0 FS3–FS0 Filter Update Rate Select Bits (see Table 16).

Table 15. Operating Modes

MD2 MD1 MD0 Mode

0 0 0 Continuous Conversion Mode (Default).

In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communications register. After power-on, the first conversion is available after a period 2/f when chopping is disabled. Subsequent conversions are available at a frequency of f enabled or disabled.

0 0 1 Single Conversion Mode.

When single conversion mode is selected, the ADC powers up and performs a single conversion. The oscillator requires 1 ms to power up and settle. The ADC then performs the conversion which takes a time of 2/f chopping is enabled or 1/f

goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY

active (low) until the data is read or another conversion is performed. 0 1 0 Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still provided. 0 1 1 Power-Down Mode.

In power-down mode, all the AD7794 circuitry is powered down including the current sources, power switch,

burnout currents, bias voltage generator, and CLKOUT circuitry. 1 0 0 Internal Zero-Scale Calibration.

An internal short is automatically connected to the enabled channel. A calibration takes 2 conversion cycles to

complete when chopping is enabled and 1 conversion cycle when chopping is disabled. RDY

calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a

calibration. The measured offset coefficient is placed in the offset register of the selected channel. 1 0 1 Internal Full-Scale Calibration. A full-scale input voltage is automatically connected to the selected analog input for this calibration.

When the gain equals 1, a calibration takes 2 conversion cycles to complete when chopping is enabled and 1

conversion cycle when chopping is disabled.

For higher gains, 4 conversion cycles are required to perform the full-scale calibration when chopping is enabled

and 2 conversion cycles when chopping is disabled.

goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed

RDY

in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the

selected channel.

These bits are used to select the clock source for the AD7794. Either the on-chip 64 kHz clock can be used or an external clock can be used. The ability to use an external clock allows several AD7794 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7794.

CLK1 CLK0 ADC Clock Source

External 64 kHz clock used. The external clock can have a 45:55 duty cycle. See specifications for external clock.

This bit is used to enable or disable chopping. On power-up or following a reset, CHOP-DIS is cleared so chopping is enabled. When CHOP-DIS is set, chopping is disabled. This bit is used in conjunction with the AMP-CM bit. When chopping is disabled, the AMP-CM bit should be set. This will limit the common mode voltage which can be used by the ADC but the dc common-mode rejection will not degrade.

goes low when a conversion is complete. The user can read these conversions by placing the device in

when chopping is enabled or 1/f

ADC

when chopping is disabled. The conversion result in placed in the data register, RDY

ADC

with chopping either

ADC

when

remains

goes high when the

Rev. 0 | Page 18 of 36

Page 19

AD7794

MD2 MD1 MD0 Mode

Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a system fullscale calibration can be performed.

A full-scale calibration is required each time the gain of a channel is changed to minimize the Full-Scale error.

1 1 0 System Zero-Scale Calibration.

1 1 1 System Full-Scale Calibration. User should connect the system full-scale input to the channel input pins as selected by the CH2–CH0 bits.

A full-scale calibration is required each time the gain of a channel is changed.

Table 16. Update Rates Available (Chopping Enabled)

FS3 FS2 FS1 FS0 f

0 0 0 0 x x 0 0 0 1 500 4 0 0 1 0 250 8 0 0 1 1 125 16 0 1 0 0 62.5 32 0 1 0 1 50 40 0 1 1 0 39.2 48 0 1 1 1 33.3 60 1 0 0 0 19.6 101 90 dB (60 Hz only) 1 0 0 1 16.7 120 80 dB (50 Hz only) 1 0 1 0 16.7 120 65 dB (50 Hz and 60 Hz) 1 0 1 1 12.5 160 66 dB (50 Hz and 60 Hz) 1 1 0 0 10 200 69 dB (50 Hz and 60 Hz) 1 1 0 1 8.33 240 70 dB (50 Hz and 60 Hz) 1 1 1 0 6.25 320 72 dB (50 Hz and 60 Hz) 1 1 1 1 4.17 480 74 dB (50 Hz and 60 Hz)

User should connect the system zero-scale input to the channel input pins as selected by the CH2–CH0 bits. A system offset calibration takes 2 conversion cycles to complete when chopping is enabled and one conversion cycle when chopping is disabled. RDY calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel.

A calibration takes 2 conversion cycles to complete when chopping is enabled and one conversion cycle when chopping is disabled. RDY complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel.

ADC

goes high when the calibration is initiated and returns low when the calibration is

(Hz) T

goes high when the calibration is initiated and returns low when the

(ms) Rejection@ 50 Hz/60 Hz (Internal Clock)

SETTLE

With chopping disabled, the update rates remain unchanged but the settling time for each update rate is reduced by a factor of 2. The rejection at 50 Hz/60 Hz for a 16.6 Hz update rate degrades to 60 dB.

CONFIGURATION REGISTER

(RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710)

The configuration register is a 16-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain, and select the analog input channel. Table 17 outlines the bit designations for the filter register. CON0 through CON15 indicate the bit locations, CON denoting the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.

CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8

VBIAS1(0) VBIAS0(0) BO(0)

CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0

REFSEL1(0) REFSEL0(0) REF_DET(0) BUF(1) CH3(0) CH2(0) CH1(0) CH0(0)

Rev. 0 | Page 19 of 36

U/B

(0)

BOOST0) G2(1) G1(1) G0(1)

Page 20

AD7794

Table 17. Configuration Register Bit Designations

Bit Location Bit Name Description

CON15– CON14

0 0 Bias Voltage Generator Disabled 0 1 Bias Voltage Generator connected to AIN1(−) 1 0 Bias Voltage Generator connected to AIN2(−) 1 1 Bias Voltage Generator connected to AIN3(−) CON13 BO This bit must be programmed with a Logic 0 for correct operation.

CON12

CON11 BOOST

CON10– CON8

Written by the user to select the ADC input range as follows:

0 0 0 1 (In-Amp not used) 2.5 V 0 0 1 2 (In-Amp not used) 1.25 V 0 1 0 4 625 mV 0 1 1 8 312.5 mV 1 0 0 16 156.2 mV 1 0 1 32 78.125 mV 1 1 0 64 39.06 mV 1 1 1 128 19.53 mV CON7–

CON6

0 0 External Reference applied between REFIN1(+) and REFIN1(–) 0 1 External Reference applied between REFIN2(+) and REFIN2(–) 1 0 Internal 1.17 V Reference 1 1 Reserved CON5 REF_DET Enables the Reference Detect Function.

When cleared, the reference detect function is disabled. CON4 BUF

CON3– CON0

Written by the user to select the active analog input channel to the ADC.

VBIAS1 – VBIAS0

Bias Voltage Generator Enable. The negative terminal of the analog inputs can be biased up to AV These bits are used in conjunction with the BOOST bit.

VBIAS1 VBIAS0 Bias Voltage

Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer or in-amp is active.

Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in

U/B

0x000000 output and a full-scale differential input will result in 0xFFFFFF output. Cleared by the user to enable bipolar coding. Negative full-scale differential input will result in an output code of 0x000000, zero differential input will result in an output code of 0x800000, and a positive full-scale differential input will result in an output code of 0xFFFFFF.

This bit is used in conjunction with the VBIAS1 and VBIAS0 bits. When set, the current consumed by the bias voltage generator is increased which reduces its power-up time.

G2–G0 Gain Select Bits.

G2 G1 G0 Gain ADC Input Range (2.5 V Reference)

REFSEL1/REFSEL0 Reference Select Bits. The reference source for the ADC is selected using these bits.

REFSEL1 REFSEL0 Reference Source

When set, the NOXREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.5 V.

Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. For gains of 1 and 2, the buffer can be enabled or disabled. For higher gains, the buffer is automatically enabled.

With the buffer disabled, the voltage on the analog input pins can be from 30 mV below GND to 30 mV above AV

. When the buffer is enabled, it requires some headroom so the voltage on any input pin must

be limited to 100 mV within the power supply rails.

CH3–CH0 Channel Select Bits.

/2.

Rev. 0 | Page 20 of 36

Page 21

AD7794

Bit Location Bit Name Description

0 0 0 0 AIN1(+) − AIN1(−) 0 0 0 0 1 AIN2(+) – AIN2(−) 1 0 0 1 0 AIN3(+)− AIN3(−) 2 0 0 1 1 AIN4(+)− AIN4(−) 3 0 1 0 0 AIN5(+)− AIN5(−) 3 0 1 0 1 AIN6(+)− AIN6(−) 3 0 1 1 0 Temp Sensor

0 1 1 1 AVDD Monitor

1 0 0 0 AIN1(−)− AIN1(−) 0 1 0 0 1 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved

DATA REGISTER

(RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000)

CH3 CH2 CH1 CH0 Channel Calibration Pair

Automatically selects the internal reference and sets the gain to 1

Automatically selects the internal 1.17 V reference and sets the gain to 1/6

The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from

RDY

this register, the

bit/pin is set.

ID REGISTER

(RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xXF)

The identification number for the AD7794 is stored in the ID register. This is a read-only register.

IO REGISTER

(RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00)

The IO register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the excitation currents and select the value of the excitation currents. Table 18 outlines the bit designations for the IO register. IO0 t hrough IO7 indicate the bit locations, IO denoting the bits are in the IO register. IO7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.

IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

0(0) IOEN(0) IO2DAT(0) IO1DAT(0) IEXCDIR1(0) IEXCDIR0(0) IEXCEN1(0) IEXCEN0(0)

Rev. 0 | Page 21 of 36

Page 22

AD7794

Table 18. IO Register Bit Designations

Bit Location Bit Name Description IO7 0 This bit must be programmed with a Logic 0 for correct operation. IO6 IOEN Configures the pins AIN6(+)/P2 and AIN6(−)/P2 as analog input pins or digital output pins. When this bit is set, the pins are configured as Digital Output Pins P1 and P2. When this bit is cleared, these pins are configured as Analog Input Pins AIN6(+) and AIN6(−). IO5–IO4 IO2DAT/IO1DAT P2/P1 Data.

IO3–IO2

0 0

0 1

1 0

1 1

IO3–IO2

0 0 Excitation Currents Disabled 0 1 10 µA 1 0 210 µA 1 1 1 mA

IEXCDIR1– IEXCDIR0

IEXCEN1– IEXCEN0

When IOEN is set, the data for the Digital Output Pins P1 and P2 is written to Bits IO2DAT and IO1DAT.

Direction of Current Sources Select bits.

EXCDIR1 IEXCDIR0 IEXCDIR0

Current Source IEXC1 connected to Pin IOUT1. Current Source IEXC2 connected to Pin IOUT2.

Current Source IEXC1 connected to Pin IOUT2. Current Source IEXC2 connected to Pin IOUT1.

Both current sources connected to Pin IOUT1. Permitted only when the current sources are set to 10 µA or 210 µA.

Both current sources connected to Pin IOUT2. Permitted only when the current sources are set to 10 µA or 210 µA.

These bits are used to enable and disable the current sources along with selecting the value of the excitation currents.

IEXCEN1 IEXCEN0 Current Source Value

OFFSET REGISTER

(RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000)

The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The AD7794 has four offset registers. Channels AIN1 to AIN3 have dedicated offset registers while channels AIN4, AIN5 and AIN6 share an offset register. Each of these registers is a 24-bit read/write register. This register is used in conjunction with its associated full-scale register to form a register pair. The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7794 must be placed in power-down mode or idle mode when writing to the offset register.

FULL-SCALE REGISTER

(RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX00)

The full-scale register is a 24-bit register that holds the full-scale calibration coefficient for the ADC. The AD7794 has 4 full-scale registers. Channels AIN1, AIN2 and AIN3 have dedicated full-scale registers while channels AIN4, AIN5, and AIN6 share a register. The full-scale registers are read/write registers. However, when writing to the full-scale registers, the ADC must be placed in power-down mode or idle mode. These registers are configured on power-on with factory-calibrated full-scale calibration coefficients, the calibration being performed at gain = 1. Therefore, every device will have different default coefficients. The coefficients are different depending on whether the internal reference or an external reference is selected. The default value will be automatically overwritten if an internal or system full-scale calibration is initiated by the user, or the full-scale register is written to.

Rev. 0 | Page 22 of 36

Page 23

AD7794

ADC CIRCUIT INFORMATION

OVERVIEW

The AD7794 is a low power ADC that incorporates a ∑-∆ modulator, a buffer, reference, In-amp, and on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in pressure transducers, weigh scales, and temperature measurement applications.

The part has six differential inputs that can be buffered or unbuffered. The device can be operated with the internal 1.17 V reference or an external reference can be used. Figure 12 shows the basic connections required to operate the part.

REFIN1(+)

GND AV

AD7794

INTERFACE

MUX

BUF

GND

IN-AMP

Σ-∆

ADC

INTERNAL

CLOCK

CLK

SERIAL

AND

LOGIC

CONTROL

DOUT/RDY DIN SCLK CS

IN+

OUT– OUT+

IN–

IN+

OUT– OUT+

IN–

AIN1(+) AIN1(–)

AIN2(+) AIN2(–) AIN3(+)

AIN3(–) REFIN2(+)

REFIN2(–) IOUT1

REFIN1(–) PSW

Figure 12. Basic Connection Diagram

04854-012

–20

–40

(dB)

–60

–80

–100

0 12010080604020

FREQUENCY (Hz)

Figure 13. Filter Profile with Update Rate = 4.17 Hz (Chop Enabled)

–20

–40

(dB)

–60

04854-017

The output rate of the AD7794 (f

) is user programmable.

ADC

The allowable update rates along with the corresponding settling times are listed in Table 16 for chop enabled. With chop disabled, the allowable update rates remain unchanged but the settling time equals 1/f

. Normal mode rejection is the major

ADC

function of the digital filter. Simultaneous 50 Hz and 60 Hz rejection is optimized when the update rate equals 16.7 Hz or less as notches are placed at both 50 Hz and 60 Hz with these update rates (see Figure 14).

The AD7794 uses slightly different filter types depending on the output update rate so that the rejection of quantization noise and device noise is optimized. When the update rate is from

4.17 Hz to 12.5 Hz, a Sinc

filter along with an averaging filter is

used. When the update rate is from 16.7 Hz to 39.2 Hz, a

modified Sinc

filter is used. This filter gives simultaneous

50 Hz/60 Hz rejection when the update rate equals 16.7 Hz. A

filter is used when the update rate is from 50 Hz to 250

Sinc Hz. Finally, an integrate-only filter is used when the update rate equals 500 Hz. Figure 13 to Figure 16 show the frequency response of the different filters types for some of the update rates when chopping is enabled. In this mode, the settling time equals twice the update rate. Figure 17 to Figure 20 show the filter response with chopping disabled.

–80

–100

0 20018016014012010080604020

FREQUENCY (Hz)

Figure 14. Filter Profile with Update Rate = 16.7 Hz (Chop Enabled)

–20

–40

(dB)

–60

–80

–100

0 30002500200015001000500

FREQUENCY (Hz)

Figure 15. Filter Profile with Update Rate = 250 Hz (Chop Enabled)

04854-018

04854-019

Rev. 0 | Page 23 of 36

Page 24

AD7794

(dB)

–10

–20

–30

–40

–50

–60

0 10000900080007000600050004000300020001000

FREQUENCY (Hz)

Figure 16. Filter Response at 50 0 Hz Update Rate (Chop Enabled)

–20

–40

(dB)

–60

04854-020

–20

–40

(dB)

–60

–80

–100

0 30002500200015001000500

FREQUENCY (Hz)

Figure 19. Filter Response at 25 0 Hz Update Rate (Chop Disabled)

–10

–20

–30

(dB)

–40

04854-023

–80

–100

0 12010080604020

FREQUENCY (Hz)

Figure 17. Filter Response at 4. 17 Hz Update Rate (Chop Disabled)

–20

–40

(dB)

–60

–80

–100

0 200100 120 140 160 18080604020

FREQUENCY (Hz)

Figure 18. Filter Response at 16 .7 Hz Update Rate (Chop Disabled)

04854-021

04854-022

–50

–60

0 100005000 6000 7000 8000 90004000300020001000

FREQUENCY (Hz)

Figure 20. Filter Response at 50 0 Hz Update Rate (Chop Disabled)

04854-024

Rev. 0 | Page 24 of 36

Page 25

AD7794

DIGITAL INTERFACE

As previously outlined, the AD7794’s programmable functions are controlled using a set of on-chip registers. Data is written to these registers via the part’s serial interface and read access to the on-chip registers is also provided by this interface. All communications with the part must start with a write to the communications register. After power-on or reset, the device expects a write to its communications register. The data written to this register determines whether the next operation is a read operation or a write operation and also determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part begins with a write operation to the communications register followed by a write to the selected register. A read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register followed by a read operation from the selected register.

shows the timing for a read operation from the AD7794’s output shift register while Figure 4 shows the timing for a write operation to the input shift register. It is possible to read the same word from the data register several times even though the

RDY

DOUT/

line returns high after the first read operation. However, care must be taken to ensure that the read operations have been completed before the next output update occurs. In continuous read mode, the data register can be read only once.

The serial interface can operate in 3-wire mode by tying

RDY

In this c ase, t he SCLK, DIN, and D OUT/

lines are used to

low.

communicate with the AD7794. The end of the conversion can be monitored using the scheme is suitable for interfacing to microcontrollers. If

RDY

bit in the status register. This

is required as a decoding signal, it can be generated from a port pin. For microcontroller interfaces, it is recommended that SCLK idles high between data transfers.

The AD7794’s serial interface consists of four signals:

RDY

SCLK, and DOUT/ into the on-chip registers while DOUT/

. The DIN line is used to transfer data

RDY

is used for

, DIN,

accessing from the on-chip registers. SCLK is the serial clock input for the device and all data transfers (either on DIN or

RDY

DOUT/ DOUT/

) occur with respect to the SCLK signal. The

RDY

pin operates as a data ready signal also, the line going low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the data register to indicate when not to read from the device, to ensure that a data read is not attempted while the register is being updated.

is used to select a device. It can be used to decode the AD7794 in systems where several components are connected to the serial bus.

Figure 3 and Figure 4 show timing diagrams for interfacing to

the AD7794 with

being used to decode the part. Figure 3

The AD7794 can be operated with

being used as a frame synchronization signal. This scheme is useful for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by

since

would normally occur after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers, provided the timing numbers are obeyed.

The serial interface can be reset by writing a series of 1s on the DIN input. If a Logic 1 is written to the AD7794 line for at least 32 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system. Reset returns the interface to the state in which it is expecting a write to the communications register. This operation resets the contents of all registers to their power-on values. Following a reset, the user should allow a period of 500 µs before addressing the serial interface.

The AD7794 can be configured to continuously convert or to perform a single conversion. See Figure 21 through Figure 23.

Rev. 0 | Page 25 of 36

Page 26

AD7794

DIN

DOUT/RD

SCLK

0x08 0x200A

Figure 21. Single Conversion

Single Conversion Mode

In single conversion mode, the AD7794 is placed in shutdown mode between conversions. When a single conversion is initiated by setting MD2, MD1, MD0 to 0, 0, 1 in the mode register, the AD7794 powers up, performs a single conversion, and then returns to shutdown mode. The on-chip oscillator requires 1 ms to power up. A conversion will require a time period of 2 × t

. DOUT/

ADC

goes low to indicate the com-

RDY

pletion of a conversion. When the data-word has been read from the data register, DOUT/

DOUT/

will remain high until another conversion is

RDY

will go high. If CS is low,

RDY

initiated and completed. The data register can be read several times, if required, even when DOUT/

has gone high.

RDY

0x58

DATA

Continuous Conversion Mode

This is the default power-up mode. The AD7794 continuously converts, the

a conversion is complete. If

pin in the status register going low each time

RDY

is low, the DOUT/

RDY

line also

goes low when a conversion is complete. To read a conversion, the user can write to the communications register, indicating that the next operation is a read of the data register. The digital conversion is placed on the DOUT/

pulses are applied to the ADC. DOUT/

pin as soon as SCLK

RDY

returns high when

RDY

the conversion is read. The user can read this register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion or else the new conversion word will be lost.

04854-014

DIN

DOUT/RDY

SCLK

0x58 0x58

DATA DATA

04854-015

Figure 22. Continuous Conversion

Rev. 0 | Page 26 of 36

Page 27

AD7794

CONTINUOUS READ

Rather than write to the communications register each time a conversion is complete to access the data, the AD7794 can be configured so that the conversions are placed on the DOUT/ RDY

line automatically. By writing 01011100 to the communications register, the user needs only to apply the appropriate number of SCLK cycles to the ADC and the 24-bit word will

RDY

automatically be placed on the DOUT/ conversion is complete. The ADC should be configured for continuous conversion mode.

When DOUT/

RDY

goes low to indicate the end of a conversion, sufficient SCLK cycles must be applied to the ADC and the data conversion will be placed on the DOUT/

RDY

the conversion is read, DOUT/

will return high until the next conversion is available. In this mode, the data can be read only once. Also, the user must ensure that the data-word is read

line when a

RDY

line. When

before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the AD7794 to read the word, the serial output register is reset when the next conversion is complete and the new conversion is placed in the output serial register.

To exit the continuous read mode, the instruction 01011000 must be written to the communications register while the pin is low. While in the continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit the continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device.

RDY

DIN

DOUT/RDY

SCLK

0x5C

DATA DATA DATA

Figure 23. Continuous Read

04854-016

Rev. 0 | Page 27 of 36

Page 28

AD7794

CIRCUIT DESCRIPTION

ANALOG INPUT CHANNEL

The AD7794 has six differential analog input channels. These are connected to the on-chip buffer amplifier when the device is operated in buffered mode and directly to the modulator when the device is operated in unbuffered mode. In buffered mode (the BUF bit in the mode register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. Therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive-type sensors such as strain gauges or resistance temperature detectors (RTDs).

When BUF = 0, the part is operated in unbuffered mode. This results in a higher analog input current. Note that this unbuffered input path provides a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input pins can cause gain errors, depending on the output impedance of the source that is driving the ADC input. allowable external resistance/capacitance values for unbuffered mode such that no gain error at the 20-bit level is introduced.

Table 19. External R-C Combination for No 20-Bit Gain Error

C (pF) R (Ω)

50 9 K 100 6 K 500 1.5 K 1000 900 5000 200

The AD7794 can be operated in unbuffered mode only when the gain equals 1 or 2. At higher gains, the buffer is automatically enabled. The absolute input voltage range in buffered mode is restricted to a range between GND + 100 mV and AV – 100 mV. When the gain is set to 4 or higher, the in-amp is enabled. The absolute input voltage range when the in-amp is active is restricted to a range between GND + 300 mV and

– 1.1 V. Care must be taken in setting up the common-

mode voltage so that these limits are not exceeded. Otherwise, there will be degradation in linearity and noise performance.

The absolute input voltage in unbuffered mode includes the range between GND – 30 mV and AV being unbuffered. The negative absolute input voltage limit does allow the possibility of monitoring small true bipolar signals with respect to GND.

INSTRUMENTATION AMPLIFIER

Amplifying the analog input signal by a gain of 1 or 2 is performed digitally within the AD7794. However, when the gain equals 4 or higher, the output from the buffer is applied to the input of the on-chip instrumentation amplifier. This low noise in-amp means that signals of small amplitude can be gained

Table 1 9 shows the

+ 30 mV as a result of

within the AD7794 while still maintaining excellent noise performance. For example, when the gain is set to 64, the rms noise is 40 nV typically which is equivalent to 20.5 bits effective resolution or 18 bits peak-to-peak resolution.

The AD7794 can be programmed to have a gain of 1, 2, 4, 8, 16, 32, 64, and 128 using the Bits G2 to G0 in the configuration register. Therefore, with an external 2.5V reference, the unipolar ranges are from 0 mV to 20 mV to 0 V to 2.5 V while the bipolar ranges are from ±20 mV to ±2.5 V. When the in-amp is active (Gain >

4), the common-mode voltage ((AIN(+) + AIN(-))/2) must be greater than or equal to 0.5 V when chopping is enabled. With chopping disabled, and with the AMP-CM bit set to 1 to prevent degradation in the common-mode rejection, the allowable common-mode voltage is limited to between

0.2 + (Gain/2 x (AIN(+) - AIN(–)))

and

AVDD − 0.2 - (Gain/2 × (AIN(+) - AIN(–)))

If the AD7794 is operated with an external reference that has a value equal to AV signal must be limited to 90% of V

, for correct operation the analog input

/gain when the in-amp

REF

is active.

BIPOLAR/UNIPOLAR CONFIGURATION

The analog input to the AD7794 can accept either unipolar or bipolar input voltage ranges. A bipolar input range does not imply that the part can tolerate negative voltages with respect to system GND. Unipolar and bipolar signals on the AIN(+) input are referenced to the voltage on the AIN(−) input. For example, if AIN(−) is 2.5 V and the ADC is configured for unipolar mode with a gain of 1, the input voltage range on the AIN(+) pin is

2.5 V to 5 V.

If the ADC is configured for bipolar mode, the analog input range on the AIN(+) input is 0 V to 5 V. The bipolar/unipolar option is chosen by programming the B/U bit in the configuration register.

DATA OUTPUT CODING

When the ADC is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input voltage resulting in a code of 00...00, a mid-scale voltage resulting in a code of 100...000, and a full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as

Code = 2

× (AIN/V

REF

)

Rev. 0 | Page 28 of 36

Page 29

AD7794

When the ADC is configured for bipolar operation, the output code is offset binary with a negative full-scale voltage resulting in a code of 000...000, a zero differential input voltage resulting in a code of 100...000, and a positive full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as

Code = 2

× [(AIN/V

REF

) + 1]

N – 1

where AIN is the analog input voltage and N = 24.

BURNOUT CURRENTS

The AD7794 contains two 100 nA constant current generators, one sourcing current from AV current from AIN(–) to GND. The currents are switched to the selected analog input pair. Both currents are either on or off, depending on the burnout current enable (BO) bit in the configuration register. These current s can be used to verify that an external transducer is still operational before attempting to take measurements on that channel. Once the burnout currents are turned on, they will flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. If the resultant voltage measured is full scale, the user needs to verify why this is the case. A full-scale reading could mean that the front end sensor is open circuit, it could also mean that the front end sensor is overloaded and is justified in outputting full scale or, the reference may be absent and the NOXREF bit is set, thus clamping the data to all ones.

to AIN(+) and one sinking

amplifier requires headroom so signals close to GND or AV will not be converted accurately.

The bias voltage generator is controlled using the VBIAS1 and VBIAS0 bits in conjunction with the boost bit in the configuration register. The power up time of the bias voltage generator is dependent on the load capacitance. To accommodate higher load capacitances, the AD7794 has a boost bit. When this bit is set to 1, the current consumed by the bias voltage generator is increased so that the power up time is considerably reduced. Figure 11 shows the power up times when boost equals 0 and 1 for different load capacitances. The current consumption of the AD7794 increases by 40 µA when the bias voltage generator is enabled and boost equals 0. With the boost function enabled, the current consumption increases by 250 µA.

REFERENCE

The AD7794 has an embedded 1.17 V reference. This reference can be used to supply the ADC or an external reference can be applied. The embedded reference is a low noise, low drift reference, the drift being 4 ppm/ references, the ADC has a fully differential input capability for the channel. In addition, the user has the option of selecting one of two external reference options (REFIN1 or REFIN2). The reference source for the AD7794 is selected using the REFSEL1 and REFSEL0 bits in the configuration register. When the internal reference is selected, it is internally connected to the modulator (it is not available on the REFIN pins).

C typically. For external

When reading all ones from the output, the user needs to check these three cases before making a judgment. If the voltage measured is 0 V, it may indicate that the transducer has short circuited. For normal operation, these burnout currents are turned off by writing a 0 to the BO bit in the configuration register. The current sources work over the normal absolute input voltage range specifications with buffers on.

EXCITATION CURRENTS

The AD7794 also contains two matched, software configurable constant current sources which can be programmed to equal 10 µA, 210 µA or 1 mA. Both source currents from AV

are directed to either IOUT1 or IOUT2 pins of the device. These current sources are controlled via bits in the IO register. The configuration bits enable the current sources, direct the current sources to IOUT1 or IOUT2 along with selecting the value of the current. These current sources can be used to excite external resistive bridge or RTD sensors.

BIAS VOLTAGE GENERATOR

A bias voltage generator is included on the AD7794. This will bias the negative terminal of the selected input channel to

/2. This function is available on inputs AIN1 to AIN3. It is

useful in thermocouple applications as the voltage generated by the thermocouple must be biased about some dc voltage if the gain is greater than 2. This is required since the instrumentation

The common-mode range for these differential inputs is from GND to AV

. The reference input is unbuffered and, therefore,

excessive R-C source impedances will introduce gain errors. The reference voltage REFIN (REFIN(+) – REFIN(−)) is 2.5 V nominal, but the AD7794 is functional with reference voltages from 0.1 V to AV

. In applications where the excitation (vol-

tage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source will be removed because the application is ratiometric. If the AD7794 is used in a nonratiometric application, a low noise reference should be used.

Recommended 2.5 V reference voltage sources for the AD7794 include the ADR381 and ADR391, which are low noise, low power references. Also note that the reference inputs provide a high impedance, dynamic load. Because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors, depending on the output impedance of the source driving the reference inputs.

Reference voltage sources like those recommended above (e.g., ADR391) will typically have low output impedances and are, therefore, tolerant to having decoupling capacitors on REFIN(+) without introducing gain errors in the system. Deriving the reference input voltage across an external resistor will mean that

Rev. 0 | Page 29 of 36

Page 30

AD7794

the reference input sees a significant external source impedance. External decoupling on the REFIN pins would not be recommended in this type of circuit configuration.

REFERENCE DETECT

The AD7794 includes on-chip circuitry to detect if the part has a valid reference for conversions or calibrations if the user selects an external reference as the reference source. This feature is enabled when the REF-DET bit in the configuration register is set to 1. If the voltage between the selected REFIN(+) and REFIN(–) pins goes below 0.3 V or either the REFIN(+) or REFIN(–) inputs are open circuit, the AD7794 detects that it no longer has a valid reference. In this case, the NOXREF bit of the status register is set to 1. If the AD7794 is performing normal conversions and the NOXREF bit becomes active, the conversion results revert to all 1s. Therefore it is not necessary to continuously monitor the status of the NOXREF bit when performing conversions. It is only necessary to verify its status if the conversion result read from the ADC’s data register is all 1s. If the AD7794 is performing either an offset of full-scale calibration and the NOXREF bit becomes active, the updating of the respective calibration registers is inhibited to avoid loading incorrect coefficients to these registers and the ERR bit in the status register is set. If the user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the ERR bit should be checked at the end of the calibration cycle.

RESET

The circuitry and serial interface of the AD7794 can be reset by writing 32 consecutive 1s to the device. This will reset the logic, the digital filter and the analog modulator while all on-chip registers are reset to their default values. A reset is automatically performed on power up. When a reset is initiated, the user must allow a period of 500 µs before accessing any of the on-chip registers. A reset is useful if the serial interface becomes asynchronous due to noise on the SCLK line.

AVDD MONITOR

Along with converting external voltages, the ADC can be used to monitor the voltage on the AV equals 1, the voltage on the AV 6 and the resultant voltage is applied to the ∑-∆ modulator using an internal 1.17 V reference for analog to digital conversion. This is useful because variations in the power supply voltage can be monitored.

CALIBRATION

The AD7794 provides four calibration modes that can be programmed via the mode bits in the mode register. These are internal zero-scale calibration, internal full-scale calibration, system zero-scale calibration and system full-scale calibration which will effectively reduce the offset error and full-scale error to the order of the noise. After each conversion, the ADC

pin. When bit CH2 to CH0

pin is internally attenuated by

conversion result is scaled using the ADC calibration registers before being written to the data register. The offset calibration coefficient is subtracted from the result prior to multiplication by the full-scale coefficient.

To start a calibration, write the relevant value to the MD2 to MD0 bits in the mode register. After the calibration is complete, the contents of the corresponding calibration registers are

RDY

updated, the RDY

pin goes low (if CS is low) and the AD7794 reverts to idle

mode.

During an internal zero-scale or full-scale calibration, the respective zero input and full-scale input are automatically connected internally to the ADC input pins. A system calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the ADC pins before initiating the calibration mode. In this way, external ADC errors are removed.

From an operational point of view, a calibration should be treated like another ADC conversion. A zero-scale calibration (if required) should always be performed before a full scale calibration. System software should monitor the status register or the DOUT/ calibration via a polling sequence or an interrupt-driven routine.

With chopping enabled, both an internal offset calibration and a system offset calibration take two conversion cycles. With chopping enabled, an internal offset calibration is not needed as the ADC itself removes the offset continuously. With chopping disabled, an internal offset calibration or system offset calibration takes one conversion cycle to complete. Internal offset calibrations are required with chopping disabled and should occur before the full-scale calibration.

To perform an internal full-scale calibration, a full-scale input voltage is automatically connected to the selected analog input for this calibration. When the gain equals 1 a calibration takes 2 conversion cycles to complete when chopping is enabled and 1 conversion cycle when chopping is disabled. For higher gains, 4 conversion cycles are required to perform the full-scale calibration when chopping is enabled and 2 conversion cycles when chopping is disabled. DOUT/ calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the fullscale register of the selected channel. Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a system full-scale calibration can be performed. A full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error.

An internal full-scale calibration can be performed at specified update rates only. For gains of 1, 2, and 4, an internal full-scale

bit in the status register is set, the DOUT/

RDY

bit in the

RDY

pin to determine the end of

RDY

goes high when the

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AD7794

calibration can be performed at any update rate. However, for higher gains, internal full-scale calibrations can only be performed when the update rate is less than or equal to 16.7 Hz,

33.3Hz, and 50 Hz only. However, the full-scale error does not vary with update rate so a calibration at one update is valid for all update rates (assuming the gain or reference source is not changed).

A system full-scale calibration takes 2 conversion cycles to complete irrespective of the gain setting when chopping is enabled and 1 conversion cycle when chopping is disabled. A system full-scale calibration can be performed at all gains and all update rates. With chopping disabled, the offset calibration (internal or system offset) should be performed before the system full-scale calibration is initiated.

GROUNDING AND LAYOUT

Since the analog inputs and reference inputs of the ADC are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejection of the part will remove common-mode noise on these inputs. The digital filter will provide rejection of broadband noise on the power supply, except at integer multiples of the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. As a result, the AD7794 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7794 is so high, and the noise levels from the AD7794 are so low, care must be taken with regard to grounding and layout.

The printed circuit board that houses the AD7794 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. A minimum etch technique is generally best for ground planes because it gives the best shielding.

It is recommended that the AD7794’s GND pin be tied to the AGND plane of the system. In any layout, it is important that the user keep in mind the flow of currents in the system, ensuring that the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND sections of the layout.

The AD7794’s ground plane should be allowed to run under the AD7794 to prevent noise coupling. The power supply lines to the AD7794 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side.

Good decoupling is important when using high resolution ADCs. AV parallel with 0.1 µF capacitors to GND. DV

should be decoupled with 10 µF tantalum in

should be

decoupled with 10 µF tantalum in parallel with 0.1 µF capacitors to the system’s DGND plane with the system’s AGND to DGND connection being close to the AD7794. To achieve the best from these decoupling components, they should be placed as close as possible to the device, ideally right up against the device. All logic chips should be decoupled with 0.1 µF ceramic capacitors to DGND.

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AD7794

APPLICATIONS

The AD7794 provides a low-cost, high resolution analog-todigital function. Because the analog-to-digital function is provided by a ∑-∆ architecture, it makes the part more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process control applications.

FLOWMETER

Figure 24 shows the AD7794 being used in a flowmeter application that consists of two pressure transducers, the rate of flow being equal to the pressure difference. The pressure transducers shown are the BP01 from Sensym. The pressure transducers are arranged in a bridge network and give a differential output voltage between its OUT+ and OUT– terminals. With rated full-scale pressure (in this case 300 mmHg) on the transducer, the differential output voltage is 3 mV/V of the input voltage (i.e. the voltage between its IN(+) and IN(–) terminals).

Assuming a 5 V excitation voltage, the full-scale output range from the transducer is 15 mV. The excitation voltage for the bridge can be used to directly provide the reference for the ADC as the reference input range includes the supply voltage.

A second advantage of using the AD7794 in transducer-based applications is that the low-side power switch can be fully utilized in low power applications. The low-side power switch is connected in series with the cold side of the bridges. In normal operation, the switch is closed and measurements can be taken. In applications where power is of concern, the AD7794 can be placed in standby mode, thus significantly reducing the power consumed in the application. In addition, the low-side power switch can be opened while in standby mode, thus avoiding unnecessary power consumption by the front-end transducers. When the part is taken out of standby mode and the low-side power switch is closed, the user should ensure that the frontend circuitry is fully settled before attempting a read from the AD7794.

In the diagram, temperature compensation is performed using a thermistor. The on-chip excitation current supplies the thermistor. In addition, the reference voltage for the temperature measurement is derived from a precision resistor in series with the thermistor. This allows a ratiometric measurement so that variation of the excitation current has no affect on the measurement (it is the ratio of the precision reference resistance to the thermistor resistance which is measured).

OUT– OUT+

IN+

OUT– OUT+

IN–

IN+

IN–

REFIN1(+)

AIN1(+) AIN1(–)

AIN2(+) AIN2(–) AIN3(+)

AIN3(–)

REFIN2(+) REFIN2(–)

IOUT1

REFIN1(–) PSW

GND AV

MUX

GND

BUF

AD7794

SERIAL

INTERFACE

CLK

Σ-∆

ADC

INTERNAL

CLOCK

AND

LOGIC

CONTROL

IN-AMP

DOUT/RDY DIN SCLK CS

04854-012

Figure 24. Typical Application (Flowmeter)

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AD7794

OUTLINE DIMENSIONS

7.90

7.80

7.70

PIN 1

0.15

0.05

0.10 COPLANARITY

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AD

121

1.20

MAX

SEATING PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09

8° 0°

0.75

0.60

0.45

Figure 25. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

ORDERING GUIDE

Models Temperature Range Package Description Package Option

AD7794BRU –40°C to +105°C 24-Lead TSSOP RU-24 AD7794BRU-REEL –40°C to +105°C 24-Lead TSSOP RU-24

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AD7794

NOTES

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AD7794

NOTES

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AD7794

NOTES

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Datasheet AD7794 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual