Datasheet AD7762 Datasheet (ANALOG DEVICES)

625 kSPS, 24-Bit, 109 dB Σ−Δ ADC

FEATURES

120 dB dynamic range at 78 kHz output data rate
109 dB dynamic range at 625 kHz output data rate
112 dB SNR at 78 kHz output data rate
106 dB SNR at 625 kHz output data rate
625 kHz maximum fully filtered output word rate
Programmable over-sampling rate (32× to 256×)
Fully differential modulator input
On-chip differential amplifier for signal buffering
Low-pass finite impulse response (FIR) filter with default or

user-programmable coefficients
Overrange alert bit
Digital offset and gain correction registers
Filter bypass modes
Low power and power-down modes
Synchronization of multiple devices via

APPLICATIONS

Data acquisition systems
Vibration analysis
Instrumentation

GENERAL DESCRIPTION

SYNC

pin

V

REF+

MCLK

SYNC

RESET

With On-Chip Buffer

FUNCTIONAL BLOCK DIAGRAM

V

V

IN+

IN–

MULTIBIT

Σ-Δ

MODULATOR

RECONSTRUCTION

PROGRAMMABLE

DECIMATION

FIR FILTER

ENGINE

BUF

AD7762

CONTROL LOGIC

OFFSET AND GAIN

REGISTERS

DIFF

I/O

DB0 TO DB15CS DRDYRD/WR

Figure 1.

AD7762

AV

DD1

AV

DD2

AV

DD3

AV

DD4

DECAPA/B
R

BIAS

AGND
V

DRIVE

DV

DD

DGND

05477-001

The AD7762 is a high performance, 24-bit Σ- analog-to­digital converter (ADC). It combines wide input bandwidth
and high speed with the benefits of Σ- conversion with a
performance of 106 dB SNR at 625 kSPS, making it ideal for
high speed data acquisition. Wide dynamic range combined
with significantly reduced antialiasing requirements simplify
the design process. An integrated buffer to drive the reference,
a differential amplifier for signal buffering and level shifting, an
overrange flag, internal gain and offset registers, and a low-pass
digital FIR filter make the AD7762 a compact, highly integrated
data acquisition device requiring minimal peripheral com­ponent selection. In addition, the device offers programmable
decimation rates, and the digital FIR filter can be adjusted if
the default characteristics are not appropriate to the application.
The AD7762 is ideal for applications demanding high SNR
without a complex front end signal processing design.

The differential input is sampled at up to 40 MSPS by an analog
modulator. The modulator output is processed by a series of low­pass filters, the final filter having default or user-programmable

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

coefficients. The sample rate, filter corner frequencies, and output
word rate are set by a combination of the external clock frequency
and the configuration registers of the AD7762.

The reference voltage supplied to the AD7762 determines the
analog input range. With a 4 V reference, the analog input range
is ±3.2 V differential biased around a common mode of 2 V.
This common-mode biasing can be achieved using the on-chip
differential amplifier, further reducing the external signal
conditioning requirements.

The AD7762 is available in an exposed paddle, 64-lead TQFP
and is specified over the industrial temperature range from

−40°C to +85°C.

Table 1. Related Devices

Part No. Description

AD7760 24-bit, 2.5 MSPS, 100 dB Σ-∆, parallel interface
AD7763 24-bit, 625 kSPS, 109 dB Σ-∆, serial interface

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD7762

TABLE OF CONTENTS

General Description......................................................................... 1

Bias Resistor Selection............................................................... 17

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Timing Diagrams.......................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Terminology ......................................................................................9

Typical Performance Characteristics........................................... 10

Theory of Operation ......................................................................13

AD7762 Interface............................................................................ 14

Reading Data............................................................................... 14

Sharing the Parallel Bus............................................................. 14

Writing to the AD7762.............................................................. 14

Reading Status and Other Registers......................................... 14

Clocking the AD7762 ................................................................ 15

Decoupling and Layout Recommendations................................ 18

Supply Decoupling..................................................................... 19

Additional Decoupling.............................................................. 19

Reference Voltage Filtering .......................................................19

Differential Amplifier Components ........................................19

Layout Considerations............................................................... 19

Programmable FIR Filter............................................................... 20

Downloading a User-Defined Filter ............................................ 21

Example Filter Download ......................................................... 21

AD7762 Registers........................................................................... 23

Control Register 1—Reg 0x0001.............................................. 23

Control Register 2—Address 0x0002 ...................................... 23

Status Register (Read Only)...................................................... 24

Offset Register—Address 0x0003............................................. 24

Gain Register—Address 0x0004............................................... 24

Example 1 ....................................................................................15

Example 2 ....................................................................................15

Driving the AD7762....................................................................... 16

Using the AD7762...................................................................... 17

REVISION HISTORY

8/05—Revision 0: Initial Version

Overrange Register—Address 0x0005..................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Rev. 0 | Page 2 of 28

AD7762

SPECIFICATIONS

AV

= DVDD = V

DD1

using on-chip amplifier with components as shown in

Table 2.

Parameter Test Conditions/Comments Specification Unit

DYNAMIC PERFORMANCE

Decimate by 256 MCLK = 40 MHz, ODR = 78 kHz, FIN = 1 kHz

Dynamic Range Modulator inputs shorted 119

Signal-to-Noise Ratio (SNR)
Input amplitude = −60 dBFS 59 dB typ
Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 126 dBc typ
Input amplitude = −60 dBFS 77 dBc typ

Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS −105 dB typ
Input amplitude = −6 dBFS −106 dB typ
Input amplitude = −60 dBFS −75 dB typ
Decimate by 64 MCLK = 40 MHz, ODR = 312.5 kHz, FIN = 1 kHz

Dynamic Range Modulator inputs shorted 112

Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 126 dBc typ

Decimate by 32 MCLK = 40 MHz, ODR = 625 kHz, FIN =100 kHz

Dynamic Range Modulator inputs shorted 108

Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 120 dBc typ
Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS −108 dB typ

Input amplitude = −6 dBFS −106 dB typ

DC ACCURACY

Resolution 24 Bits
Differential Nonlinearity Guaranteed monotonic to 24 bits
Integral Nonlinearity 0.00076 % typ
Zero Error 0.014 % typ

0.02 % max
Gain Error 0.015 % typ
Zero Error Drift 0.019 %/°C typ
Gain Error Drift 0.0002 %/°C typ

DIGITAL FILTER RESPONSE

Decimate by 32

Group Delay MCLK = 40 MHz 47 µs typ

Decimate by 64

Group Delay MCLK = 40 MHz 91.5 µs typ

Decimate by 256

Group Delay MCLK = 40 MHz 358 µs typ

ANALOG INPUT

Differential Input Voltage VIN(+) – VIN(−), V
V
Input Capacitance At internal buffer inputs 5 pF typ

At modulator inputs 55 pF typ

= 2.5 V, AV

DRIVE

DD2

= AV

DD3

= AV

= 5 V, V

DD4

= 4.096 V, MCLK amplitude = 5 V, TA = 25°C, normal mode,

REF

Table 8, unless otherwise noted.

1

dB min

2

Input amplitude = −0.5 dBFS 112 dB typ

120.5

dB typ

dB min

2

Input amplitude = −0.5 dBFS 109.5 dB typ

114

dB typ

dB min

2

Input amplitude = −0.5 dBFS 107 dB typ

= 2.5 V ±2 V p-p

REF

(+) – VIN(−), V

IN

= 4.096 V ±3.25 V p-p

REF

Rev. 0 | Page 3 of 28

109.5

dB typ

AD7762

Parameter Test Conditions/Comments Specification Unit

REFERENCE INPUT/OUTPUT

V

Input Voltage V

REF

V
V

Input DC Leakage Current ±6 µA max

REF

V

Input Capacitance 5 pF max

REF

POWER DISSIPATION

Total Power Dissipation Normal mode 958 mW max
Low power mode 661 mW max
Standby Mode Clock stopped 6.35 mW max

POWER REQUIREMENTS

AV

(Modulator Supply) ±5% +2.5 V

DD1

AV

(General Supply) ±5% +5 V

DD2

AV

(Diff Amp Supply) +3.15/+5.25 V min/max

DD3

AV

(Ref Buffer Supply) +3.15/+5.25 V min/max

DD4

DVDD ±5% +2.5 V
V

+1.65/+2.7 V min/max

DRIVE

Normal Mode

AI

(Modulator) 49/51 mA typ/max

DD1

AI

(General) 40/42 mA typ/max

DD2

AI

(Reference Buffer) AV

DD4

Low Power Mode

AI

(Modulator) 26/28 mA typ/max

DD1

AI

(General) 20/23 mA typ/max

DD2

AI

(Reference Buffer) AV

DD4

AI

(Diff Amp) AV

DD3

DIDD Both modes 63/70 mA typ/max

DIGITAL I/O

MCLK Input Amplitude

3

Input Capacitance 7.3 pF typ
Input Leakage Current ±5 A max
Three-State Leakage Current (D15:D0) ±5 A max
V

0.7 × V

INH

V

0.3 × V

INL

4

V

OH

4

V

OL

1

See the Terminology section.

2

SNR specifications in dBs are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

3

While the AD7762 can function with an MCLK amplitude of less than 5 V, this is the recommended amplitude to achieve the performance as stated.

4

Tested with a 400 µA load current.

= 3.3 V ± 5% +2.5 V max

DD3

= 5 V ± 5% +4.096 V max

DD3

= 5 V 34/36 mA typ/max

DD4

= 5 V 9/10 mA typ/max

DD4

= 5 V, both modes 41/44 mA typ/max

DD3

5 V typ

V min

DRIVE

V max

DRIVE

1.5 V min

0.1 V max

Rev. 0 | Page 4 of 28

AD7762

TIMING SPECIFICATIONS

AV

= DVDD = V

DD1

Table 3.

Parameter Limit at T

f

1 MHz min Applied master clock frequency

MCLK

40 MHz max
f

500 kHz min Internal modulator clock derived from MCLK

ICLK

20 MHz max

1, 2

t

1

t2 10 ns min
t3 3 ns min
t4 (0.5 × t

t5 t
t6 t
t7 3 ns min
t8 11 ns max Bus relinquish time
t9 4 × t
t10 4 × t
t11 5 ns min Data setup time
t12 0 ns min Data hold time

1

t

= 1/f

ICLK

.

ICLK

2

When ICLK = MCLK,

DRIVE

0.5 × t

= 2.5 V, AV

MIN

typ

ICLK

= AV

DD2

, T

Unit Description

MAX

DD3

= AV

= 5 V, TA = 25°C, normal mode, unless otherwise noted.

DD4

DRDY pulse width
DRDY falling edge to CS falling edge
RD/WR setup time to CS falling edge

) + 16 ns max Data access time

ICLK

min

ICLK

min

ICLK

CS low read pulse width
CS high pulse width between reads
RD/WR hold time to CS rising edge

min

ICLK

min

ICLK

DRDY

pulse width depends on the mark/space ratio of applied MCLK.

CS low write pulse width
CS high period between address and data

TIMING DIAGRAMS

DRDY

RD/WR

D[0:15]

CS

CS

RD/WR

D[0:15]

t

1

t

2

t

5

t

3

t

4

DATA MSW LSW + STATUS

Figure 2. Parallel Interface Timing Diagram

t

9

t

11

REGISTER ADDRESS REGISTER DATA

t

12

t

6

t

7

t

8

05477-002

t

10

05477-004

Figure 3. AD7762 Register Write

Rev. 0 | Page 5 of 28

AD7762

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameters Rating

AV

to GND −0.3 V to +3 V

DD1

AV

–AV

DD2

to GND −0.3 V to +6 V

DD4

DVDD to GND −0.3 V to +3 V
V

to GND −0.3 V to +3 V

DRIVE

V

, V

to GND −0.3 V to +6 V

IN+

IN–

Digital input voltage to GND1 −0.3 V to DV

+ 0.3 V

DD

−0.3 V to +6 V MCLK to MCLKGND

V

to GND2 −0.3 V to AV

REF

DD4

+ 0.3 V
AGND to DGND −0.3 V to +0.3 V
Input Current to Any Pin

Except Supplies

3

Operating Temperature Range

±10 mA

−40°C to +85°C Commercial

−65°C to +150°C Storage Temperature Range
150°C Junction Temperature

TQFP Exposed Paddle Package

θJA Thermal Impedance 92.7°C/W
θJC Thermal Impedance 5.1°C/W

Lead Temperature, Soldering

215°C Vapor Phase (60 sec)
220°C Infrared (15 sec)

ESD 600 V

1

Absolute maximum voltage on digital inputs is 3.0 V or DVDD + 0.3 V,

whichever is lower.

2

Absolute maximum voltage on V

whichever is lower.

3

Transient currents of up to 200 mA do not cause SCR latch-up.

input is 6.0 V or AV

REF

+ 0.3 V,

DD4

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 28

AD7762

E

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRIV

DGND63V

DGND61DB060DB159DB258DB357DB456DB555DB654DB753DGND52DB851DB950DB1049DB11

64

62

31

AGND332AGND3

DECAPB

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

DB12
DB13
DB14
DB15
V

DRIVE

DGND
DGND
DV

DD

CS
RD/WR
DRDY
RESET
SYNC
DGND
AGND1
AV

DD1

05477-005

DGND

MCLKGND

MCLK

AV

DD2

AGND2

AV

DD1

AGND1
DECAPA
REFGND

V

REF+

AGND4

AV

DD4

AGND2

AV

DD2

AV

DD2

AGND2

1

PIN 1

2

3

4
5
6
7

8
9
10
11
12
13
14
15
16

17

18

19

20

A+

BIAS

IN

R

V

AGND2

21

A–

IN

V

AD7762

TOP VIEW

(Not to Scale)

22

23

A–

A+

OUT

OUT

V

V

24

DD3

AV

AGND3

25

Figure 4. 64-Lead TQFP Pin Configuration

26

27

28

DD2

AV

AGND229AGND3

30

–

+

IN

IN

V

V

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

6, 33 AV

DD1

2.5 V Power Supply for Modulator. These pins should be decoupled to AGND1 with 100 nF and 10 µF
capacitors on each pin.

4, 14, 15, 27 AV

DD2

5 V Power Supply. These pins should be decoupled to AGND2 with 100 nF capacitors on each of Pin 4,
Pin 14, and Pin 15. Pin 27 should be connected to Pin 14 via a 15 nH inductor.

24 AV

DD3

3.3 V to 5 V Power Supply for Differential Amplifier. These pins should be decoupled to AGND3 with a
100 nF capacitor.

12 AV

DD4

3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to AGND4 with a

10 nF capacitor in series with a 10 Ω resistor.
7, 34 AGND1 Power Supply Ground for Analog Circuitry Powered by AV
5, 13, 16, 18, 28 AGND2 Power Supply Ground for Analog Circuitry Powered by AV
23, 29, 31, 32 AGND3 Power Supply Ground for Analog Circuitry Powered by AV
11 AGND4 Power Supply Ground for Analog Circuitry Powered by AV

DD1

DD2

DD3

DD4

.
.
.

.
9 REFGND Reference Ground. Ground connection for the reference voltage.
41 DVDD

2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to DGND with a
100 nF capacitor.

44, 63 V

DRIVE

Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines the operating
voltage of the logic interface. Both these pins must be connected together and tied to the same supply.
Each pin should also be decoupled to DGND with a100 nF capacitor.

1, 35, 42, 43,

DGND Ground Reference for Digital Circuitry.

53, 62, 64
19 VINA+ Positive Input to Differential Amplifier.
20 VINA− Negative Input to Differential Amplifier.
21 V
22 V

A− Negative Output from Differential Amplifier.

OUT

A+ Positive Output from Differential Amplifier.

OUT

25 VIN+ Positive Input to the Modulator.
26 VIN− Negative Input to the Modulator.
10 V

REF+

Reference Input. The input range of this pin is determined by the reference buffer supply voltage

). See the Reference Voltage Filtering section for more details.

(AV

DD4

8 DECAPA Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND1.

Rev. 0 | Page 7 of 28

AD7762

Pin No. Mnemonic Description

30 DECAPB Decoupling Pin. A 33 pF capacitor must be inserted between this pin and AGND3.
17 R

45 to 52,
54 to 61

37

3 MCLK

2 MCLKGND Master Clock Ground Sensing Pin.
36

39

38

40

BIAS

DB15 to DB8
DB7 to DB0

Bias Current Setting Pin. A resistor must be inserted between this pin and AGND1. For more details, see

Bias Resistor Selection section.

the
16-Bit Bidirectional Data Bus. These are three-state pins that are controlled by the CS pin and the RD/WR

pin. The operating voltage for these pins is determined by the V

voltage. See the AD7762 Interface

DRIVE

section for more details.

RESET A falling edge on this pin resets all internal digital circuitry and powers down the part. Holding this pin

low keeps the AD7762 in a reset state.
Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends

on the frequency of this clock. See the section

Clocking the AD7762 for more details.

SYNC Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to

synchronize multiple devices in a system.

RD/WR Read/Write Input. This pin, in conjunction with the chip select pin, is used to read and write data to and

from the AD7762. If this pin is low when CS is low, a read takes place. If this pin is high and CS is low, a

DRDY

write occurs. See the
Data Ready Output. Each time that new conversion data is available, an active low pulse, ½ ICLK period

AD7762 Interface section for more details.

wide, is produced on this pin. See the AD7762 Interface section for more details.

CS Chip Select Input. Used in conjunction with the RD/WR pin to read and write data to and from the

AD7762. See the AD7762 Interface section for more details.

Rev. 0 | Page 8 of 28

AD7762

TERMINOLOGY

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental. For
the AD7762, it is defined as

22222

VVVVV

++++

54

THD

()

log20dB

=

32

V

1

6

where:

V

is the rms amplitude of the fundamental.

1

V2, V3, V4, V

,.and V6 are the rms amplitudes of the second to

5

the sixth harmonics.

Nonharmonic Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component, excluding harmonics.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured with the inputs shorted together. The
value for dynamic range is expressed in decibels.

Integral Nonlinearity (INL)

The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.

Differential Nonlinearity (DNL)

The difference between the measured and the ideal 1-LSB
change between any two adjacent codes in the ADC.

Zero Error

The zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.

Zero Error Drift

The change in the actual zero error value due to a temperature
change of 1°C. It is expressed as a percentage of the zero error at
room temperature.

Gain Error

The first transition (from 100…000 to 100…001) should occur
for an analog voltage 1/2 LSB above the nominal negative full
scale. The last transition (from 011…110 to 011…111) should
occur for an analog voltage 1 1/2 LSB below the nominal full
scale. The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of the
first transition, from the difference between the ideal levels.

Gain Error Drift

The change in the actual gain error value due to a temperature
change of 1°C. It is expressed as a percentage of the gain error at
room temperature.

Rev. 0 | Page 9 of 28

AD7762

TYPICAL PERFORMANCE CHARACTERISTICS

AV

= DVDD = V

DD1

are generated from 65536 samples using a 7-term Blackman-Harris window.

0

= 2.5 V, AV

DRIVE

DD2

= AV

DD3

= AV

= 5 V, V

DD4

= 4.096 V, TA = 25°C, normal mode, unless otherwise noted. All FFTs

REF

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

0 4000 8000 12000 16000 20000

FREQUENCY (Hz)

05477-006

24000

Figure 5. Normal Mode FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

0 4000 8000 12000 16000 20000

FREQUENCY (Hz)

24000

05477-007

Figure 6. Normal Mode FFT, 1 kHz, −6 dB Input Tone, 256× Decimation

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

0 4000 8000 12000 16000 20000

FREQUENCY (Hz)

05477-009

24000

Figure 8. Low Power FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

0 4000 8000 12000 16000 20000

FREQUENCY (Hz)

05477-010

24000

Figure 9. Low Power FFT, 1 kHz, −6 dB Input Tone, 256× Decimation

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

0 4000 8000 12000 16000 20000

FREQUENCY (Hz)

24000

05477-008

Figure 7. Normal Mode FFT, 1 kHz, −60 dB Input Tone, 256× Decimation

Rev. 0 | Page 10 of 28

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

0 4000 8000 12000 16000 20000

FREQUENCY (Hz)

24000

Figure 10. Low Power FFT, 1 kHz, −60 dB Input Tone, 256× Decimation

05477-011

AD7762

0

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

600000 120000 180000 240000 300000

FREQUENCY (Hz)

05477-060

Figure 11. Normal Mode FFT, 100 kHz, −0.5 dB Input Tone, 32× Decimation

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

600000 120000 180000 240000 300000

FREQUENCY (Hz)

05477-063

Figure 14. Low Power FFT, 100 kHz, −0.5 dB Input Tone, 32× Decimation

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

600000 120000 180000 240000 300000

FREQUENCY (Hz)

05477-061

Figure 12. Normal Mode FFT, 100 kHz, −6 dB Input Tone, 32× Decimation

120

118

116

114

112

SNR (dBFS)

110

108

106

0 256

64 128 192

DECIMATION RATE (x)

–60dB

–6dB

–0.5dB

05477-062

Figure 13. Normal Mode SNR vs. Decimation Rate, 1 kHz Input Tone

–175

–200

600000 120000 180000 240000 300000

FREQUENCY (Hz)

Figure 15. Low Power FFT, 100 kHz, −6 dB Input Tone, 32× Decimation

116

–60dB

112

SNR (dBFS)

108

104

0 256

64 128 192

DECIMATION RATE (x)

–6dB

–0.5dB

Figure 16. Low Power SNR vs. Decimation Rate, 1 kHz Input Tone

05477-064

05477-065

Rev. 0 | Page 11 of 28

AD7762

4500

4000

3500

3000

2500

2000

OCCURRENCE

1500

1000

500

0

8385222

Figure 17. Normal Mode, 24-Bit Histogram, 256× Decimation

8385238 8385254 8385270

24-BIT CODE

3000

2500

2000

1500

OCCURRENCE

1000

500

05477-055

0

8383530

83835246 8383562 8383578 8383594 8383610

24-BIT CODE

Figure 20. Low Power, 24-Bit Histogram, 256× Decimation

05477-058

0.0010

0.0005

INL (%)

–0.0005

–0.0010

+85°C

+25°C

0

–40°C

0 16777216

4194304 8388608 12582912

24-BIT CODE

Figure 18. 24-Bit INL, Normal Mode

0.6

0.4

0.2

0

DNL (LSB)

–0.2

0.0015

+85°C

0.0010

0.0005

INL (%)

–0.0005

05477-056

–0.0010

+25°C

0

–40°C

0 16777216

4194304 8388608 12582912

24-BIT CODE

Figure 21. 24-Bit INL, Low Power Mode

05477-059

–0.4

–0.6

0 16777216

4194304 8388608 12582912

24-BIT CODE

05477-057

Figure 19. 24-Bit DNL

Rev. 0 | Page 12 of 28

AD7762

THEORY OF OPERATION

The AD7762 employs a Σ- conversion technique to convert
the analog input into an equivalent digital word. The modulator
samples the input waveform and outputs an equivalent digital
word to the digital filter at a rate equal to ICLK.

rate to be chosen from 4× to 32×. The third filter has a fixed
decimation rate of 2×, is user programmable, and has a default
configuration. It is described in detail in the

section. This filter can be bypassed.

Filter

Programmable FIR

Due to the high oversampling rate, that spreads the
quantization noise from 0 to
the band of interest is reduced (

f

, the noise energy contained in

ICLK

Figure 22 a). To further reduce
the quantization noise, a high order modulator is employed to
shape the noise spectrum; so that most of the noise energy is
shifted out of the band of interest (

Figure 22 b).

The digital filtering that follows the modulator removes the
large out-of-band quantization noise (
reducing the data rate from

f

/8 or less at the output of the filter, depending on the

ICLK

f

ICLK

Figure 22 c) while also

at the input of the filter to

decimation rate used.

Digital filtering has certain advantages over analog filtering. It
does not introduce significant noise or distortion and can be
made perfectly linear phase.

The AD7762 employs three FIR filters in series. By using
different combinations of decimation ratios and filter selection
and bypassing, data can be obtained from the AD7762 at a large
range of data rates. The first filter receives data from the
modulator at ICLK MHz where it is decimated by four to
output data at ICLK/4 MHz. This partially filtered data can also
be output at this stage. The second filter allows the decimation

Table 6 lists some characteristics of the default filter. The group
delay of the filter is defined to be the delay to the center of the
impulse response and is equal to the computation + filter delays.
The delay until valid data is available (the DVALID status bit is
set) is equal to 2× the filter delay + the computation delay.

a.

QUANTIZATION NOISE

f

\2

BAND OF INTEREST

b.

NOISE SHAPING

BAND OF INTEREST

c.

DIGITAL FILTER CUTOFF FREQUENCY

BAND OF INTEREST

Figure 22. Σ-Δ ADC

ICLK

f

ICLK

f

ICLK

\2

\2

04975-037

Table 6. Configuration with Default Filter

ICLK
Frequency

Filter 1 Filter 2 Filter 3 Data State Filter Delay

Computation
Delay

Pass-Band
Bandwidth

Output Data
Rate (ODR)

20 MHz 4× 4× 2× Fully filtered 1.775 µs 44.4 µs 250 kHz 625 kHz
20 MHz 4× 8× Bypassed Partially filtered 2.6 µs 10.8 µs 140.625 kHz 625 kHz
20 MHz 4× 8× 2× Fully filtered 2.25 µs 87.6 µs 125 kHz 312.5 kHz
20 MHz 4× 16× Bypassed Partially filtered 4.175 µs 20.4 µs 70.3125 kHz 312.5 kHz
20 MHz 4× 16× 2× Fully filtered 3.1 µs 174 µs 62.5 kHz 156.25 kHz
20 MHz 4× 32× Bypassed Partially filtered 7.325 µs 39.6 µs 35.156 kHz 156.25 kHz
20 MHz 4× 32× 2× Fully filtered 4.65 µs 346.8 µs 31.25 kHz 78.125 kHz

12.288 MHz 4× 8× 2× Fully filtered 3.66 µs 142.6 µs 76.8 kHz 192 kHz

12.288 MHz 4× 16× 2× Fully filtered 5.05 µs 283.2 µs 38.4 kHz 96 kHz

12.288 MHz 4× 32× Bypassed Partially filtered 11.92 µs 64.45 µs 21.6 kHz 96 kHz

12.288 MHz 4× 32× 2× Fully filtered 7.57 µs 564.5 µs 19.2 kHz 48 kHz

Rev. 0 | Page 13 of 28

AD7762

AD7762 INTERFACE

READING DATA

The AD7762 uses a 16-bit bidirectional parallel interface. This
interface is controlled by the

When a new conversion result is available, an active low pulse is
output on the

AD7762, two 16-bit read operations are performed. The
pulse indicates that a new conversion result is available. Both

/WR and CS go low to perform the first read operation.

RD
Shortly after both these lines go low, the data bus becomes

active and the 16 most significant bits (MSBs) of the conversion
result are output. The

for a full ICLK period before the second read is performed. This
second read contains the 8 least significant bits (LSBs) of the
conversion result along with 6 status bits. These status bits are
shown in
Table 15.

Table 7. Status Bits During Data Read

D7 D0

DValid Ovr UFilt LPwr FiltOk DLOk 0 0

Shortly after RD/WR and CS return high, the data bus returns
to a high impedance state. Both read operations must be

completed before a new conversion result is available because
the new result overwrites the contents on the output register.
If a

is invalid.

Table 7. Descriptions of the other status bits are in

pulse occurs during a read operation, the data read

DRDY

pin. To read a conversion result from the

DRDY

RD

SHARING THE PARALLEL BUS

By its nature, the high accuracy of the AD7762 makes it
sensitive to external noise sources. These include digital activity
on the parallel bus. For this reason, it is recommended that the
AD7762 data lines are isolated from the system data bus by
means of a latch or buffer to ensure that there is no digital
activity on the D0 to D15 pins that is not controlled by the
AD7762. If multiple, synchronized AD7762 parts that share a
properly distributed common MCLK signal exist in a system,
these parts can share a common bus without being isolated
from each other. This bus can then be isolated from the system
bus by a single latch or buffer.

/WR and CS pins.

RD

DRDY

/WR and CS lines must return high

WRITING TO THE AD7762

While the AD7762 is configured to convert analog signals with
the default settings on reset, there are many features and
parameters on this part that the user can change by writing to
the device. Because some of the programmable registers are
16 bits wide, two write operations are required to program a
register. The first write contains the register address while the
second write contains the register data. An exception is when a
user filter is being downloaded to the AD7762. This is
described in detail in the
section. The
addresses and more details.

Figure 3 shows a write operation to the AD7762. The RD/WR
line is held high while the
of 4 ICLK periods. The register address is latched during this

period. The
4 ICLK periods before the register data is put onto the data bus.

If a read operation occurs between the writing of the register
address and the register data, the register address is cleared and
the next write must be the register address again. This also
provides a method to get back to a known situation if the user
forgets whether the next write is an address or data.

Generally, the AD7762 is written to and configured on power­up and very infrequently, if at all, after that. Following any write
operation, the full group delay of the filter must pass before
valid data is output from the AD7762.

AD7762 Registers section contains the register

line is brought high again for a minimum of

CS

Downloading a User-Defined Filter

line is brought low for a minimum

CS

READING STATUS AND OTHER REGISTERS

The AD7762 features a number of programmable registers. To
read back the contents of these registers or the status register, the
user must first write to the control register of the device, setting
a bit corresponding to the register to be read. The next read
operation outputs the contents of the selected register instead
of a conversion result. The
more information on the relevant bits in the control register.

AD7762 Registers section provides

Rev. 0 | Page 14 of 28

AD7762

CLOCKING THE AD7762 EXAMPLE 2

The AD7762 requires an external low jitter clock source. This
signal is applied to the MCLK pin, and the MCLKGND pin is
used to sense the ground from the clock source. An internal
clock signal (ICLK) is derived from the MCLK input signal.
The ICLK controls the internal operations of the AD7762. The
maximum ICLK frequency is 20 MHz, but due to an internal
clock divider, a range of MCLK frequencies can be used. There
are two ways to generate the ICLK:

ICLK = MCLK (

ICLK = MCLK/2 (

CDIV

CDIV

= 1)

= 0)

These options are selected from the control register (see the
AD7762 Registers section for more details). On power-up, the
default is ICLK = MCLK/2 to ensure that the part can handle
the maximum MCLK frequency of 40 MHz. For output data
rates equal to those used in audio systems, a 12.288 MHz ICLK
frequency can be used. As shown in

Table 6, output data rates
of 192 kHz, 96 kHz, and 48 kHz are achievable with this ICLK
frequency. As mentioned previously, this ICLK frequency can
be derived from different MCLK frequencies.

The MCLK jitter requirements depend on a number of factors
and are given by

f

OSR

IN

)dB(

SNR

20

102

××π×

=

t

)(

rmsj

where:

f

OSR = Over-sampling ratio =

f

= Maximum input frequency

IN

ICLK

ODR

SNR(dB) = Target SNR

EXAMPLE 1

This example can be taken from Table 6, where:

ODR = 625 kHz
f

= 20 MHz

ICLK

f

(max) = 250 kHz

IN

SNR = 108 dB

=

t

)(

rmsj

32

10102502

×××π×

This is the maximum allowable clock jitter for a full-scale,
250 kHz input tone with the given ICLK and output data rate.

ps6.3

=

63

Take a second example from Ta ble 6, where:

ODR = 48 kHz
f

= 12.288 MHz

ICLK

f

(max) = 19.2 kHz

IN

SNR = 120 dB

=

t

)(

rmsj

256

10102.192

×××π×

ps133

=

63

The input amplitude also has an effect on these jitter figures.
If, for example, the input level was 3 dB below full scale, the
allowable jitter would be increased by a factor of √2, increasing
the first example to 2.53 ps rms. This happens when the
maximum slew rate is decreased by a reduction in amplitude.
Figure 23 and Figure 24 illustrate this point, showing the
maximum slew rate of a sine wave of the same frequency but
with different amplitudes.

1

0.5

0

–0.5

–1.0

Figure 23. Maximum Slew Rate of Sine Wave with Amplitude of 2 V p-p

04975-038

1

0.5

0

–0.5

–1.0

Figure 24. Maximum Slew Rate of Same Frequency Sine Wave with

Amplitude of 1 V p-p

04975-039

Rev. 0 | Page 15 of 28

AD7762

+

V

–

+

V

–

V

DRIVING THE AD7762

The AD7762 has an on-chip differential amplifier that operates
with a supply voltage (AV
V reference, the supply voltage must be 5 V.

To achieve the specified performance in normal mode, the
differential amplifier should be configured as a first-order
antialias filter, as shown in
should be carried out in previous stages using low noise, high
performance op amps, such as the AD8021.

Suitable component values for the first-order filter are listed in
Table 8. The values in Table 8 yield a 10 dB attenuation at the
first alias point of 19 MHz.

) from 3.15 V to 5.25 V. For a 4.096

DD3

Figure 25. Any additional filtering

C

FB

R

FB

2.5

2.5V

2.5

2.5V

+3.685V

V

+

0V

A

B

0V

+2.048V

+0.410V

+3.685V

+2.048V

+0.410V

IN

V

–

IN

04975-041

Figure 26. Differential Amplifier Signal Conditioning

C

FB

R

IN

A

C

B

R

IN

A1

S

R

FB

C

FB

R

M

VIN–

R

M

V

+

IN

04975-040

Figure 25. Differential Amplifier Configuration

Table 8. Normal Mode Component Values

V

R

REF

R

IN

R

FB

C

M

C

S

FB

4.096 V 1 kΩ 655 Ω 18 Ω 5.6 pF 33 pF

Figure 26 shows the signal conditioning that occurs using the
circuit in

Figure 25 with a ±2.5 V input signal biased around
ground and having the component values and conditions in
Table 8. The differential amplifier always biases the output
signal to sit on the optimum common mode of V

/2, in this

REF

case 2.048 V. The signal is also scaled to give the maximum
allowable voltage swing with this reference value. This is
calculated as 80% of V

, that is, 0.8 × 4.096 V ≈ 3.275 V p-p

REF

on each input.

To obtain maximum performance from the AD7762, it is
advisable to drive the ADC with differential signals.

Figure 27
shows how a bipolar, single-ended signal biased around ground
can drive the AD7762 with the use of an external op amp, such
as the AD8021.

2R

V

IN

2R

AD8021

R

R

R

R

FB

IN

C

IN

A1

S

R

FB

C

FB

R

M

VIN–

R

M

VIN+

Figure 27. Single-Ended-to-Differential Conversion

+

IN

CPA

SS1

SH1

SS2

SH2

CPB1

CPB2

CS1

CS2

SS3

SS4

SH3

SH4

ANALOG

MODULATOR

05477-043

Figure 28. Equivalent Input Circuit

The AD7762 employs a double sampling front end, as shown in
Figure 28. For simplicity, only the equivalent input circuit for VIN+
is shown. The equivalent input circuitry for V

− is the same.

IN

04975-042

With a 4.096 V reference, a 5 V supply must be provided to the
reference buffer (AV
must be provided to AV

). With a 2.5 V reference, a 3.3 V supply

DD4

.

DD4

Rev. 0 | Page 16 of 28

AD7762

The sampling switches SS1 and SS3 are driven by ICLK, whereas
the sampling switches SS2 and SS4 are driven by

ICLK is high, the analog input voltage is connected to CS1. On
the falling edge of ICLK, the SS1 and SS3 switches open, and the
analog input is sampled on CS1. Similarly, when ICLK is low, the
analog input voltage is connected to CS2. On the rising edge of
ICLK, the SS2 and SS4 switches open, and the analog input is
sampled on CS2.

Capacitors CPA, CPB1, and CPB2 represent parasitic capacitances
that include the junction capacitances associated with the MOS
switches.

Table 9. Equivalent Component Values

Mode CS1 CS2 CPA CPB1/2

Normal 51 pF 51 pF 12 pF 20 pF
Low Power 13 pF 13 pF 12 pF 5 pF

ICLK

. When

USING THE AD7762

The following is the recommended sequence for powering up
and using the AD7762.

Data can then be read from the part using the default filter,
offset, gain, and overrange threshold values. The conversion
data read is not valid, however, until the group delay of the filter
has passed. When this has occurred, the DVALID bit read with
the data LSW is set, indicating that the data is indeed valid.

The user can then download a different filter, if required
(see

Downloading a User-Defined Filter). Values for gain, offset,
and overrange threshold registers can be written or read at this
stage.

BIAS RESISTOR SELECTION

The AD7762 requires a resistor to be connected between the
R

pin and AGND1. The value for this resistor is dependant

BIAS

on the reference voltage being applied to the device. The resistor
value should be selected to give a current of 25 µA through the
resistor to ground. For a 2.5 V reference voltage, the correct
resistor value is 100 kΩ and for a 4.096 V reference, the correct
resistor value is 160 kΩ.

1.

Apply power.

2.

Start the clock oscillator, applying MCLK.

3.

Ta ke
Wait a minimum of 2 MCLK cycles after

4.
released.

5. Write to Control Register 2 to power up the ADC and the
differential amplifier as required. The correct clock divider
(

CDIV

Write to Control Register 1 to set the output data rate.

6.

7.

Wait a minimum of 5 MCLK cycles after

released.

8.

Ta ke

required, to synchronize multiple parts.

low for a minimum of 1 MCLK cycle.

RESET

) ratio should be programmed now.

low for a minimum of 4 MCLK cycles, if

SYNC

RESET

has been

CS

has been

Rev. 0 | Page 17 of 28

AD7762

5

DECOUPLING AND LAYOUT RECOMMENDATIONS

Due to the high performance nature of the AD7762, correct decoupling and layout techniques are required to obtain the performance as
stated within this datasheet.

Figure 29 shows a simplified connection diagram for the AD7762.

PIN 14PIN 1

PIN 4

PIN 12

PIN 6

PIN 33PIN 24PIN 27PIN 44PIN 63PIN 41

AV

PIN 4

(RHS)

DD2

C48

100nF

14154

1263324274463

100nF

INA+

INA–
OUTA–
OUTA+

C64

C7

33pF

VIN+

VIN–

19
20
21
22

8

30

25
26

VINA+

A–

V

IN

V

A–

OUT

A+

V

OUT

DECAPA
DECAPB

+

V

IN

–

V

IN

DD2AVDD2

DD2

AV

AV

DD4AVDD1AVDD1AVDD3AVDD2

AV

DRIVEVDRIVE

V

AD7762BSV

10

+

VREF

R19

160kΩ

L1

PIN 15

(VBIAS)

C50

100nF

L3

PIN 14

(LHS) PIN 27

C62

100nF

L2

L9

9

17

1
35
42
43
53
62
64

AV

PIN 12

(VBUF)

V

REF

REFGND

R

BIAS

DGND
DGND
DGND
DGND
DGND
DGND
DGND

DD4

R38
10Ω

C59

10nF

AGND1

AGND1

AGND2

AGND2

AGND2

AGND2

AGND2

AGND3

AGND3

AGND3

7

5

34

AV

L4

(VMOD1)

DD1

PIN 5

C52

100nF

L5

131618

PIN 33

(VMOD2)

28

100nF

L11

C53

232931

AGND3

32

AV

DD3

PIN 24

(VDIF1)

41

DV

AGND4

11

C54

100nF

DD

L6

U2

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8

DB9
DB10
DB11
DB12
DB13
DB14
DB15

RD/WR

RESET

SYNC
DRDY

MCLK

MCLKGND

V

DRIVE

PIN 44

(VDRV1)

DB (0:15)

61

DB0

60

DB1

59

DB2

58

DB3

57

DB4

56

DB5

55

DB6

54

DB7

52

DB8

51

DB9

50

DB10

49

DB11

48

DB12

47

DB13

46

DB14

45

DB15

40

CS

39

37
36
38

3
2

L7

C56

100nF

PIN 63

(VDRV2)

CS
RD/WR

RESET
SYNC
DRDY

MCLK

L12

C57

100nF

DV

PIN 41

(DVDD)

DD

C58

100nF

L8

05477-046

Figure 29. Simplified Connection Diagram

Rev. 0 | Page 18 of 28

AD7762

SUPPLY DECOUPLING DIFFERENTIAL AMPLIFIER COMPONENTS

Every supply pin must be connected to the appropriate supply
via a ferrite bead and decoupled to the correct ground pin with
a 100 nF, 0603 case size, X7R dielectric capacitor. There are two
exceptions to this:

• Pin 12 (AV

) must have a 10  resistor inserted between

DD4

the pin and a 10 nF decoupling capacitor.

• Pin 27 (AV

) does not require a separate decoupling

DD2

capacitor or a direct connection to the supply, but instead
is connected to Pin 14 via a 15 nH inductor.

ADDITIONAL DECOUPLING

There are two other decoupling pins on the AD7762—Pin 8
(DECAPA) and Pin 30 (DECAPB). Pin 8 should be decoupled
with a 100 nF capacitor, and Pin 30 requires a 33 pF capacitor.

The correct components for use around the on-chip differential
amplifier are detailed in

Table 8. Matching the components on
both sides of the differential amplifier is important to minimize
distortion of the signal applied to the amplifier. A tolerance of

0.1% or better is required for these components. Symmetrical
routing of the tracks on both sides of the differential amplifier
also assists in achieving stated performance.

LAYOUT CONSIDERATIONS

While using the correct components is essential to achieve
optimum performance, the correct layout is just as important.
The Design Tools section of the AD7762 product page on
the Analog Devices website contains the gerber files for the
AD7762 evaluation board. These files should be used as a
reference when designing any system using the AD7762.

REFERENCE VOLTAGE FILTERING

A low noise reference source, such as the ADR431 (2.5 V) or
ADR434 (4.096 V), is suitable for use with the AD7762. The
reference voltage supplied to the AD7762 should be decoupled
and filtered, as shown in

The recommended scheme for the reference voltage supply
is a 100  series resistor connected to a 100 F tantalum
capacitor, followed by series resistor of 10 , and finally a
10 nF decoupling capacitor very close to the V

+12V PIN10VOUT

+

C15

10μFC9100nF

Figure 30.

U3

ADR434

2

+VIN

GND

4

Figure 30. Reference Connection

6

100nF

C10

R30

100Ω

C11

100μF

pin.

REF+

R17
10Ω

+

C46

10nF

The location and orientation of some of the components
mentioned in previous sections is critical, and particular
attention must be paid to the components which are located
close to the AD7762. Locating these components further away
from the devices can have a direct impact on the maximum
performance achievable.

The use of ground planes also should be carefully considered.
To ensure that the return currents through the decoupling
capacitors are flowing to the correct ground pin, the ground
side of the capacitors should be as close to the ground pin
associated with that supply. A ground plane should not be relied
on as the sole return path for decoupling capacitors because the
return current path using ground planes is not easily
predictable.

04975-047

Rev. 0 | Page 19 of 28

AD7762

PROGRAMMABLE FIR FILTER

As previously mentioned, the third FIR filter on the AD7762 is
user programmable. The default coefficients that are loaded on
reset are given in
shown in
directly with the output data rate.

Table 10. Default Filter Coefficients

Dec.

No.

Value

0 53656736 332BCA0 24 700847 AB1AF
1 25142688 17FA5A0 25 −70922 401150A
2 −4497814 444A196 26 −583959 408E917
3 −11935847 4B62067 27 −175934 402AF3E
4 −1313841 4140C31 28 388667 5EE3B
5 6976334 6A734E 29 294000 47C70
6 3268059 31DDDB 30 −183250 402CBD2
7 −3794610 439E6B2 31 −302597 4049E05
8 −3747402 4392E4A 32 16034 3EA2
9 1509849 1709D9 33 238315 3A2EB
10 3428088 344EF8 34 88266 158CA
11 80255 1397F 35 −143205 4022F65
12 −2672124 428C5FC 36 −128919 401F797
13 −1056628 4101F74 37 51794 CA52
14 1741563 1A92FB 38 121875 1DC13
15 1502200 16EBF8 39 16426 402A
16 −835960 40CC178 40 −90524 401619C
17 −1528400 4175250 41 −63899 400F99B
18 93626 16DBA 42 45234 B0B2
19 1269502 135EFE 43 114720 1C020
20 411245 6466D 44 102357 18FD5
21 −864038 40D2F26 45 52669 CDBD
22 −664622 40A242E 46 15559 3CC7
23 434489 6A139 47 1963 7AB

The default filter should be sufficient for almost all applications.
It is a standard brick wall filter with a symmetrical impulse
response. The default filter has a length of 96 taps in non­aliasing with 120 dB of attenuation at Nyquist. This filter not
only performs signal antialiasing, but also suppresses out-of­band quantization noise produced by the analog-to-digital
conversion process. Any significant relaxation in the stop-band
attenuation or transition bandwidth relative to the default filter
can result in a failure to meet the SNR specifications.

Table 10 and the frequency responses are

Figure 31. The frequencies quoted in Figure 31 scale

Hex
Value

No.

Dec.
Value

Hex
Value

To create a filter, note the following:

• The filter must be even, symmetrical FIR.

• The coefficients are in sign-and-magnitude format with

26 magnitude bits and sign coded as positive = 0.

• The filter length must be between 12 taps and 96 taps in

steps of 12.

• Because the filter is symmetrical, the number of

coefficients that must be downloaded is half the filter
length. The default filter coefficients exemplify this with
only 48 coefficients listed for a 96-tap filter.

• Coefficients are written from the center of impulse

response (adjacent to the point of symmetry) outwards.

• The coefficients are scaled so that the in-band gain of the

filter is equal to 134217726 with the coefficients rounded
to the nearest integer. For a low-pass filter, this is the
equivalent of having the coefficients sum arithmetically
(including sign) to a 67108863 (0x3FF FFFF) positive
value over the half-impulse response coefficient set
(maximum 48 coefficients). Any deviation from this
introduces a gain error.

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

0 100 400 500300200 600

Figure 31. Default Filter Frequency Response (625 kHz ODR)

PASS-BAND RIPPLE = 0.05dB

–0.1dB FREQUENCY = 251kHz

–3dB FREQUENCY = 256kHz

STOP BAND = 312.5kHz

FREQUENCY (kHz)

05477-044

The procedure for downloading a user-defined filter is detailed

Downloading a User-Defined Filter section.

in the

Rev. 0 | Page 20 of 28

AD7762

DOWNLOADING A USER-DEFINED FILTER

As previously mentioned, the filter coefficients are 27 bits in
length; 1 sign and 26 magnitude bits. Because the AD7762
has a 16-bit parallel bus, the coefficients are padded with
5 MSB 0s to generate a 32-bit word and split into two 16-bit
words for downloading. The first 16-bit word for each coefficient
becomes (00000, Sign bit, Magnitude [25:16]), while the second
word becomes (Magnitude [15:0]). To ensure that a filter is
down-loaded correctly, a checksum must also be generated and
then downloaded following the final coefficient. The checksum
is a 16-bit word generated by splitting each 32-bit word into
4 bytes and summing all bytes from all coefficients up to a
maximum of 192 bytes (48 coefficients × 4 bytes). The same
checksum is generated internally in the AD7762 and compared
with the checksum downloaded. The DL_OK bit in the status
register is set if these two checksums agree.

To download a user filter:

1.

Write to Control Register 1, setting the DL_Filt bit and

also the correct filter length bits corresponding to the
length of the filter to be downloaded (see

Table 11 ).

EXAMPLE FILTER DOWNLOAD

The following is an example of downloading a short user­defined filter with 24 taps. The frequency response is shown

Figure 32.

in

10

0

–10

–20

–30

–40

AMPLITUDE (dB)

–50

–60

–70

–80

100 200 300 400 500

0 600

Figure 32. 24-Tap FIR Frequency Response

FREQUENCY (kHz)

04975-045

2.

Write the first half of the current coefficient data

(00000, Sign bit, Magnitude [25:16]). The first coefficient
to be written must be the one adjacent to the point of filter
symmetry.

3.

Write the second half of the current coefficient data

(Magnitude [15:0]).

4.

Repeat Step 2 and Step 3 for each coefficient.

5.

Write the 16-bit checksum.

6.

Use these methods to verify that the filter coefficients are

downloaded correctly:

Read the status register, checking the DL_OK bit.

a.

b.

Read data and observe the status of the DL_OK bit.

Note that because the user coefficients are stored in RAM, they
are cleared after a

operation or a loss of power.

RESET

Table 11. Filter Length Values

FLEN[3:0] Number of Coefficients Filter Length

0000 Default Default
0001 6 12
0011 12 24
0101 18 36
0111 24 48
1001 30 60
1011 36 72
1101 42 84
1111 48 96

The coefficients for the filter are listed in Table 12 and are
shown from the center of symmetry outwards. The raw
coefficients were generated using a commercial filter
design tool and scaled appropriately so their sum equals
67108863 (0x3FF FFFF).

Table 12. 24-Tap FIR Coefficients

Coefficient Raw Scaled

1 0.365481974 53188232
2 0.201339905 29300796
3 0.009636604 1402406
4 −0.075708848 −11017834
5 −0.042856209 −6236822
6 0.019944246 2902466
7 0.036437914 5302774
8 0.007592007 1104856
9 −0.021556583 −3137108
10 −0.024888355 −3621978
11 −0.012379538 −1801582
12 −0.001905756 −277343

Rev. 0 | Page 21 of 28

AD7762

Table 13 shows the hex values (in sign and magnitude format)
that are downloaded to the AD7762 to realize this filter. The
table is also split into the bytes that are all summed to produce
the checksum. The checksum generated from these coefficients
is 0x0E6B.

Table 13. Filter Hex Values

Word 1 Word 2
Coefficient Byte 1 Byte 2 Byte 3 Byte 4

1 03 2B 96 88
2 01 BF 18 3C
3 00 15 66 26
4 04 A8 1E 6A
5 04 5F 2A 96
6 00 2C 49 C2
7 00 50 E9 F6
8 00 10 DB D8
9 04 2F DE 54
10 04 37 44 5A
11 04 1B 7D 6E
12 04 04 3B 5F

Table 14 lists the 16-bit words the user would write to the
AD7762 to set up the ADC and download this filter, assuming
an output data rate of 625 kHz has already been selected.

Table 14.

Word Description

0x0001 Address of Control Register 1.
0x8079

0x032B First coefficient, Word 1.
0x9688 First coefficient, Word 2.
0x01BF Second coefficient, Word 1.
0x183C Second coefficient, Word 2.

…

0x0404 Twelfth (final) coefficient, Word 1.
0x3B5F Final coefficient, Word 2.
0x0E6B

0x0001 Address of control register.
0x0879

Control register data. DL filter, set filter length = 24,
set output data rate = 625 kHz.

Other coefficients.

Checksum. Wait (0.5 × t
Coefficients) for AD7762 to fill remaining unused
coefficients with 0s.

Control register data. Set read status and maintain
filter length and decimation settings. Read contents
of status register. Check Bit 7 (DL_OK) to determine
that the filter was downloaded correctly.

× Number of Unused

ICLK

Rev. 0 | Page 22 of 28

AD7762

AD7762 REGISTERS

The AD7762 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter
configuration, the clock divider, and so on. There are also digital gain, offset, and overrange threshold registers. Writing to these registers
involves writing the register address first, then a 16-bit data-word. Register addresses, details of individual bits, and default values are
given here.

CONTROL REGISTER 1—REG 0X0001

Default Value 0x001A

MSB

DL_ Filt RD Ovr RD Gain RD Off RD Stat 0 SYNC FLEN3 FLEN2 FLEN1 FLEN0

Table 15.

Bit Mnemonic Description

15 DL_Filt

14 RD Ovr

13 RD Gain
12 RD Off
11 RD Stat
10 0 0 must be written to this bit.
9 SYNC

8-5 FLEN3:0 Filter Length Bits. These bits must be set when the DL Filt bit is set and before a user-defined filter is downloaded.
4

3 1 1 must be written to this bit.
2-0 DEC2:0

1

Bit 15 to Bit 9 are all self clearing bits.

2

Only one of the bits from Bit 14 to Bit 11 can be set in any write operation because it determines the contents of the next read operation.

BYP F3

1

Download Filter. Before downloading a user-defined filter, this bit must be set. The Filter Length bits must also be set at

1 DEC2 DEC1 DEC0

this time. The write operations that follow are interpreted as the user coefficients for the FIR filter until all the
coefficients and the checksum have been written.

1, 2

Read Overrange. If this bit has been set, the next read operation outputs the contents of the Overrange Threshold
Register instead of a conversion result.

1, 2

1, 2

1

Read Gain. If this bit has been set, the next read operation outputs the contents of the digital gain register.
Read Offset. If this bit has been set, the next read operation outputs the contents of the digital offset register.

1, 2

Read Status. If this bit has been set, the next read operation outputs the contents of the status register.

Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously on multiple
devices synchronizes all filters.

BYP F3

Bypass Filter 3. If this bit is 0, Filter 3 (programmable FIR) is bypassed.

Decimation Rate. These bits set the decimation rate of Filter 2. All 0s implies that the filter is bypassed. A value of 1
corresponds to 2× decimation, a value of 2 corresponds to 4× decimation, and so on up to the maximum value of 5,
corresponding to 32× decimation.

LSB

CONTROL REGISTER 2—ADDRESS 0X0002

Default Value 0x009B

MSB LSB

0 0 0 0 0 0 0 0 0 0

CDIV

0 PD LPWR 1 D1PD

Table 16.

Bit Mnemonic Description

5

CDIV Clock Divider Bit. This sets the divide ratio of the MCLK signal to produce the internal ICLK. Setting CDIV = 0 divides the

MCLK by 2. If CDIV = 1, then the ICLK frequency is equal to the MCLK.
3 PD Power Down. Setting this bit powers down the AD7762, reducing the power consumption to 6.35 mW.
2 LPWR

Low Power. If this bit is set, the AD7762 is operating in a low power mode. The power consumption is reduced for a 6 dB

reduction in noise performance.
1 1 Write 1 to this bit.
0 D1PD Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier.

Rev. 0 | Page 23 of 28

AD7762

STATUS REGISTER (READ ONLY)

MSB LSB

PART 1 PART 0 DIE 2 DIE 1 DIE 0 DVALID LPWR OVR DL OK Filter OK U Filter

BYP F3

Table 17.

Bit Mnemonic Comment

15, 14 PART1:0 Part Number. These bits are constant for the AD7762.
13 to 11 DIE2:0 Die Number. These bits reflect the current AD7762 die number for identification purposes within a system.
10 DVALID Data Valid. This bit corresponds to the DVALID bit in the status word output in the second 16-bit read operation.
9 LPWR Low Power. If the AD7762 is operating in low power mode, this bit is set to 1.
8 OVR If the current analog input exceeds the current overrange threshold, this bit is set.
7 DL OK

6 Filter OK

5 U Filter If a user-defined filter is in use, this bit is set.
4

3 1 This bit is always set.
2-0 DEC2:0 Decimation Rate. These correspond to the bits set in Control Register 1.

BYP F3

When downloading a user filter to the AD7762, a checksum is generated. This checksum is compared to the one
downloaded following the coefficients. If these checksums agree, this bit is set.

When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. This
generated checksum is compared to the one downloaded. If they match, this bit is set.

Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set.

1 DEC2 DEC1 DEC0

OFFSET REGISTER—ADDRESS 0X0003

Non-bitmapped, Default Value 0x0000

The offset register uses twos complement notation and is scaled such that 0x7FFF (maximum positive value) and 0x8000 (maximum
negative value) correspond to an offset of +0.78125% and −0.78125%, respectively. Offset correction is applied after any gain correction.
Using the default gain value of 1.25 and assuming a reference voltage of 4.096V, the offset correction range is approximately ±25 mV.

GAIN REGISTER—ADDRESS 0X0004

Non-bitmapped, Default Value 0xA000

The gain register is scaled such that 0x8000 corresponds to a gain of 1.0. The default value of this register is 1.25 (0xA000). This gives a
full-scale digital output when the input is at 80% of V

. This ties in with the maximum analog input range of ±80% of V

REF

REF

p-p.

OVERRANGE REGISTER—ADDRESS 0X0005

Non-bitmapped, Default Value 0xCCCC

The overrange register value is compared with the output of the first decimation filter to obtain an overload indication with minimum
propagation delay. This is prior to any gain scaling or offset adjustment. The default value is 0xCCCC which corresponds to 80% of V
(the maximum permitted analog input voltage). Assuming V

= 4.096 V, the bit is then set when the input voltage exceeds

REF

approximately 6.55 V p-p differential. Note that the overrange bit is also set immediately if the analog input voltage exceeds 100% of V
for more than four consecutive samples at the modulator rate.

REF

REF

Rev. 0 | Page 24 of 28

AD7762

OUTLINE DIMENSIONS

12.20

1.20

0.75
MAX

0.60

0.45

1

SEATING
PLANE

VIEW A

0° MIN

0.08 MAX
COPLANARITY

0.20

0.09
7°

3.5°
0°

16

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-ACD-HD

1.05

1.00

0.95

0.15

0.05

ROTATED 90° CCW

12.00 SQ

11.80

64

PIN 1

TOP VIEW

(PINS DOWN)

17

49

48

10.20

10.00 SQ

9.80

33

32

49 64

48

EXPOSED

PAD

BOTTOM VIEW

33

LEAD PITCH

(PINS UP)

32

0.50

BSC

0.38

0.32

0.22

1

7.50

BSC SQ

16

17

Figure 33. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-64-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7762BSVZ −40°C to +85°C 64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-64-4
AD7762BSVZ-REEL −40°C to +85°C 64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-64-4
EVAL-AD7762EB Evaluation Board

1

Z = Pb-free part.

1

1

Rev. 0 | Page 25 of 28

AD7762

NOTES

Rev. 0 | Page 26 of 28

AD7762

Rev. 0 | Page 27 of 28

AD7762

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05477–0–8/05(0)

Rev. 0 | Page 28 of 28