Datasheet AD7760 Datasheet (ANALOG DEVICES)

2.5 MSPS, 24-Bit, 100 dB

V

VIN–

www.BDTIC.com/ADI

Sigma-Delta ADC with On-Chip Buffer

FEATURES

120 dB dynamic range at 78 kHz output data rate
100 dB dynamic range at 2.5 MHz output data rate
112 dB SNR at 78 kHz output data rate
100 dB SNR at 2.5 MHz output data rate

2.5 MHz maximum fully filtered output word rate
Programmable oversampling rate (8× to 256×)
Fully differential modulator input
On-chip differential amplifier for signal buffering
Low-pass finite impulse response (FIR) filter with default or

ogrammable coefficients

user-pr
Modulator output mode
Overrange alert bit
Digital offset and gain correction registers
Filter bypass modes
Low power and power-down modes
Synchronization of multiple devices via

APPLICATIONS

Data acquisition systems
Vibration analysis
Instrumentation

GENERAL DESCRIPTION

SYNC

pin

V

REF+

MCLK

SYNC

RESET

FUNCTIONAL BLOCK DIAGRAM

+

IN

MULTIBIT

Σ-Δ

MODULATO R

RECONSTRUCT ION

PROGRAMMABLE

DECIMATI ON

FIR FILTER

ENGINE

BUF

AD7760

CONTROL LOGIC

OFFSET AND GAIN

REGISTERS

DIFF

I/O

DB0 TO DB 15CS DRDYRD/WR

Figure 1.

AD7760

AVDD1

AVDD2

3

AV

DD

4

AV

DD

DECAPA/B

R

BIAS

AGND

V

DRIVE

DV

DD

DGND

4975-001

The AD7760 is a high performance, 24-bit Σ- analog-to-digital
converter (ADC). It combines wide input bandwidth and high
speed with the benefits of Σ- conversion to achieve a perfor­mance of 100 dB SNR at 2.5 MSPS, making it ideal for high
speed data acquisition. Wide dynamic range combined with
significantly reduced antialiasing requirements simplify the
design process. An integrated buffer to drive the reference, a
differential amplifier for signal buffering and level shifting, an
overrange flag, internal gain and offset registers, and a low-pass
digital FIR filter make the AD7760 a compact, highly integrated
data acquisition device requiring minimal peripheral component
selection. In addition, the device offers programmable decimation
rates, and the digital FIR filter can be adjusted if the default
characteristics are not appropriate for the application. The
AD7760 is ideal for applications demanding high SNR
without a complex front-end signal processing design.

The differential input is sampled at up to 40 MSPS by an analog

odulator. The modulator output is processed by a series of low-

m
pass filters, with the final filter having default or user-programmable

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

coefficients. The sample rate, filter corner frequencies, and output
w

ord rate are set by a combination of the external clock frequency

and the configuration registers of the AD7760.

The reference voltage supplied to the AD7760 determines the

alog input range. With a 4 V reference, the analog input range

an
is ±3.2 V differential biased around a common mode of 2 V.
This common-mode biasing can be achieved using the on-chip
differential amplifier, further reducing the external signal
conditioning requirements.

The AD7760 is available in an exposed paddle, 64-lead TQFP
a

nd is specified over the industrial temperature range from

−40°C to +85°C.

Table 1. Related Devices

Part No. Description

AD7762 24-bit, 625 kSPS, 109 dB, Σ-∆ parallel interface
AD7763 24-bit, 625 kSPS, 109 dB, Σ-∆ serial interface

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD7760

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TABLE OF CONTENTS

Features.............................................................................................. 1

Writing to the AD7760.............................................................. 23

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

General Description......................................................................... 1

Revision History ...............................................................................3

Specifications..................................................................................... 4

Timing Specifications ..................................................................6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Terminology ....................................................................................11

Typical Performance Characteristics........................................... 12

Theory of Operation ......................................................................18

Modulator Data Output Mode...................................................... 19

Modulator Inputs........................................................................ 19

Clocking the AD7760 .................................................................... 24

Buffering the MCLK signal....................................................... 24

MCLK Jitter Requirements ....................................................... 24

Driving the AD7760....................................................................... 26

Using the AD7760...................................................................... 27

Decoupling and Layout Recommendations................................ 28

Supply Decoupling..................................................................... 29

Additional Decoupling.............................................................. 29

Reference Voltage Filtering .......................................................29

Differential Amplifier Components ........................................29

Bias Resistor Selection............................................................... 29

Layout Considerations............................................................... 29

Exposed Paddle........................................................................... 29

Programmable FIR Filter............................................................... 30

Downloading a User-Defined Filter ............................................ 31

Modulator Data Output Scaling............................................... 19

Modulator Data Output Mode Interface..................................... 20

Clock Divide-by-1 Mode (

Clock Divide-by-2 Mode (

Using the AD7760 in Modulator Output Mode..................... 21

AD7760 Interface............................................................................ 22

Reading Data............................................................................... 22

Reading Status and Other Registers......................................... 22

Sharing the Parallel Bus............................................................. 22

Synchronization.......................................................................... 22

CDIV

= 1) .....................................20

CDIV

= 0) .....................................20

Example Filter Download ......................................................... 31

AD7760 Registers........................................................................... 33

Control Register 1—Address 0x0001 ...................................... 33

Control Register 2—Address 0x0002 ...................................... 33

Status Register (Read Only)...................................................... 34

Offset Register—Address 0x0003............................................. 34

Gain Register—Address 0x0004............................................... 34

Overrange Register—Address 0x0005..................................... 34

Outline Dimensions....................................................................... 35

Ordering Guide .......................................................................... 35

Rev. A | Page 2 of 36

AD7760

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REVISION HISTORY

8/06—Rev. 0 to Rev. A

Updated Package Option................................................... Universal

Change to Features............................................................................1

Changes to Specifications.................................................................4

Changes to Absolute Maximum Ratings........................................8

Changes to Terminology Section ..................................................11

Added Figure 36 Through Figure 39............................................17

Added Modulator Data Output Mode Section ...........................19

Added Figure 41 Through Figure 47............................................19

Added Modulator Data Output Mode Interface Section...........20

Changes to Reading Data Section.................................................22

Added Synchronization Section....................................................22

Changes to Clocking the AD7760 Section...................................24

Added Buffering the MCLK Signal Section.................................24

A

dded MCLK Jitter Requirements Heading ...............................24

Changes to Driving the AD7760 Section.....................................26

Changes to Figure 51......................................................................26

Added Figure 52..............................................................................26

Changes to Figure 55......................................................................28

Changes to Figure 56......................................................................29

Added Exposed Paddle Section.....................................................29

Change to Control Register 2—Address 0x0002 Section ..........33

Changes to Status Register (Read Only) Section........................34

7/05—Revision 0: Initial Version

Rev. A | Page 3 of 36

AD7760

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SPECIFICATIONS

AVDD1 = DVDD = V
the on-chip amplifier with components as shown in Tabl e 8, unless otherwise noted.

Table 2.

Parameter Test Conditions/Comments Specification Unit

DYNAMIC PERFORMANCE

Decimate by 256 MCLK = 40 MHz, ODR = 78 kHz, fIN = 1 kHz

Dynamic Range Modulator inputs shorted 119 dB min

120.5 dB typ
Signal-to-Noise Ratio (SNR)
Input amplitude = −60 dBFS 59 dB typ
Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 126 dBc typ
Input amplitude = −60 dBFS 77 dBc typ
Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS −105 dB typ
Input amplitude = −6 dBFS −106 dB typ
Input amplitude = −60 dBFS −75 dB typ

Decimate by 32 MCLK = 40 MHz, ODR = 625 kHz, fIN =100 kHz

Dynamic Range Modulator inputs shorted 108 dB min

109.5 dB typ
Signal-to-Noise Ratio (SNR)2 Input amplitude = −0.5 dBFS 107 dB typ
Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 120 dBc typ
Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS −105 dB typ
Input amplitude = −6 dBFS −106 dB typ

Decimate by 8 MCLK = 40 MHz, ODR = 2.5 MHz

Dynamic Range Modulator inputs shorted 99 dB min

100.5 dB typ
Signal-to-Noise Ratio (SNR)2 f
f
f
Spurious-Free Dynamic Range (SFDR) Nonharmonic, fIN = 100 kHz, input amplitude = −6 dBFS 120 dBc typ
Nonharmonic, fIN = 1 MHz, input amplitude = −6 dBFS 114 dBc typ
Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS, fIN = 100 kHz −103 dB typ
Input amplitude = −6 dBFS, fIN = 100 kHz −102 dB typ
IMD Second Order fIN A = 989.95 kHz, fIN B = 999.95 kHz −115 dB typ
IMD Third Order fIN A = 989.95 kHz, fIN B = 999.95 kHz −89 dB typ

DC ACCURACY

Resolution 24 Bits
Differential Nonlinearity Guaranteed monotonic to 24 bits
Integral Nonlinearity 0.00076 % typ
Zero Error 0.014 % typ

0.02 % max
Gain Error 0.016 % typ
Zero Error Drift 0.00001 % FS/°C typ
Gain Error Drift 0.0002 % FS/°C typ

DIGITAL FILTER RESPONSE

Decimate by 8

Group Delay MCLK = 40 MHz 12 µs typ

Decimate by 32

Group Delay MCLK = 40 MHz 47 µs typ

Decimate by 256

Group Delay MCLK = 40 MHz 358 µs typ

= 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, V

DRIVE

2

Input amplitude = −0.5 dBFS 112 dB typ

= 1 kHz, input amplitude = −0.5 dBFS 100 dB typ

IN

= 100 kHz, input amplitude = −0.5 dBFS 99 dB typ

IN

= 1 MHz, input amplitude = −0.5 dBFS 98 dB typ

IN

= 4.096 V, MCLK amplitude = 5 V, TA = 25°C, normal mode, using

REF+

1

Rev. A | Page 4 of 36

AD7760

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Parameter Test Conditions/Comments Specification Unit

ANALOG INPUT

Differential Input Voltage VIN(+) – VIN(−), V
V

(+) – VIN(−), V

IN

Input Capacitance At internal buffer inputs 5 pF typ
At modulator inputs 55 pF typ
REFERENCE INPUT/OUTPUT

V

Input Voltage VDD3 = 3.3 V ± 5% +2.5 V max

REF

V

V

Input DC Leakage Current ±6 µA max

REF

V

Input Capacitance 5 pF max

REF

3 = 5 V ± 5% +4.096 V max

DD

POWER DISSIPATION

Total Power Dissipation Normal mode 958 mW max

Low power mode 661 mW max

Standby Mode Clock stopped 6.35 mW max
POWER REQUIREMENTS

AVDD1 (Modulator Supply) ±5% +2.5 V

AVDD2 (General Supply) ±5% +5 V

AVDD3 (Differential Amplifier Supply) +3.15/+5.25 V min/max

AVDD4 (Reference Buffer Supply) +3.15/+5.25 V min/max

DVDD ±5% +2.5 V

V

+1.65/+2.7 V min/max

DRIVE

Normal Mode

AIDD1 (Modulator) 49/51 mA typ/max
AIDD2 (General)

3

40/42 mA typ/max

AIDD4 (Reference Buffer) AVDD4 = 5 V 34/36 mA typ/max

Low Power Mode

AIDD1 (Modulator) 26/28 mA typ/max
AIDD2 (General)

3

20/23 mA typ/max
AIDD4 (Reference Buffer) AVDD4 = 5 V 9/10 mA typ/max
AIDD3 (Differential Amplifier) AVDD3 = 5 V, both modes 41/44 mA typ/max
DIDD Both modes 63/70 mA typ/max

DIGITAL I/O

MCLK Input Amplitude

4

5 V typ

Input Capacitance 7.3 pF typ
Input Leakage Current ±5 A max
Three-State Leakage Current (D15:D0) ±5 A max
V

0.7 × V

INH

V

0.3 × V

INL

5

V

OH

6

V

OH

4

V

0.1 V max

OL

1

See the Terminology section.

2

SNR specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

3

Current scales with ICLK frequency. See the Typical Performance Characteristics section.

4

Although the AD7760 can function with an MCLK amplitude of less than 5 V, this is the recommended amplitude to achieve the performance as stated.

5

Tested using the minimum V

6

Tested using V

= 2.5 V with a 400 A load current.

DRIVE

voltage of 1.65 V with a 400 µA load current.

DRIVE

1.5 V min

2.4 V typ

= 2.5 V ±2 V p-p

REF

= 4.096 V ±3.25 V p-p

REF

V min

DRIVE

V max

DRIVE

Rev. A | Page 5 of 36

AD7760

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TIMING SPECIFICATIONS

AVDD1 = DVDD = V

Table 3.

Parameter Limit at T

f

1 MHz min Applied master clock frequency

MCLK

40 MHz max
f

500 kHz min Internal modulator clock derived from MCLK

ICLK

20 MHz max

1, 2

t

1

t2 10 ns min
t3 3 ns min
t4 (0.5 × t

t5 t
t6 t
t7 3 ns min
t8 11 ns max Bus relinquish time

2

t

0.5 × t

9

2

t

0.5 × t

10

t11 (0.5 × t

3, 4

t

12

3, 4

t

13

t14 11 ns max Bus relinquish time
t15 4 × t

t16 4 × t
t17 5 ns min Data setup time
t18 0 ns min Data hold time

4, 5

t

19

4, 5

t

20

1

t

= 1/f

ICLK

.

ICLK

2

When ICLK = MCLK,

3

Valid when using the modulator output mode with

4

See the Modulator Data Output Mode section for timing diagrams.

5

Valid when using the modulator output mode with

= 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.

DRIVE

, T

MIN

0.5 × t

typ

ICLK

) + 16 ns max Data access time

ICLK

min

ICLK

min

ICLK

typ

ICLK

typ

ICLK

) + 16 ns max Data access time

ICLK

23 ns min
19 ns min

min

ICLK

min

ICLK

23 ns min
19 ns min

DRDY

pulse width depends on the mark-space ratio of applied MCLK.

Unit Description

MAX

DRDY
DRDY

/WR setup time to CS falling edge

RD

low read pulse width

CS

high pulse width between reads

CS

/WR hold time to CS rising edge

RD

DRDY
DRDY

Data valid prior to DRDY
Data valid after DRDY

low write pulse width

CS

high period between address and data

CS

Data valid prior to MCLK falling edge while DRDY
Data valid after MCLK falling edge while DRDY

CDIV

= 1.

CDIV

= 0.

pulse width
falling edge to CS falling edge

high period
low period

rising edge

rising edge

is logic low

is logic low

Rev. A | Page 6 of 36

AD7760

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TIMING DIAGRAMS

DRDY

t

1

t

5

t

6

CS

RD/WR

D[0:15]

t

2

t

3

t

4

DATA MSW LSW + STATUS

Figure 2. Filtered Output—Para

llel Interface Timing Diagram

t

7

t

8

04975-002

CS

RD/WR

D[0:15]

t

15

t

17

REGISTER ADDRESS REGISTER DAT A

t

16

t

18

04975-004

Figure 3. AD7760 Register Write

Rev. A | Page 7 of 36

AD7760

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameters Rating

AV

1 to GND −0.3 V to +3 V

DD

AVDD2:AV
DV
V

DRIVE

VIN+, VIN– to GND
VINA+, VINA− to GND

4 to GND −0.3 V to +6 V

DD

to GND −0.3 V to +3 V

DD

to GND −0.3 V to +3 V

1

−0.3 V to +6 V

1

−0.3 V to +6 V

Digital Input Voltage to GND2 −0.3 V to DVDD + 0.3 V
MCLK to MCLKGND −0.3 V to +6 V

to GND

3

−0.3 V to AVDD4 + 0.3 V

V

REF+

AGND to DGND −0.3 V to +0.3 V

Input Current to Any Pin Except

Supplies

4

Operating Temperature Range

±10 mA

Commercial −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TQFP Exposed Paddle Package

θ

Thermal Impedance 92.7°C/W

JA

θ

Thermal Impedance 5.1°C/W

JC

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C
ESD 600 V

1

Absolute maximum voltage for VIN−, VIN+ and V

whichever is lower.

2

Absolute maximum voltage on digital inputs is 3.0 V or DVDD + 0.3 V,

whichever is lower.

3

Absolute maximum voltage on V

whichever is lower.

4

Transient currents of up to 200 mA do not cause SCR latch-up.

input is 6.0 V or AVDD4 + 0.3 V,

REF+

−, V

+ is 6.0 V or AVDD3 + 0.3 V,

INA

INA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 8 of 36

AD7760

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRIVE

DGND63V

DGND61DB060DB159DB258DB357DB456DB555DB654DB753DGND52DB851DB950DB1049DB11

64

62

1

DGND

MCLKGND

MCLK

AVDD2

AGND2

AVDD1

AGND1

DECAPA

REFGND

V

REF+

AGND4

AVDD4

AGND2

AVDD2

AVDD2

AGND2

PIN 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A+

BIAS

IN

R

V

AGND2

Figure 4. 64-Lead TQFP Pin

21

A–

IN

V

AD7760

TOP VIEW

(Not to Scale)

22

23

A–

A+

OUT

OUT

V

V

24

25

26

27

28

3

–

+

IN

IN

DD

V

V

AV

AGND3

2

AV

30

DD

AGND229AGND3

Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

6, 33 AVDD1

2.5 V Power Supply for Modulator. These pins should be decoupled t
with 100 nF and 10 µF capacitors on each pin. See the Decoupling and Layout Recommendations section
fo

r details.

4, 14, 15, 27 AVDD2

5 V Power Supply. These pins should be decoupled to A
on each of Pin 4, Pin 14, and Pin 15). Pin 27 should be connected to Pin 14 via a 15 nH inductor. See the
Decoupling and Layout Recommendations section for details.

24 AVDD3

3.3 V to 5 V Power Supply for Differential Amplifier. This pin shou
100 nF capacitor. See the Decoupling and Layout Recommendations section for details.

12 AVDD4

3.3 V to 5 V Power Supply for Reference Buffer. This pin s

in series with a 10 Ω resistor.
7, 34 AGND1 Power Supply Ground for Analog Circuitry Powered by AVDD1.
5, 13, 16, 18, 28 AGND2 Power Supply Ground for Analog Circuitry Powered by AVDD2.
23, 29, 31, 32 AGND3 Power Supply Ground for Analog Circuitry Powered by AVDD3.
11 AGND4 Power Supply Ground for Analog Circuitry Powered by AVDD4.
9 REFGND Reference Ground. Ground connection for the reference voltage.
41 DVDD

2.5 V Power Supply for Digital Circuitry and FIR Filter.

capacitor.
44, 63 V

DRIVE

Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines the operating

oltage of the logic interface. Both of these pins must be connected together and tied to the same supply.

v

Each pin should also be decoupled to DGND with a 100 nF capacitor.
1, 35, 42, 43,

DGND Ground Reference for Digital Circuitry.

53, 62, 64
19 VINA+ Positive Input to Differential Amplifier.
20 VINA− Negative Input to Differential Amplifier.
21 V
22 V

A− Negative Output from Differential Amplifier.

OUT

A+ Positive Output from Differential Amplifier.

OUT

25 VIN+ Positive Input to the Modulator.
26 VIN− Negative Input to the Modulator.
10 V

REF+

Reference Input. The input range of this pin is determined by the reference buffer supply voltage (AV

See the Reference Voltage Filtering section for more details.
8 DECAPA Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND.

48

DB12

47

DB13

46

DB14

45

DB15

44

V

DRIVE

43

DGND

42

DGND

41

DV

DD

40

CS

39

RD/WR

38

DRDY

37

RESET

36

SYNC

35

DGND

34

AGND1

33

AVDD1

31

AGND332AGND3

DECAPB

4975-005

o AGND1 (Pin 7 and Pin 34, respectively)

GND2 (Pin 5 and Pin 13, with 100 nF capacitors

ld be decoupled to AGND3 (Pin 23) with a

hould be decoupled to Pin 9 with a 10 nF capacitor

This pin should be decoupled to DGND with a 100 nF

4).

DD

Rev. A | Page 9 of 36

AD7760

www.BDTIC.com/ADI

Pin No. Mnemonic Description

30 DECAPB Decoupling Pin. A 33 pF capacitor must be inserted between this pin and AGND3.
17 R

45 to 52,
54 to 61

37

3 MCLK

2 MCLKGND Master Clock Ground Sensing Pin.
36

39

38

40

BIAS

DB15:DB8,
DB7:DB0

RESET

SYNC

/WR Read/Write Input. This pin, in conjunction with the chip select pin, is used to read and write data to and

RD

DRDY

CS

Bias Current Setting Pin. A resistor must be inserted bet
Bias Resistor Selection section.

16-Bit Bidirectional Data Bus. These are three-state pins that are controlled by the CS pin and the RD/WR
pin. The operating voltage for these pins is determined by the V
Output Mode and AD7760 Interface sections for more details.

A falling edge on this pin resets all internal digital circuitry and powers down the part. Holding this pin low
keeps the AD7760 in a reset state.

Master Clock Input. A low jitter, buffered digital clock must be applied t
depends on the frequency of this clock. See the Clocking the AD7760 section for more details.

Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize
multiple devices in a system. See the Synchronization section for more details.

from the AD7760. If this pin is low when CS is low, a read takes place. If this pin is high when CS is low, a
write occurs. See the Modulator Data Output Mode and AD7760 Interface sections for more details.

Data Ready Output. Each time new conversion data is available, an active low pulse, ½ ICLK period wide, is
produced on this pin. See the Modulator Data Output Mode and AD7760 Interface sections for more details.

Chip Select Input. Used in conjunction with the RD/WR pin to read and write data from and to the AD7760.
See the Modulator Data Output Mode and AD7760 Interface sections for more details.

ween this pin and AGND. For more details, see the

voltage. See the Modulator Data

DRIVE

o this pin. The output data rate

Rev. A | Page 10 of 36

AD7760

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TERMINOLOGY

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the

ms sum of all other spectral components below the Nyquist

r
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the fundamental.

or the AD7760, it is defined as

F

22222

++++

VVVVV

54

()

THD

where:

V

is the rms amplitude of the fundamental.

1

, V3, V4, V5, and V6 are the rms amplitudes of the second to

V

2

the sixth harmonics.

log20dB

=

32

V

1

6

Integral Nonlinearity (INL)

INL is the maximum deviation from a straight line passing

rough the endpoints of the ADC transfer function.

th

Differential Nonlinearity (DNL)

DNL is the difference between the measured and the ideal

B change between any two adjacent codes in the ADC.

1 LS

Zero Error

Zero error is the difference between the ideal midscale input
voltage (w
voltage producing the midscale output code.

Zero Error Drift

Zero error drift is the change in the actual zero error value due

o a temperature change of 1°C. It is expressed as a percentage

t
of full scale at room temperature.

hen both inputs are shorted together) and the actual

Nonharmonic Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of the rms signal amplitude to the rms value

f the peak spurious spectral component, excluding harmonics.

o

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to

he rms noise measured with the inputs shorted together. The

t
value for the dynamic range is expressed in decibels.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb

, any active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa ± nfb, where m, n = 0,
1, 2, 3, and so on. Intermodulation distortion terms are those
for which neither m nor n are equal to 0. For example, the second­order terms include (fa + fb) and (fa − fb), and the third-order
terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The AD7760 is tested using the CCIF standard, where two input

requencies near the top end of the input bandwidth are used.

f
In this case, the second-order terms are usually distanced in

f

requency from the original sine waves, and the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in decibels.

Gain Error

The first transition (from 100 … 000 to 100 … 001) should
occur for an an
full scale. The last transition (from 011 … 110 to 011 … 111)
should occur for an analog voltage 1½ LSB below the nominal
full scale. The gain error is the deviation of the difference
between the actual level of the last transition and the actual
level of the first transition, from the difference between the
ideal levels.

Gain Error Drift

Gain error drift is the change in the actual gain error value due

o a temperature change of 1°C. It is expressed as a percentage

t
of full scale at room temperature.

alog voltage ½ LSB above the nominal negative

Rev. A | Page 11 of 36

AD7760

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD1 = DVDD = V
FFTs are generated from 65,536 samples using a 7-term Blackman-Harris window.

0

= 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, V

DRIVE

= 4.096 V, TA = 25°C, normal mode, unless otherwise noted. All

REF

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

0 4000 8000 12000 16000 20000

FREQUENCY (Hz)

04975-006

24000

Figure 5. Normal Mode FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

0 4000 8000 12000 16000 20000

Figure 6. Normal Mode FFT, 1 kHz, −6

FREQUENCY (Hz)

dB Input Tone, 256× Decimation

24000

04975-007

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

0 4000 8000 12000 16000 20000

FREQUENCY (Hz)

04975-009

24000

Figure 8. Low Power FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

0 4000 8000 12000 16000 20000

FREQUENCY (Hz)

04975-010

24000

Figure 9. Low Power FFT, 1 kHz, −6 dB Input Tone, 256× Decimation

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

24000

8
0
0

­5
7
9
4

0

–175

–200

0 4000 8000 12000 16000 20000

FREQUENCY (Hz)

Figure 7. Normal Mode FFT, 1 kHz, −60 dB Input Tone, 256× Decimation

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

0 4000 8000 12000 16000 20000

FREQUENCY (Hz)

Figure 10. Low Power FFT, 1 kHz, −60 dB Input Tone, 256× Decimation

Rev. A | Page 12 of 36

04975-011

24000

AD7760

www.BDTIC.com/ADI

0

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

0 250 500 750 1000 1250

FREQUENCY (kHz)

04975-012

Figure 11. Normal Mode FFT, 100 kHz, −0.5 dB Input Tone, 8× Decimation

0

–25

–50

–75

–100

AMPLITUDE ( dB)

–125

–150

–25

–50

–75

–100

–125

AMPLITUDE ( dB)

–150

–175

–200

0 250 500 750 1000 1250

Figure 14. Low Power FFT, 100 kHz, −0.

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

FREQUE NCY (kHz)

5 dB Input Tone, 8× Decimation

04975-015

–175

–200

0 250 500 750 1000

FREQUENCY (kHz)

04975-013

1250

Figure 12. Normal Mode FFT, 100 kHz, −6 dB Input Tone, 8× Decimation

0

–25

–50

–75

–100

–125

AMPLITUDE (d B)

–150

–175

–200

0 250 500 750 1000 1250

FREQUENCY (kHz)

Figure 13. Normal Mode FFT, 1 MHz, −0.

5 dB Input Tone, 8× Decimation

04975-014

–175

–200

0 250 500 750 1000 1250

Figure 15. Low Power FFT, 100 kHz, −6

0

–25

–50

–75

–100

–125

AMPLITUDE (dB)

–150

–175

–200

0 250 500 750 1000 1250

FREQUENCY (kHz)

dB Input Tone, 8× Decimation

FREQUENCY (kHz)

Figure 16. Low Power FFT, 1 MHz, −0.5 dB Input Tone, 8× Decimation

04975-016

04975-017

Rev. A | Page 13 of 36

AD7760

www.BDTIC.com/ADI

0

0

–25

–50

–75

–100

–125

AMPLITUDE (d B)

–150

–175

–200

0 1250

Figure 17. Normal Mode FFT, 1 MHz, −6

0

–25

–50

–75

–100

250 500 750 1000

FREQUENCY (kHz)

TONE A: 999.75kHz
TONE B: 1.00025MHz

dB Input Tone, 8× Decimation

–25

–50

–75

–100

–125

AMPLITUDE (d B)

–150

–175

04975-018

–200

0 1250

Figure 20. Low Power FFT, 1 MHz, −6 d

0

–25

–50

–75

–100

250 500 750 1000

FREQUENCY (kHz)

TONE A: 999.75kHz
TONE B: 1.00025MHz

B Input Tone, 8× Decimation

04975-021

–125

AMPLITUDE (dB)

–150

–175

–200

0 1250

250 500 750 1000

FREQUENCY (kHz)

Figure 18. Normal Mode IMD, 1 MHz Center Frequency, 8× Decimation

0

TONE A: 999.75kHz

–20

TONE B: 1.00025MHz
SECOND-ORDER I MD: –105.6dB

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

0 10000

2000 4000 6000 8000

FREQUENCY (kHz)

Figure 19. Normal Mode IMD, 1 MHz Center Frequency, 8× Decimation

–125

AMPLITUDE (dB)

–150

–175

04975-019

–200

0 1250

250 500 750 1000

FREQUENCY (kHz)

04975-022

Figure 21. Low Power IMD, 1 MHz Center Frequency, 8× Decimation

0

TONE A: 999.75kHz

–20

TONE B: 1.00025MHz
SECOND-ORDER I MD: –115.7dB

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

04975-020

–160

0 10000

2000 4000 6000 8000

FREQUENCY (kHz)

04975-023

Figure 22. Low Power IMD, 1 MHz Center Frequency, 8× Decimation

Rev. A | Page 14 of 36

AD7760

–

www.BDTIC.com/ADI

0

TONE A: 999.75kHz
TONE B: 1.00025MHz

–20

THIRD-ORDER
IMD: –89.15dB

–40

0

TONE A: 999.75kHz
TONE B: 1.00025MHz

–20

THIRD-ORDER
IMD: –87.67dB

–40

–60

–80

–100

AMPLITUDE (d B)

–120

–140

–160

995 1005

997 999 1001 1003

FREQUENCY (kHz)

04975-024

Figure 23. Normal Mode IMD, 1 MHz Center Frequency, 8× Decimation

100.5

100.0

99.5

99.0

98.5

SNR (dBFS)

98.0

97.5

97.0

96.5
04

NORMAL MODE

LOW POWER MODE

10 20 30

MCLK FREQ UENCY (MHz)

04975-025

0

Figure 24. SNR vs. MCLK Frequency, 8× Decimation, −6 dB, 1 kHz Input Tone

–60

–80

–100

AMPLITUDE (d B)

–120

–140

–160

995 1005

997 999 1001 1003

FREQUENCY (kHz)

Figure 26. Normal Mode IMD, 1 MHz Center Frequency, 8× Decimation

105

–107

–109

–111

THD (dBc)

–113

–115

–117

040

Figure 27. THD vs. MCLK Frequency, 8× De

NORMAL MODE

LOW POWER MODE

10 20 30

MCLK FREQ UENCY (MHz)

cimation, −6 dB, 1 kHz Input Tone

04975-027

04975-028

120

–60dB

115

–0.5dB

110

105

SNR (dBFS)

100

95

0 256

Figure 25. Normal Mode SNR vs. Decim

64 128 192

DECIMATION RATE

ation Rate, 1 kHz Input Tone

–6dB

04975-026

116

112

108

104

SNR (dBFS)

100

96

0 256

64 128 192

Figure 28. Low Power SNR vs. Decim

Rev. A | Page 15 of 36

–60dB

DECIMATION RATE

ation Rate, 1 kHz Input Tone

–6dB

–0.5dB

04975-029

AD7760

6

6

www.BDTIC.com/ADI

4500

4000

3500

3000

2500

2000

OCCURRENCE

1500

1000

500

0

8385222

Figure 29. Normal Mode, 24-Bit His

8385238 8385254 8385270

24-BIT CODE

togram, 256× Decimation

3000

2500

2000

1500

OCCURRENCE

1000

500

04975-030

0

83835246 8383562 8383578 8383594 8383610

8383530

24-BIT CODE

04975-032

Figure 32. Low Power, 24-Bit Histogram, 256× Decimation

600

500

400

300

OCCURRENCE

200

100

0

8385016

8385116 8385216 83854168385316 8385516

Figure 30. Normal Mode, 24-Bit His

0.0010

0.0005

–0.0005

+85°C

+25°C

0

INL (%)

–40°C

24-BIT CODE

togram, 8× Decimation

450

400

350

300

250

200

OCCURRENCE

150

100

50

04975-031

0

8383236

8383386 8383536 8383686 8383836

24-BIT CODE

04975-033

Figure 33. Low Power, 24-Bit Histogram, 8× Decimation

0.0015

+85°C

0.0010

0.0005

INL (%)

–0.0005

+25°C

0

–40°C

–0.0010

0 1677721

4194304 8388608 12582912

24-BIT CO DE

Figure 31. 24-Bit INL, Normal Mode

04975-034

–0.0010

0 1677721

4194304 8388608 12582912

Figure 34. 24-Bit INL, Low Power Mode

Rev. A | Page 16 of 36

24-BIT CO DE

04975-036

AD7760

6

www.BDTIC.com/ADI

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

0 1677721

4194304 8388608 12582912

24-BIT CO DE

Figure 35. 24-Bit DNL

04975-035

50

45

40

35

30

(mA)

25

DD

DI

20

15

10

5

0

02

Figure 38. Decimate × 32, DI

ICLK FREQ UENCY (MHz)

vs. ICLK Frequency (DVDD = 2.5 V)

DD

04975-059

02 4 6 8 10 12 14 16 18

40

35

30

25

20

2 (mA)

DD

AI

15

10

5

0

020

2 4 6 8 10 12 14 16 18

Figure 36. AI

LK FREQUENCY (MHz)

IC

2 vs. ICLK Frequency (AVDD2 = 5 V)

DD

04975-057

45

40

35

30

25

(mA)

DD

20

DI

15

10

5

0

020

2 4 6 8 10 12 14 16 18

Figure 39. Decimate × 256, DI

60

50

40

(mA)

30

DD

DI

20

ICLK FREQ UENCY (MHz)

vs. ICLK Frequency (DVDD = 2.5 V)

DD

04975-060

10

0

02

2 4 6 8 10 12 14 16 18

Figure 37. Decimate × 8, DI

ICLK FREQUENCY (MHz)

vs. ICLK Frequency (DVDD = 2.5 V)

DD

04975-058

0

Rev. A | Page 17 of 36

AD7760

www.BDTIC.com/ADI

THEORY OF OPERATION

The AD7760 employs a Σ- conversion technique to convert
the analog input into an equivalent digital word. The modulator
samples the input waveform and outputs an equivalent digital
word to the digital filter at a rate equal to ICLK.

The third filter has a fixed decimation rate of 2×, is user
programmable, and has a default configuration. It is described
in detail in the Programmable FIR Filter section. This filter can
also be

bypassed.

By employing oversampling, the quantization noise is spread
acr

oss a wide bandwidth from 0 to f

. This means that the

ICLK

noise energy contained in the signal band of interest is reduced
(see

Figure 40a). To further reduce the quantization noise in the

nal band of interest, a high order modulator is employed to

sig
shape the noise spectrum so that most of the noise energy is
shifted out of the signal band (see Figure 40b).

Table 6 shows some characteristics of the default filter. The

roup delay of the filter is defined to be the delay to the center

g
of the impulse response and is equal to the computation plus
the filter delays. The delay until valid data is available (the
DVALID status bit is set) is equal to twice the filter delay plus
the computation delay.

a.

The digital filtering that follows the modulator removes the
l

arge out-of-band quantization noise (see Figure 40c) while also

r

educing the data rate from f

f

/8 or less at the output of the filter, depending on the

ICLK

at the input of the filter to

ICLK

BAND OF INTEREST

QUANTIZAT ION NOISE

f

ICLK

\2

decimation rate used.

Digital filtering has certain advantages over analog filtering: It

es not introduce significant noise or distortion and can be

do
made perfectly linear in terms of phase.

The AD7760 employs three FIR filters in series. By using

ferent combinations of decimation ratios, filter selection,

dif
and bypassing, data can be obtained from the AD7760 at a large

BAND OF INTEREST

b.

NOISE S HAPING

c.

f

ICLK

\2

range of data rates. Multibit data from the modulator can be
obtained at the ICLK rate (see
s

ection). The first filter receives the data from the modulator at

Modulator Data Output Mode

a maximum frequency of 20 MHz and decimates it by 4 to output
the data at 5 MHz. The partially filtered data can be output at
this stage. The second filter allows the decimation rate to be
chosen from 2× to 32× or to be completely bypassed.

BAND OF INTEREST

DIGITAL FIL TER CUTOFF F REQUENCY

f

ICLK

Figure 40. Σ-Δ ADC

\2

04975-037

Table 6. Configuration with Default Filter

ICLK
Frequency

20 MHz Bypassed Bypassed Bypassed Unfiltered 0 0 10 MHz 20 MHz
20 MHz 4× Bypassed Bypassed Partially filtered 0.325 µs 1.2 µs 1.35 MHz 5 MHz
20 MHz 4× Bypassed 2× Fully filtered 1.075 µs 10.8 µs 1 MHz
20 MHz 4× 2× Bypassed Partially filtered 1.35 µs 3.6 µs 562.5 kHz
20 MHz 4× 2× 2× Fully filtered 1.625 µs 22.8 µs 500 kHz
20 MHz 4× 4× Bypassed Partially filtered 1.725 µs 6 µs 281.25 kHz
20 MHz 4× 4× 2× Fully filtered 1.775 µs 44.4 µs 250 kHz
20 MHz 4× 8x Bypassed Partially filtered 2.6 µs 10.8 µs 140.625 kHz
20 MHz 4× 8× 2× Fully filtered 2.25 µs 87.6 µs 125 kHz
20 MHz 4× 16× Bypassed Partially filtered 4.175 µs 20.4 µs 70.3125 kHz
20 MHz 4× 16× 2× Fully filtered 3.1 µs 174 µs 62.5 kHz
20 MHz 4× 32× Bypassed Partially filtered 7.325 µs 39.6 µs 35.156 kHz
20 MHz 4× 32× 2× Fully filtered 4.65 µs 346.8 µs 31.25 kHz

12.288 MHz 4× 8× 2× Fully filtered 3.66 µs 142.6 µs 76.8 kHz

12.288 MHz 4× 16× 2× Fully filtered 5.05 µs 283.2 µs 38.4 kHz

12.288 MHz 4× 32× Bypassed Partially filtered 11.92 µs 64.45 µs 21.6 kHz

12.288 MHz 4× 32× 2× Fully filtered 7.57 µs 564.5 µs 19.2 kHz 48 kHz

Filter 1 Filter 2 Filter 3 Data State

Rev. A | Page 18 of 36

Computation
Delay

Filter Delay

Pass-Band
Bandwidth

Output Data
Rate (ODR)

2.5 MHz

2.5 MHz

1.25 MHz

1.25 MHz
625 kHz
625 kHz

312.5 kHz

312.5 kHz

156.25 kHz

156.25 kHz

78.125 kHz
192 kHz
96 kHz
96 kHz

AD7760

www.BDTIC.com/ADI

MODULATOR DATA OUTPUT MODE

Operating the AD7760 in modulator output mode enables the
output of data directly from the Σ- modulator. This mode of
operation bypasses the AD7760 on-board digital filtering
capabilities, outputting data in its unfiltered form.

As discussed in the Theory of Operation section, the AD7760
op

erates using oversampling, which spreads quantization noise
over a wide bandwidth. The decrease in the quantization noise
energy in the resulting signal band is illustrated in

upling the use of oversampling with the use of a high

By co

Figure 40a.

order, multibit Σ- modulator, the AD7760 further reduces the
quantization noise in the signal band.

iltered data output from the AD7760 when it is used in

unf

Figure 41 is an FFT of

modulator output mode. This clearly demonstrates the shaping
of the quantization noise performed by the AD7760’s Σ-
modulator.

MODULATOR INPUTS

The maximum voltage input to each differential modulator
input pin is 0.8 × 4.096 V ≈ 3.275 V (80% of V
sit on a common mode of V

/2. This maximum differential

REF

), which must

REF

input voltage is shown as the conditioned output of the AD7760’s
on-board differential amplifier in

Figure 52 in the Driving the

AD7760 section.

Further details on the signal conditioning implemented by the
AD7760’

s on-board differential amplifier and the recommended
external circuitry that accompanies it is described in the
Driving the AD7760 section.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

AMPLITUDE (dB)

–110

–120

–130

–140

–150

–160

Figure 41. FFT of Data Output by the

123456789

01

FREQUENCY (MHz)

AD7760 in Modulator Output Mode

0

04975-048

MODULATOR DATA OUTPUT SCALING

In modulator output mode, data is output in a 16-bit twos
complement format on Pins D [15:0]; however, this data is

scaled to 15 bits. The transfer function in Figure 42 shows the
s

caling involved for the 16 data bits output from Modulator
Pins D[15:0] vs. the maximum differential voltage input
allowed for the modulator inputs (V

D[15:0]

0011 1111 1111 1111

0011 0011 0011 0010

0000 0000 0000 0000

1100 1100 1100 1100

1100 0000 0000 0000

+4.096V

+3.275V = MO DULATOR F ULL SCALE = 80% OF +4. 096V

80% OF +4.096V = M ODULATOR F ULL SCALE = –3.275V

Figure 42. Modulator Output Data Scaling

+ and VIN−).

IN

–4.096V

VIN+ = 3.685 5V

– = 0.4105V

V

IN

+=2.048V

V

IN

– = 2.048V

V

IN

V

+ = 0.410 5V

IN

– = 3.6855V

V

IN

As the nature of the modulator output is coarse relative to
the fully filtered output of the AD7760 (due to the associated
quantization noise of the modulator output), Bits D[3:0] of the
modulator output are zero when operating in modulator data
output mode. Thus, the data outputs for the calculations listed
in

Example 1 and Example 2 for inputs to the modulator pins

V

+ and VIN− show Bits D[3:0] of the modulator output as zero.

IN

Example 1

VIN+ = 3.5 V
V

− = 0.595 V

IN

Modulator Output Code = ([V

(+) − VIN(−)]/4.096 V) × 16384

IN

= [(3.5 V − 0.595 V)/4.096 V] × 16384
= +11620
Direct Scaling: [0010 1101 0110 0100]
Value Output on Data Output Pins D[15:0]:
D [15:0] = [0010 1101 0110 0000].

Example 2

VIN+ = 0.595 V
V

− = 3.5 V

IN

Modulator Output Code = ([V

(+) − VIN(−)]/4.096 V) × 16384

IN

= [(0.595 V − 3.5 V)/4.096 V] × 16384
= −11620
Direct Scaling: [1101 0010 1001 1100]
Value Output on Data Output Pins D[15:0]:
D [15:0] = [1101 0010 1001 0000].

04975-049

Rev. A | Page 19 of 36

AD7760

www.BDTIC.com/ADI

MODULATOR DATA OUTPUT MODE INTERFACE

The AD7760 can be configured in modulator data output mode
(bypassing the default decimation filtering) by writing 0 to each
of the bits contained in Control Register 1:

BYP F1

and DEC [2:0]. This will bypass all digital decimation filtering
offered by the AD7760. See the

rther details.

fu

AD7760 Registers section for

When the AD7760 is operating in modulator data output mode,

ferent parallel interfacing scheme than that used for config-

a dif
urations, where the AD7760’s data output is filtered is necessary.

The data output rate depends on the clock divider ratio that is

CDIV

. When the

used

bit in Control Register 2 is set to logic
high, data is output at the MCLK frequency. If the
set to logic low, data is output at a frequency of MCLK/2. See

the Clocking the AD7760 section.

CLOCK DIVIDE-BY-1 MODE (CDIV = 1)

When obtaining data from the AD7760 in modulator output
mode, both the

brings the data bus out of its high impedance state. Figure 43
s

hows the timing diagram for reading data in the modulator data

/WR and CS lines must be held low. This

RD

BYP F3

,

CDIV

t

9

,

bit is

t

10

output mode when operating with
MCLK). A

pulse is generated for each word. The data on

DRDY

= 1 (that is, ICLK =

CDIV

each of the 16 data output pins, D [15:0], is valid on the rising
edge of the

DRDY

pulse. The

pulse can be used to latch

DRDY
the modulator data into a FIFO or as a DMA control signal. Shortly
after the

/WR and CS lines return high, the AD7760 stops

RD

outputting data and the data bus returns to high impedance.

CLOCK DIVIDE-BY-2 MODE (CDIV = 0)

When operating in modulator output mode with
(that is, ICLK = MCLK/2), the frequency of the
created is half that of the MCLK frequency input to the device.
The timing scheme that is used when

CDIV

number of MCLK cycles that occur between
If the number of MCLK cycles (n) between the rising edge of
RESET

and the rising edge of

SYNC

(see Figure 44) is an even

value, use the interface timing shown in Figure 43. If n is an odd

ue, use the interface timing shown in Figure 45.

val

CDIV

= 0

DRDY

signal

= 0 depends on the

RESET

and

SYNC

.

DRDY

t

CS, RD/WR

D[0:15]

t

11

INVALID DAT A MOD DATA M MOD DATA M + 1 MO D D...

Figure 43. AD7760 Modulator Output Mode (

13

t

t

12

CDIV

= 1) and (

CDIV

= 0, n is even)

14

04975-050

RESET

MCLK

n×

t

MCLK

SYNC

Figure 44. AD7760 Relative Timing Between

RESET

and

SYNC

in Modulator Output Mode

CDIV

= 0

04975-051

Rev. A | Page 20 of 36

AD7760

www.BDTIC.com/ADI

DRDY

D[0:15]

MCLK

CS, RD/WR

t

11

INVALID DAT A MOD DATA M M OD DATA M + 1 MOD D...

Figure 45. AD7760 Modulator Output Mode (

In the case where n is an odd number of MCLK cycles, the

dulator data output on Pins D [15:0] is output on the rising

mo

DRDY

edge of
on the falling edge of MCLK when

. In this case, the modulator data should be read

DRDY

is logic low. Figure 45

shows timing details to be used when reading the modulator

CDIV

output data where
MCLK cycles between the rising edge of

SYNC

edge of

. The edge of MCLK that should be used under

= 0 and there is an odd number of

RESET

and the rising

these conditions is illustrated in Figure 45 by arrows on the
MCLK f

alling edges in question.

USING THE AD7760 IN MODULATOR OUTPUT MODE

The following is the recommended sequence for powering up
and using the AD7760:

1. Ap

ply power.

2. S

tart the clock oscillator, applying MCLK.

3. Ta

k e

low for a minimum of one MCLK cycle.

RESET

t

9

t

10

t

20

t

19

t

14

04975-052

CDIV

= 0, n is odd)

5. W

rite to Control Register 2 to power up the ADC and the

differential amplifier as required. The correct clock divider

) ratio should be programmed at this time.

(

CDIV

6. W

rite to Control Register 1 to set the bypass filter bits,

BYP F3

and

ait a minimum of six MCLK cycles after the rising edge

7. W

of

CS

8. Ta

k e

, and the decimation rate bits, DEC [2:0], to 0.

has been released.

low for a minimum of four MCLK cycles, if

SYNC

BYP F1

required, to synchronize multiple parts.

Using this sequence results in an even number of MCLK cycles
bet

ween the rising edge of

Therefore, when using this sequence with

and the rising edge of

RESET

CDIV

SYNC

= 0, the interface

.

timing shown in Figure 43 should be implemented.

Note that whether the number of MCLK cycles between the

sing edge of

ri
when the AD7760 is operated with

RESET

and

is odd or even is irrelevant

SYNC

= 1.

CDIV

ait a minimum of two MCLK cycles after the rising edge

4. W

of

RESET

.

When using the AD7760 in modulator output mode, the offset,

in, and overrange registers are not operational. The only

ga
registers that can be used are Control Register 1 and Control
Register 2.

Rev. A | Page 21 of 36

AD7760

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AD7760 INTERFACE

READING DATA

When the AD7760 is outputting data at a 5 MHz output data
rate or less, the interface operates in a conventional mode, as
shown in Figure 2, using a 16-bit bidirectional parallel interface.
This in

terface is controlled by the

conversion data is output in twos complement format. When a
new conversion result is available, an active low pulse is output
on the

To read a conversion result from the AD7760, two 16-bit read
op

erations are performed. The
conversion result is available. Both
perform the first read operation. Shortly after both lines go low,

the data bus becomes active and the 16 most significant bits
(MSBs) of the conversion result are output. The

lines must return high for a full ICLK period before the second
read is performed. This second read contains the eight least
significant bits (LSBs) of the conversion result along with six
status bits. These status bits are shown in

the other status bits are found in Ta ble 17.

of

Table 7. Status Bits During Data Read

MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0

DVALID OVR UFILT LPWR FILTOK DLOK 0 0

Shortly after RD/WR and CS return high, the data bus returns
to a high impedance state. Both read operations must be

completed before a new conversion result is available because
the new result overwrites the contents of the output register.
If a

DRDY

is invalid.

pin.

DRDY

pulse occurs during a read operation, the data read

READING STATUS AND OTHER REGISTERS

The AD7760 features a number of programmable registers. To
read back the contents of these registers or the status register,
the user must first write to the control register of the device,
setting a bit that corresponds to the register to be read. The next
read operation outputs the contents of the selected register
instead of a conversion result. The
p

rovides more information on the relevant bits in the control

register.

/WR and CS pins. The 24-bit

RD

pulse indicates that a new

DRDY

/WR and CS go low to

RD

/WR and CS

RD

Table 7. Descriptions

AD7760 Registers section

If multiple synchronized AD7760 parts that share a properly
dis

tributed common MCLK signal exist in a system, these parts
can share a common bus without being isolated from each
other. This bus can then be isolated from the system bus by a
single latch or buffer.

SYNCHRONIZATION

SYNC

The
function that allows the user to begin gathering samples of the
analog front-end input from a known point in time.

The
the same MCLK,
so that each ADC simultaneously updates its output register.
The distribution of the signals that are common to each of the
devices that are to be synchronized is extremely important in
ensuring that the timing of each of the AD7760 devices is
correct, that is, that each AD7760 device sees the same digital

edges synchronously.

The
first falling edge of MCLK after
filter sequencer is reset to 0. The filter is held in a reset state until
a falling edge of the MCLK senses
signal must remain logic low for a minimum of four MCLK
cycles.
signal with respect to MCLK.

MCLK

SYNC

The rising edge of
edge of MCLK. Thus, the next falling edge of MCLK senses
SYNC
applying this signal scheme to multiple ADCs using the same
MCLK and
samples synchronously.

input to the AD7760 provides a synchronization

SYNC

function allows multiple AD7760s, operated from

RESET

SYNC

signal is sensed on the falling edge of MCLK. On the

Figure 46 shows the recommended timing for the

MINSYNCLOGICLOW

4×

t

MCLK

Figure 46. Recommended

SYNC

logic high and takes the filter out of its reset state. By

SYNC

signals, all of the devices will gather input

SYNC

, and

should be coincident with the rising

signals, to be synchronized

SYNC

goes logic low, the digital

SYNC

logic high. The

DEVICE SYNCHRONI ZED
FROM THIS POINT IN TIME

SYNC

Timing

SYNC

SYNC

04975-053

SYNC

SHARING THE PARALLEL BUS

By its nature, the high accuracy of the AD7760 makes it
sensitive to external noise sources. These include digital activity
on the parallel bus. For this reason, it is recommended that the
AD7760 data lines be isolated from the system data bus by
means of a latch or buffer to ensure all digital activity on the
D0 to D15 pins is controlled by the AD7760.

Rev. A | Page 22 of 36

Following a
before valid data can be read from the AD7760. The DVALID
status bit (D7 in

hen valid data is being output by the converter. The time from

w
the rising edge of
dependent on the filter configuration used. See the Theory of
Ope

ration section and the values listed in Table 6 for details on

c

alculating the time until DVALID is asserted.

signal, the digital filter needs time to settle

Table 7) output with each conversion indicates

SYNC

until the DVALID bit is asserted is

AD7760

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WRITING TO THE AD7760

There are many features and parameters that the user can
change by writing to the AD7760 device. See the Using the
AD7760 section, which details the writing sequence needed to
ini

tialize the operation of the part.

The AD7760 has programmable registers that are 16 bits wide.

means that two write operations are required to program a

This
register. The first write contains the register address, and the
second write contains the register data. An exception is when a
user-defined filter is being downloaded to the AD7760. This is
described in detail in the
secti

on. The AD7760 Registers section contains the register

addr

esses and details.

Downloading a User-Defined Filter

Figure 3 shows a write operation to the AD7760. The
line is held high while the
of four ICLK periods. The register address is latched during this

period. The
four ICLK periods before the register data is put onto the data

bus. If a read operation occurs between the writing of the
register address and the register data, the register address is
cleared and the next write must be the register address. This
also provides a method to revert back to a known situation if
the user forgets whether the next write is an address or data.

Generally, the AD7760 is written to and configured on power-

p and very infrequently, if at all, after that. Following any write

u
operation, the full group delay of the filter must elapse before
valid data is output from the AD7760.

line is brought high again for a minimum of

CS

line is brought low for a minimum

CS

RD

/WR

Rev. A | Page 23 of 36

AD7760

www.BDTIC.com/ADI

CLOCKING THE AD7760

The AD7760 requires an external low jitter clock source. This
signal is applied to the MCLK pin, and the MCLKGND pin is
used to sense the ground from the clock source. An internal
clock signal (ICLK) is derived from the MCLK input signal. The
ICLK controls all internal operations of the AD7760. The
maximum ICLK frequency is 20 MHz, but due to an internal
clock divider, a range of MCLK frequencies can be used. There
are two ways to generate the ICLK:

ICLK = MCL

ICLK = MCL

K (

K/2 (

These options are selected from the control register (see the
AD7760 Registers section for more details). On power-up, the

ult is ICLK = MCLK/2 to ensure that the part can handle

defa
the maximum MCLK frequency of 40 MHz. For output data
rates equal to those used in audio systems, a 12.288 MHz ICLK
frequency can be used. As shown in
192 kH

z, 96 kHz, and 48 kHz are achievable with this ICLK
frequency. As mentioned previously, this ICLK frequency can
be derived from different MCLK frequencies.

It is recommended that the MCLK signal applied to the
AD7760 has a 5

0-50 mark-space ratio. When operating in clock

divide-by-1 mode (that is,
ratios reduces the maximum MCLK frequency that can be

applied to the AD7760 yielding maximum performance. For
example, using a mark-space ratio of 60-40 (with

reduces the maximum MCLK frequency that will yield the
maximum INL and THD performance to 16 MHz.

BUFFERING THE MCLK SIGNAL

The MCLK signal for the AD7760 must be buffered before
being input to the MCLK pin on the AD7760 device. This can
be done simply by routing the MCLK signal to both inputs of an
AND gate (see Figure 47).

The recommended buffer is the NC7SZ08M5, which is a two­in

put AND gate from Fairchild Semiconductor. Using the buffer
with a supply voltage of 5 V is advised to achieve optimum
performance from the AD7760.

MCLK

SOURCE

Figure 47. Buffering the MCLK Signal Using the NC7SZ08M5 AND Gate

CDIV

CDIV

NC7SZ08M5
(AND GATE)

= 1)

= 0)

Table 6, output data rates of

= 1), using higher mark-space

CDIV

CDIV

AD7760

3

MCLK

= 1)

04975-054

MCLK JITTER REQUIREMENTS

The MCLK jitter requirements depend on a number of factors
and are given by

t

=

)(

rmsj

OSR

f

××π×

102

IN

where:

OS

R = oversampling ratio = f

f

= maximum input frequency.

IN

ICLK

SNR(dB) = target SNR.

Example 1

This example can be taken from Table 6, where:
ODR = 2.5 MHz.

= 20 MHz.

f

ICLK

(max) = 1 MHz.

f

IN

SNR = 108 dB.

=

t

)(

rmsj

8

4.56

10102

××π×

This is the maximum allowable clock jitter for a full-scale,

z input tone with the given ICLK and output data rate.

1 MH

Example 2

Take a second example from Ta ble 6, where:
ODR = 48 kHz.

= 12.288 MHz.

f

ICLK

f

(max) = 19.2 kHz.

IN

SNR = 120 dB.

=

t

)(

rmsj

256

×××π×

The input amplitude also has an effect on these jitter figures.
F

or example, if the input level was 3 dB below full-scale, the
allowable jitter would be increased by a factor of √2, increasing
the first example to 2.53 ps rms. This happens when the
maximum slew rate is decreased by a reduction in amplitude.
Figure 48 and Figure 49 illustrate this point, showing the

imum slew rate of a sine wave of the same frequency but

max
with different amplitudes.

dBSNR

20

/ODR.

=

63

10102.192

)(

ps79.1

ps133

=

Rev. A | Page 24 of 36

AD7760

–

–

–

–

www.BDTIC.com/ADI

1.0

1.0

0.5

0

0.5

1.0

Figure 48. Maximum Slew Rate of Sine Wave with Amplitude of 2 V p-p

0.5

0

0.5

04975-038

1.0

Figure 49. Maximum Slew Rate of Sine Wave (with the Same Frequency as in

Figure 48) with Amplitude of 1 V p-p

04975-039

Rev. A | Page 25 of 36

AD7760

O

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DRIVING THE AD7760

The AD7760 has an on-chip differential amplifier that operates
with a supply voltage (AV
For a 4.096 V reference, the supply voltage must be 5 V.

To achieve the specified performance in normal mode, the
dif

ferential amplifier should be configured as a first-order

antialias filter, as shown in Figure 50. Any additional filtering

hould be carried out in previous stages using low noise, high

s
performance op amps, such as the AD8021.

Suitable component values for the first-order filter are listed in
Table 8. Using the values in the table as an example yields a
10 dB a

ttenuation at the first alias point of 19 MHz.

A

B

Figure 50. Differential Amplifier Configuration

Table 8. Normal Mode Component Values

V

R

REF

R

IN

4.096 V 1 kΩ 655 Ω 18 Ω 5.6 pF 33 pF

Figure 52 shows the signal conditioning that occurs using the
circuit shown in Figure 50 with a ±2.5 V input signal biased

round ground and the component values and conditions listed

a
in

Table 8. The differential amplifier always biases the output

3) within the 3.15 V to 5.25 V range.

DD

C

FB

R

FB

R

IN

C

R

IN

FB

A1

S

R

FB

C

FB

R

R

M

VIN–

R

M

V

IN

C

M

C

S

+

4975-040

FB

nal to sit on the optimum common mode of V

sig

/2, in this

REF

case 2.048 V. The signal is also scaled to give the maximum
allowable voltage swing with this reference value. This is
calculated as 80% of V

, that is, 0.8 × 4.096 V ≈ 3.275 V p-p

REF

on each input.

With a 4.096 V reference, a 5 V supply must be provided to the
re

ference buffer (AV

must be provided to AV

4). With a 2.5 V reference, a 3.3 V supply

DD

4.

DD

Figure 51 shows the transfer function in terms of the 24-bit
dig

ital output codes (twos complement coding) of the AD7760

vs. the voltage signals V

and VB applied to the on-board

A

differential amplifier A1, as shown in Figure 52.

24 BITS

011…111

011…110

000…010

AD7760

24-BIT

UTPUT

Figure 51. Transfer Function for the AD7760 Filtered Output Where V

000…001

000…000

111…111

111…110

100…001

100…000

B=+2.5V
A = –2.5V

A=0V
B=0V

are Inputs to the On-Board Differential Amplifier A1

A=+2.5V
B = –2.5V

and VB

A

04975-056

+2.5V

0V

A

–2.5V

+2.5V

B

0V

–2.5V

INPUTS TO T HE AD7760 DI FFERENTIAL AMPLIF IER

+3.685V

+2.048V

+0.410V

+3.685V

+2.048V

+0.410V

OUTPUTS OF THE AD7760 DIFFERENTIAL AMPLIFIER

VIN+

V

IN

–

Figure 52. Differential Amplifier Signal Conditioning

Rev. A | Page 26 of 36

4975-055

AD7760

V

www.BDTIC.com/ADI

To obtain maximum performance from the AD7760, it is
advisable to drive the ADC with differential signals. Figure 53

ws how a bipolar, single-ended signal biased around ground

sho
can drive the AD7760 with the use of an external op amp, such
as the

AD8021.

C

FB

USING THE AD7760

The following is the recommended sequence for powering up
and using the AD7760:

Apply power.

1.

Start the clock oscillator, applying MCLK.

2.

2R

V

IN

2R

AD8021

R

Figure 53. Single-Ended-to-D

R

R

R

FB

IN

C

IN

ifferential Conversion

A1

S

R

FB

C

FB

R

M

VIN–

R

M

VIN+

The AD7760 employs a double-sampling front end, as shown in
Figure 54. For simplicity, only the equivalent input circuit for V

SH3

SH4

− is the same.

IN

ANALOG

MODULATOR

is shown. The equivalent input circuitry for V

+

IN

CPA

SS1

SH1

SS2

SH2

Figure 54. Equivalent Input Circuit

CPB1

CPB2

CS1

SS3

CS2

SS4

3.

Ta ke
Wait a minimum of two MCLK cycles after

4.

low for a minimum of one MCLK cycle.

RESET

RESET

has

been released.

Write to Control Register 2 to power up the ADC and the

5.
differential amplifier as required. The correct clock divider

) ratio should be programmed at this time.

(

CDIV

4975-042

+

IN

Write to Control Register 1 to set the output data rate.

6.

Wait a minimum of five MCLK cycles after

7.

has been

CS

released.

8.

Ta ke

low for a minimum of four MCLK cycles, if

SYNC

required, to synchronize multiple parts.

Data can then be read from the part using the default filter,

ffset, gain, and overrange threshold values. The conversion

o
data read is not valid, however, until the group delay of the filter
has elapsed. Once this has occurred, the DVALID bit read with
the data LSW is set, indicating that the data is indeed valid.

The user can then download a different filter if required (see the
Downloading a User-Defined Filter section). Values for gain,

ffset, and overrange threshold registers can be written or read

04975-043

o
at this stage.

Sampling Switches SS1 and SS3 are driven by ICLK, whereas
Sampling Switches SS2 and SS4 are driven by

. When ICLK is

ICLK
high, the analog input voltage is connected to CS1. On the falling
edge of ICLK, the SS1 and SS3 switches open and the analog input
is sampled on CS1. Similarly, when ICLK is low, the analog input
voltage is connected to CS2. On the rising edge of ICLK, the SS2
and SS4 switches open and the analog input is sampled

on CS2.

Capacitors CPA, CPB1, and CPB2 represent parasitic capacitances

at include the junction capacitances associated with the MOS

th
switches.

Table 9. Equivalent Component Values

Mode CS1 (pF) CS2 (pF) CPA (pF) CPB1/2 (pF)

Normal 51 51 12 20
Low Power 13 13 12 5

Rev. A | Page 27 of 36

AD7760

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DECOUPLING AND LAYOUT RECOMMENDATIONS

Due to the high performance nature of the AD7760, correct decoupling and layout techniques are required to obtain the performance as
stated within this data sheet. Figure 55 shows a simplified connection diagram for the AD7760.

PIN 14PIN 15PIN 4

PIN 12PIN 6

PIN 33PIN 24PIN 27PIN 44PIN 63PIN 41

AVDD2

PIN 4

(RHS)

C48

100nF

14154

1263324274463

2

2

2

4

1

1

3

2

DD

DD

DD

DD

AV

DRIVEVDRIVE

AV

AV

V

100nF

V

A+

IN

V

A–

IN

V

A–

OUT

V

A+

OUT

C64

C7

33pF

VIN+
V

IN

–

19
20
21
22

8

30

25
26

VINA+
V

A–

IN

V

A–

OUT

V

A+

OUT

DECAPA
DECAPB

+

V

IN

V

–

IN

DD

DD

DD

DD

AV

AV

AV

AV

AV

AD7760BSV

10

V

REFX

R19

160kΩ

L1

PIN 15

(VBIAS)

C50

100nF

L3

L2

PIN 14

(LHS) P IN 27

C62

100nF

L9

9

17

1
35
42
43
53
62
64

AVDD4

PIN 12

(VBUF)

V

REF+

REFGND

R

BIAS

DGND
DGND
DGND
DGND
DGND
DGND
DGND

R38
10Ω

C59

10nF

AGND1

AGND1

AGND2

AGND2

AGND2

AGND2

AGND2

AGND3

AGND3

AGND3

7

L4

(VMOD1)

34

AVDD1

PIN 5

C52

100nF

5

L5

131618

PIN 33

(VMOD2)

28

L11

C53

100nF

AGND3

2329313211

AVDD3

PIN 24

(VDIF1)

41

DV

AGND4

C54

100nF

DD

L6

U2

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8

DB9
DB10
DB11
DB12
DB13
DB14
DB15

RD/WR

RESET

SYNC
DRDY

MCLK

MCLKGND

V

DRIVE

PIN 44

(VDRV1)

DB [0:15]

61

DB0

60

DB1

59

DB2

58

DB3

57

DB4

56

DB5

55

DB6

54

DB7

52

DB8

51

DB9

50

DB10

49

DB11

48

DB12

47

DB13

46

DB14

45

DB15

40

CS

39

37
36
38

3
2

L7

C56

100nF

PIN 63

(VDRV2)

CS
RD/WR

RESET
SYNC
DRDY

MCLK

L12

C57

100nF

DV

PIN 41

(DV

DD

DD

)

C58

100nF

L8

04975-046

Figure 55. Simplified Connection Diagram

Rev. A | Page 28 of 36

AD7760

www.BDTIC.com/ADI

SUPPLY DECOUPLING

Every supply pin must be connected to the appropriate supply
via a ferrite bead and decoupled to the correct ground pin with
a 100 nF, 0603 case size, X7R dielectric capacitor. There are two
exceptions to this:

• Pin 12 (AV

4) must have a 10  resistor inserted between

DD

the pin and a 10 nF decoupling capacitor, which is
connected to ground at Pin 9.

• Pin 27 (AV

2) does not require a separate decoupling

DD

capacitor or a direct connection to the supply, but instead
is connected to Pin 14 via a 15 nH inductor.

ADDITIONAL DECOUPLING

There are two other decoupling pins on the AD7760—Pin 8
(DECAPA) and Pin 30 (DECAPB). Pin 8 should be decoupled
with a 100 nF capacitor, and Pin 30 requires a 33 pF capacitor.

REFERENCE VOLTAGE FILTERING

A low noise reference source, such as the ADR431 (2.5 V) or

ADR434 (4.096 V), is suitable for use with the AD7760. The

eference voltage supplied to the AD7760 should be decoupled

r
and filtered as shown in

Figure 56.

The recommended scheme for the reference voltage supply is a

eries resistor connected to a 100 F tantalum capacitor,

100  s
followed by a series resistor of 10 , and finally a 10 nF capacitor
placed as close as possible to the V

pin, decoupling this

REF+

capacitor to the associated ground pin, Pin 11.

U3

ADR434

2

7.5V PIN 10V

+

C15

10µFC9100nF

V

IN

GND

4

Figure 56. Reference Connection

OUT

R30

100Ω

6

C11

100µF

R17
10Ω

+

C46

10nF

DIFFERENTIAL AMPLIFIER COMPONENTS

The correct components for use around the on-chip differential
amplifier are detailed in Table 8. Matching the components on

oth sides of the differential amplifier is important to minimize

b
distortion of the signal applied to the amplifier. A tolerance of

0.1% or better is required for these components. Symmetrical
routing of the tracks on both sides of the differential amplifier
also assists in achieving the stated performance.

04975-047

BIAS RESISTOR SELECTION

The AD7760 requires a resistor to be connected between the

and AGND pins. The value of this resistor is dependent

R

BIAS

on the reference voltage being applied to the device. The resistor
value should be selected to produce a current of 25 µA through
the resistor to ground. For a 2.5 V reference voltage, the correct
resistor value is 100 kΩ, and for a 4.096 V reference, the correct
resistor value is 160 kΩ.

LAYOUT CONSIDERATIONS

While using the correct components is essential to achieve
optimum performance, the correct layout is just as important.
The AD7760 product page on the Analog Devices website

ntains the Gerber files for the AD7760 evaluation board.

co
These files should be used as a reference when designing any
system using the AD7760.

The location and orientation of some of the components

entioned in previous sections of this data sheet are critical,

m
and particular attention must be paid to the components that
are located close to the AD7760. Locating these components
farther away from the device can have a direct impact on the
achievable maximum performance.

The use of ground planes should also be carefully considered.
T

o ensure that the return currents through the decoupling
capacitors are flowing to the correct ground pin, the ground side
of the capacitors should be as close as possible to the ground pin
associated with that supply. A ground plane should not be relied
on as the sole return path for decoupling capacitors because the
return current path using ground planes is not easily predictable.

EXPOSED PADDLE

The AD7760 64-lead TQFP employs a 6 mm × 6 mm exposed
paddle (see Figure 59). The paddle reduces the thermal

esistance of the package by providing a path for heat energy to

r
flow between the package and the PCB and, in turn, increases
the heat transfer efficiency from the AD7760 package.
Connecting the exposed paddle to the AGND plane of the PCB
is essential in creating the conditions that allow the AD7760
package to perform to the highest specifications possible. The
exposed paddle should not be connected directly to any of the
ground pins on the AD7760 and should only be connected to
the analog ground plane. Best practice is to use multiple vias
connecting the exposed paddle to the AGND plane of the PCB.

Rev. A | Page 29 of 36

AD7760

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PROGRAMMABLE FIR FILTER

As previously mentioned, the third FIR filter on the AD7760
is user programmable. The default coefficients that are loaded
upon reset are given in Table 10 , and the frequency responses

shown in Figure 57. The frequencies quoted in Figure 57

are
s

cale directly with the output data rate.

Table 10. Default Filter Coefficients

Dec

No.

Va

lue

0 53656736 332BCA0 24 700847 AB1AF
1 25142688 17FA5A0 25 −70922 401150A
2 −4497814 444A196 26 −583959 408E917
3 −11935847 4B62067 27 −175934 402AF3E
4 −1313841 4140C31 28 388667 5EE3B
5 6976334 6A734E 29 294000 47C70
6 3268059 31DDDB 30 −183250 402CBD2
7 −3794610 439E6B2 31 −302597 4049E05
8 −3747402 4392E4A 32 16034 3EA2
9 1509849 1709D9 33 238315 3A2EB
10 3428088 344EF8 34 88266 158CA
11 80255 1397F 35 −143205 4022F65
12 −2672124 428C5FC 36 −128919 401F797
13 −1056628 4101F74 37 51794 CA52
14 1741563 1A92FB 38 121875 1DC13
15 1502200 16EBF8 39 16426 402A
16 −835960 40CC178 40 −90524 401619C
17 −1528400 4175250 41 −63899 400F99B
18 93626 16DBA 42 45234 B0B2
19 1269502 135EFE 43 114720 1C020
20 411245 6466D 44 102357 18FD5
21 −864038 40D2F26 45 52669 CDBD
22 −664622 40A242E 46 15559 3CC7
23 434489 6A139 47 1963 7AB

The default filter should be sufficient for most applications. It is
a standard brick wall filter with a symmetrical impulse response.
The default filter has a length of 96, is nonaliasing, and provides
120 dB of attenuation at Nyquist. This filter not only performs
signal antialiasing, but also suppresses out-of-band quantization
noise produced by the analog-to-digital conversion process. Any
significant relaxation in the stop-band attenuation or transition
bandwidth relative to the default filter can result in a failure to
meet the SNR specifications.

Hex
Value No.

Dec
Value

Hex
Value

To create a filter, note the following:

• The filter must be an even, symmetrical FIR.

• The coefficients are in sign-and-magnitude format, with

26 magnitude bits and sign coded as positive = 0.

• The filter length must be between 12 taps and 96 taps in

steps of 12.

• Because the filter is symmetrical, the number of

coefficients that must be downloaded is half the filter
length. The default filter coefficients exemplify this with
only 48 coefficients listed for a 96-tap filter.

• Coefficients are written from the center of the impulse

response (adjacent to the point of symmetry) outwards.

• The coefficients are scaled so that the in-band gain of the

filter is equal to 134,217,726, with the coefficients rounded
to the nearest integer. For a low-pass filter, this is the
equivalent of having the coefficients summed arithmetically
(including sign) to a +67,108,863 (0x3FF FFFF) positive
value over the half-impulse-response coefficient set (a
maximum of 48 coefficients). Any deviation from this
introduces a gain error.

0

–20

–40

–60

–80

–100

AMPLI TUDE (d B)

–120

–140

–160

0 500 200015001000 2500

Figure 57. Default Filter Frequency Respo

PASS-BAND RIP PLE = 0.05dB

–0.1dB FREQUENCY = 1.004MHz

–3dB FREQ UENCY = 1. 06MHz

STOP BAND = 1.25MHz

FREQUENCY (kHz)

nse (2.5 MHz ODR)

04975-044

The procedure for downloading a user-defined filter is detailed
in the Downloading a User-Defined Filter section.

The default filter characteristics scale with both the MCLK

requency applied and the decimation rate chosen by the user.

f

Rev. A | Page 30 of 36

AD7760

www.BDTIC.com/ADI

DOWNLOADING A USER-DEFINED FILTER

As previously mentioned, the filter coefficients are 27 bits in
length—one sign and 26 magnitude bits. Because the AD7760
has a 16-bit parallel bus, the coefficients are padded with 5 MSB
0s to generate a 32-bit word, split into two 16-bit words for
downloading. The first 16-bit word for each coefficient becomes
(00000, sign bit, Magnitude [25:16]), whereas the second word
becomes (Magnitude [15:0]). To ensure that a filter is downloaded
correctly, a checksum must also be generated and then downloaded
following the final coefficient. The checksum is a 16-bit word
generated by splitting each 32-bit word into four bytes and
summing the bytes from all coefficients up to a maximum of
192 bytes (48 coefficients × four bytes). The same checksum
is generated internally in the AD7760 and compared with the
downloaded checksum. The DL_OK bit in the status register is
set if these two checksums agree.

To download a user filter

Write to Control Register 1, setting the DL_FILT bit and

1.
the correct filter length bits corresponding to the length of
the filter to be downloaded (see Tabl e 11 ).

Write the first half of the current coefficient data

2.
(00000, sign bit, Magnitude [25:16]). The first coefficient
to be written must be the one adjacent to the point of filter
symmetry.

3.

Write the second half of the current coefficient data

(Magnitude [15:0]).

Repeat Step 2 and Step 3 for each coefficient.

4.

5.

Write the 16-bit checksum.
Use the following methods to verify that the filter coefficients

6.
are downloaded correctly:

Read the status register, checking the DL_OK bit.

a.

Read data and observe the status of the DL_OK bit.

b.

Note that because the user coefficients are stored in RAM, they
are

cleared after a

operation or a loss of power.

RESET

Table 11. Filter Length Values

FLEN [3:0] Number of Coefficients Filter Length

0000 Default Default
0001 6 12
0011 12 24
0101 18 36
0111 24 48
1001 30 60
1011 36 72
1101 42 84
1111 48 96

EXAMPLE FILTER DOWNLOAD

The following is an example of downloading a short user­defined filter with 24 taps. The frequency response is shown in
Figure 58.

10

0

–10

–20

–30

–40

AMPLITUDE (d B)

–50

–60

–70

–80

06

100 200 300 400 500

FREQUENCY (kHz)

Figure 58. 24-Tap FIR Fr

equency Response

The coefficients for the filter are listed in Table 12 and are
shown from the center of symmetry outwards. The raw
coefficients were generated using a commercial filter design
tool and were scaled appropriately so that their sum equals
67,108,863 (0x3FF FFFF).

Table 12. 24-Tap FIR Coefficients

Coefficient Raw Scaled

1 0.365481974 53188232
2 0.201339905 29300796
3 0.009636604
4 −0.075708848
5 −0.042856209
6 0.019944246
7 0.036437914
8 0.007592007
9 −0.021556583
10 −0.024888355
11 −0.012379538
12 −0.001905756 −277343

1402406

−11017834

−6236822
2902466
5302774
1104856

−3137108

−3621978

−1801582

00

04975-045

Rev. A | Page 31 of 36

AD7760

www.BDTIC.com/ADI

Table 13 shows the hexadecimal values (in sign-and-magnitude
format) that are downloaded to the AD7760 to realize this filter.
The table is also split into the bytes that are summed to produce
the checksum. The checksum generated from these coefficients
is 0x0E6B.

Table 13. Filter Hexadecimal Values

Word 1 Word 2
Coefficient Byte 1 Byte 2 Byte 3 Byte 4

1 03 2B 96 88
2 01 BF 18 3C
3 00 15 66 26
4 04 A8 1E 6A
5 04 5F 2A 96
6 00 2C 49 C2
7 00 50 E9 F6
8 00 10 DB D8
9 04 2F DE 54
10 04 37 44 5A
11 04 1B 7D 6E
12 04 04 3B 5F

Table 14 lists the 16-bit words the user would write to the
AD7760 to set up the ADC and download this filter, assuming
an output data rate of 1.25 MHz has been selected.

Table 14. Sequence of Write Instructions to Set Up Device
and Download the Filter Example

Word Description

0x0001 Address of Control Register 1.
0x8079

0x032B First coefficient, Word 1.
0x9688 First coefficient, Word 2.
0x01BF Second coefficient, Word 1.
0x183C Second coefficient, Word 2.

…

0x0404 Twelfth (final) coefficient, Word 1.
0x3B5F Final coefficient, Word 2.
0x0E6B

0x0001 Address of control register.
0x0879

Control register data. DL filter: set filter length = 24,
set output da

Other coefficients.

Checksum. Wait (0.5 × t
coefficients) for AD7760 to write 0s to the remaining
unused coefficients.

Control register data. Set read status and maintain

er length and decimation settings. Read contents

filt
of status register. Check Bit 7 (DL_OK) to determine
if the filter was downloaded correctly.

ta rate = 1.25 MHz.

× number of unused

ICLK

Rev. A | Page 32 of 36

AD7760

www.BDTIC.com/ADI

AD7760 REGISTERS

The AD7760 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter configuration, the
clock divider, and so on. There are also digital gain, offset, and overrange threshold registers. Writing to these registers involves writing
the register address first, then a 16-bit data-word. Register addresses, details of individual bits, and default values are given in this section.

CONTROL REGISTER 1—ADDRESS 0x0001

Default Value 0x001A

MSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DL_
FILT

RD
OVR

RD
GAIN

RD
OFF

RD
STAT

0

SYNC FLEN3 FLEN2 FLEN1 FLEN0 BYP F3 BYP F1 DEC2 DEC1 DEC0

Table 15. Bit Descriptions of Control Register 1

Bit Mnemonic Description

15 DL_FILT

1

Download Filter. Before downloading a user-defined filter, this bit must be set. The filter length bits must
also be set at this time. The write operations that follow are interpreted as the user coefficients for the FIR
filter until all the coefficients and the checksum have been written.

14 RD OVR

1, 2

Read Overrange. If this bit has been set, the next read operation outputs the contents of the overrange

threshold register instead of a conversion result.
13 RD GAIN
12 RD OFF
11 RD STAT

1, 2

Read Gain. If this bit has been set, the next read operation outputs the contents of the digital gain register.

1, 2

Read Offset. If this bit has been set, the next read operation outputs the contents of the digital offset register.

1, 2

Read Status. If this bit has been set, the next read operation outputs the contents of the status register.
10 0 0 must be written to this bit.
9 SYNC1

Synchronize. Setting this bit initiates an internal synchr

onization routine. Setting this bit simultaneously on

multiple devices synchronizes all filters.
8 to 5 FLEN [3:0] Filter Length Bits. These bits must be set when the DL_FILT bit is set before a user-defined filter is downloaded.
4
3

BYP F3
BYP F1

Bypass Filter 3. If this bit is 0, Filter 3 (programmable FIR) is bypassed.

Bypass Filter 1. If this bit is 0, Filter 1 is bypassed. This should only occur when the user requires unfiltered

modulator data to be output.
2 to 0 DEC [2:0]

Decimation Rate. These bits set the decimation rate of Filter 2. A

ll 0s implies that the filter is bypassed. A value
of 1 corresponds to 2× decimation, a value of 2 corresponds to 4× decimation, and so on, up to the maximum
value of 5, corresponding to 32× decimation.

1

Bit 15 to Bit 9 are self-clearing bits.

2

Only one of the bits from Bit 14 to Bit 11 can be set in any write operation because it determines the contents of the next read operation.

CONTROL REGISTER 2—ADDRESS 0x0002

Default Value After

Recommended register setting for power-up and normal operation using clock divide-by-2 (

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

0

Table 16. Bit Descriptions of Control Register 2

Bit Mnemonic Description

5 CDIV

3 PD Power Down. Setting this bit powers down the AD7760, reducing the power consumption to 6.35 mW.
2 LPWR

1 1 Write 1 to this bit.
0 D1PD Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier.

RESET

: 0x009B

CDIV

= 0) mode: 0x0002

0

0

0

0

0

0

0

0

CDIV

0

PD

LPWR 1

Clock Divider Bit. This sets the divide ratio of the MCLK signal to produce the internal ICLK. Setting CDIV = 0 divides the
MCLK by 2. If CDIV

Low Power. If this bit is set, the AD7760 is operating in a lo

= 1, the ICLK frequency is equal to the MCLK.

w power mode. The power consumption is reduced for a 6 dB

reduction in noise performance.

LSB

D1PD

Rev. A | Page 33 of 36

AD7760

www.BDTIC.com/ADI

STATUS REGISTER (READ ONLY)

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

PART 1 PART 0 DIE 2 DIE 1 DIE 0 0

LPWR OVR DL_OK FILTOK UFILT

BYP F3

BYP F1

Table 17. Bit Descriptions of Status Register

Bit Mnemonic Comment

15, 14 PART [1:0] Part Number. These bits are constant for the AD7760.
13 to 11 DIE [2:0] Die Number. These bits reflect the current AD7760 die number for identification purposes within a system.
10 0 This bit is set to 0.
9 LPWR Low Power. If the AD7760 is operating in low power mode, this bit is set to 1.
8 OVR If the current analog input exceeds the current overrange threshold, this bit is set.
7 DL_OK

6 FILTOK

5 UFILT If a user-defined filter is in use, this bit is set.
4

3
2 to 0 DEC [2:0] Decimation Rate. These bits correspond to the bits set in Control Register 1.

BYP F3
BYP F1

When downloading a user filter to the AD7760,
downloaded following the coefficients. If these checksums agree, this bit is set.

When a user-defined filter is in use, a checksum is generated when the filter c
generated checksum is compared to the one downloaded. If they match, this bit is set.

Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set.
Bypass Filter 1. If Filter 1 is bypassed by setting the relevant bit in Control Register 1, this bit is also set.

a checksum is generated. This checksum is compared to the one

oefficients pass through the filter. This

DEC2 DEC1 DEC0

OFFSET REGISTER—ADDRESS 0x0003

Non-bit-mapped, Default Value 0x0000

The offset register uses twos complement notation and is scaled
such that 0x7FFF (maximum positive value) and 0x8000 (max­imum negative value) correspond to an offset of +0.78125% and

−0.78125%, respectively. Offset correction is applied after any
gain correction. Using the default gain value of 1.25 and assuming
a reference voltage of 4.096 V, the offset correction range is
approximately ±25 mV.

GAIN REGISTER—ADDRESS 0x0004

Non-bit-mapped, Default Value 0xA000

The gain register is scaled such that 0x8000 corresponds to a
gain of 1.0. The default value of this register is 1.25 (0xA000).
This results in a full-scale digital output when the input is at
80% of V
±80% of V

, tying in with the maximum analog input range of

REF

p-p.

REF

OVERRANGE REGISTER—ADDRESS 0x0005

Non-bit-mapped, Default Value 0xCCCC

The overrange register value is compared with the output of
the first decimation filter to obtain an overload indication with
minimum propagation delay. This is prior to any gain scaling
or offset adjustment. The default value is 0xCCCC, which
corresponds to 80% of V
input voltage). Assuming V
the input voltage exceeds approximately 6.55 V p-p differential.
Once the overrange bit is set, the DVALID bit in the status bits
of the AD7760 ouptut is set to zero, providing another indication
that an input overrange has occurred. Note that the overrange
bit is set immediately if the analog input voltage exceeds 100% of
V

for more than four consecutive samples at the modulator rate.

REF

(the maximum permitted analog

REF

= 4.096 V, the bit is then set when

REF

Rev. A | Page 34 of 36

AD7760

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

12.20

1.20

0.75
MAX

0.60

0.45

1

SEATING
PLANE

VIEW A

0° MIN

0.08 MAX
COPLANARIT Y

0.20

0.09

7°

3.5°
0°

16

VIEW A

COMPLIANT TO JE DEC STANDARDS MS-026-ACD-HD

1.05

1.00

0.95

0.15

0.05

ROTATED 90° CCW

Figure 59. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7760BSVZ
AD7760BSVZ-REEL
EVAL-AD7760EB Evaluation Board

1

Z = Pb-free part.

1

−40°C to +85°C 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-64-2

1

−40°C to +85°C 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-64-2

12.00 SQ

11.8 0

64

PIN 1

TOP VIEW

(PINS DOWN)

17

(SV

49

48

33

32

-64-2)

Dimensions shown in millimeters

10.20

10.00 SQ

9.80

49

48

33

32

0.50

BSC

LEAD PITCH

EXPOSED

PAD

BOTTOM VIEW

(PINS UP)

0.38

0.32

0.22

64

1

6.00

BSC SQ

16

17

Rev. A | Page 35 of 36

AD7760

www.BDTIC.com/ADI

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04975-0-8/06(A)

Rev. A | Page 36 of 36