Datasheet AD7755 Datasheet (Analog Devices)

Energy Metering IC

a

FEATURES
High Accuracy, Supports 50 Hz/60 Hz IEC 687/1036

Less than 0.1% Error Over a Dynamic Range of
500 to 1

The AD7755 Supplies

Frequency Outputs F1 and F2

The High Frequency Output CF Is Intended for

Calibration and Supplies

The Logic Output REVP Can Be Used to Indicate a

Potential Miswiring or Negative Power

Direct Drive for Electromechanical Counters and

Two Phase Stepper Motors (F1 and F2)

A PGA in the Current Channel Allows the Use of Small

Values of

Shunt

Proprietary ADCs and DSP Provide High Accuracy over

Large Variations in Environmental Conditions and

Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V 6 8% (30 ppm/8C Typical)

with External Overdrive Capability
Single 5 V Supply, Low Power (15 mW Typical)
Low Cost CMOS Process

Average Real Power

Instantaneous Real Power

and

Burden

Resistance

on the

with Pulse Output

AD7755*

GENERAL DESCRIPTION

The AD7755 is a high accuracy electrical energy measurement
IC. The part specifications surpass the accuracy requirements
as quoted in the IEC1036 standard. See Analog Devices’
Application Note AN-559 for a description of an IEC1036
watt-hour meter reference design.

The only analog circuitry used in the AD7755 is in the ADCs
and reference circuit. All other signal processing (e.g., multipli­cation and filtering) is carried out in the digital domain. This
approach provides superior stability and accuracy over extremes
in environmental conditions and over time.

The AD7755 supplies average real power information on the
low frequency outputs F1 and F2. These logic outputs may be
used to directly drive an electromechanical counter or interface
to an MCU. The CF logic output gives instantaneous real power
information. This output is intended to be used for calibration
purposes, or interfacing to an MCU.

The AD7755 includes a power supply monitoring circuit on the
AV

supply pin. The AD7755 will remain in a reset condition

DD

until the supply voltage on AV
below 4 V, the AD7755 will also be reset and no pulses will be
issued on F1, F2 and CF.

Internal phase matching circuitry ensures that the voltage and
current channels are phase matched whether the HPF in Chan­nel 1 is on or off. An internal no-load threshold ensures that the
AD7755 does not exhibit any creep when there is no load.

The AD7755 is available in 24-lead DIP and SSOP packages.

reaches 4 V. If the supply falls

DD

FUNCTIONAL BLOCK DIAGRAM

G0

G1

V1P

V1N

V2P

V2N

*U.S. Patents 5,745,323, 5,760,617, 5,862,069, 5,872,469.

PGA

x1, x2, x8, x16

2.5V

REFERENCE

AV

AGND

DD

POWER

SUPPLY MONITOR

...

ADC

...

ADC

4k⍀

REF

IN/OUT

110101

11011001

CLKIN

AD7755

CORRECTION

...

...

CLKOUT

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

DV

AC/DC

PHASE

⌽

HPF

MULTIPLIER

DIGITAL-TO-FREQUENCY

CONVERTER

S0

SCF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

S1

DD

SIGNAL

PROCESSING

BLOCK

LPF

REVP

CF

DGND

F1

RESET

F2

(AVDD = DVDD = 5 V ⴞ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.58 MHz,
T

to T

AD7755–SPECIFICATIONS

MIN

Parameter A Version B Version Unit Test Conditions/Comments

ACCURACY

1, 2

Measurement Error1 on Channel 1 Channel 2 with Full-Scale Signal (±660 mV), 25°C

Gain = 1 0.1 0.1 % Reading typ Over a Dynamic Range 500 to 1
Gain = 2 0.1 0.1 % Reading typ Over a Dynamic Range 500 to 1
Gain = 8 0.1 0.1 % Reading typ Over a Dynamic Range 500 to 1
Gain = 16 0.1 0.1 % Reading typ Over a Dynamic Range 500 to 1

Phase Error

1

Between Channels Line Frequency = 45 Hz to 65 Hz

V1 Phase Lead 37°
(PF = 0.8 Capacitive) ±0.1 ±0.1 Degrees(°) max AC/DC = 0 and AC/DC = 1
V1 Phase Lag 60°
(PF = 0.5 Inductive) ±0.1 ±0.1 Degrees(°) max AC/DC = 0 and AC/DC = 1

AC Power Supply Rejection

1

Output Frequency Variation (CF) 0.2 0.2 % Reading typ V1 = 100 mV rms, V2 = 100 mV rms, @ 50 Hz

DC Power Supply Rejection

1

Output Frequency Variation (CF) ±0.3 ±0.3 % Reading typ V1 = 100 mV rms, V2 = 100 mV rms,

ANALOG INPUTS See Analog Inputs Section

Maximum Signal Levels ± 1 ±1 V max V1P, V1N, V2N and V2P to AGND
Input Impedance (DC) 390 390 kΩ min CLKIN = 3.58 MHz
Bandwidth (–3 dB) 14 14 kHz typ CLKIN/256, CLKIN = 3.58 MHz
ADC Offset Error
Gain Error

Gain Error Match

1, 2

1

1

±25 ±25 mV max Gain = 1, See Terminology and Performance Graphs
±7 ± 7 % Ideal typ External 2.5 V Reference, Gain = 1

±0.2 ±0.2 % Ideal typ External 2.5 V Reference

REFERENCE INPUT

REF

Input Voltage Range 2.7 2.7 V max 2.5 V + 8%

IN/OUT

2.3 2.3 V min 2.5 V – 8%

Input Impedance 3.2 3.2 kΩ min
Input Capacitance 10 10 pF max

ON-CHIP REFERENCE Nominal 2.5 V

Reference Error ±200 ±200 mV max
Temperature Coefficient ±30 ± 30 ppm/°C typ

±60 ppm/°C max

CLKIN Note All Specifications for CLKIN of 3.58 MHz

Input Clock Frequency 4 4 MHz max

1 1 MHz min

LOGIC INPUTS

3

SCF, S0, S1, AC/DC,
RESET, G0 and G1

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

LOGIC OUTPUTS

INH

INL

IN

IN

3

2.4 2.4 V min DVDD = 5 V ± 5%

0.8 0.8 V max DVDD = 5 V ± 5%
±3 ± 3 µA max Typically 10 nA, VIN = 0 V to DV
10 10 pF max

F1 and F2

Output High Voltage, V

OH

4.5 4.5 V min DV

Output Low Voltage, V

OL

0.5 0.5 V max DV

CF and REVP

Output High Voltage, V

OH

4 4 V min DV

Output Low Voltage, V

OL

0.5 0.5 V max DVDD = 5 V

= –40ⴗC to +85ⴗC)

MAX

AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0

Ripple on AV

of 200 mV rms @ 100 Hz

DD

AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0

AVDD = DVDD = 5 V ± 250 mV

V1 = 470 mV dc, V2 = 660 mV dc

DD

I

= 10 mA

SOURCE

= 5 V

DD

I

= 10 mA

SINK

= 5 V

DD

I

= 5 mA

SOURCE

= 5 V

DD

I

= 5 mA

SINK

–2–

REV. B

Parameter A Version B Version Unit Test Conditions/Comments

POWER SUPPLY For Specified Performance

AV

DD

4.75 4.75 V min 5 V – 5%

5.25 5.25 V max 5 V + 5%

DV

DD

4.75 4.75 V min 5 V – 5%

5.25 5.25 V max 5 V + 5%

AI

DD

DI

DD

NOTES

1

See Terminology section for explanation of specifications.

2

See Plots in Typical Performance Graphs.

3

Sample tested during initial release and after any redesign or process change that may affect this parameter.

Specifications subject to change without notice.

3 3 mA max Typically 2 mA

2.5 2.5 mA max Typically 1.5 mA

AD7755

(AVDD = DVDD = 5 V ⴞ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.58 MHz, T

1, 2

T

TIMING CHARACTERISTICS

= –40ⴗC to +85ⴗC)

MAX

Parameter A, B Versions Unit Test Conditions/Comments

3

t

1

t

2

t

3

3, 4

t

4

t

5

t

6

NOTES

1

Sample tested during initial release and after any redesign or process change that may affect this parameter.

2

See Figure 1.

3

The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs Section.

4

The CF pulse is always 18 µs in the high frequency mode. See Frequency Outputs section and Table IV.

Specifications subject to change without notice.

275 ms F1 and F2 Pulsewidth (Logic Low)
See Table III sec Output Pulse Period. See Transfer Function Section
1/2 t

2

sec Time Between F1 Falling Edge and F2 Falling Edge
90 ms CF Pulsewidth (Logic High)
See Table IV sec CF Pulse Period. See Transfer Function Section
CLKIN/4 sec Minimum Time Between F1 and F2 Pulse

t

1

F1

F2

t

CF

.t

6

.t

2

.t

3

.t

4

5

MIN

to

REV. B

Figure 1. Timing Diagram for Frequency Outputs

ORDERING GUIDE

Model Package Description Package Options

AD7755AAN Plastic DIP N-24
AD7755AARS Shrink Small Outline Package RS-24
AD7755ABRS Shrink Small Outline Package RS-24
EVAL-AD7755EB AD7755 Evaluation Board
AD7755AAN-REF AD7755 Reference Design PCB (See AN-559)

–3–

AD7755

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

DD

DV

to AVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DD

Analog Input Voltage to AGND

V1P, V1N, V2P and V2N . . . . . . . . . . . . . . . –6 V to +6 V

Reference Input Voltage to AGND . . –0.3 V to AV
Digital Input Voltage to DGND . . . –0.3 V to DV
Digital Output Voltage to DGND . . –0.3 V to DV

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

24-Lead Plastic DIP, Power Dissipation . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W

θ

JA

Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . . 260°C

24-Lead SSOP, Power Dissipation . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 112°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7755 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

TERMINOLOGY

MEASUREMENT ERROR

The error associated with the energy measurement made by the
AD7755 is defined by the following formula:

Percentage Error

PHASE ERROR BETWEEN CHANNELS

Energy Registered by the AD7755 – True Energy

=×

True Energy

100%

The HPF (High Pass Filter) in Channel 1 has a phase lead
response. To offset this phase response and equalize the phase
response between channels, a phase correction network is also
placed in Channel 1. The phase correction network matches the
phase to within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2°
over a range 40 Hz to 1 kHz. See Figures 22 and 23.

POWER SUPPLY REJECTION

This quantifies the AD7755 measurement error as a percentage
of reading when the power supplies are varied.

For the ac PSR measurement a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading obtained under the same
input signal levels. Any error introduced is expressed as a per­centage of reading—see Measurement Error definition.

For the dc PSR measurement a reading at nominal supplies

ADC OFFSET ERROR

This refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND, the ADCs still see a small dc signal (offset). The offset
decreases with increasing gain in channel V1. This specification
is measured at a gain of 1. At a gain of 16, the dc offset is typi­cally less than 1 mV. However, when the HPF is switched on,
the offset is removed from the current channel and the power
calculation is not affected by this offset.

GAIN ERROR

The gain error of the AD7755 is defined as the difference between
the measured output frequency (minus the offset) and the ideal
output frequency. It is measured with a gain of 1 in channel V1.
The difference is expressed as a percentage of the ideal frequency.
The ideal frequency is obtained from the AD7755 transfer func­tion—see Transfer Function section.

GAIN ERROR MATCH

The gain error match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 and a
gain of 2, 8, or 16. It is expressed as a percentage of the out­put frequency obtained under a gain of 1. This gives the gain
error observed when the gain selection is changed from 1 to 2,
8 or 16.

(5 V) is taken. The supplies are then varied ±5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.

–4–

REV. B

AD7755

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1DV

DD

2 AC/DC High Pass Filter Select. This logic input is used to enable the HPF in Channel 1 (the current channel).

3AV

DD

4, 19 NC No Connect.
5, 6 V1P, V1N Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs with

7, 8 V2N, V2P Negative and Positive Inputs for Channel 2 (Voltage Channel). These inputs provide a fully differential

9 RESET Reset Pin for the AD7755. A logic low on this pin will hold the ADCs and digital circuitry in a reset

10 REF

IN/OUT

11 AGND This provides the ground reference for the analog circuitry in the AD7755, i.e., ADCs and reference.

12 SCF Select Calibration Frequency. This logic input is used to select the frequency on the calibration output

13, 14 S1, S0 These logic inputs are used to select one of four possible frequencies for the digital-to-frequency con-

15, 16 G1, G0 These logic inputs are used to select one of four possible gains for Channel 1, i.e., V1. The possible

17 CLKIN An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can

18 CLKOUT A crystal can be connected across this pin and CLKIN as described above to provide a clock source

20 REVP This logic output will go logic high when negative power is detected, i.e., when the phase angle between

Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the AD7755.
The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be
decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.

A logic one on this pin enables the HPF. The associated phase response of this filter has been inter­nally compensated over a frequency range of 45 Hz to 1 kHz. The HPF filter should be enabled in
power metering applications.

Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the AD7755.
The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to
minimize power supply ripple and noise at this pin by the use of proper decoupling. This pin should
be decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.

a maximum differential signal level of ±470 mV for specified operation. Channel 1 also has a PGA and
the gain selections are outlined in Table I. The maximum signal level at these pins is ±1 V with respect
to AGND. Both inputs have internal ESD protection circuitry and in addition an overvoltage of ±6V
can be sustained on these inputs without risk of permanent damage.

input pair. The maximum differential input voltage is ±660 mV for specified operation. The maximum
signal level at these pins is ±1 V with respect to AGND. Both inputs have internal ESD protection
circuitry and an overvoltage of ±6 V can also be sustained on these inputs without risk of permanent
damage.

condition. Bringing this pin logic low will clear the AD7755 internal registers.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value

of 2.5 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source may
also be connected at this pin. In either case this pin should be decoupled to AGND with a 1 µF
ceramic capacitor and 100 nF ceramic capacitor.

This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground
reference for all analog circuitry, e.g., antialiasing filters, current and voltage transducers, etc. For
good noise suppression the analog ground plane should only connected to the digital ground plane at
one point. A star ground configuration will help to keep noisy digital currents away from the analog
circuits.

CF. Table IV shows how the calibration frequencies are selected.

version. This offers the designer greater flexibility when designing the energy meter. See Selecting a
Frequency for an Energy Meter Application section.

gains are 1, 2, 8 and 16. See Analog Input section.

be connected across CLKIN and CLKOUT to provide a clock source for the AD7755. The clock
frequency for specified operation is 3.579545 MHz. Crystal load capacitance of between 22 pF and
33 pF (ceramic) should be used with the gate oscillator circuit.

for the AD7755. The CLKOUT pin can drive one CMOS load when an external clock is supplied at
CLKIN or by the gate oscillator circuit.

the voltage and current signals is greater that 90°. This output is not latched and will be reset when
positive power is once again detected. The output will go high or low at the same time as a pulse is
issued on CF.

REV. B

–5–

AD7755

Pin No. Mnemonic Description

21 DGND This provides the ground reference for the digital circuitry in the AD7755, i.e., multiplier, filters and

digital-to-frequency converter. This pin should be tied to the analog ground plane of the PCB. The
digital ground plane is the ground reference for all digital circuitry, e.g., counters (mechanical and
digital), MCUs and indicator LEDs. For good noise suppression the analog ground plane should only
be connected to the digital ground plane at one point only, e.g., a star ground.

22 CF Calibration Frequency Logic Output. The CF logic output gives instantaneous real power informa-

tion. This output is intended to be used for calibration purposes. Also see SCF pin description.

23, 24 F2, F1 Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs

can be used to directly drive electromechanical counters and two phase stepper motors. See Transfer
Function section.

PIN CONFIGURATION
DIP and SSOP Packages

REF

DV

AC/DC

AV

NC

V1P

V1N

V2N

V2P

RESET

IN/OUT

AGND

SCF

DD

DD

1

2

3

4

5

AD7755

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

NC = NO CONNECT

24

23

22

21

20

19

18

17

16

15

14

13

F1

F2

CF

DGND

REVP

NC

CLKOUT

CLKIN

G0

G1

S0

S1

–6–

REV. B

Typical Performance Characteristics–

Amps

–0.5

0.01 0.1

% ERROR

–0.4

–0.3

–0.2

–0.1

0.0

0.1

0.2

0.3

0.4

0.5

1

10

100

+25ⴗC

+85ⴗC

–40ⴗC

PF = 1
GAIN = 16
ON-CHIP REFERENCE

Amps

–0.6

0.01 0.1

% ERROR

–0.4

–0.2

0.0

0.2

0.4

0.6

1

10

100

–40ⴗC PF = 0.5

+25ⴗC PF = 1

+25ⴗC PF = 0.5

+85ⴗC PF = 0.5

PF = 0.5
GAIN = 2
ON-CHIP REFERENCE

0.5

0.4

0.3

0.2

0.1

0.0

% ERROR

–0.1

–0.2

–0.3

PF = 1
GAIN = 1

–0.4

ON-CHIP REFERENCE

–0.5

0.01 0.1

Figure 2. Error as a % of Reading (Gain = 1)

–40ⴗC

+25ⴗC

+85ⴗC

1

Amps

10

AD7755

100

Figure 5. Error as a % of Reading (Gain = 16)

REV. B

0.5

0.4

0.3

0.2

0.1

0.0

% ERROR

–0.1

–0.2

–0.3

–0.4

–0.5

0.01 0.1

PF = 1
GAIN = 2
ON-CHIP REFERENCE

–40ⴗC

+25ⴗC

+85ⴗC

1

Amps

10

Figure 3. Error as a % of Reading (Gain = 2)

0.6

0.5

0.4

0.3
PF = 1
GAIN = 8

0.2
ON-CHIP REFERENCE

0.1

% ERROR

0.0

–0.1

–0.2

–0.3

–0.4

0.01 0.1

–40ⴗC

+25ⴗC

+85ⴗC

1

Amps

10

Figure 4. Error as a % of Reading (Gain = 8)

100

100

–7–

0.6

0.4

0.2

0.0

% ERROR

–0.2

–0.4

–0.6

0.01 0.1

–40ⴗC PF = 0.5

+25ⴗC PF = 1

+25ⴗC PF = 0.5

+85ⴗC PF = 0.5

PF = 0.5
GAIN = 1
ON-CHIP REFERENCE

1

Amps

10

Figure 6. Error as a % of Reading (Gain = 1)

Figure 7. Error as a % of Reading (Gain = 2)

100

AD7755

0.8

0.6

0.4

0.2

0.0

% ERROR

–0.2

–0.4

–0.6

–0.8

0.01 0.1

–40ⴗC PF = 0.5

+25ⴗC PF = 1

+25ⴗC PF = 0.5

+85ⴗC PF = 0.5

PF = 0.5
GAIN = 8
ON-CHIP REFERENCE

1

Amps

10

Figure 8. Error as a % of Reading (Gain = 8)

0.4

0.2

0.0

–0.2

–0.4

% ERROR

–0.6

–40ⴗC PF = 0.5

+25ⴗC PF = 1

+25ⴗC PF = 0.5

+85ⴗC PF = 0.5

100

0.4

PF = 1
GAIN = 16

0.3
EXTERNAL REFERENCE

0.2

0.1

0.0

% ERROR

–0.1

–0.2

–0.3

–0.4

0.01 0.1

+85ⴗC

1

Amps

–40ⴗC

+25ⴗC

10

100

Figure 11. Error as a % of Reading over Temperature with
an External Reference (Gain = 16)

0.8

0.6

0.4

0.2

0.0

% ERROR

–0.2

PF = 1

PF = 0.5

PF = 0.5

–0.8

GAIN = 16
ON-CHIP REFERENCE

–1.0

0.01 0.1

1

Amps

10

100

Figure 9. Error as a % of Reading (Gain = 16)

0.4

PF = 1
GAIN = 2

0.3
EXTERNAL REFERENCE

0.2

0.1

0.0

% ERROR

–0.1

–0.2

–0.3

–0.4

0.01 0.1

+25ⴗC

1

Amps

–40ⴗC

+85ⴗC

10

100

Figure 10. Error as a % of Reading over Temperature with
an External Reference (Gain = 2)

–0.4

–0.6

45 50 55 60 65 70 75

FREQUENCY – Hz

Figure 12. Error as a % of Reading over Frequency

V

DD

10␮F

40A TO

40mA

500␮⍀

1.5m⍀
10m⍀

1M⍀

1k⍀

220V

10␮F

NC = NO CONNECT

1k⍀

33nF

1k⍀

33nF

33nF

1k⍀

33nF

100nF

100nF

AVDD AC/DC AVDD

NC

V1P

AD7755

V1N

V2N

V2P

REF

IN/OUT

RESET AGND DGND

V

DD

U1

CLKOUT

REVP

CLKIN

SCF

100nF

F1

F2

CF

NC

G0

G1

S0

S1

10␮F

U3

33pF

Y1

33pF

3.58MHz

GAIN
SELECT

10nF 10nF 10nF

Figure 13. Test Circuit for Performance Curves

PS2501-1

V

DD

10k⍀

K7

K8

–8–

REV. B

16

FREQUENCY – Hz

–15

PHASE – Degrees

5

0

10

15

20

25

30

–9 –33 915

GAIN = 8
TEMPERATURE = +25ⴗC

DISTRIBUTION CHARACTERISTICS
NUMBER POINTS: 101
MINIMUM: –2.48959
MAXIMUM: 5.81126
MEAN: –1.26847
STD. DEV: 1.57404

DISTRIBUTION CHARACTERISTICS
NUMBER POINTS: 101

14

MINIMUM: –9.78871
MAXIMUM: 7.2939
MEAN: –1.73203

12

STD. DEV: 3.61157

10

8

6

PHASE – Degrees

4

2

0

–15

–9 –33 915

GAIN = 1
TEMPERATURE = +25ⴗC

FREQUENCY – Hz

AD7755

Figure 14. Channel 1 Offset Distribution (Gain = 1)

18

16

14

12

10

8

PHASE – Degrees

6

4

2

0

–15

Figure 15. Channel 1 Offset Distribution (Gain = 2)

0.5

0.4

0.3

0.2

0.1

–0.1

% ERROR

–0.2

–0.3

–0.4

–0.5

–0.6

0.01 1000.1

Figure 16. PSR with Internal Reference (Gain = 16)

DISTRIBUTION
CHARACTERISTICS
NUMBER POINTS: 101
MINIMUM: –5.61779
MAXIMUM: 6.40821
MEAN: –0.01746
STD. DEV: 2.35129

–9 –33 915

0

GAIN = 2
TEMPERATURE = +25ⴗC

FREQUENCY – Hz

5.25V

5V

4.75V

110

Amps

Figure 17. Channel 1 Offset Distribution (Gain = 8)

35

DISTRIBUTION CHARACTERISTICS
NUMBER POINTS: 101
MINIMUM: –1.96823

30

MAXIMUM: 5.71177
MEAN: –1.48279
STD. DEV: 1.47802

25

20

15

PHASE – Degrees

10

5

0

–15

–9 –33 915

FREQUENCY – Hz

GAIN = 16
TEMPERATURE = +25ⴗC

Figure 18. Channel 1 Offset Distribution (Gain = 16)

0.5

0.4

0.3

0.2

0.1

0

–0.1

% ERROR

–0.2

–0.3

–0.4

–0.5

–0.6

0.01 1000.1

5.25V

5V

4.75V

110

Amps

Figure 19. PSR with External Reference (Gain = 16)

REV. B

–9–

AD7755

THEORY OF OPERATION

The two ADCs digitize the voltage signals from the current and
voltage transducers. These ADCs are 16-bit second order
sigma-delta with an oversampling rate of 900 kHz. This analog
input structure greatly simplifies transducer interfacing by
providing a wide dynamic range for direct connection to the
transducer and also simplifying the antialiasing filter design. A
programmable gain stage in the current channel further facili­tates easy transducer interfacing. A high pass filter in the current
channel removes any dc component from the current signal.
This eliminates any inaccuracies in the real power calculation
due to offsets in the voltage or current signals—see HPF and
Offset Effects section.

The real power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals. In order
to extract the real power component (i.e., the dc component),
the instantaneous power signal is low-pass filtered. Figure 20
illustrates the instantaneous real power signal and shows how the
real power information can be extracted by low-pass filtering the
instantaneous power signal. This scheme correctly calculates real
power for nonsinusoidal current and voltage waveforms at all
power factors. All signal processing is carried out in the digital
domain for superior stability over temperature and time.

DIGITAL-TO­FREQUENCY

⌺

DIGITAL-TO­FREQUENCY

⌺

POWER SIGNAL

2

F1
F2

CF

CH1

CH2

VⴛI

Vⴛ I

HPF

PGA

2

TIME

ADC

MULTIPLIER

ADC

INSTANTANEOUS

POWER SIGNAL – p(t)

p(t) = i(t)ⴛv(t)
WHERE:

v(t) = Vⴛcos(␻t)
i(t) = Iⴛcos(␻t)

VⴛI

p(t) =

{

1+cos ( 2␻t)}

2

LPF

INSTANTANEOUS REAL

VⴛI

Figure 20. Signal Processing Block Diagram

The low frequency output of the AD7755 is generated by accu­mulating this real power information. This low frequency inher­ently means a long accumulation time between output pulses.
The output frequency is therefore proportional to the average
real power. This average real power information can, in turn, be
accumulated (e.g., by a counter) to generate real energy infor­mation. Because of its high output frequency and hence shorter
integration time, the CF output is proportional to the instanta­neous real power. This is useful for system calibration purposes
that would take place under steady load conditions.

Power Factor Considerations

The method used to extract the real power information from the
instantaneous power signal (i.e., by low-pass filtering) is still
valid even when the voltage and current signals are not in phase.
Figure 21 displays the unity power factor condition and a DPF
(Displacement Power Factor) = 0.5, i.e., current signal lagging

the voltage by 60°. If we assume the voltage and current wave­forms are sinusoidal, the real power component of the instanta­neous power signal (i.e., the dc term) is given by








VI×




2

× cos (60°).

This is the correct real power calculation.

INSTANTANEOUS
REAL POWER SIGNAL

INSTANTANEOUS
REAL POWER SIGNAL

CURRENT

VⴛI

2

VⴛI

ⴛcos(60ⴗ)

2

0V

0V

INSTANTANEOUS
POWER SIGNAL

CURRENT

VOLTAGE

INSTANTANEOUS
POWER SIGNAL

VOLTAGE

60ⴗ

Figure 21. DC Component of Instantaneous Power Signal
Conveys Real Power Information PF < 1

Nonsinusoidal Voltage and Current

The real power calculation method also holds true for nonsinu­soidal current and voltage waveforms. All voltage and current
waveforms in practical applications will have some harmonic
content. Using the Fourier Transform, instantaneous voltage
and current waveforms can be expressed in terms of their har­monic content.

∞

vt V Vh h t h

( ) sin( )=+× × +

2

O

h

∑

≠

0

ωα

(1)

where:

v(t) is the instantaneous voltage
V

is the average value

O

Vh is the rms value of voltage harmonic h

and
␣h is the phase angle of the voltage harmonic.

∞

it I Ih h t h

( ) sin( )=+× × +

2

O

∑

h

≠

0

ωβ

(2)

where:

i(t) is the instantaneous current
I

is the dc component

O

Ih is the rms value of current harmonic h

and
␤h is the phase angle of the current harmonic.

–10–

REV. B

AD7755

Using Equations 1 and 2, the real power P can be expressed in
terms of its fundamental real power (P
power (P

).

H

PPP

=+

) and harmonic real

1

H

1

where:

PVI

=×=cos–φ

111 1

φαβ

1

and

PVhIhh

=×

H

hhh

=

φαβ

1

∑

h

1

∝

cos–φ

≠

1

(3)

(4)

As can be seen from Equation 4 above, a harmonic real power
component is generated for every harmonic, provided that har­monic is present in both the voltage and current waveforms.
The power factor calculation has previously been shown to be
accurate in the case of a pure sinusoid, therefore the harmonic
real power must also correctly account for power factor since it
is made up of a series of pure sinusoids.

Note that the input bandwidth of the analog inputs is 14 kHz
with a master clock frequency of 3.5795 MHz.

ANALOG INPUTS
Channel V1 (Current Channel )

The voltage output from the current transducer is connected to
the AD7755 here. Channel V1 is a fully differential voltage
input. V1P is the positive input with respect to V1N.

The maximum peak differential signal on Channel 1 should be
less than ±470 mV (330 mV rms for a pure sinusoidal signal) for
specified operation. Note that Channel 1 has a programmable
gain amplifier (PGA) with user selectable gain of 1, 2, 8 or 16
(see Table I). These gains facilitate easy transducer interfacing.

V1

+470mV

V

–470mV

DIFFERENTIAL INPUT

CM

ⴞ470mV MAX PEAK

COMMON-MODE

ⴞ100mV MAX

AGND

V1P

V1

V1N

V

CM

Figure 22. Maximum Signal Levels, Channel 1, Gain = 1

The diagram in Figure 22 illustrates the maximum signal levels
on V1P and V1N. The maximum differential voltage is ±470 mV
divided by the gain selection. The differential voltage signal on
the inputs must be referenced to a common mode, e.g. AGND.
The maximum common mode signal is ±100 mV as shown in
Figure 22.

Table I. Gain Selection for Channel 1

Maximum

G1 G0 Gain Differential Signal

001 ±470 mV
012 ±235 mV
108 ±60 mV
1116 ± 30 mV

Channel V2 (Voltage Channel )

The output of the line voltage transducer is connected to the
AD7755 at this analog input. Channel V2 is a fully differential
voltage input. The maximum peak differential signal on Chan­nel 2 is ±660 mV. Figure 23 illustrates the maximum signal
levels that can be connected to the AD7755 Channel 2.

V2

+660mV

V

–660mV

DIFFERENTIAL INPUT

CM

ⴞ660mV MAX PEAK

COMMON-MODE

ⴞ100mV MAX

AGND

V2P

V2

V2N

V

CM

Figure 23. Maximum Signal Levels, Channel 2

Channel 2 must be driven from a common-mode voltage, i.e.,
the differential voltage signal on the input must be referenced to
a common mode (usually AGND). The analog inputs of the
AD7755 can be driven with common-mode voltages of up to
100 mV with respect to AGND. However best results are
achieved using a common mode equal to AGND.

Typical Connection Diagrams

Figure 24 shows a typical connection diagram for Channel V1.
A CT (current transformer) is the current transducer selected for
this example. Notice the common-mode voltage for Channel 1
is AGND and is derived by center tapping the burden resistor
to AGND. This provides the complementary analog input sig­nals for V1P and V1N. The CT turns ratio and burden resistor
Rb are selected to give a peak differential voltage of ±470 mV/
Gain at maximum load.

Rb

Rf

ⴞ470mV

GAIN

Rf

CT

IP

AGND

NEUTRALPHASE

V1P

Cf

V1N

Cf

Figure 24. Typical Connection for Channel 1

REV. B

–11–

AD7755

Figure 25 shows two typical connections for Channel V2. The
first option uses a PT (potential transformer) to provide com­plete isolation from the mains voltage. In the second option the
AD7755 is biased around the neutral wire, and a resistor divider
is used to provide a voltage signal that is proportional to the line
voltage. Adjusting the ratio of Ra, Rb and VR is also a conve­nient way of carrying out a gain calibration on the meter.

CT

ⴞ660mV

AGND

NEUTRALPHASE

*

Rb

*

VR

*

*

Ra >> Rb + VR

*

Rb + VR = Rf

Cf

ⴞ660mV

Ra

NEUTRALPHASE

Rf

Rf

Rf

V2P

Cf

V2N

Cf

V2P

V2N

Cf

Figure 25. Typical Connections for Channel 2

POWER SUPPLY MONITOR

The AD7755 contains an on-chip power supply monitor. The
Analog Supply (AV

) is continuously monitored by the AD7755.

DD

If the supply is less than 4 V ± 5%, the AD7755 will be reset.
This is useful to ensure correct device start-up at power-up and
power-down. The power supply monitor has built in hysteresis
and filtering. This gives a high degree of immunity to false trig­gering due to noisy supplies.

As can be seen from Figure 26, the trigger level is nominally set
at 4 V. The tolerance on this trigger level is about ±5%. The
power supply and decoupling for the part should be such that
the ripple at AV

does not exceed 5 V ± 5% as specified for

DD

normal operation.

AV

DD

5V

4V

0V

TIME

HPF and Offset Effects

Figure 27 shows the effect of offsets on the real power calcula­tion. As can be seen, an offset on Channel 1 and Channel 2 will
contribute a dc component after multiplication. Since this dc
component is extracted by the LPF and used to generate the
real power information, the offsets will have contributed a con­stant error to the real power calculation. This problem is easily
avoided by enabling the HPF (i.e., pin AC/DC is set logic high)
in Channel 1. By removing the offset from at least one channel,
no error component can be generated at dc by the multiplica­tion. Error terms at cos(ωt) are removed by the LPF and the
digital-to-frequency conversion—see Digital-to-Frequency
Conversion section.

ωω

VtV ItI

cos cos

{}

VI

×

2

VI

+

+

()

VIVI tIV t

+×+×

OS OS OS OS

×

cos

×

2

ⴛ I

V

OS

V ⴛ I

×

OS OS

ω

2

t

()

OS

2

0

()

{}

DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION

IOS ⴛ V

V

OS

␻

FREQUENCY – RAD/S

+

cos cos

ⴛ I

=

ωω

+×

()

2␻

()

Figure 27. Effect of Channel Offset on the Real Power
Calculation

The HPF in Channel 1 has an associated phase response that is
compensated for on-chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
activated. Figures 28 and 29 show the phase error between
channels with the compensation network activated. The AD7755
is phase compensated up to 1 kHz as shown. This will ensure
correct active harmonic power calculation even at low power
factors.

INTERNAL

RESET

RESET

ACTIVE RESET

Figure 26. On-Chip Power Supply Monitor

–12–

REV. B

AD7755

0.30

0.25

0.20

0.15

0.10

0.05

PHASE – Degrees

0

–0.05

–0.10

0

200 300 400 500 600 700 800 900 1000

100

FREQUENCY – Hz

Figure 28. Phase Error Between Channels (0 Hz to 1 kHz)

0.30

0.25

0.20

0.15

0.10

Figure 30 shows the instantaneous real power signal at the output
of the CPF which still contains a significant amount of instanta­neous power information, i.e., cos (2ωt). This signal is then
passed to the digital-to-frequency converter where it is integrated
(accumulated) over time in order to produce an output fre­quency. This accumulation of the signal will suppress or average
out any non-dc components in the instantaneous real power
signal. The average value of a sinusoidal signal is zero. Hence
the frequency generated by the AD7755 is proportional to the
average real power. Figure 30 shows the digital-to-frequency
conversion for steady load conditions, i.e., constant voltage and
current.

F1

DIGITAL-TO-

MULTIPLIER

V ⴛ I

2

V

LPF

I

LPF TO EXTRACT

REAL POWER

(DC TERM)

ATTENUATED BY LPF

cos(2␻t)

FREQUENCY

⌺

DIGITAL-TO-

FREQUENCY

⌺

F1
F2

CF

FREQUENCY

TIME

FOUT

FREQUENCY

TIME

0.05

PHASE – Degrees

0

–0.05

–0.10

40

45 50 55 60 65 70

FREQUENCY – Hz

Figure 29. Phase Error Between Channels (40 Hz to 70 Hz)

DIGITAL-TO-FREQUENCY CONVERSION

As previously described, the digital output of the low-pass filter
after multiplication contains the real power information. How­ever since this LPF is not an ideal “brick wall” filter implemen­tation, the output signal also contains attenuated components
at the line frequency and its harmonics, i.e., cos(hωt) where
h = 1, 2, 3, . . . etc.

The magnitude response of the filter is given by:

|()|

Hf

=

(/. )

fHz

+1189

(5)

For a line frequency of 50 Hz this would give an attenuation of
the 2ω (100 Hz) component of approximately –22 dBs. The
dominating harmonic will be at twice the line frequency, i.e.,
cos (2ωt) and this is due to the instantaneous power signal.

␻

0

INSTANTANEOUS REAL POWER SIGNAL

(FREQUENCY DOMAIN)

2␻

FREQUENCY – RAD/S

Figure 30. Real Power-to-Frequency Conversion

As can be seen in the diagram, the frequency output CF is seen
to vary over time, even under steady load conditions. This fre­quency variation is primarily due to the cos (2 ωt) component in
the instantaneous real power signal. The output frequency on
CF can be up to 2048 times higher than the frequency on F1
and F2. This higher output frequency is generated by accumu­lating the instantaneous real power signal over a much shorter
time while converting it to a frequency. This shorter accumula­tion period means less averaging of the cos (2 ωt) component.
As a consequence, some of this instantaneous power signal passes
through the digital-to-frequency conversion. This will not be a
problem in the application. Where CF is used for calibration
purposes, the frequency should be averaged by the frequency
counter. This will remove any ripple. If CF is being used to
measure energy, e.g., in a microprocessor-based application, the
CF output should also be averaged to calculate power. Because
the outputs F1 and F2 operate at a much lower frequency, a lot
more averaging of the instantaneous real power signal is carried
out. The result is a greatly attenuated sinusoidal content and a
virtually ripple-free frequency output.

REV. B

–13–

AD7755

Interfacing the AD7755 to a Microcontroller for Energy
Measurement

The easiest way to interface the AD7755 to a microcontroller is
to use the CF high frequency output with the output frequency
scaling set to 2048 × F1, F2. This is done by setting SCF = 0
and S0 = S1 = 1, see Table IV. With full-scale ac signals on the
analog inputs, the output frequency on CF will be approximately

5.5 kHz. Figure 31 illustrates one scheme which could be used
to digitize the output frequency and carry out the necessary
averaging mentioned in the previous section.

CF

AVERAGE

FREQUENCY

AD7755

CF

*

REVP

*

REVP MUST BE USED IF THE METER IS BIDIRECTIONAL OR

DIRECTION OF ENERGY FLOW IS NEEDED

FREQUENCY

RIPPLE

TIME

ⴞ10%

MCU

COUNTER

UP/DOWN

TIMER

Figure 31. Interfacing the AD7755 to an MCU

As shown, the frequency output CF is connected to an MCU
counter or port. This will count the number of pulses in a given
integration time which is determined by an MCU internal timer.
The average power is proportional to the average frequency is
given by:

Average Frequency Average al Power

==Re

Counter

Timer

The energy consumed during an integration period is given by:

Energy Average Power Time

Counter

Time

Time Counter=×=×=

For the purpose of calibration, this integration time could be 10
to 20 seconds in order to accumulate enough pulses to ensure
correct averaging of the frequency. In normal operation the inte­gration time could be reduced to one or two seconds depending,
for example, on the required undate rate of a display. With
shorter integration times on the MCU the amount of energy in
each update may still have some small amount of ripple, even
under steady load conditions. However, over a minute or more
the measured energy will have no ripple.

Power Measurement Considerations

Calculating and displaying power information will always have
some associated ripple that will depend on the integration period
used in the MCU to determine average power and also the load.
For example, at light loads the output frequency may be 10 Hz.
With an integration period of two seconds, only about 20 pulses
will be counted. The possibility of missing one pulse always exists
as the AD7755 output frequency is running asynchronously to
the MCU timer. This would result in a one-in-twenty or 5%
error in the power measurement.

TRANSFER FUNCTION
Frequency Outputs F1 and F2

The AD7755 calculates the product of two voltage signals (on
Channel 1 and Channel 2) and then low-pass filters this product
to extract real power information. This real power information
is then converted to a frequency. The frequency information is
output on F1 and F2 in the form of active low pulses. The pulse
rate at these outputs is relatively low, e.g., 0.34 Hz maximum
for ac signals with S0 = S1 = 0—see Table III. This means that
the frequency at these outputs is generated from real power
information accumulated over a relatively long period of time.
The result is an output frequency that is proportional to the
average real power. The averaging of the real power signal is
implicit to the digital-to-frequency conversion. The output
frequency or pulse rate is related to the input voltage signals by
the following equation.

806 1 2

.

V V Gain F

Freq

=

×× × ×

2

V

REF

−

14

where:

Freq = Output frequency on F1 and F2 (Hz)

V1 = Differential rms voltage signal on Channel 1 (volts)

V2 = Differential rms voltage signal on Channel 2 (volts)

Gain = 1, 2, 8 or 16, depending on the PGA gain selection

made using logic inputs G0 and G1

V

= The reference voltage (2.5 V ± 8%) (volts)

REF

F

= One of four possible frequencies selected by using the

1–4

logic inputs S0 and S1—see Table II.

Table II. F

S1 S0 F

0 0 1.7 3.579 MHz/2
0 1 3.4 3.579 MHz/2
1 0 6.8 3.579 MHz/2
1 1 13.6 3.579 MHz/2

NOTE
*F

is a binary fraction of the master clock and therefore will vary if the speci-

1–4

fied CLKIN frequency is altered.

Frequency Selection

1–4

(Hz) XTAL/CLKIN*

1–4

21

20

19

18

–14–

REV. B

AD7755

Example 1

Thus if full-scale differential dc voltages of +470 mV and –660 mV
are applied to V1 and V2 respectively (470 mV is the maximum
differential voltage that can be connected to Channel 1 and
660 mV is the maximum differential voltage that can be con­nected to Channel 2), the expected output frequency is calcu­lated as follows:

Gain = 1, G0 = G1 = 0

F

= 1.7 Hz, S0 = S1 = 0

1–4

V1 = +470 mV dc = 0.47 V (rms of dc = dc)

V2 = –660 mV dc = 0.66 V (rms of dc = |dc|)

V

= 2.5 V (nominal reference value).

REF

NOTE: If the on-chip reference is used, actual
output frequencies may vary from device to device
due to reference tolerance of ±8%.

××××

806 047 066 1 17

Freq =

Example 2

... .

2

25

.

=

068

.

In this example, with ac voltages of ±470 mV peak applied to
V1 and ±660 mV peak applied to V2, the expected output fre­quency is calculated as follows:

Gain = 1, G0 = G1 = 0

F

= 1.7 Hz, S0 = S1 = 0

1–4

V1 = rms of 470 mV peak ac = 0.47/√2 volts
V2 = rms of 660 mV peak ac = 0.66/√2 volts

V

= 2.5 V (nominal reference value).

REF

NOTE: If the on-chip reference is used, actual
output frequencies may vary from device to device
due to reference tolerance of ±8%.

××××

806 047 066 1 17

Freq =

... .

××

2225

2

.

=

034

.

As can be seen from these two example calculations, the maxi­mum output frequency for ac inputs is always half of that for dc
input signals. Table III shows a complete listing of all maximum
output frequencies.

Table III. Maximum Output Frequency on F1 and F2

Max Frequency Max Frequency

S1 S0 for DC Inputs (Hz) for AC Inputs (Hz)

0 0 0.68 0.34
0 1 1.36 0.68
1 0 2.72 1.36
1 1 5.44 2.72

Frequency Output CF

The pulse output CF (Calibration Frequency) is intended for
use during calibration. The output pulse rate on CF can be up
to 2048 times the pulse rate on F1 and F2. The lower the F

1–4

frequency selected, the higher the CF scaling (except for the
high frequency mode SCF = 0, S1 = S0 = 1). Table IV shows
how the two frequencies are related, depending on the states of

the logic inputs S0, S1 and SCF. Because of its relatively high
pulse rate, the frequency at this logic output is proportional to
the instantaneous real power. As is the case with F1 and F2, the
frequency is derived from the output of the low-pass filter after
multiplication. However, because the output frequency is high,
this real power information is accumulated over a much shorter
time. Hence less averaging is carried out in the digital-to­frequency conversion. With much less averaging of the real
power signal, the CF output is much more responsive to power
fluctuations—see Signal Processing Block in Figure 20.

Table IV. Maximum Output Frequency on CF

SCF S1 S0 F

(Hz) CF Max for AC Signals (Hz)

1–4

1 0 0 1.7 128 × F1, F2 = 43.52
0 0 0 1.7 64 × F1, F2 = 21.76
1 0 1 3.4 64 × F1, F2 = 43.52
0 0 1 3.4 32 × F1, F2 = 21.76
1 1 0 6.8 32 × F1, F2 = 43.52
0 1 0 6.8 16 × F1, F2 = 21.76
1 1 1 13.6 16 × F1, F2 = 43.52
0 1 1 13.6 2048 × F1, F2 = 5.57 kHz

SELECTING A FREQUENCY FOR AN ENERGY METER
APPLICATION

As shown in Table II, the user can select one of four frequen­cies. This frequency selection determines the maximum fre­quency on F1 and F2. These outputs are intended to be used to
drive the energy register (electromechanical or other). Since only
four different output frequencies can be selected, the available
frequency selection has been optimized for a meter constant of
100 imp/kWhr with a maximum current of between 10 A and
120 A. Table V shows the output frequency for several maxi­mum currents (I

) with a line voltage of 220 V. In all cases

MAX

the meter constant is 100 imp/kWhr.

Table V. F1 and F2 Frequency at 100 imp/kWhr

I

MAX

F1 and F2 (Hz)

12.5 A 0.076
25 A 0.153
40 A 0.244
60 A 0.367
80 A 0.489
120 A 0.733

The F

frequencies allow complete coverage of this range of

1–4

output frequencies on F1 and F2. When designing an energy
meter the nominal design voltage on Channel 2 (voltage) should
be set to half-scale to allow for calibration of the meter constant.
The current channel should also be no more than half-scale
when the meter sees maximum load. This will allow over current
signals and signals with high crest factors to be accommodated.
Table VI shows the output frequency on F1 and F2 when both
analog inputs are half-scale. The frequencies listed in Table
VI align very well with those listed in Table V for maximum load.

REV. B

–15–

AD7755

Table VI. F1 and F2 Frequency with Half-Scale AC Inputs

Frequency on F1 and F2–

S1 S0 F

1–4

CH1 and CH2 Half-Scale AC Inputs

0 0 1.7 0.085 Hz
0 1 3.4 0.17 Hz
1 0 6.8 0.34 Hz
1 1 13.6 0.68 Hz

When selecting a suitable F
frequency output at I

MAX

frequency for a meter design, the

1–4

(maximum load) with a meter con­stant of 100 imp/kWhr should be compared with Column 4 of
Table VI. The frequency that is closest in Table VI will deter­mine the best choice of frequency (F

). For example, if a meter

1–4

with a maximum current of 25 A is being designed, the out­put frequency on F1 and F2 with a meter constant of 100 imp/
kWhr is 0.153 Hz at 25 A and 220 V (from Table V). Looking
at Table VI, the closest frequency to 0.153 Hz in column four is

0.17 Hz. Therefore F

(3.4 Hz—see Table II) is selected for this

2

design.

Frequency Outputs

Figure 1 shows a timing diagram for the various frequency out­puts. The outputs F1 and F2 are the low frequency outputs that
can be used to directly drive a stepper motor or electromechani­cal impulse counter. The F1 and F2 outputs provide two alter­nating low going pulses. The pulsewidth (t
the time between the falling edges of F1 and F2 (t
mately half the period of F1 (t

). If however the period of F1

2

) is set at 275 ms and

1

) is approxi-

3

and F2 falls below 550 ms (1.81 Hz) the pulsewidth of F1 and
F2 is set to half of their period. The maximum output frequen­cies for F1 and F2 are shown in Table III.

The high frequency CF output is intended to be used for com­munications and calibration purposes. CF produces a 90 ms­wide active high pulse (t

) at a frequency proportional to active

4

power. The CF output frequencies are given in Table IV. As in
the case of F1 and F2, if the period of CF (t

) falls below 180 ms,

5

the CF pulsewidth is set to half the period. For example, if the CF
frequency is 20 Hz, the CF pulsewidth is 25 ms.

NOTE: When the high frequency mode is selected, (i.e., SCF =
0, S1 = S0 = 1) the CF pulsewidth is fixed at 18 µs. Therefore t

4

will always be 18 µs, regardless of output frequency on CF.

NO LOAD THRESHOLD

The AD7755 also includes a “no load threshold” and “start-up
current” feature that will eliminate any creep effects in the
meter. The AD7755 is designed to issue a minimum output
frequency on all modes except when SCF = 0 and S1 = S0 = 1.
The no-load detection threshold is disabled on this output mode
to accommodate specialized application of the AD7755. Any
load generating a frequency lower than this minimum frequency
will not cause a pulse to be issued on F1, F2 or CF. The mini­mum output frequency is given as 0.0014% of the full-scale
output frequency for each of the F

frequency selections—see

1–4

Table II. For example, an energy meter with a meter constant
of 100 imp/kWhr on F1, F2 using F
output frequency at F1 or F2 would be 0.0014% of 3.4 Hz or

4.76 × 10

–5

Hz. This would be 3.05 × 10–3Hz at CF (64 × F1 Hz).

(3.4 Hz), the maximum

2

In this example the no-load threshold would be equivalent to

1.7 W of load or a start-up current of 8 mA at 220 V. Compar­ing this value to the IEC1036 specification which states that the
meter must start up with a load equal to or less than 0.4% Ib.
For a 5A (Ib) meter 0.4% of Ib is equivalent to 20 mA.

C01022a–0–8/00 (rev. B)

PIN 1

0.210

(5.33)

MAX

0.200 (5.05)

0.125 (3.18)

24

1

0.022 (0.558)

0.014 (0.356)

24-Lead Plastic DIP

(N-24)

1.275 (32.30)

1.125 (28.60)

13

12

0.100

0.070 (1.77)

(2.54)

0.045 (1.15)

BSC

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

SEATING
PLANE

0.150
(3.81)
MIN

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

0.311 (7.9)

0.301 (7.64)

0.078 (1.98)

0.068 (1.73)

0.008 (0.203)

0.002 (0.050)

24-Lead Shrink Small Outline Package

(RS-24)

0.328 (8.33)

0.318 (8.08)

24

1

PIN 1

0.0256
(0.65)

BSC

0.015 (0.38)

0.010 (0.25)

13

0.212 (5.38)

0.205 (5.207)

12

0.07 (1.78)

0.066 (1.67)

SEATING

PLANE

0.009 (0.229)

0.005 (0.127)

8°
0°

0.037 (0.94)

0.022 (0.559)

PRINTED IN U.S.A.

–16–

REV. B