Datasheet AD7745 Datasheet (ANALOG DEVICES)

Page 1

24-Bit Capacitance-to-Digital Converter

FEATURES

Capacitance-to-digital converter

New standard in single chip solutions Interfaces to single or differential floating sensors Resolution down to 4 aF (that is, up to 21 ENOB) Accuracy: 4 fF Linearity: 0.01% Common-mode (not changing) capacitance up to 17 pF Full-scale (changing) capacitance range: ±4 pF Tolerant of parasitic capacitance to ground up to 60 pF Update rate: 10 Hz to 90 Hz Simultaneous 50 Hz and 60 Hz rejection at 16 Hz

Temperature sensor on-chip

Resolution: 0.1°C, accuracy: ±2°C Voltage input channel Internal clock oscillator

2-wire serial interface (I Power

2.7 V to 5.25 V single-supply operation

0.7 mA current consumption Operating temperature: –40°C to +125°C 16-lead TSSOP package

APPLICATIONS

Automotive, industrial, and medical systems for

Pressure measurement Position sensing Level sensing Flowmeters Humidity sensing Impurity detection

C®-compatible)

FUNCTIONAL BLOCK DIAGRAMS

VDD

with Temperature Sensor

AD7745/AD7746

GENERAL DESCRIPTION

The AD7745/AD7746 are a high resolution, Σ-Δ capacitance-todigital converter (CDC). The capacitance to be measured is connected directly to the device inputs. The architecture features inherent high resolution (24-bit no missing codes, up to 21-bit effective resolution), high linearity (±0.01%), and high accuracy (±4 fF factory calibrated). The AD7745/AD7746 capacitance input range is ±4 pF (changing), while it can accept up to 17 pF common-mode capacitance (not changing), which can be balanced by a programmable on-chip, digital-tocapacitance converter (CAPDAC).

The AD7745 has one capacitance input channel, while the AD7746 has two channels. Each channel can be configured as single-ended or differential. The AD7745/AD7746 are designed for floating capacitive sensors. For capacitive sensors with one plate connected to ground, the AD7747 is recommended.

The parts have an on-chip temperature sensor with a resolution of 0.1°C and accuracy of ±2°C. The on-chip voltage reference and the on-chip clock generator eliminate the need for any external components in capacitive sensor applications. The parts have a standard voltage input, which together with the differential reference input allows easy interface to an external temperature sensor, such as an RTD, thermistor, or diode.

The AD7745/AD7746 have a 2-wire, I interface. Both parts can operate with a single power supply from 2.7 V to 5.25 V. They are specified over the automotive temperature range of –40°C to +125°C and are housed in a 16-lead TSSOP package.

C-compatible serial

VDD

VIN(+) VIN(–)

CIN1(+) CIN1(–)

EXCA EXCB

TEMP

SENSOR

CAP DAC

EXCITATION

MUX

CLOCK

GENERATOR

24-BIT Σ-∆

MODULATOR

REFIN(+) REFIN(–) GND

DIGITAL

FILTER

CONTROL LOGIC

CALIBRATION

VOLTAGE

REFERENCE

AD7745

SERIAL

INTERFACE

I2C

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

SDA

SCL

RDY

05468-001

VIN(+) VIN(–)

CIN1(+) CIN1(–)

CIN2(+) CIN2(–)

EXC1 EXC2

TEMP

SENSOR

CAP DAC

EXCITATION

MUX

CLOCK

GENERATOR

24-BIT Σ-∆

MODULATOR

REFIN(+) REFIN(–) GND

DIGITAL

FILTER

CONTROL LOGIC

CALIBRATION

VOLTAGE

REFERENCE

Figure 2.

www.analog.com

AD7746

SERIAL

INTERFACE

I2C

SDA

SCL

RDY

05468-002

Page 2

AD7745/AD7746

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics .............................................8

Output Noise and Resolution Specifications ..............................11

Serial Interface ................................................................................ 12

Read Operation........................................................................... 12

Write Operation.......................................................................... 12

AD7745/AD7746 Reset ............................................................. 13

General Call................................................................................. 13

Status Register ............................................................................. 15

Cap Data Register....................................................................... 15

VT Data Register........................................................................ 15

Cap Set-Up Register................................................................... 16

VT Set-Up Register .................................................................... 16

EXC Set-Up Register.................................................................. 17

Configuration Register .............................................................. 18

Cap DAC A Register................................................................... 19

Cap DAC B Register................................................................... 19

Cap Offset Calibration Register................................................ 19

REVISION HISTORY

4/05—Revision 0: Initial Version

Cap Gain Calibration Register.................................................. 19

Volt Gain Calibration Register ................................................. 19

Circuit Description......................................................................... 20

Overview ..................................................................................... 20

Capacitance-to-Digital Converter ........................................... 20

Excitation Source........................................................................ 20

CAPDAC..................................................................................... 21

Single-Ended Capacitive Input................................................. 21

Differential Capacitive Input .................................................... 21

Parasitic Capacitance to Ground.............................................. 22

Parasitic Resistance to Ground................................................. 22

Parasitic Parallel Resistance ...................................................... 22

Parasitic Serial Resistance ......................................................... 23

Capacitive Gain Calibration ..................................................... 23

Capacitive System Offset Calibration...................................... 23

Internal Temperature Sensor .................................................... 23

External Temperature Sensor ................................................... 24

Volt a ge In p ut ............................................................................... 24

Monitor ................................................................................ 24

Typical Applicati on D iagram .................................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Rev. 0 | Page 2 of 28

Page 3

AD7745/AD7746

SPECIFICATIONS

VDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; GND = 0 V; EXC = 32 kHz; EXC = ±VDD/2; –40°C to +125°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

CAPACITIVE INPUT

Conversion Input Range ±4.096 pF Integral Nonlinearity (INL)

±0.01 % of FSR

No Missing Codes2 24 Bit Conversion time ≥ 62 ms Resolution, p-p 16.5 Bit Conversion time = 62 ms, see Table 5 Resolution Effective 19 Bit Conversion time = 62 ms, see Table 5 Output Noise, rms 2

Absolute Error Offset Error

2, 4

±4 fF 32 aF1

System Offset Calibration Range2 ±1 pF Offset Drift vs. Temperature –1 aF/°C Gain Error

0.02 0.08 % of FS 25°C, VDD = 5 V Gain Drift vs. Temperature2 –28 –26 –24 ppm of FS/°C Allowed Capacitance to GND2 60 pF See Figure 9 and Figure 10 Power Supply Rejection 0.3 1 fF/V Normal Mode Rejection 65 dB 50 Hz ± 1%, conversion time = 62 ms 55 dB 60 Hz ± 1%, conversion time = 62 ms Channel-to-Channel Isolation 70 dB AD7746 only

CAPDAC

Full Range 17 21 pF Resolution

164 fF 7-bit CAPDAC

Drift vs. Temperature2 24 26 28 ppm of FS/°C

EXCITATION

Frequency 32 kHz Voltage Across Capacitance ±VDD/8 V Configurable via digital interface ±VDD/4 V

±V

× 3/8

±VDD/2 V Average DC Voltage Across

<±40 mV

Capacitance

Allowed Capacitance to GND2 100 pF See Figure 11

TEMPERATURE SENSOR

V Resolution 0.1 °C Error2 ±0.5 ±2 °C Internal temperature sensor ±2 °C External sensing diode

VOLTAGE INPUT7 V

Differential VIN Voltage Range ±V

REF

V Absolute VIN Voltage2 GND − 0.03 VDD + 0.03 V Integral Nonlinearity (INL) ±3 ±15 ppm of FS No Missing Codes2 24 Bit Conversion time = 122.1 ms Resolution, p-p 16 Bits

Output Noise 3 µV rms

Offset Error ±3 µV Offset Drift vs. Temperature 15 nV/°C Full-Scale Error

2, 9

0.025 0.1 % of FS

Factory calibrated

aF/√Hz

25°C, VDD = 5 V, after offset calibration

See Table 5

After system offset calibration, Excluding effect of noise

internal

REF

internal or V

REF

= 2.5 V

Conversion time = 62 ms See Table 6 and Table 7

Rev. 0| Page 3 of 28

Page 4

AD7745/AD7746

Parameter Min Typ Max Unit Test Conditions/Comments

Full-Scale Drift vs. Temperature 5 ppm of FS/°C Internal reference

0.5 ppm of FS/°C External reference Average VIN Input Current 300 nA/V Analog VIN Input Current Drift ±50 pA/V/°C Power Supply Rejection 80 dB Internal reference, VIN = V Power Supply Rejection 90 dB External reference, VIN = V Normal Mode Rejection 75 dB 50 Hz ± 1%, conversion time = 122.1 ms 50 dB 60 Hz ± 1%, conversion time = 122.1 ms Common-Mode Rejection 95 dB VIN = 1 V

INTERNAL VOLTAGE REFERENCE

Voltage 1.169 1.17 1.171 V TA = 25°C Drift vs. Temperature 5 ppm/°C

EXTERNAL VOLTAGE REFERENCE INPUT

Differential REFIN Voltage2 0.1 2.5 V

V Absolute REFIN Voltage2 GND − 0.03 VDD + 0.03 V Average REFIN Input Current 400 nA/V Average REFIN Input Current Drift ±50 pA/V/°C Common-Mode Rejection 80 dB

SERIAL INTERFACE LOGIC INPUTS (SCL, SDA)

VIH Input High Voltage 2.1 V VIL Input Low Voltage 0.8 V Hysteresis 150 mV Input Leakage Current (SCL) ±0.1 ±1 µA

OPEN-DRAIN OUTPUT (SDA)

VOL Output Low Voltage 0.4 V

IOH Output High Leakage Current 0.1 1 µA V

LOGIC OUTPUT (

RDY

) VOL Output Low Voltage 0.4 V I VOH Output High Voltage 4.0 V I VOL Output Low Voltage 0.4 V I VOH Output High Voltage VDD – 0.6 V I

= −6.0 mA

SINK

= V

OUT

= 1.6 mA, VDD = 5 V

SINK

= 200 µA, VDD = 5 V

SOURCE

= 100 µA, VDD = 3 V

SINK

= 100 µA, VDD = 3 V

SOURCE

POWER REQUIREMENTS

VDD-to-GND Voltage 4.75 5.25 V VDD = 5 V, nominal

2.7 3.6 V VDD = 3.3 V, nominal IDD Current 850 µA Digital inputs equal to VDD or GND 750 µA VDD = 5 V 700 µA VDD = 3.3 V IDD Current Power-Down Mode 0.5 2 µA Digital inputs equal to VDD or GND

Capacitance units: 1 pF = 10

Specification is not production tested, but is supported by characterization data at initial product release.

Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C. At

different temperatures, compensation for gain drift over temperature is required.

The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register

LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter + system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF, the larger offset can be removed using CAPDACs.

The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required.

The CAPDAC resolution is seven bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can

further reduce the CIN offset or the unchanging CIN component.

The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance.

Using an external temperature sensing diode 2N3906, with nonideality factor nf = 1.008, connected as in Figure 41, with total serial resistance <100 Ω.

Full-scale error applies to both positive and negative full scale.

-12

F; 1 fF = 10

-15

F; 1 aF = 10

-18

REF

Rev. 0 | Page 4 of 28

Page 5

AD7745/AD7746

TIMING SPECIFICATIONS

VDD = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; –40°C to +125°C, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

SERIAL INTERFACE

SCL Frequency 0 400 kHz SCL High Pulse Width, t SCL Low Pulse Width, t SCL, SDA Rise Time, t SCL, SDA Fall Time, t Hold Time (Start Condition), t Set-Up Time (Start Condition), t Data Set-Up Time, t Data Set-Up Time, t Set-Up Time (Stop Condition), t Data Hold Time, t Bus-Free Time (Between Stop and Start Condition, t

Sample tested during initial release to ensure compliance.

All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

Output load = 10 pF.

1, 2

HIGH

LOW

HD;STA

SU;STA

SU;DAT

SU;STO

(Master) 0 µs

HD;DAT

See Figure 3

0.6 µs

1.3 µs

0.3 µs

0.6 µs After this period, the first clock is generated

0.6 µs Relevant for repeated start condition

0.25 µs VDD ≥ 3.0 V

0.35 µs VDD < 3.0 V

0.6 µs

) 1.3 µs

BUF

LOW

HD:STA

SCL

BUF

HD:STA

HD:DAT

HIGH

SU:DAT

Figure 3. Serial Interface Timing Diagram

SU:STA

SU:STO

05468-003

Rev. 0| Page 5 of 28

Page 6

AD7745/AD7746

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

Positive Supply Voltage VDD to GND

Voltage on any Input or Output Pin to GND

ESD Rating (ESD Association Human Body Model, S5.1)

Operating Temperature Range –40°C to +125°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C

TSSOP Package θJA, (Thermal Impedance-to-Air)

TSSOP Package θJC, (Thermal Impedance-to-Case)

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

−0.3 V to +6.5 V

–0.3 V to V

2000 V

128°C/W

14°C/W

+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 6 of 28

Page 7

AD7745/AD7746

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SCL

RDY

EXCA

EXCB REFIN(+) REFIN(–)

CIN1(–) CIN1(+)

AD7745

TOP VIEW

(Not to Scale)

6 7 8

NC = NO CONNECT

Figure 4. AD7745 Pin Configuration (16-Lead TSSOP)

SDA

VDD

GND

VIN(–)

VIN(+)

NC NC

05468-004

Figure 5. AD7746 Pin Configuration (16-Lead TSSOP)

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 SCL

Serial Interface Clock Input. Connects to the master clock line. Requires pull-up resistor if not already provided in the system.

RDY Logic Output. A falling edge on this output indicates that a conversion on enabled channel(s) has been

finished and the new data is available. Alternatively, the status register can be read via the 2-wire serial interface and the relevant bit(s) decoded to query the finished conversion. If not used, this pin should be left as an open circuit.

3, 4 EXCA, EXCB

CDC Excitation Outputs. The measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, these pins should be left as an open circuit.

5, 6

REFIN(+), REFIN(–)

Differential Voltage Reference Input for the Voltage Channel (ADC). Alternatively, the on-chip internal reference can be used for the voltage channel. These reference input pins are not used for conversion on capacitive channel(s) (CDC). If not used, these pins can be left as an open circuit or connected to GND.

7 CIN1(–)

CDC Negative Capacitive Input in Differential Mode. This pin is internally disconnected in single-ended CDC configuration. If not used, this pin can be left as an open circuit or connected to GND.

8 CIN1(+)

CDC Capacitive Input (in Single-Ended Mode) or Positive Capacitive Input (in Differential Mode). The measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, this pin can be left as an open circuit or connected to GND.

9, 10

NC Not Connected. This pin should be left as an open circuit.

(AD7745) 9

(AD7746) 10

(AD7746) 11, 12 VIN(+), VIN(–)

CIN2(+)

CIN2(–)

CDC Second Capacitive Input (in Single-Ended Mode) or Positive Capacitive Input (in Differential Mode). If not used, this pin can be left open circuit or connected to GND.

CDC Negative Capacitive Input in Differential Mode. This pin is internally disconnected in a single-ended CDC configuration. If not used, this pin can be left as an open circuit or connected to GND.

Differential Voltage Input for the Voltage Channel (ADC). These pins are also used to connect an external

temperature sensing diode. If not used, these pins can be left as an open circuit or connected to GND. 13 GND Ground Pin. 14 VDD

Power Supply Voltage. This pin should be decoupled to GND, using a low impedance capacitor, for example

in combination with a 10 µF tantalum and a 0.1 µF multilayer ceramic. 15 NC Not Connected. This pin should be left as an open circuit. 16 SDA

Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided

elsewhere in the system.

SCL RDY

EXCA

EXCB REFIN(+) REFIN(–)

CIN1(–) CIN1(+)

1 2 3

AD7746

TOP VIEW

(Not to Scale)

6 7 8

NC = NO CONNECT

16 15 14 13 12 11 10

SDA NC VDD GND VIN(–) VIN(+) CIN2(–) CIN2(+)

05468-005

Rev. 0| Page 7 of 28

Page 8

AD7745/AD7746

TYPICAL PERFORMANCE CHARACTERISTICS

100

INL (ppm)

–4 –3 –2 –1 0 1 2 3 4

–5 5

INPUT CAPACITANCE (pF)

Figure 6. Capacitance Input Integral Nonlinearity,

= 5 V, the Same Configuration as in Figure 31

2000

1000

–1000

GAIN ERROR (ppm)

–2000

–3000

–25 0 25 50 75 100 125

–50 150

TEMPERATURE (°C)

GAIN TC ≈ –26ppm/°C

Figure 7. Capacitance Input Offset Drift vs. Temperature,

= 5 V, CIN and EXC Pins Open Circuit

100

–25

OFFSET ERROR (aF)

–50

–75

–100

–25 0 25 50 75 100 125

–50 150

TEMPERATURE (°C)

Figure 8. Capacitance Input Gain Drift vs. Temperature,

= 5 V, CIN(+) to EXC = 4 pF, the Same Configuration as in Figure 30

05468-014

05468-015

05468-016

CAPACITANCE ERROR (fF)

–2

0 500

50 100 150 200 250 300 350 400 450

CAPACITANCE CIN PIN TO GND (pF)

2.7V 3V 5V3.3V

05468-017

Figure 9. Capacitance Input Error vs. Capacitance between CIN and GND.

CIN(+) to EXC = 4 pF, CIN(−) to EXC = 0 pF, V

= 2 .7 V, 3 V, 3. 3 V, an d 5 V,

the Same Configuration as in Figure 33

CAPACITANCE ERROR (fF)

–2

0 500

50 100 150 200 250 300 350 400 450

2.7V 3V 3.3V

CAPACITANCE CIN PIN TO GND (pF)

05468-018

Figure 10. Capacitance Input Error vs. Capacitance between CIN and GND,

CIN(+) to EXC = 21 pF, CIN(−) to EXC = 23 pF, V

= 2.7 V, 3 V, 3.3 V, and 5 V,

the Same Configuration as in Figure 34

CAPACITANCE ERROR (fF)

–1

0 500

50 100 150 200 250 300 350 400 450

CAPACITANCE EXC PIN TO GND (pF)

2.7V

3.3V

05468-019

Figure 11. Capacitance Input Error vs. Capacitance between EXC and GND,

CIN(+) to EXC = 21 pF, CIN(−) to EXC = 23 pF, V

= 2.7 V, 3 V, 3.3 V, and 5 V,

the Same Configuration as in Figure 34

Rev. 0 | Page 8 of 28

Page 9

AD7745/AD7746

–2

–4

–6

CAPACITANCE ERROR (fF)

–8

–10

–12

–250

2.7V

–200 –150 –100 –50 0 50 100 150 200

CIN LEAKAGE TO GND (nA)

Figure 12. Capacitance Input Error vs. Leakage Current to GND,

CIN(+) to EXC = 4 pF, CIN(−) to EXC = 0 pF,

= 2.7 V and 3 V

5V –2

–4

–6

CAPACITANCE ERROR (fF)

–8

–10

–12

–250 250

3.3V

–200 –150 –100 –50 0 50 100 150 200

CIN LEAKAGE TO GND (nA)

Figure 13. Capacitance Input Error vs. Leakage Current to GND,

CIN(+) to EXC =4 pF, CIN(−) to EXC = 0 pF,

VDD=3.3 V and 5 V

250

05468-028

05468-030

–2

–4

–6

CAPACITANCE ERROR (fF)

–8

–10

123456

SERIAL RESISTANCE (kΩ)

05468-031

Figure 15. Capacitance Input Error vs. Serial Resistance,

CIN(+) to EXC = 21 pF, CIN(−) to EXC = 23 pF, V

= 5 V,

the Same Configuration as in Figure 34.

0.2

–0.2

–0.4

–0.6

CAPACITANCE ERROR (fF)

–0.8

–1.0

2.5

3.0 3.5 4.0 4.5 5.0 VDD (V)

5.5

05468-032

Figure 16. Capacitance Input Power Supply Rejection (PSR),

CIN(+) to EXC = 4 pF, the Same Configuration as in Figure 30

0.20

0.1

0.01

CAPACITANCE ERROR (pF)

0.001

0.0001 1 100000

10 100 1000 10000

PARALLEL RESISTANCE (MΩ)

Figure 14. Capacitance Input Error vs. Resistance in Parallel

with Measured Capacitance

05468-029

Rev. 0| Page 9 of 28

0.15

0.10

0.05

–0.05

CAPDAC CODE DNL (pF)

–0.10

–0.15

–0.20

0 128

16 32 48 64 80 96 112

CAPDAC CODE

Figure 17. CAPDAC Differential Nonlinearity (DNL)

05468-033

Page 10

AD7745/AD7746

2.0

1.5

1.0

0.5

ERROR (°C)

–0.5

–1.0

–1.5

–2.0

–25 0 25 50 75 100 125

–50 150

TEMPERATURE (°C)

Figure 18. Internal Temperature Sensor Error vs. Temperature

1.0

0.5

–0.5

–1.0

ERROR (°C)

–1.5

–2.0

–2.5

–3.0

–25 0 25 50 75 100 125

–50 150

TEMPERATURE (°C)

05468-034

05468-035

–20

–40

–60

GAIN (dB)

–80

–100

–120

0 400

50 100 150 200 250 300 350

INPUT SIGNAL FREQUENCY (Hz)

Figure 21. Capac itance Channe l Frequenc y Respons e,

Conversion Time = 62 ms

–20

–40

–60

GAIN (dB)

–80

–100

–120

0 400

50 100 150 200 250 300 350

INPUT SIGNAL FREQUENCY (Hz)

05468-037

05468-038

Figure 19. External Temperature Sensor Error vs. Temperature

–20

–40

–60

GAIN (dB)

–80

–100

–120

0 1000

100 200 300 400 500 600 700 800 900

INPUT SIGNAL FREQUENCY (Hz)

Figure 20. Capacitance Channel Frequenc y Response,

Conversion Time = 11 ms

05468-036

Rev. 0 | Page 10 of 28

Figure 22. Capac itance Channe l Frequenc y Respons e,

Conversion Time = 109.6 ms

–20

–40

–60

GAIN (dB)

–80

–100

–120

0 400

50 100 150 200 250 300 350

INPUT SIGNAL FREQUENCY (Hz)

Figure 23. Voltage Channel Frequency Response,

Conversion Time = 122.1 ms

05468-039

Page 11

AD7745/AD7746

OUTPUT NOISE AND RESOLUTION SPECIFICATIONS

The AD7745/AD7746 resolution is limited by noise. The noise performance varies with the selected conversion time.

Table 5 shows typical noise performance and resolution for the capacitive channel. These numbers were generated from 1000 data samples acquired in continuous conversion mode, at an excitation of 32 kHz, ±V

/2, and with all CIN and EXC pins

connected only to the evaluation board (no external capacitors.)

Table 5. Typical Capacitive Input Noise and Resolution vs. Conversion Time

Conversion Time (ms)

11.0 90.9 87.2 4.3 40.0 212.4 17.6 15.2

11.9 83.8 79.0 3.1 27.3 137.7 18.2 15.9

20.0 50.0 43.6 1.8 12.2 82.5 19.4 16.6

38.0 26.3 21.8 1.6 7.3 50.3 20.1 17.3

62.0 16.1 13.8 1.5 5.4 33.7 20.5 17.9

77.0 13.0 10.5 1.5 4.9 28.3 20.7 18.1

92.0 10.9 8.9 1.5 4.4 27.8 20.8 18.2

109.6 9.1 8.0 1.5 4.2 27.3 20.9 18.2

Output Data Rate (Hz)

–3dB Frequency (Hz)

RMS Noise (aF/√Hz)

Table 6. Typical Voltage Input Noise and Resolution vs. Conversion Time, Internal Voltage Reference

Conversion Time (ms)

20.1 49.8 26.4 11.4 62 17.6 15.2

32.1 31.2 15.9 7.1 42 18.3 15.7

62.1 16.1 8.0 4.0 28 19.1 16.3

122.1 8.2 4.0 3.0 20 19.5 16.8

Output Data Rate (Hz)

–3dB Frequency (Hz)

RMS Noise (µV)

Table 7. Typical Voltage Input Noise and Resolution vs. Conversion Time, External 2.5 V Voltage Reference

Conversion Time (ms)

20.1 49.8 26.4 14.9 95 18.3 15.6

32.1 31.2 15.9 6.3 42 19.6 16.8

62.1 16.1 8.0 3.3 22 20.5 17.7

122.1 8.2 4.0 2.1 15 21.1 18.3

Output Data Rate (Hz)

–3dB Frequency (Hz)

RMS Noise (µV)

Table 6 and Table 7 show typical noise performance and resolution for the voltage channel. These numbers were generated from 1000 data samples acquired in continuous conversion mode with VIN pins shorted to ground.

RMS noise represents the standard deviation and p-p noise represents the difference between minimum and maximum results in the data. Effective resolution is calculated from rms noise, and p-p resolution is calculated from p-p noise.

RMS Noise (aF)

P-P Noise (aF)

P-P Noise (µV)

Effective Resolution (Bits)

P-P Resolution (Bits)

Rev. 0| Page 11 of 28

Page 12

AD7745/AD7746

SERIAL INTERFACE

The AD7745/AD7746 supports an I2C-compatible 2-wire serial interface. The two wires on the I and SDA (data). These two wires carry all addressing, control, and data information one bit at a time over the bus to all connected peripheral devices. The SDA wire carries the data, while the SCL wire synchronizes the sender and receiver during the data transfer. I slave devices. A device that initiates a data transfer message is called a master, while a device that responds to this message is called a slave.

To control the AD7745/AD7746 device on the bus, the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that the start byte follows. This 8-bit start byte is made up of a 7-bit address plus an R/W bit indicator.

All peripherals connected to the bus respond to the start condition and shift in the next 8 bits (7-bit address + R/W bit). The bits arrive MSB first. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. An exception to this is the general call address, which is described later in this document. The idle condition is where the device monitors the SDA and SCL lines waiting for the start condition and the correct address byte. The R/W bit determines the direction of the data transfer. A Logic 0 LSB in the start byte means that the master writes information to the addressed peripheral. In this case the AD7745/AD7746 becomes a slave receiver. A Logic 1 LSB in the start byte means that the master reads information from the addressed peripheral. In this case, the AD7745/AD7746 becomes a slave transmitter. In all instances, the AD7745/AD7746 acts as a standard slave device on the I

The start byte address for the AD7745/AD7746 is 0x90 for a write and 0x91 for a read.

C devices are classified as either master or

READ OPERATION

When a read is selected in the start byte, the register that is currently addressed by the address pointer is transmitted on to the SDA line by the AD7745/AD7746. This is then clocked out by the master device and the AD7745/AD7746 awaits an acknowledge from the master.

If an acknowledge is received from the master, the address autoincrementer automatically increments the address pointer register and outputs the next addressed register content on to the SDA line for transmission to the master. If no acknowledge is received, the AD7745/AD7746 return to the idle state and the address pointer is not incremented.

C bus are called SCL (clock)

C bus.

The address pointers’ auto-incrementer allow block data to be written or read from the starting address and subsequent incremental addresses.

In continuous conversion mode, the address pointers’ autoincrementer should be used for reading a conversion result. That means, the three data bytes should be read using one multibyte read transaction rather than three separate single byte transactions. The single byte data read transaction may result in the data bytes from two different results being mixed. The same applies for six data bytes if both the capacitive and the voltage/temperature channel are enabled.

The user can also access any unique register (address) on a oneto-one basis without having to update all the registers. The address pointer register contents cannot be read.

If an incorrect address pointer location is accessed or, if the user allows the auto-incrementer to exceed the required register address, the following applies:

• In read mode, the AD7745/AD7746 continues to output

various internal register contents until the master device issues a no acknowledge, start, or stop condition. The address pointers’ auto-incrementer’s contents are reset to point to the status register at Address 0x00 when a stop condition is received at the end of a read operation. This allows the status register to be read (polled) continually without having to constantly write to the address pointer.

• In write mode, the data for the invalid address is not loaded

into the AD7745/AD7746 registers but an acknowledge is issued by the AD7745/AD7746.

WRITE OPERATION

When a write is selected, the byte following the start byte is always the register address pointer (subaddress) byte, which points to one of the internal registers on the AD7745/ AD7746. The address pointer byte is automatically loaded into the address pointer register and acknowledged by the AD7745/ AD7746. After the address pointer byte acknowledge, a stop condition, a repeated start condition, or another data byte can follow from the master.

A stop condition is defined by a low-to-high transition on SDA while SCL remains high. If a stop condition is ever encountered by the AD7745/AD7746, it returns to its idle condition and the address pointer is reset to Address 0x00.

If a data byte is transmitted after the register address pointer byte, the AD7745/AD7746 load this byte into the register that is currently addressed by the address pointer register, send an acknowledge, and the address pointer auto-incrementer automatically increments the address pointer register to the next internal register address. Thus, subsequent transmitted data bytes are loaded into sequentially incremented addresses.

Rev. 0 | Page 12 of 28

Page 13

AD7745/AD7746

If a repeated start condition is encountered after the address pointer byte, all peripherals connected to the bus respond exactly as outlined above for a start condition, that is, a repeated start condition is treated the same as a start condition. When a master device issues a stop condition, it relinquishes control of the bus, allowing another master device to take control of the bus. Hence, a master wanting to retain control of the bus issues successive start conditions known as repeated start conditions.

AD7745/AD7746 RESET

To reset the AD7745/AD7746 without having to reset the entire

C bus, an explicit reset command is provided. This uses a

I particular address pointer word as a command word to reset the part and upload all default settings. The AD7745/AD7746 do not respond to the I during the default values upload for approximately 150 µs (max 200 µs).

The reset command address word is 0xBF.

C bus commands (do not acknowledge)

GENERAL CALL

When a master issues a slave address consisting of seven 0s with the eighth bit (R/W bit) set to 0, this is known as the general call address. The general call address is for addressing every device connected to the I this address and read in the following data byte.

If the second byte is 0x06, the AD7745/AD7746 are reset, completely uploading all default values. The AD7745/AD7746 do not respond to the I during the default values upload for approximately 150 µs (max 200 µs).

The AD7745/AD7746 do not acknowledge any other general call commands.

C bus. The AD7745/AD7746 acknowledge

C bus commands (do not acknowledge)

SDATA

SCLOCK

1–7 8 9 1

START ADDR

–7 8 9 1–7 8 9 PS

ACK SUBADDRESS ACK DATA ACK STOP

R/W

Figure 24. Bus Data Transfer

05468-006

WRITE

SEQUENCE

READ

SEQUENCE

LSB = 0

S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA

S = START BIT P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER

Figure 25. Write and Read Sequences

DATA A(S)S SLAVE ADDR A(S) SUB ADDR A(S)

LSB = 1

A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER

DATA P

A(M)

A(S)

DATA P

A(M)

05468-007

Rev. 0| Page 13 of 28

Page 14

AD7745/AD7746

REGISTER DESCRIPTIONS

The master can write to or read from all of the AD7745/ AD7746 registers except the address pointer register, which is a write-only register. The address pointer register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the address pointer register. After the part has been

Table 8. Register Summary

Address

Pointer

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Status 0 0x00 R

- - - - EXCERR RDY RDYVT RDYCAP

0 0 0 0 0 1 1 1

Cap Data H 1 0x01 R Capacitive channel data—high byte, 0x00

Cap Data M 2 0x02 R Capacitive channel data—middle byte, 0x00

Cap Data L 3 0x03 R Capacitive channel data—low byte, 0x00

VT Data H 4 0x04 R Voltage/temperature channel data—high byte, 0x00

accessed over the bus and a read/write operation is selected, the address pointer register is set up. The address pointer register determines from or to which register the operation takes place. A read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed.

VT Data M 5 0x05 R Voltage/temperature channel data—middle byte, 0x00

VT Data L 6 0x06 R Voltage/temperature channel data—low byte, 0x00

Cap Setup 7 0x07 R/W

VT Setup 8 0x08 R/W

EXC Setup 9 0x09 R/W

Configuration 10 0x0A R/W

Cap DAC A 11 0x0B R/W

Cap DAC B 12 0x0C R/W

CAPEN CIN2

0 0 0 0 0 0 0 0

VTEN VTMD1 VTMD0 EXTREF - - VTSHORT VTCHOP

0 0 0 0 0 0 0 0

CLKCTRL EXCON EXCB

0 0 0 0 0 0 1 1

VTFS1 VTFS0 CAPFS2 CAPFS1 CAPFS0 MD2 MD1 MD0

1 0 1 0 0 0 0 0

DACAENA DACA—7-Bit Value

0 0x00

DACBENB DACB—7-Bit Value

0 0x00

CAPDIFF - - - - CAPCHOP

EXCB

EXCA

EXCLVL1 EXCLVL0

Cap Offset H 13 0x0D R/W Capacitive offset calibration—high byte, 0x80

Cap Offset L 14 0x0E R/W Capacitive offset calibration—low byte, 0x00

Cap Gain H 15 0x0F R/W Capacitive gain calibration—high byte, factory calibrated

Cap Gain L 16 0x10 R/W Capacitive gain calibration—low byte, factory calibrated

Volt Gain H 17 0x11 R/W Voltage gain calibration—high byte, factory calibrated

Volt Gain L 18 0x12 R/W Voltage gain calibration—low byte, factory calibrated

The CIN2 bit is relevant only for AD7746. The CIN2 bit should always be 0 on the AD7745.

Rev. 0 | Page 14 of 28

Page 15

AD7745/AD7746

RDY

STATUS REGISTER

Address Pointer 0x00, Read Only, Default Value 0x07

This register indicates the status of the converter. The status

The RDY indication of the finished conversion.

Table 9. Status Register Bit Map

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic - - - - EXCERR RDY RDYVT RDYCAP Default 0 0 0 0 0 1 1 1

Table 10.

Bit Mnemonic Description

7-4 - Not used, always read 0. 3 EXCERR

2 RDY

1 RDYVT

0 RDYCAP

EXCERR = 1 indicates that the excitation output cannot be driven properly. The possible reason can be a short circuit or too high capacitance between the excitation pin and ground.

RDY = 0 indicates that conversion on the enabled channel(s) has been finished and new unread data is available. If both capacitive and voltage/temperature channels are enabled, the RDY bit is changed to 0 after conversion on both channels is finished. The RDY bit returns to 1 either when data is read or prior to finishing the next conversion. If, for example, only the capacitive channel is enabled, then the RDY bit reflects the RDYCAP bit.

RDYVT = 0 indicates that a conversion on the voltage/temperature channel has been finished and new unread data is available.

RDYCAP = 0 indicates that a conversion on the capacitive channel has been finished and new unread data is available.

pin reflects the status of the RDY bit. Therefore, the

pin high-to-low transition can be used as an alternative

CAP DATA REGISTER

24 Bits, Address Pointer 0x01, 0x02, 0x03, Read-Only, Default Value 0x000000

Capacitive channel output data. The register is updated after finished conversion on the capacitive channel, with one exception: When the serial interface read operation from the CAP DATA register is in progress, the data register is not updated and the new capacitance conversion result is lost.

The stop condition on the serial interface is considered to be the end of the read operation. Therefore, to prevent data corruption, all three bytes of the data register should be read sequentially using the register address pointer auto-increment feature of the serial interface.

To prevent losing some of the results, the CAP DATA register should be read before the next conversion on the capacitive channel is finished.

The 0x000000 code represents negative full scale (–4.096 pF), the 0x800000 code represents zero scale (0 pF), and the 0xFFFFFF code represents positive full scale (+4.096 pF).

VT DATA REGISTER

24 Bits, Address Pointer 0x04, 0x05, 0x06, Read-Only, Default Value 0x000000

Voltage/temperature channel output data. The register is updated after finished conversion on the voltage channel or temperature channel, with one exception: When the serial interface read operation from the VT DATA register is in progress, the data register is not updated and the new voltage/temperature conversion result is lost.

For voltage input, Code 0 represents negative full scale (–V the 0x800000 code represents zero scale (0 V), and the 0xFFFFFF code represents positive full scale (+V

REF

To prevent losing some of the results, the VT DATA register should be read before the next conversion on the voltage/ temperature channel is finished.

For the temperature sensor, the temperature can be calculated from code using the following equation:

Temp e ra t ur e (°C) = (Code/2048) − 4096

REF

Rev. 0| Page 15 of 28

Page 16

AD7745/AD7746

CAP SET-UP REGISTER

Address Pointer 0x07, Default Value 0x00

Capacitive channel setup.

Table 11. CAP Set-Up Register Bit Map

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic CAPEN CIN2 CAPDIFF - - - - CAPCHOP Default 0 0 0 0 0 0 0 0

Table 12.

Bit Mnemonic Description

7 CAPEN CAPEN = 1 enables capacitive channel for single conversion, continuous conversion, or calibration. 6 CIN2 CIN2 = 1 switches the internal multiplexer to the second capacitive input on the AD7746. 5 CAPDIFF DIFF = 1 sets differential mode on the selected capacitive input. 4-1 - These bits must be 0 for proper operation. 0 CAPCHOP

VT SET-UP REGISTER

Address Pointer 0x08, Default Value 0x00

Voltage/Temperature channel setup.

Table 13. VT Set-Up Register Bit Map

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic VTEN VTMD1 VTMD0 EXTREF - - VTSHORT VTCHOP Default 0 0 0 0 0 0 0 0

Table 14.

Bit Mnemonic Description

7 VTEN VTEN = 1 enables voltage/temperature channel for single conversion, continuous conversion, or calibration. 6

4 EXTREF

3-2 - These bits must be 0 for proper operation. 1 VTSHORT VTSHORT = 1 internally shorts the voltage/temperature channel input for test purposes. 0 VTCHOP = 1

VTMD1 VTMD0

The CAPCHOP bit should be set to 0 for the specified capacitive channel performance. CAPCHOP = 1 approximately doubles the capacitive channel conversion times and slightly improves the capacitive channel noise performance for the longest conversion times.

Voltage/temperature channel input configuration.

VTMD1 VTMD0 Channel Input

0 0 Internal temperature sensor 0 1 External temperature sensor diode 1 0 VDD monitor 1 1 External voltage input (VIN) EXTREF = 1 selects an external reference voltage connected to REFIN(+), REFIN(–) for the voltage input or the

monitor.

EXTREF = 0 selects the on-chip internal reference. The internal reference must be used with the internal temperature sensor for proper operation.

VTCHOP = 1 sets internal chopping on the voltage/temperature channel. The VTCHOP bit must be set to 1 for the specified voltage/temperature channel performance.

Rev. 0 | Page 16 of 28

Page 17

AD7745/AD7746

EXC SET-UP REGISTER

Address Pointer 0x09, Default Value 0x03

Capacitive channel excitation setup.

Table 15. EXC Set-Up Bit Map

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic CLKCTRL EXCON EXCB

EXCB

Default 0 0 0 0 0 0 0 0

Table 16.

Bit Mnemonic Description

7 CLKCTRL The CLKCTRL bit should be set to 0 for the specified AD7745/AD7746 performance.

CLKCTRL = 1 decreases the excitation signal frequency and the modulator clock frequency by factor of 2. This also increases the conversion time on all channels (capacitive, voltage, and temperature) by a factor of 2.

6 EXCON

When EXCON = 0, the excitation signal is present on the output only during capacitance channel conversion. When EXCON = 1, the excitation signal is present on the output during both capacitance and

voltage/temperature conversion. 5 EXCB EXCB = 1 enables EXCB pin as the excitation output. 4

EXCB

= 1 enables EXCB pin as the inverted excitation output.

EXCB

Only one of the EXCB or the

bits should be set for proper operation. 3 EXCA EXCA = 1 enables EXCA pin as the excitation output. 2

1 0

EXCA

EXCLVL1, EXCLVL0

EXCA

= 1 enables EXCA pin as the inverted excitation output.

EXCA

Only one of the EXCA or the

bits should be set for proper operation.

Excitation Voltage Level.

EXCLVL1 EXCLVL0 Voltage on Cap EXC Pin Low Level EXC Pin High Level

0 0 ±VDD/8 V 0 1 ±VDD/4 V 1 0 ±V 1 1 ±V

× 3/8 V

/2 0 V

EXCA

× 3/8 V × 1/4 V × 1/8 V

EXCLVL1 EXCLVL0

× 5/8

× 3/4

× 7/8

Rev. 0| Page 17 of 28

Page 18

AD7745/AD7746

CONFIGURATION REGISTER

Address Pointer 0x0A, Default Value 0xA0

Converter update rate and mode of operation setup.

Table 17. Configuration Register Bit Map

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic VTF1 VTF0 CAPF2 CAPF1 CAPF0 MD2 MD1 MD0 Default 0 0 0 0 0 0 0 0

Table 18.

Bit Mnemonic Description

7 6

5 4 3

2 1 0

VTF1 VTF0

CAPF2 CAPF1 CAPF0

MD2 MD1 MD0

Voltage/temperature channel digital filter setup—conversion time/update rate setup. The conversion times in this table are valid for the CLKCTRL = 0 in the EXC SETUP register. The conversion times are longer by a factor of two for the CLKCTRL = 1.

VTF1 VTF0 Conversion Time (ms) Update Rate (Hz) –3 dB Frequency (Hz)

0 0 20.1 49.8 26.4 0 1 32.1 31.2 15.9 1 0 62.1 16.1 8.0 1 1 122.1 8.2 4.0 Capacitive channel digital filter setup—conversion time/update rate setup.

The conversion times in this table are valid for the CLKCTRL = 0 in the EXC SETUP register. The conversion times are longer by factor of two for the CLKCTRL = 1.

CAP CHOP = 0 CAPF2 CAPF1 CAPF0 Conversion Time (ms) Update Rate –3 dB Frequency (Hz)

0 0 0 11.0 90.9 87.2 0 0 1 11.9 83.8 79.0 0 1 0 20.0 50.0 43.6 0 1 1 38.0 26.3 21.8 1 0 0 62.0 16.1 13.1 1 0 1 77.0 13.0 10.5 1 1 0 92.0 10.9 8.9 1 1 1 109.6 9.1 8.0 Converter mode of operation setup.

MD2 MD1 MD0 Mode

0 0 0 Idle 0 0 1 Continuous conversion 0 1 0 Single conversion 0 1 1 Power-Down 1 0 0 1 0 1 Capacitance system offset calibration 1 1 0 Capacitance or voltage system gain calibration 1 1 1

VTCHOP = 1

Rev. 0 | Page 18 of 28

Page 19

AD7745/AD7746

CAP DAC A REGISTER

Address Pointer 0x0B, Default Value 0x00

Capacitive DAC setup.

Table 19. Cap DAC A Register Bit Map

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic DACAENA DACA—7-Bit Value Default 0 0x00

Table 20.

Bit Mnemonic Description

7 DACAENA DACAENA = 1 connects capacitive DACA to the positive capacitance input. 6-1 DACA

CAP DAC B REGISTER

Address Pointer 0x0C, Default Value 0x00

Capacitive DAC setup.

Table 21. Cap DAC B Register Bit Map

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic DACBENB DACB—7-bit value Default 0 0x00

Table 22.

Bit Mnemonic Description

7 DACBENB DACBENB = 1 connects capacitive DACB to the negative capacitance input. 6-1 DACB

DACA value, Code 0x00 ≈ 0 pF, Code 0x7F ≈ full range.

DACB value, Code 0x00 ≈ 0 pF, Code 0x7F ≈ full range.

CAP OFFSET CALIBRATION REGISTER

16 Bits, Address Pointer 0x0D, 0x0E, Default Value 0x8000

The capacitive offset calibration register holds the capacitive channel zero-scale calibration coefficient. The coefficient is used to digitally remove the capacitive channel offset. The register value is updated automatically following the execution of a capacitance offset calibration. The capacitive offset calibration resolution (cap offset register LSB) is less than 32 aF; the full range is 1 pF.

On the AD7746, the register is shared by the two capacitive channels. If the capacitive channels need to be offset-calibrated individually, the host controller software should read the AD7746 capacitive offset calibration register values after performing the offset calibration on individual channels and then reload the values back to the AD7746 before executing conversion on a different channel.

CAP GAIN CALIBRATION REGISTER

16 Bits, Address Pointer 0x0F, 0x10, Default Value 0xXXXX

Capacitive gain calibration register. The register holds the capacitive channel full-scale factory calibration coefficient. On the AD7746, the register is shared by the two capacitive channels.

VOLT GAIN CALIBRATION REGISTER

16 Bits, Address Pointer 0x11,0x12, Default Value 0xXXXX

Voltage gain calibration register. The register holds the voltage channel full-scale factory calibration coefficient.

Rev. 0| Page 19 of 28

Page 20

AD7745/AD7746

CIRCUIT DESCRIPTION

VDD

TEMP

VIN(+) VIN(–)

CIN1(+) CIN1(–)

EXCA EXCB

SENSOR

MUX

CAP DAC

EXCITATION

Figure 26. AD7745 Block Diagram

OVERVIEW

The AD7745/AD7746 core is a high precision converter consisting of a second order (Σ-Δ or charge balancing) modulator and a third order digital filter. It works as a CDC for the capacitive inputs and as a classic ADC for the voltage input or for the voltage from a temperature sensor.

In addition to the converter, the AD7745/AD7746 integrates a multiplexer, an excitation source and CAPDACs for the capacitive inputs, a temperature sensor, a voltage reference for the voltage and temperature inputs, a complete clock generator, a control and calibration logic, and an I interface.

The AD7745 has one capacitive input, while the AD7746 has two capacitive inputs. All other features and specifications are identical for both parts.

CAPACITANCE-TO-DIGITAL CONVERTER

Figure 28 shows the CDC simplified functional diagram. The measured capacitance C source and the Σ-Δ modulator input. A square-wave excitation signal is applied on the C modulator continuously samples the charge going through the

. The digital filter processes the modulator output, which is a

stream of 0s and 1s containing the information in 0 and 1 density. The data from the digital filter is scaled, applying the calibration coefficients, and the final result can be read through the serial interface.

The AD7745/AD7746 is designed for floating capacitive sensors. Therefore, both C ground.

CLOCK

GENERATOR

24-BIT Σ-∆

MODULATOR

REFIN(+) REFIN(–) GND

is connected between the excitation

during the conversion and the

plates have to be isolated from

AD7745

DIGITAL

FILTER

CONTROL LOGIC

CALIBRATION

VOLTAGE

REFERENCE

I2C

SERIAL

INTERFACE

C-compatible serial

SDA

SCL

RDY

VDD

TEMP

VIN(+) VIN(–)

CIN1(+) CIN1(–)

CIN2(+) CIN2(–)

EXC1 EXC2

05468-001

SENSOR

MUX

CAP DAC

EXCITATION

Figure 27. AD7746 Block Diagram

CLOCK

GENERATOR

24-BIT Σ-∆

MODULATOR

REFIN(+) REFIN(–) GND

DIGITAL

FILTER

CONTROL LOGIC

CALIBRATION

VOLTAGE

REFERENCE

AD7746

SERIAL

INTERFACE

I2C

SDA

SCL

RDY

05468-002

CAPACITANCE TO DIGITAL CONVERTER

CLOCK

GENERATOR

CIN

EXC

24-BIT Σ-∆

MODULATOR

EXCITATION

Figure 28. CDC Simplified Block Diagram

(CDC)

FILTER

DATA

05468-027

DIGITAL

EXCITATION SOURCE

The two excitation pins EXCA and EXCB are independently programmable. They are identically functional and therefore either of them can be used for the capacitive sensor excitation.

On the 2-channel AD7746 using a separate excitation pin for each capacitive channel is recommended.

Rev. 0 | Page 20 of 28

Page 21

AD7745/AD7746

()(

)

−

CAPDAC

The AD7745/AD7746 CDC full-scale input range is ±4.096 pF. For simplicity of calculation, however, the following text and diagrams use ±4 pF. The part can accept a higher capacitance on the input and the common-mode or offset (not-changing component) capacitance can be balanced by programmable on-chip CAPDACs.

The CAPDAC can be used for programmable shifting the input range. The example in Figure 31 shows how to use the full ±4 pF CDC span to measure capacitance between 0 pF to 8 pF.

CAPDAC(+)

CIN(+)

CIN(–)

4pF

CAPDIFF = 0

± 4pF

CDC

0x000000 ... 0xFFFFFF DATA

CAPDAC(+)

CIN(+)

CIN(–)

CAPDAC(–)

EXC

CDC

DATA

Figure 29. Using a CAPDAC

The CAPDAC can be understood as a negative capacitance connected internally to the CIN pin. There are two independent CAPDACs, one connected to the CIN(+) and the second connected to the CIN(–). The relation between the capacitance input and output data can be expressed as

−−+−≈ CAPDACCCAPDACCDATA

)()(

The CAPDACs have a 7-bit resolution, monotonic transfer function, are well matched to each other, and have a defined temperature coefficient. The CAPDAC full range (absolute value) is not factory calibrated and can vary up to ±20% with the manufacturing process. See the Specifications section and typical performance characteristics in Figure 17.

The CAPDACs are shared by the two capacitive channels on the AD7746. If the CAPDACs need to be set individually, the host controller software should reload the CAPDAC values to the AD7746 before executing conversion on a different channel.

SINGLE-ENDED CAPACITIVE INPUT

When configured for a single-ended mode (the CAPDIFF bit in the Cap Setup register is set to 0), the AD7745/AD7746 CIN(–) pin is disconnected internally. The CDC (without using the CAPDACs) can measure only positive input capacitance in the range of 0 pF to 4 pF (see Figure 30).

CAPDAC(+)

0 ... 4pF

EXC

OFF

CAPDIFF = 0

CAPDAC(–) OFF

0 ... 4pF

CIN(+)

CIN(–)

Figure 30. CDC Single-Ended Input Mode

CDC

0x800000 ... 0xFFFFFF DATA

05468-010

05468-024

EXC

CAPDAC(–) 0pF

0 ... 8pF

Figure 31. Using CAPDAC in Single-Ended Mode

Figure 32 shows how to shift the input range further, up to 21 pF absolute value of capacitance connected to the CIN(+).

CAPDAC(+)

13 ... 21pF (17 ± 4pF)

CIN(+)

CIN(–)

EXC

17pF

CAPDIFF = 0

CAPDAC(–) 0pF

± 4pF

CDC

0x000000 ... 0xFFFFFF DATA

Figure 32. Using CAPDAC in Single-Ended Mode

DIFFERENTIAL CAPACITIVE INPUT

When configured for a differential mode (the CAPDIFF bit in the Cap Setup register set to 1), the AD7745/AD7746 CDC measures the difference between positive and negative capacitance input.

Each of the two input capacitances C and CIN pins must be less than 4 pF (without using the CAPDACs) or must be less than 21 pF and balanced by the CAPDACs. Balancing by the CAPDACs means that both C

–CAPDAC(+) and CY–CAPDAC(–) are less than 4 pF.

If the unbalanced capacitance between the EXC and CIN pins is higher than 4 pF, the CDC introduces a gain error, an offset error, and nonlinearity error.

See the examples shown in Figure 33, Figure 34, and Figure 35.

CAPDAC(+) OFF

CAPDIFF = 1

CAPDAC(–) OFF

Figure 33. CDC Differential Input Mode

0 ... 4pF

CIN(+)

CIN(–)

0 ... 4pF

EXC

and CY between the EXC

0x000000 ... 0xFFFFFF

DATA ± 4pF CDC

05468-025

05468-026

05468-020

Rev. 0| Page 21 of 28

Page 22

AD7745/AD7746

CAPDAC(+) 17pF

CAPDIFF = 1

CAPDAC(–) 17pF

15 ... 19pF (17 ± 2pF)

CIN(+)

CIN(–)

15 ... 19pF (17 ± 2pF)

EXC

Figure 34. Using CAPDAC in Differential Mode

CAPDAC(+) 17pF

CAPDIFF = 1

CAPDAC(–) 17pF

± 4pF

CDC

13 ... 21pF (17 ± 4pF)

CIN(+)

CIN(–)

17pF

EXC

Figure 35. Using CAPDAC in Differential Mode

PARASITIC CAPACITANCE TO GROUND

GND1

CIN

± 4pF

CDC

0x000000 ... 0xFFFFFF DATA

DATA

05468-021

05468-011

PARASITIC RESISTANCE TO GROUND

GND1

GND2

CIN

EXC

CDC

DATA

Figure 37. Parasitic Resistance to Ground

The AD7745/AD7746 CDC result would be affected by a leakage current from the C

to ground, therefore the CX should be

isolated from the ground. The influence of the leakage current varies with the power supply voltage. The following limits can be used as a guideline for the allowed leakage current or the equivalent resistance between the C

≈ 5 V: I

≥ 3 V: I

≥ 2.7 V: I

< 150 nA (that is, R

GND

< 60 nA (that is, R

GND

< 30 nA (that is, R

GND

and ground (Figure 37).

> 30 MΩ)

GND

> 50 MΩ)

GND

> 100 MΩ)

GND

A higher leakage current to ground results in a gain error, an offset error, and a nonlinearity error. See the typical performance characteristics shown in Figure 12 and Figure 13.

PARASITIC PARALLEL RESISTANCE

05468-013

GND2

EXC

Figure 36. Parasitic Capacitance to Ground

The CDC architecture used in the AD7745/AD7746 measures the capacitance C CIN pin. In theory, any capacitance C

connected between the EXC pin and the

to ground should not

affect the CDC result (see Figure 36).

The practical implementation of the circuitry in the chip implies certain limits and the result is gradually affected by capacitance to ground. See the allowed capacitance to GND in the specification table for CIN and excitation. Also see the typical performance characteristics shown in Figure 9, Figure 10, and Figure 11

05468-012

CIN

EXC

CDC

Figure 38. Parasitic Parallel Resistance

DATA

05468-022

The AD7745/AD7746 CDC measures the charge transfer between EXC pin and CIN pin. Any resistance connected in parallel to the measured capacitance CX (see Figure 38), such as the parasitic resistance of the sensor, also transfers charge. Therefore, the parallel resistor is seen as an additional capacitance in the output data. The equivalent parallel capacitance (or error caused by the parallel resistance) can be approximately calculated as

EXC

41××

is the excitation

EXC

Where R

is the parallel resistance and C

frequency. See the typical performance characteristics shown in Figure 14.

Rev. 0 | Page 22 of 28

Page 23

AD7745/AD7746

PARASITIC SERIAL RESISTANCE

CIN

EXC

Figure 39. Parasitic Serial Resistance

CDC

DATA

05468-023

The AD7745/AD7746 CDC result is affected by a resistance in series with the measured capacitance. The total serial resistance, which refers to R

+ RS2 on Figure 39, should be less than 1 kΩ

for the specified performance. See typical performance characteristics shown in Figure 15.

CAPACITIVE GAIN CALIBRATION

The AD7745/AD7746 gain is factory calibrated for the full scale of ±4.096 pF in the production for each part individually. The factory gain coefficient is stored in a one-time programmable (OTP) memory and is copied to the capacitive gain register at power-up or after reset.

The gain can be changed by executing a capacitance gain calibration mode, for which an external full-scale capacitance needs to be connected to the capacitance input, or by writing a user value to the capacitive gain register. This change would be only temporary and the factory gain coefficient would be reloaded back after power-up or reset. The part is tested and specified only for use with the default factory calibration coefficient.

CAPACITIVE SYSTEM OFFSET CALIBRATION

The capacitive offset is dominated by the parasitic offset in the application, such as the initial capacitance of the sensor, any parasitic capacitance of tracks on the board, and the capacitance of any other connections between the sensor and the CDC. Therefore, the AD7745/AD7746 are not factory calibrated for capacitive offset. It is the user’s responsibility to calibrate the system capacitance offset in the application.

Any offset in the capacitance input larger than ±1 pF should first be removed using the on-chip CAPDACs. The small offset within ±1 pF can then be removed by using the capacitance offset calibration register.

One method of adjusting the offset is to connect a zero-scale capacitance to the input and execute the capacitance offset calibration mode. The calibration sets the midpoint of the ±4.096 pF range (that is, Output Code 0x800000) to that zero-scale input.

Another method would be to calculate and write the offset calibration register value, the LSB is value 31.25 aF (4.096 pF/2

The offset calibration register is reloaded by the default value at power-on or after reset. Therefore, if the offset calibration is not repeated after each system power-up, the calibration coefficient value should be stored by the host controller and reloaded as part of the AD7745/AD7746 setup.

On the AD7746, the register is shared by the two capacitive channels. If the capacitive channels need to be offset calibrated individually, the host controller software should read the AD7746 capacitive offset calibration register values after performing the offset calibration on individual channels and then reload the values back to the AD7746 before executing a conversion on a different channel.

INTERNAL TEMPERATURE SENSOR

IN× I

CLOCK

GENERATOR

24-BIT Σ-∆

MODULATOR

VOLTAGE

REFERENCE

∆V

Figure 40. Internal Temperature Sensor

The temperature sensing method used in the AD7745/AD7746 is to measure a difference in ∆V operated at two different currents (see Figure 40). The ∆V change with temperature is linear and can be expressed as

×=∆

where:

K is Boltzmann’s constant (1.38 × 10

T is the absolute temperature in Kelvin.

q is the charge on the electron (1.6 × 10

N is the ratio of the two currents.

is the ideality factor of the thermal diode.

The AD7745/AD7746 uses an on-chip transistor to measure the temperature of the silicon chip inside the package. The Σ-Δ ADC converts the ∆V

to digital, the data are scaled using

factory calibration coefficients, thus the output code is proportional to temperature:

Code

()

CeTemperatur

2048

The AD7745/AD7746 has a low power consumption resulting in only a small effect due to the part self-heating (less than

0.5°C at V

= 5 V).

DIGITAL

FILTER

AND

SCALING

voltage of a transistor

)ln()( N

–23

–19

coulombs).

4096

−=°

DATA

05468-040

Rev. 0| Page 23 of 28

Page 24

AD7745/AD7746

If the capacitive sensor can be considered to be at the same temperature as the AD7745/AD7746 chip, the internal temperature sensor can be used as a system temperature sensor. That means the complete system temperature drift compensation can be based on the AD7745/AD7746 internal temperature sensor without need for any additional external components. See the typical performance characteristics in Figure 18.

EXTERNAL TEMPERATURE SENSOR

EXTERNAL

TEMPERATURE

SENSOR

2N3906

∆V

VIN (+)

VIN (–)

.N×

Figure 41. Transistor as an External Temperature Sensor

The AD7745/AD7746 provide the option of using an external transistor as a temperature sensor in the system. The ∆V method, which is similar to the internal temperature sensor method, is used. However, it is modified to compensate for the serial resistance of connections to the sensor. Total serial resistance (R

+ RS2 in Figure 41) up to 100 Ω is compensated.

The VIN(–) pin must be grounded for proper external temperature sensor operation.

The AD7745/AD7746 are factory calibrated for Transistor 2N3906 with the ideality factor n See the typical performance characteristics shown in Figure 19.

CLOCK

GENERATOR

24-BIT Σ-∆

MODULATOR

VOLTAGE

REFERENCE

DIGITAL

FILTER

AND

SCALING

= 1.008.

DATA

05468-041

VOLTAGE INPUT

VDD

ANALOG TO DIGITAL CONVERTER

VIN(+)

RTD

VIN(–)

REFIN(+)

REF

REFIN(–)

MODULATOR

Figure 42. Resistive Temperature Sensor Connected to the Voltage Input

(ADC)

CLOCK

GENERATOR

24-BIT Σ-∆

DIGITAL

FILTER

VOLTAGE

REFERENCE

GND

DATA

05468-042

The AD7745/AD7746 Σ-Δ core can work as a high resolution (up to 21 ENOB) classic ADC with a fully differential voltage input. The ADC can be used either with the on-chip high precision, low drift, 1.17 V voltage reference, or an external reference connected to the fully differential reference input pins.

The voltage and reference inputs are continuously sampled by a Σ-Δ modulator during the conversion. Therefore, the input source impedance should be kept low. See the application example in Figure 42.

VDD MONITOR

Along with converting external voltages, the AD7745/AD7746 Σ-Δ ADC can be used for monitoring the V voltage from the VDD pin is internally attenuated by 6.

voltage. The

TYPICAL APPLICATION DIAGRAM

TEMP

SENSOR VIN(+) VIN(–)

CIN1(+) CIN1(–)

CAP DAC

EXCA EXCB

EXCITATION

Figure 43. Basic Application Diagram for a Differential Capacitive Sensor

GENERATOR

MUX

24-BIT Σ-∆

MODULATOR

REFIN(+) REFIN(–)

VDD

CLOCK

DIGITAL

FILTER

VOLTAGE

REFERENCE

Rev. 0 | Page 24 of 28

0.1µF

AD7745

I2C

SERIAL

INTERFACE

CONTROL LOGIC

CALIBRATION

GND

3V/5V

10µF

10kΩ

SDA

SCL

RDY

POWER SUPPL

10kΩ

HOST

SYSTEM

05468-008

Page 25

AD7745/AD7746

OUTLINE DIMENSIONS

5.10

5.00

4.90

4.50

4.40

4.30

PIN 1

0.15

0.05

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 44. 16-Lead Thin Shrink Small Outline Package [TSSOP]

0.10

0.30

0.19

BSC

1.20 MAX

SEATING PLANE

6.40

0.20

0.09 8°

0°

0.75

0.60

0.45

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7745ARUZ AD7745ARUZ-REEL1 –40°C to +125°C 16-Lead TSSOP RU-16 AD7745ARUZ-REEL71 –40°C to +125°C 16-Lead TSSOP RU-16 AD7746ARUZ1 –40°C to +125°C 16-Lead TSSOP RU-16 AD7746ARUZ-REEL1 –40°C to +125°C 16-Lead TSSOP RU-16 AD7746ARUZ-REEL71 –40°C to +125°C 16-Lead TSSOP RU-16 EVAL-AD7746EB Evaluation Board

Z = Pb-free part.

–40°C to +125°C 16-Lead TSSOP RU-16

Rev. 0 | Page 25 of 28

Page 26

AD7745/AD7746

NOTES

Rev. 0 | Page 26 of 28

Page 27

AD7745/AD7746

NOTES

Rev. 0 | Page 27 of 28

Page 28

AD7745/AD7746

NOTES

Purchase of licensed I Patent Rights to use these components in an I

C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

C05468-0-4/05(0)

Rev. 0 | Page 28 of 28

Datasheet AD7745 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

OUTPUT NOISE AND RESOLUTION SPECIFICATIONS

SERIAL INTERFACE

READ OPERATION

WRITE OPERATION

AD7745/AD7746 RESET

GENERAL CALL

REGISTER DESCRIPTIONS

STATUS REGISTER

Address Pointer 0x00, Read Only, Default Value 0x07

CAP DATA REGISTER

VT DATA REGISTER

CAP SET-UP REGISTER

Address Pointer 0x07, Default Value 0x00

VT SET-UP REGISTER

Address Pointer 0x08, Default Value 0x00

EXC SET-UP REGISTER

Address Pointer 0x09, Default Value 0x03

CONFIGURATION REGISTER

Address Pointer 0x0A, Default Value 0xA0

CAP DAC A REGISTER

Address Pointer 0x0B, Default Value 0x00

CAP DAC B REGISTER

Address Pointer 0x0C, Default Value 0x00

CAP OFFSET CALIBRATION REGISTER

16 Bits, Address Pointer 0x0D, 0x0E, Default Value 0x8000

CAP GAIN CALIBRATION REGISTER

16 Bits, Address Pointer 0x0F, 0x10, Default Value 0xXXXX

VOLT GAIN CALIBRATION REGISTER

16 Bits, Address Pointer 0x11,0x12, Default Value 0xXXXX

CIRCUIT DESCRIPTION

OVERVIEW

CAPACITANCE-TO-DIGITAL CONVERTER

EXCITATION SOURCE

CAPDAC

SINGLE-ENDED CAPACITIVE INPUT

DIFFERENTIAL CAPACITIVE INPUT

PARASITIC CAPACITANCE TO GROUND

PARASITIC RESISTANCE TO GROUND

PARASITIC PARALLEL RESISTANCE

CAPACITIVE GAIN CALIBRATION

CAPACITIVE SYSTEM OFFSET CALIBRATION

INTERNAL TEMPERATURE SENSOR

EXTERNAL TEMPERATURE SENSOR

VOLTAGE INPUT

VDD MONITOR

TYPICAL APPLICATION DIAGRAM

OUTLINE DIMENSIONS

ORDERING GUIDE