Datasheet AD7739 Datasheet (Analog Devices)

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Page 1

8-Channel, High Throughput,

FEATURES

High resolution ADC

24 bits no missing codes ±0.0015% nonlinearity

Optimized for fast channel switching

18-bit p-p resolution (21 bits effective) at 500 Hz 16-bit p-p resolution (19 bits effective) at 4 kHz On-chip per channel system calibration

Configurable inputs

8 single-ended or 4 fully differential

Input ranges

+625 mV, ±625 mV, +1.25 V, ±1.25 V, +2.5 V, ±2.5 V

3-wire serial interface

SPI®, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on logic inputs

Single-supply operation

5 V analog supply 3 V or 5 V digital supply

Package: 24-lead TSSOP

24-Bit ∑-∆ ADC

FUNCTIONAL BLOCK DIAGRAM

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

INCOM/P0

SYNC/P1

MUX

I/O PORT

BUFFER

AD7739

CALIBRATION

CIRCUITRY

CLOCK

GENERATOR

AD7739

REFIN(–) REFIN(+)

REFERENCE

DETECT

24-BIT

Σ-∆ ADC

SERIAL

INTERFACE

CONTROL

LOGIC

SCLK

DOUT

DIN

RESET

RDY

APPLICATIONS

PLCs/DCSs Multiplexing applications Process control Industrial instrumentation

GENERAL DESCRIPTION

The AD7739 is a high precision, high throughput analog front end. True 16-bit p-p resolution is achievable with a total conversion time of 250 µs (4 kHz channel switching), making it ideally suited to high resolution multiplexing applications.

The part can be configured via a simple digital interface, which allows users to balance the noise performance against data throughput up to 15 kHz.

The analog front end features eight single-ended or four fully differential input channels with unipolar or bipolar 625 mV,

1.25 V, and 2.5 V input ranges. It accepts a common-mode input voltage from 200 mV above AGND to AV

The differential reference input features “No-Reference” detect capability. The ADC also supports per channel system calibration options.

– 300 mV.

DGND DV

MCLKINMCLKOUTAGND AV

Figure 1.

03742-0-001

The digital serial interface can be configured for 3-wire operation and is compatible with microcontrollers and digital signal processors. All interface inputs are Schmitt triggered. The part is specified for operation over the extended industrial temperature range of –40°C to +105°C.

Other parts in the AD7739 family are the AD7738, AD7734, and AD7732.

The AD7738 is similar to the AD7739 but has higher speed (8.5 kHz channel switching for 16-bit performance) and higher AIN leakage current. The AD7738 multiplexer output is pinned out externally, allowing the user to implement programmable gain or signal conditioning before being applied to the ADC.

The AD7734 analog front end features four single-ended input channels with unipolar or true bipolar input ranges to ±10 V while operating from a single +5 V analog supply. The AD7734 accepts an analog input overvoltage to ±16.5 V without degrading the performance of the adjacent channels.

The AD7732 is similar to the AD7734, but its analog front end features two fully differential input channels.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

www.analog.com

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AD7739

TABLE OF CONTENTS

AD7739—Specifications.................................................................. 3

Digital Interface Description ........................................................ 22

Timing Specifications....................................................................... 6

Absolute Maximum Ratings............................................................ 8

Typical Performance Characteristics ............................................. 9

Output Noise and Resolution Specification................................ 10

Chopping Enabled...................................................................... 10

Chopping Disabled..................................................................... 11

Pin Configuration and Function Descriptions........................... 12

Communications Register......................................................... 15

I/O Port Register......................................................................... 16

Revision Register ........................................................................16

Test Register ................................................................................ 16

ADC Status Register................................................................... 17

Checksum Register..................................................................... 17

Hardware ..................................................................................... 22

Reset ............................................................................................. 23

Access the AD7739 Registers.................................................... 23

Single Conversion and Reading Data...................................... 23

Dump Mode................................................................................ 23

Continuous Conversion Mode ................................................. 24

Continuous Read (Continuous Conversion) Mode .............. 25

Circuit Description......................................................................... 26

Analog Inputs.............................................................................. 26

Sigma-Delta ADC....................................................................... 26

Chopping..................................................................................... 26

Multiplexer, Conversion, and Data Output Timing............... 27

Frequency Response .................................................................. 28

Analog Input’s Extended Voltage Range ................................. 29

Voltage Reference Inputs........................................................... 29

ADC Zero-Scale Calibration Register ..................................... 17

ADC Full-Scale Calibration Register....................................... 17

Channel Data Registers ............................................................. 17

Channel Zero-Scale Calibration Registers.............................. 18

Channel Full-Scale Calibration Registers................................ 18

Channel Status Registers ...........................................................18

Channel Setup Registers............................................................ 19

Channel Conversion Time Registers ....................................... 20

Mode Register ............................................................................. 20

REVISION HISTORY

Revision 0: Initial Version

Reference Detect......................................................................... 29

I/O Port........................................................................................ 29

Calibration................................................................................... 30

ADC Zero-Scale Self-Calibration ........................................ 30

ADC Full-Scale Self-Calibration.......................................... 30

Per Channel System Calibration .......................................... 30

Outline Dimensions....................................................................... 32

ESD Caution................................................................................ 32

Ordering Guide .......................................................................... 32

Rev. 0 | Page 2 of 32

Page 3

AD7739

AD7739—SPECIFICATIONS

Table 1. (–40°C to +105°C; AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; REFIN(+) = 2.5 V; REFIN(–) = 0 V, AINCOM = 2.5 V; Internal Buffer On, AIN Range = ±1.25 V; f

Parameter Min Typ Max Unit Test Conditions/Comments

ADC PERFORMANCE CHOPPING ENABLED

Conversion Time Rate 372 11840 Hz Configure via Conv. Time Register No Missing Codes

1, 2

24 Bits

Output Noise See Table 4 Resolution

See Table 5

and Table 6 Integral Nonlinearity (INL)2 ±5 ±0.0015 % of FSR Offset Error (Unipolar, Bipolar)3 ±10 µV Before Calibration Offset Drift vs. Temperature1 ±25 nV/°C Gain Error3 ±0.2 % Before Calibration Gain Drift vs. Temperature1 ±2.5 ppm of FS/°C Positive Full-Scale Error3 ±0.2 % of FSR Before Calibration Positive Full-Scale Drift vs. Temp.1 ±2.5 ppm of FS/°C Bipolar Negative Full-Scale Error4 ±0.0030 % of FSR After Calibration Common-Mode Rejection 80 95 dB At DC, AIN = 1 V Power Supply Rejection 70 80 dB At DC, AIN = 1 V

ADC PERFORMANCE CHOPPING DISABLED

Conversion Time Rate 737 15133 Hz Configure via Conv. Time Register No Missing Codes

1, 2

24 Bits

Output Noise See Table 7 Resolution

See Table 8

and Table 9 Integral Nonlinearity (INL)2 ±0.0015 % of FSR Offset Error (Unipolar, Bipolar)5 ±1mV mV Before Calibration Offset Drift vs. Temperature ±1.5 µV/°C Gain Error3 ±0.2 % Before Calibration Gain Drift vs. Temperature ±2.5 ppm of FS/°C Positive Full-Scale Error3 ±0.2 % of FSR Before Calibration Positive Full-Scale Drift vs. Temp. ±2.5 ppm of FS/°C Bipolar Negative Full-Scale Error4 ±0.0030 % of FSR After Calibration Common-Mode Rejection 75 dB At DC, AIN = 1 V Power Supply Rejection 65 dB At DC, AIN = 1 V

ANALOG INPUTS

Analog Input Voltage

1, 6

±2.5 V Range ±2.5 V +2.5 V Range 0 to +2.5 V ±1.25 V Range ±1.25 V +1.25 V Range 0 to +1.25 V ±0.625 V Range ±0.625 V +0.625 V Range 0 to +0.625 V

AIN, AINCOM Common-Mode/ Absolute Voltage

Analog Input Slew Rate AIN, AINCOM Input Current

1, 7

0.5 V/Conv. Time AIN Absolute Voltage > 3 V

1, 8

1 5 nA Only One Channel, Chop Disabled

0.2 AV

= 6.144 MHz; unless otherwise noted.)

MCLKIN

FW ≥ 12 (Conversion Time ≥ 290 µs)

– 0.3 V

Rev. 0 | Page 3 of 32

Page 4

AD7739

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE INPUTS

REFIN(+) to REFIN(–) Voltage NOREF Trigger Voltage 0.5 V NOREF Bit in Channel Status Register REFIN(+), REFIN(–) Common-Mode/

Absolute Voltage

Reference Input DC Current10 400 µA

SYSTEM CALIBRATION

1, 11

Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span

LOGIC INPUTS

Input Current Input Current CS

–40 µA

Input Capacitance 5 pF

1.4 2 V DVDD = 5 V

T+

0.8 1.4 V DVDD = 5 V

T–

VT+ – V V

0.3 0.85 V DVDD = 5 V

T–

0.95 2 V DVDD = 3 V

T+

VT– 1 0.4 1.1 V DVDD = 3 V VT+ – V

0.3 0.85 V DVDD = 3 V

T–

MCLK IN ONLY

Input Current Input Capacitance 5 pF

Input Low Voltage 0.8 V DVDD = 5 V

INL

Input High Voltage 3.5 V DVDD = 5 V

INH

Input Low Voltage 0.4 V DVDD = 3 V

INL

Input High Voltage 2.5 V DVDD = 3 V

INH

LOGIC OUTPUTS12

VOL Output Low Voltage 0.4 V I VOH Output High Voltage 4.0 V I VOL Output Low Voltage 0.4 V I VOH Output High Voltage DVDD – 0.6 V I Floating State Leakage Current

Floating State Leakage Capacitance 3 pF

P0, P1 INPUTS/OUTPUTS Levels Referenced to Analog Supplies

Input Current V

Input Low Voltage 0.8 V AVDD = 5 V

INL

Input High Voltage 3.5 V AVDD = 5 V

INH

VOL Output Low Voltage 0.4 V I VOH Output High Voltage 4.0 V I

1, 9

2.475 2.5 2.525 V

0 AV

µA µA

CS = DVDD

= DGND, Internal Pull-Up Resistor

µA

= 800 µA, DVDD = 5 V

SINK

= 200 µA, DVDD = 5 V

SOURCE

= 100 µA, DVDD = 3 V

SINK

= 100 µA, DVDD = 3 V

SOURCE

µA

= 8 mA, AVDD = 5 V

SINK

= 200 µA, AVDD = 5 V

SOURCE

–1.05 × FS

0.8 × FS

+1.05 × FS

2.1 × FS

±1 ±10

±10

±1

±10

Rev. 0 | Page 4 of 32

Page 5

AD7739

Parameter Min Typ Max Unit Test Conditions/Comments

POWER REQUIREMENTS

AVDD to AGND Voltage 4.75 5.25 V DVDD to DGND Voltage 4.75 5.25 V

2.70 3.60 V AVDD Current (Normal Mode) 13.6 16 mA AVDD Current (Reduced Power Mode) 9.2 11 mA MCLK = 4 MHz AVDD Current (Internal Buffer Off) 8.5 mA DVDD Current (Normal Mode) DVDD Current (Normal Mode) 13 1.0 1.5 mA DVDD = 3 V Power Dissipation (Normal Mode) Power Dissipation

(Reduced Power Mode) Power Dissipation

(Reduced Power Mode) AVDD + DVDD Current

(Standby Mode)

Power Dissipation (Standby Mode)14 500 µW

2.7 3 mA DVDD = 5 V

85 100 mW

60 70 mW DV

50 mW DVDD = 3 V, MCLK = 4 MHz

80 µA

= 5 V, MCLK = 4 MHz

Specification is not production tested, but is supported by characterization data at initial product release.

See Typical Performance Characteristics.

Specifications before calibration. Channel system calibration reduces these errors to the order of the noise.

Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error.

Specifications before calibration. ADC zero-scale self-calibration or channel zero-scale system calibration reduce this error to the order of the noise.

For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for details.

For specified performance. If the analog input absolute voltage (referred to AGND) changes more than 0.5 V during one conversion time, the result could be affected by distortion in the input buffer. This limit does not apply to analog input absolute voltages below 3 V.

If chopping is enabled or when switching between channels, a dynamic current charges the capacitance of the multiplexer. See the circuit description for details.

For specified performance. Part is functional with lower V

Dynamic current charging the sigma-delta modulator input switching capacitor.

Outside the specified calibration range, calibration is possible but the performance may degrade.

These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.

With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register).

External MCLKIN = 0 V or DVDD, digital inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD.

REF

Rev. 0 | Page 5 of 32

Page 6

AD7739

TIMING SPECIFICATIONS

Table 2. (AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DVDD; unless otherwise noted.)

Parameter Min Typ Max Unit Test Conditions/Comments

Master Clock Range 1 6.144 MHz

1 4 MHz Reduced Power Mode t1 50 ns

t2 500 ns

Read Operation

t4 0 ns

SCLK Falling Edge to Data Valid Delay

0 60 ns DVDD of 4.75 V to 5.25 V 0 80 ns DVDD of 2.7 V to 3.3 V

2, 3

0 60 ns DVDD of 4.75 V to 5.25 V 0 80 ns DVDD of 2.7 V to 3.3 V

t6 50 ns SCLK High Pulsewidth t7 50 ns SCLK Low Pulsewidth t8 0 ns

10 80 ns Bus Relinquish Time after SCLK Rising Edge

Write Operation

t11 0 ns t12 30 ns Data Valid to SCLK Rising Edge Setup Time

t13 25 ns Data Valid after SCLK Rising Edge Hold Time t14 50 ns SCLK High Pulsewidth t15 50 ns SCLK Low Pulsewidth t16 0 ns

Pulsewidth

SYNC

Pulsewidth

RESET

Falling Edge to SCLK Falling Edge Setup Time

Falling Edge to Data Valid Delay

Rising Edge after SCLK Rising Edge Hold Time

Falling Edge to SCLK Falling Edge Setup

Rising Edge after SCLK Rising Edge Hold Time

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of

1.6 V. See Figure 2 and Figure 3.

These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the VOL or VOH limits.

This specification is relevant only if CS goes low while SCLK is low.

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then

extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Specifications are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.

Rev. 0 | Page 6 of 32

Page 7

AD7739

SCLK

DOUT MSB LSB

Figure 2. Read Cycle Timing Diagram

CLK

DIN

MSB

Figure 3. Write Cycle Timing Diagram

LSB

03742-0-002

03742-0-003

(800µA AT DVDD = 5V

SINK

O OUTPUT

50pF

100µA AT DV

(200µA AT DVDD = 5V

SOURCE

100µA AT DV

1.6V

= 3V)

03742-0-004

Figure 4. Load Circuit for Access Time and Bus Relinquish Time

Rev. 0 | Page 7 of 32

Page 8

AD7739

ABSOLUTE MAXIMUM RATINGS

Table 3. (TA = 25°C, unless otherwise noted.)

Parameter Rating

AVDD to AGND, DVDD to DGND –0.3 V to +7 V AGND to DGND –0.3 V to +0.3 V AVDD to DVDD –5 V to +5 V AIN, AINCOM to AGND –0.3 V to AVDD + 0.3 V REFIN+, REFIN– to AGND –0.3 V to AVDD + 0.3 V P0, P1 Voltage to AGND –0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND –0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND –0.3 V to DVDD + 0.3 V ESD Rating (ESD Association Human Body Model, S5.1) 4000 V Operating Temperature Range –40°C to +105°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C

TSSOP Package θJA Thermal Impedance Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

128°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. 0 | Page 8 of 32

Page 9

AD7739

TYPICAL PERFORMANCE CHARACTERISTICS

NO MISSING CODES

5 6 7 8 9 101112131415

CHOP = 1

FILTER WORD

03742-0-005

Figure 5. No Missing Codes Performance, Chopping Enabled

NO MISSING CODES

5 6 7 8 9 101112131415

CHOP = 0

FILTER WORD

03742-0-006

Figure 6. No Missing Codes Performance, Chopping Disabled

–20

–40

–60

–80

–100

GAIN (dB)

–120

–140

–160

–180

0 200 400 600 800 1000 1200 1400

THD = 110dB

INPUT FREQUENCY (Hz)

03742-0-007

Figure 7. Typical FFT Plot; Input Sine Wave 183 Hz,1.2 V Peak, AIN Range ±1.25 V, Conversion Time 397 µs, Chopping Enabled, MCLK = 6.144 MHz

CHOP = 1

RESOLUTION (bits)

EFFECTIVE (rms)

p-p

1068240 121416

OUTPUT DATA RATE (kHz)

03742-0-008

Figure 8. Typical Effective and Peak-to-Peak Resolution; AIN Voltage = 0 V,

AIN Range ±1.25 V, Chopping Enabled, MCLK = 6.144 MHz

CHOP = 0

RESOLUTION (bits)

EFFECTIVE (rms)

p-p

1068240 121416

OUTPUT DATA RATE (kHz)

03742-0-009

Figure 9. Typical Effective and Peak-to-Peak Resolution; AIN Voltage = 0 V,

AIN Range ±1.25 V, Chopping Disabled, MCLK = 6.144 MHz

120

CHOP = 1

110

100

CMR (dB)

AIN DIFFERENTIAL VOLTAGE (V)

0–0.5–1.0–1.5 0.5 1.0 1.5

03742-0-010

Figure 10. Typical Common-Mode Rejection vs. AIN Voltage; AIN Range

±1.25 V, Conversion Time 397 µs, Chopping Enabled, MCLK = 6.144 MHz

Rev. 0 | Page 9 of 32

Page 10

AD7739

OUTPUT NOISE AND RESOLUTION SPECIFICATION

The AD7739 can be operated with chopping enabled or disabled, allowing the ADC to be programmed to optimize either the offset drift performance or the throughput rate and channel switching time. Noise tables for these two primary modes of operation are outlined below for a selection of output rates and settling times.

The AD7739 noise performance depends on the selected chopping mode, the filter word (FW) value, and the selected analog input range. The AD7739 noise will not vary significantly with MCLK frequency.

CHOPPING ENABLED

The first mode, in which the AD7739 is configured with chopping enabled (CHOP = 1), provides very low noise with lower output rates.

Table 4. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Enabled

Conversion

Time

127 0xFF 2689 372 200 1.8 1.1

46 0xAE 1001 999 500 2.7 1.7 17 0x91 397 2519 1325 4.8 2.7 10 0x8A 251 3982 2209 9.3 4.7

9 0x89 230 4342 2450 10.8 6.3 2 0x82 84 11838 9500 600 460

Time

(µs)

Output Data

Rate

(Hz)

–3 dB

Frequency

(Hz)

Table 4 to Table 6 show the –3 dB frequencies and typical performance versus the channel conversion time and equivalent output data rate, respectively.

Table 4 shows the typical output rms noise. Table 5 shows the typical effective resolution based on rms noise. Table 6 shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a 6-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise but on peak-to-peak noise.

These typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input voltage set to 0 V and MCLK = 6.144 MHz. The conversion time is selected via the channel conversion time register.

Input Range / RMS Noise (µV) FW Conversion

±2.5 V, +2.5 V ±1.25 V, +1.25 V, ±0.625 V, +0.625 V

Table 5. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled

Conversion

Time

127 0xFF 2689 372 200 21.4 20.4 21.2 20.2 20.2 19.2

46 0xAE 1001 999 500 20.8 19.8 20.5 19.5 19.5 18.5

17 0x91 397 2519 1325 20.0 19.0 19.8 18.8 18.8 17.8

10 0x8A 251 3982 2209 19.0 18.0 19.0 18.0 18.0 17.0

9 0x89 230 4342 2450 18.8 17.8 18.6 17.6 17.6 16.6

2 0x82 84 11838 9500 12.9 11.9 12.4 11.4 11.4 10.4

Time

(µs)

Output Data

Rate

(Hz)

–3 dB

Frequency

(Hz)

±2.5 V +2.5 V ±1.25 V +1.25 V ±0.625 V +0.625 V

Input Range / Effective Resolution (Bits) FW Conversion

Table 6. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled

Conversion

Time

127 0xFF 2689 372 200 18.6 17.6 18.3 17.3 17.3 16.3

46 0xAE 1001 999 500 17.9 16.9 17.6 16.6 16.6 15.6

17 0x91 397 2519 1325 17.1 16.1 16.9 15.9 15.9 14.9

10 0x8A 251 3982 2209 16.2 15.2 16.2 15.2 15.2 14.2

9 0x89 230 4342 2450 16.0 15.0 15.8 14.8 14.8 13.8

2 0x82 84 11838 9500 10.7 9.7 9.7 8.7 8.7 7.7

Time

(µs)

Output Data

Rate

(Hz)

–3 dB

Frequency

(Hz)

Input Range / Peak-to-Peak Resolution (Bits) FW Conversion

±2.5 V +2.5 V ±1.25 V +1.25 V ±0.625 V +0.625 V

Rev. 0 | Page 10 of 32

Page 11

AD7739

CHOPPING DISABLED

The second mode, in which the AD7739 is configured with chopping disabled (CHOP = 0), provides faster conversion time while maintaining high resolution. Table 7 to Table 9 show the –3 dB frequencies and typical performance versus the channel conversion time and equivalent output data rate, respectively. Table 7 shows the typical output rms noise. Table 8 shows the typical effective resolution based on the rms noise.

Table 7. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Disabled

Conversion

Time

127 0x7F 1358 737 675 2.4 1.5

92 0x5C 993 1007 950 3.0 1.8 35 0x23 399 2504 2500 4.5 2.7 16 0x10 201 4963 5400 6.9 4.1 12 0x0C 160 6257 7250 9.6 5.3 11 0x0B 149 6693 7900 11.4 6.9

3 0x03 66 15133 29000 200 90

Time

(µs)

Output Data

Rate

(Hz)

–3 dB

Frequency

(Hz)

Table 9 shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a 6-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise but on peak-to-peak noise.

Input Range / RMS Noise (µV) FW Conversion

±2.5 V, +2.5 V ±1.25 V, +1.25 V, ±0.625 V, +0.625 V

Table 8. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled

Conversion

Time

127 0x7F 1358 737 675 21.0 20.0 20.6 19.6 19.6 18.6

92 0x5C 993 1007 950 20.7 19.7 20.4 19.4 19.4 18.4

35 0x23 399 2504 2500 20.1 19.1 19.8 18.8 18.8 17.8

16 0x10 201 4963 5400 19.4 18.4 19.2 18.2 18.2 17.2

12 0x0C 160 6257 7250 18.9 17.9 18.8 17.8 17.8 16.8

11 0x0B 149 6693 7900 18.8 17.8 18.5 17.5 17.5 16.5

3 0x03 66 15133 29000 14.6 13.6 14.7 13.7 13.7 12.7

Time

(µs)

Output Data

Rate

(Hz)

–3 dB

Frequency

(Hz)

±2.5 V +2.5 V ±1.25 V +1.25 V ±0.625 V +0.625 V

Input Range / Effective Resolution (Bits) FW Conversion

Table 9. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled

Conversion

Time

127 0x7F 1358 737 675 18.2 17.2 17.8 16.8 16.8 15.8

92 0x5C 993 1007 950 17.8 16.8 17.6 16.6 16.6 15.6

35 0x23 399 2504 2500 17.2 16.2 17.0 16.0 16.0 15.0

16 0x10 201 4963 5400 16.6 15.6 16.4 15.4 15.4 14.4

12 0x0C 160 6257 7250 16.1 15.1 16.0 15.0 15.0 14.0

11 0x0B 149 6693 7900 16.0 15.0 15.7 14.7 14.7 13.7

3 0x03 66 15133 29000 11.7 10.7 12.0 11.0 11.0 10.0

Time

(µs)

Output Data

Rate

(Hz)

–3 dB

Frequency

(Hz)

Input Range / Peak-to-Peak Resolution (Bits) FW Conversion

±2.5 V +2.5 V ±1.25 V +1.25 V ±0.625 V +0.625 V

Rev. 0 | Page 11 of 32

Page 12

AD7739

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK

MCLKIN

MCLKOUT

RESET

AINCOM/P0

SYNC/P1

AIN7

AIN6

AIN5

AIN4

AD7739

TOP VIEW

(Not to Scale)

DGND

DIN

DOUT

RDY

AGND

REFIN(–)

REFIN(+)

AIN0

AIN1

AIN2

AIN3

03742-0-011

Figure 11. Pin Configuration (24-Lead TSSOP)

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AINCOM/P0

SYNC/P1

MUX

I/O PORT

BUFFER

AD7739

CALIBRATION

CIRCUITRY

CLOCK

GENERATOR

REFIN(–) REFIN(+)

REFERENCE

DETECT

24-BIT

Σ-∆ ADC

SERIAL

INTERFACE

CONTROL

LOGIC

SCLK

DOUT

DIN

RESET

RDY

Figure 12. Block Diagram

Table 10. Pin Function Descriptions

Pin No. Mnemonic Description

1 SCLK

Serial Clock. Schmitt triggered logic input. An external serial clock is applied to this input to transfer serial data to or from the AD7739.

2 MCLKIN

Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins. Alternatively, MCLKIN can be driven with a CMOS compatible clock and MCLKOUT can be left unconnected.

3 MCLKOUT

Master Clock Signal for the ADC. When the master clock for the device is a crystal/ resonator, the crystal/resonator is connected between MCLKIN and MCLKOUT. If an external clock is applied to the MCLKIN, MCLKOUT provides an inverted clock signal or can be switched off to reduce the device power consumption. MCLKOUT can drive one CMOS load.

Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor.

With this input hardwired low, the AD7739 can operate in its 3-wire interface mode using SCLK, DIN, and DOUT. CS

can be used to select the device in systems with more than one

device on the serial bus. It can also be used as an 8-bit frame synchronization signal.

Schmitt Triggered Logic Input. Active low input that resets the control logic, interface

RESET

logic, digital filter, analog modulator, and all on-chip registers of the part to power-on status. Effectively, everything on the part except the clock oscillator is reset when the RESET

pin is exercised.

6 AVDD Analog Positive Supply Voltage, 5 V to AGND Nominal. 7 AINCOM/P0

Analog Inputs Common Terminal/Digital Output. The function of this pin is determined by the P0 DIR bit in the I/O port register; the digital value can be written as the P0 bit in the I/O port register. The digital voltage is referenced to analog supplies. When configured as an input (P0 DIR bit set to 1), the single-ended analog inputs 0 to 7 (AIN0–AIN7) can be referenced to this pin’s voltage level.

DGND DV

MCLKINMCLKOUTAGND AV

03742-0-012

Rev. 0 | Page 12 of 32

Page 13

AD7739

Pin No. Mnemonic Description

9–16 AIN0–AIN7 Analog Inputs. 17 REFIN(+)

18 REFIN(–)

19 AGND Ground Reference Point for Analog Circuitry. 20

21 DOUT

22 DIN

23 DVDD Digital Supply Voltage, 3 V or 5 V Nominal. 24 DGND Ground Reference Point for Digital Circuitry.

/P1 SYNC/Digital Input/Digital Output. The pin direction is determined by the P1 DIR bit;

SYNC

the digital value can be read/written as the P1 bit in the I/O port register. When the SYNC bit in the I/O port register is set to 1, then the SYNC the AD7739 modulator and digital filter with other devices in the system. The digital voltage is referenced to the analog supplies. When configured as an input, the pin should be tied high or low.

Positive Terminal of the Differential Reference Input. REFIN(+) voltage potential can lie anywhere between AVDD and AGND. In normal circuit configuration, this pin should be connected to a 2.5 V reference voltage.

Negative Terminal of the Differential Reference Input. REFIN(–) voltage potential can lie anywhere between AV connected to a 0 V reference voltage.

Logic Output. Used as a status output in both conversion mode and calibration mode. In

RDY

conversion mode, a falling edge on this output indicates that either any channel or all channels have unread data available, according to the RDYFN bit in the I/O port register. In calibration mode, a falling edge on this output indicates that calibration is complete (see the Digital Interface Description section for details).

Serial Data Output. Serial data is read from the output shift register on the part. This output shift register can contain information from any AD7739 register, depending on the address bits of the communications register.

Serial Data Input (Schmitt Triggered). Serial data is written to the input shift register on the part. Data from this input shift register is transferred to any AD7739 register, depending on the address bits of the communications register.

and AGND. In normal circuit configuration, this pin should be

/P1 pin can be used to synchronize

Rev. 0 | Page 13 of 32

Page 14

AD7739

REGISTER DESCRIPTIONS

Table 11. Register Summary

Communications 0x00 W

I/O Port 0x01 R/W

Revision 0x02 R

Test 0x03 R/W

ADC Status 0x04 R

Checksum 0x05 R/W

ADC Zero-Scale Calibration 0x06 R/W

ADC Full-Scale Calibration 0x07 R/W

Channel Data1 0x08–0x0F R

Channel Zero-Scale Cal.1 0x10–0x17 R/W

Channel Full-Scale Cal.1 0x18–0x1F R/W

Channel Status1 0x20–0x27 R

Channel Setup1 0x28–0x2F R/W

Channel Conversion Time1 0x30–0x37 R/W

Mode2 0x38–0x3F R/W

The three LSBs of the register address, i.e., Bit 2, Bit 1, and Bit 0 in the communications register, specify the channel number of the register being accessed.

The AD7739 has only one mode register, although the mode register can be accessed in one of eight address locations. The address used to write the mode register

specifies the ADC channel on which the mode will be applied. Only address 0x38 must be used for reading from the mode register.

Table 12. Operational Mode Summary

MD2 MD1 MD0 Mode

0 0 0 Idle 0 0 1 Continuous Conversion 0 1 0 Single Conversion 0 1 1 Power-Down (Standby) 1 0 0 ADC Zero-Scale Self-Calibration 1 0 1 ADC Full-Scale Self-Calibration (for 2.5 V) 1 1 0 Channel Zero-Scale System Calibration 1 1 1 Channel Full-Scale System Calibration

(hex) Default Value

R/W

6-Bit Register Address

P0 P1 P0 DIR P1 DIR RDYFN REDPWR 0 SYNC

P0 Pin P1 Pin 1 1 0 0 0 0

Chip Revision Code Chip Generic Code

x x x x 1 0 0 1

24-Bit Manufacturing Test Register

RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0

0 0 0 0 0 0 0 0

16-Bit Checksum Register

24-Bit ADC Zero-Scale Calibration Register

0x80 0000

24-Bit ADC Full-Scale Register

0x80 0000

16-/24-Bit Data Registers

0x8000

24-Bit Channel Zero-Scale Calibration Registers

0x80 0000

24-Bit Channel Full-Scale Calibration Registers

0x20 0000

CH2 CH1 CH0 0/P0 RDY/P1 NOREF SIGN OVR

Channel Number 0 0 0 0 0

BUFOFF COM1 COM0 Stat OPT ENABLE RNG2 RNG1 RNG0

0 0 0 0 0 0 0 0

CHOP FW (7-Bit Filter Word)

1 0x11

MD2 MD1 MD0 CLKDIS DUMP Cont RD 24/16 BIT CLAMP

0 0 0 0 0 0 0 0

Table 13. Input Range Summary

RNG2 RNG1 RNG0 Nominal Input Voltage Range

1 0 0 ±2.5 V 1 0 1 +2.5 V 0 0 0 ±1.25 V 0 0 1 +1.25 V 0 1 0 ±0.625 V 0 1 1 +0.625 V

Rev. 0 | Page 14 of 32

Page 15

AD7739

REGISTER ACCESS

The AD7739 is configurable through a series of registers. Some of them configure and control general AD7739 features, while others are specific to each channel. The register data widths vary from 8 bits to 24 bits. All registers are accessed through the communications register, i.e., any communication to the AD7739 must start with a write to the communications register specifying which register will be subsequently read or written.

COMMUNICATIONS REGISTER

8 Bits, Write-Only Register, Address 0x00

All communications to the part must start with a write operation to the communications register. The data written to

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic 0

Bit Mnemonic Description

7 0 This bit must be 0 for proper operation. 6

5–0 Address

A 0 in this bit indicates that the next operation will be a write to a specified register.

R/W

A 1 in this bit indicates that the next operation will be a read from a specified register. These bits specify to which register the read or write operation will be directed. For channel specific registers,

the three LSBs, i.e., Bit2, Bit 1, and Bit 0, specify the channel number. When the subsequent operation writes to the mode register, the three LSBs specify the channel selected for the operation determined by the mode register value. The analog inputs configuration depends on the COM1 and COM0 bits in the channel setup register.

Bit 2 Bit 1 Bit 0 Channel Single Input Differential Input

0 0 0 0 AIN0–AINCOM AIN0–AIN1 0 0 1 1 AIN1–AINCOM AIN2–AIN3 0 1 0 2 AIN2–AINCOM AIN4–AIN5 0 1 1 3 AIN3–AINCOM AIN6–AIN7 1 0 0 4 AIN4–AINCOM AIN0–AIN1 1 0 1 5 AIN5–AINCOM AIN2–AIN3 1 1 0 6 AIN6–AINCOM AIN4–AIN5 1 1 1 7 AIN7–AINCOM AIN6–AIN7

R/W

the communications register determines whether the subsequent operation will be a read or write and to which register this operation will be directed. The digital interface defaults to expect a write operation to the communications register after power-on, after reset, or after the subsequent read or write operation to the selected register is complete. If the interface sequence is lost, the part can be reset by writing at

least 32 serial clock cycles with DIN high and

low. (Note that all of the parts, including the modulator, filter, interface, and all registers are reset in this case.) Remember to keep DIN low while reading 32 bits or more either in continuous read mode or with the DUMP bit and 24/16 bit in the mode register set.

6-Bit Register Address

Rev. 0 | Page 15 of 32

Page 16

AD7739

I/O PORT REGISTER

8 Bits, Read/Write Register, Address 0x01, Default Value 0x30 + Digital Input Value × 0x40

The bits in this register are used to configure and access the digital I/O port on the AD7739.

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic P0 P1 P0 DIR P1 DIR RDYFN REDPWR 0 SYNC Default P0 Pin P1 Pin 1 1 0 0 0 0

Bit Mnemonic Description

7, 6 P0, P1

5, 4 P0 DIR, P1 DIR

3 RDYFN

2 REDPWR

1 0 This bit must be 0 for proper operation. 0 SYNC

When the P0 and P1 pins are configured as outputs, the P0 and P1 bits determine the pins’ output level. When the P0 and P1 pins are configured as inputs, the P0 and P1 bits reflect the current input level on the pins.

These bits determine whether the P0 and P1 pins are configured as inputs or outputs. When set to 1, the corresponding pin will be an input; when reset to 0, the corresponding pin will be an output.

This bit is used to control the function of the RDY goes low when any channel has unread data. When this bit is set to 1, the RDY enabled channels have unread data.

Reduced Power. If this bit is set to 1, the AD7739 works in the reduced power mode. The maximum MCLK frequency is limited to 4 MHz in the reduced power mode.

This bit enables the SYNC When the SYNC bit is set to 1, the SYNC filter with other devices in the system.

pin function. By default, this bit is 0 and SYNC/P1 can be used as a digital I/O pin.

pin can be used to synchronize the AD7739 modulator and digital

pin on the AD7739. When this bit is reset to 0, the RDY pin

pin will go low only if all

REVISION REGISTER

8 Bits, Read-Only Register, Address 0x02, Default Value 0x09 + Chip Revision × 0x10

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic Chip Revision Code Chip Generic Code Default x x x x 1 0 0 1

Bit Mnemonic Description

7–4 Chip Revision Code 4-Bit Factory Chip Revision Code 3–0 Chip Generic Code On the AD7739, these bits will read back as 0x09.

TEST REGISTER

24 Bits, Read/Write Register, Address 0x03

This register is used for testing the part in the manufacturing process. The user must not change the default configuration of this register.

Rev. 0 | Page 16 of 32

Page 17

AD7739

ADC STATUS REGISTER

8 Bits, Read-Only Register, Address 0x04, Default Value 0x00

In conversion modes, the register bits reflect the individual channel status. When a conversion is complete, the corresponding channel data register is updated and the corresponding RDY bit is set to 1. When the channel data register is read, the corresponding bit is reset to 0. The bit is reset to 0 also when no read operation has taken place and the result of the next conversion is being updated to the channel data register. Writing to the mode register resets all the bits to 0.

In calibration modes, all the register bits are reset to 0 while a calibration is in progress; all the register bits are set to 1 when the calibration is complete.

The bit corresponds to Channel 0, the RDY1 bit corresponds to Channel 1, and so on.

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 Default 0 0 0 0 0 0 0 0

CHECKSUM REGISTER

16 Bits, Read/Write Register, Address 0x05

This register is described in the Using the AD7732/AD7734/ AD7738/AD7739 Checksum Register application note

(www.analog.com/UploadedFiles/Application_Notes/71751876

AN626_0.pdf).

ADC ZERO-SCALE CALIBRATION REGISTER

24 Bits, Read/Write Register, Address 0x06, Default Value 0x80 0000

This register holds the ADC zero-scale calibration coefficient. The value in this register is used in conjunction with the value in the ADC full-scale calibration register and the corresponding channel zero-scale and channel full-scale calibration registers to scale digitally the conversion results of all channels. The value in this register is updated automatically following the execution of an ADC zero-scale self-calibration. Writing this register is possible in the idle mode only (see the Calibration section for details).

pin output is related to the content of the ADC status register as defined by the RDYFN bit in the I/O port register. The RDY0

RDY

CHANNEL DATA REGISTERS

16 Bit/24 Bit, Read-Only Registers, Address 0x08–0x0F, Default Width 16 Bits, Default Value 0x8000

These registers contain the most up-to-date conversion results corresponding to each analog input channel. The 16-bit or 24-bit data width can be configured by setting the 24/16 bit in the mode register. The relevant RDY bit in the channel status register goes high when the result is updated. The RDY bit will return low once the data register reading has begun. The

pin can be configured to indicate when any channel has unread data or waits until all enabled channels have unread data. If any channel data register read operation is in progress when a new result is updated, no update of the data register will occur. This avoids having corrupted data. Reading the status registers can be associated with reading the data registers in the dump mode. Reading the status registers is always associated with reading the data registers in the continuous read mode (see the Digital Interface Description section for details).

RDY

ADC FULL-SCALE CALIBRATION REGISTER

24 Bits, Read/Write Register, Address 0x07, Default Value 0x80 0000

This register holds the ADC full-scale calibration coefficient. The value in this register is used in conjunction with the value in the ADC zero-scale and the corresponding channel zero-scale and channel full-scale calibration registers to scale digitally the conversion results of all channels. The value in this register is updated automatically following the execution of an ADC full-scale self-calibration. Writing this register is possible in the idle mode only. The ADC full-scale self-calibration should be used only on +2.5 V and ±2.5 V input voltage ranges (see the Calibration section for details).

Rev. 0 | Page 17 of 32

Page 18

AD7739

CHANNEL ZERO-SCALE CALIBRATION REGISTERS

24 Bits, Read/Write Registers, Address 0x10–0x17, Default Value 0x80 0000

CHANNEL FULL-SCALE CALIBRATION REGISTERS

24 Bits, Read/Write Registers, Address 0x18–0x1F, Default Value 0x20 0000

These registers hold the particular channel zero-scale calibration coefficients. The value in these registers is used in conjunction with the value in the corresponding channel fullscale calibration register, the ADC zero-scale calibration register, and the ADC full-scale calibration register to digitally scale the particular channel conversion results. The value in this register is updated automatically following the execution of a channel zero-scale system calibration.

The format of the channel zero-scale calibration register is a

These registers hold the particular channel full-scale calibration coefficients. The value in these registers is used in conjunction with the value in the corresponding channel zero-scale calibration register, the ADC zero-scale calibration register, and the ADC full-scale calibration register to digitally scale the particular channel conversion results. The value in this register is updated automatically following the execution of a channel full-scale system calibration. Writing this register is possible in the idle mode only (see the Calibration section for details).

sign bit and a 22-bit unsigned value. Writing this register is possible in the idle mode only (see the Calibration section for details).

CHANNEL STATUS REGISTERS

8 Bits, Read-Only Registers, Address 0x20–0x27, Default Value 0x20 × Channel Number

These registers contain individual channel status information and some general AD7739 status information. Reading the status registers can be associated with reading the data registers in the dump mode. Reading the status registers is always associated with reading the data registers in the continuous read mode (see the Digital Interface Description section for details).

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic CH2 CH1 CH0 0/P0 RDY/P1 NOREF SIGN OVR Default Channel Number 0 0 0 0 0

Bit Mnemonic Description

7–5 CH2–CH0

4 0/P0

3 RDY/P1

2 NOREF

1 SIGN

0 OVR

These bits reflect the channel number. This can be used for current channel identification and easier operation of the dump mode and continuous read mode.

When the status option bit of the corresponding channel setup register is reset to 0, this bit is read as a 0. When the status option bit is set to 1, this bit reflects the state of the P0 pin, whether it is configured as an input or an output.

When the status option bit of the corresponding channel setup register is reset to 0, this bit reflects the selected channel RDY bit in the ADC status register. When the status option bit is set to 1, this bit reflects the state of the P1 pin, whether it is configured as an input or an output.

This bit indicates the reference input status. If the voltage between the REFIN(+) and REFIN(–) pins is less than NOREF, the trigger voltage, and a conversion is executed, then the NOREF bit goes to 1.

This bit reflects the voltage polarity at the analog input. It will be 0 for a positive voltage and 1 for a negative voltage.

This bit reflects either the overrange or the underrange on the analog input. The bit is set to 1 when the analog input voltage goes over or under the nominal voltage range (see the Analog Input’s Extended Voltage Range section).

Rev. 0 | Page 18 of 32

Page 19

AD7739

CHANNEL SETUP REGISTERS

8 Bits, Read/Write Registers, Address 0x28–0x2F, Default Value 0x00

These registers are used to configure the selected channel, to configure its input voltage range, and to set up the corresponding channel status register.

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic BUFOFF COM1 COM0 Stat OPT ENABLE RNG2 RNG1 RNG0 Default 0 0 0 0 0 0 0 0

Bit Mnemonic Description

7 BUFOFF Buffer Off. If reset to 0, then the internal buffer is enabled.

Operation only with the internal buffer enabled is recommended.

6–5 COM1, COM0 Analog inputs configuration:

COM1 COM0 COM1 COM0 Channel 0 0 1 1

0 AIN0–AINCOM AIN0–AIN1 1 AIN1–AINCOM AIN2–AIN3 2 AIN2–AINCOM AIN4–AIN5 3 AIN3–AINCOM AIN6–AIN7 4 AIN4–AINCOM AIN0–AIN1 5 AIN5–AINCOM AIN2–AIN3 6 AIN6–AINCOM AIN4–AIN5 7 AIN7–AINCOM AIN6–AIN7

4 Stat OPT

3 ENABLE

2–0 RNG2–RNG0 This is the channel input voltage range:

Status Option. When this bit is set to 1, the P0 and P1 bits in the channel status register will reflect the state of the P0 and P1 pins. When this bit is reset to 0, the RDY bit in the channel status register will reflect the channel corresponding to the RDY bit in the ADC status register.

Channel Enable. Set this bit to 1 to enable the channel in the continuous conversion mode. A single conversion will take place regardless of this bit’s value.

RNG2 RNG1 RNG0 Nominal Input Voltage Range

1 0 0 ±2.5 V 1 0 1 +2.5 V 0 0 0 ±1.25 V 0 0 1 +1.25 V 0 1 0 ±0.625 V 0 1 1 +0.625 V

Rev. 0 | Page 19 of 32

Page 20

AD7739

CHANNEL CONVERSION TIME REGISTERS

8 Bits, Read/Write Registers, Address 0x30–0x37h, Default Value 0x91

The conversion time registers enable or disable chopping and configure the digital filter for a particular channel. This register value affects the conversion time, frequency response, and noise performance of the ADC.

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic CHOP FW (7-Bit Filter Word) Default 1 0x11

Bit Mnemonic Description

7 CHOP Chopping Enable Bit. Set to 1 to apply chopping mode for a particular channel. 6–0 FW

CHOP = 1, single conversion or continuous conversion with one channel enabled. Conversion Time (µs) = (FW × 128 + 262)/MCLK Frequency (MHz), the FW range is 2 to 127.

CHOP = 1, continuous conversion with two or more channels enabled. Conversion Time (µs) = (FW × 128 + 263)/MCLK Frequency (MHz), the FW range is 2 to 127.

CHOP = 0, single conversion or continuous conversion with one channel enabled. Conversion Time (µs) = (FW × 64 + 213)/MCLK Frequency (MHz), the FW range is 3 to 127.

CHOP = 0, continuous conversion with two or more channels enabled. Conversion Time (µs) = (FW × 64 + 214)/MCLK Frequency (MHz), the FW range is 3 to 127.

MODE REGISTER

8 Bits, Read/Write Register, Address 0x38–0x3F, Default Value 0x00

The mode register configures the part and determines its operating mode. Writing to the mode register clears the ADC status register, sets the

The AD7739 contains only one mode register. The two LSBs of the address are used for writing to the mode register to specify the channel selected for the operation determined by the MD2 to MD0 bits. Only the address 0x38 must be used for reading from the mode register.

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic MD2 MD1 MD0 CLKDIS DUMP Cont RD 24/16 BIT CLAMP Default 0 0 0 0 0 0 0 0

Bit Mnemonic Description

7–5 MD2–MD0

pin to a logic high level, exits all current operations, and starts the mode specified by the mode bits.

RDY

Mode Bits. These three bits determine the AD7739 operation mode. Writing a new value to the mode bits will exit the part from the mode in which it has been operating and place it in the newly requested mode immediately. The function of the mode bits is described in more detail below.

MD2 MD1 MD0 Mode Address Used for Mode Register

Write Specifies:

0 0 0 Idle 0 0 1 Continuous Conversion First Channel to Start Converting 0 1 0 Single Conversion Channel to Convert 0 1 1 Power-Down (Standby) 1 0 0 ADC Zero-Scale Self-Calibration Conversion Time for Calibration 1 0 1 ADC Full-Scale Self-Calibration (for 2.5 V) Conversion Time for Calibration 1 1 0 Channel Zero-Scale System Calibration Channel to Calibrate 1 1 1 Channel Full-Scale System Calibration Channel to Calibrate

Rev. 0 | Page 20 of 32

Page 21

AD7739

Bit Mnemonic Description

4 CLKDIS

3 DUMP

2 Cont RD

1 24/16 BIT

0 CLAMP

MD2 MD1 MD0 Operating Mode Description

0 0 0 Idle

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Master Clock Output Disable. When this bit is set to 1, the master clock is disabled from appearing at the MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the MCLKOUT as a power saving feature. When using an external clock on MCLKIN, the AD7739 continues to have internal clocks and will convert normally regardless of the CLKDIS bit state. When using a crystal oscillator or ceramic resonator across the MCLKIN and MCLKOUT pins, the AD7739 clock is stopped and no conversions can take place when the CLKDIS bit is active. The AD7739 digital interface can still be accessed using the SCLK pin.

Dump Mode. When this bit is reset to 0, the channel status register and channel data register will be addressed and read separately. When the DUMP bit is set to 1, the channel status register will be followed immediately by

read of the channel data register regardless of whether the status or data register has been addressed through

a the communications register. The continuous read mode will always be dump mode reading the channel status and channel data registers, regardless of the DUMP bit value (see the Digital Interface Description section for

details).

When this bit is set to 1, the AD7739 will operate in the continuous read mode (see the Digital Interface Description section for details).

Channel Data Register Data Width Selection Bit. When set to 1, the channel data registers will be 24 bits wide. When set to 0, the channel data registers will be 16 bits wide.

This bit determines the channel data register’s value when the analog input voltage is outside the nominal input voltage range. When the CLAMP bit is set to 1, the channel data register will be digitally clamped to either all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range. When the CLAMP bit is reset to 0, the data registers reflect the analog input voltage even outside the nominal voltage range (see the Analog Input’s Extended Voltage Range section).

The default mode after power-on or reset. The AD7739 automatically returns to this mode after any calibration or after a single conversion.

Continuous Conversion

Single Conversion

Power-Down (Standby)

ADC Zero-Scale Self-Calibration

ADC Full-Scale Self-Calibration

Channel ZeroScale System Calibration

Channel FullScale System Calibration

The AD7739 performs a conversion on the specified channel. After the conversion is complete, the relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, and the AD7739 continues converting on the next enabled channel. The part will cycle through all enabled channels until it is put into another mode or reset. The cycle period will be the sum of all enabled channels’ conversion times, set by the corresponding channel conversion time registers.

The AD7739 performs a conversion on the specified channel. After the conversion is complete, the relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, the RDY to idle mode. Requesting a single conversion ignores the channel setup register enable bits; a conversion will be performed even if that channel is disabled.

The ADC and the analog front end (internal buffer) go into the power-down mode. The AD7739 digital interface can still be accessed. The CLKDIS bit works separately, and the MCLKOUT mode is not affected by the power-down (standby) mode.

A zero-scale self-calibration is performed on internally shorted ADC inputs. After the calibration is complete, the contents of the ADC zero-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY idle mode.

A full-scale self-calibration is performed on an internally generated full-scale signal. After the calibration is complete, the contents of the ADC full-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY AD7739 returns to idle mode.

A zero-scale system calibration is performed on the selected channel. An external system zero-scale voltage should be provided at the AD7739 analog input and this voltage should remain stable for the duration of the calibration. After the calibration is complete, the contents of the corresponding channel zero-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY

pin goes low, the MD2–MD0 bits are reset, and the AD7739 returns to idle mode.

A full-scale system calibration is performed on the selected channel. An external system full-scale voltage should be provided at the AD7739 analog input and this voltage should remain stable for the duration of the calibration. After the calibration is complete, the contents of the corresponding channel full-scale calibration register are updated, all RDY bits in the ADC status register are set, the

pin goes low, the MD2–MD0 bits are reset, and the AD7739 returns to idle mode.

RDY

pin goes low, the MD2–MD0 bits are reset, and the AD7739 returns

pin goes low, the MD2–MD0 bits are reset, and the AD7739 returns to

pin goes low, the MD2–MD0 bits are reset, and the

Rev. 0 | Page 21 of 32

Page 22

AD7739

DIGITAL INTERFACE DESCRIPTION

HARDWARE

The AD7739 serial interface can be connected to the host device via the serial interface in several different ways.

pin can be used to select the AD7739 as one of several

The

CS circuits connected to the host serial interface. When the AD7739 ignores the SCLK and DIN signals and the DOUT pin goes to the high impedance state. When the used, connect the

The

pin can be polled for high-to-low transition or can

RDY

pin to DGND.

drive the host device interrupt input to indicate that the AD7739 has finished the selected operation and/or new data from the AD7739 is available. The host system can also wait a designated time after a given command is written to the device before reading. Alternatively, the AD7739 status can be polled. When the

an open circuit. (Note that the

pin is not used in the system, it should be left as

RDY

pin is always an active

RDY

digital output, i.e., it never goes into a high impedance state.)

is high,

signal is not

The used, connect this pin to DV

pin can be used to reset the AD7739. When not

RESET

The AD7739 interface can be reduced to just two wires connecting the DIN and DOUT pins to a single bidirectional data line. The second signal in this 2-wire configuration is the SCLK signal. The host system should change the data line direction with reference to the AD7739 timing specification (see the Bus Relinquish Time in Table 2). The AD7739 cannot operate in the continuous read mode in 2-wire serial interface configuration.

All the digital interface inputs are Schmitt triggered; therefore, the AD7739 interface features higher noise immunity and can be easily isolated from the host system via optocouplers. Figure 13, Figure 14, and Figure 15 outline some of the possible

host device interfaces: SPI without using the

signal (Figure 13), a DSP interface (Figure 14), and a 2-wire configuration (Figure 15).

DGND

DDDVDD

68HC11

SCK

MISO

MOSI

INT

03742-0-013

AD7739

RESET

SCLK

DOUT

DIN

RDY

Figure 13. AD7739 to Host Device Interface, SPI

AD7739

RESET

SCLK

DOUT

DIN

RDY

ADSP-2105

SCLK

INT

TFS

RFS

03742-0-001

Figure 14. AD7739 to Host Device Interface, DSP

AD7739

RESET

SCLK

DOUT

Figure 15. AD7739 to Host Device Interface, 2-Wire Configuration

SCLK

DIN

DOUT

Figure 16. Serial Interface Signals—Registers Access

DIN

DGND

WRITE

COMMUNICATIONS

8xC51

P3.1/TxD

P3.0/RxD

03742-0-015

READ

ADC STATUS

03742-0-016

Rev. 0 | Page 22 of 32

Page 23

AD7739

RESET

The AD7739 can be reset by the sequence to the AD7739 serial interface. The reset sequence is

N × 0 + 32 × 1, which could be the data sequence 0x00 + 0xFF + 0xFF + 0xFF + 0xFF in a byte-oriented interface.

The AD7739 also features a power-on reset with a trip point of 2 V and goes to the defined default state after power-on.

It is the system designer’s responsibility to prevent an unwanted write operation to the AD7739. The unwanted write operation could happen when a spurious clock appears on the SCLK while

pin is low. Note that if the AD7739 interface signals are

the

CS floating or undefined at system power-on, the part can be inadvertently configured into an unknown state. This could be easily overcome by initiating either a hardware reset event or a 32 ones reset sequence as the first step in the system

configuration.

pin or by writing a reset

RESET

ACCESS THE AD7739 REGISTERS

All communications to the part start with a write operation to the communications register followed by either reading or writing the addressed register. In a simultaneous read-write interface (such as SPI), write 0 to the AD7739 while reading data.

Figure 16 shows the AD7739 interface read sequence for the ADC status register.

SINGLE CONVERSION AND READING DATA

When the mode register is being written, the ADC status byte is cleared and the

pin goes high, regardless of its previous

RDY

state. When the single conversion command is written to the mode register, the ADC starts the conversion on the channel selected by the address of the mode register. After the conversion is completed, the data register is updated, the mode register is changed to idle mode, the relevant RDY bit is set, and the

pin goes low. The RDY bit is reset and the

RDY

RDY pin returns high when the relevant channel data register is being read.

Figure 17 shows the digital interface signals executing a single conversion on Channel 0, waiting for the

pin to go low,

RDY

and reading the Channel 0 data register.

DUMP MODE

When the DUMP bit in the mode register is set to 1, the channel status register will be read immediately by a read of the channel data register, regardless of whether the status or the data register has been addressed through the communications register. The DIN pin should not be high while reading 24-bit data in dump mode; otherwise, the AD7739 will be reset.

Figure 18 shows the digital interface signals executing a single conversion on Channel 0, waiting for the

and reading the Channel 0 status register and data register in the dump mode.

pin to go low,

RDY

SCLK

DIN

DOUT

RDY

COMMUNICATIONS

0x38

WRITE

Figure 17. Serial Interface Signals—Single Conversion Command and 16-Bit Data Reading

0x40 0x48 (0x00) (0x00)

DATA DATA

WRITE

MODE

CONVERSION TIME READ DATA REGISTER

WRITE

COMMUNICATIONS

03742-0-017

SCLK

DIN

DOUT

RDY

COMMUNICATIONS

0x38 0x48 0x48

WRITE

Figure 18. Serial Interface Signals—Single Conversion Command, 16-Bit Data Reading, Dump Mode

WRITE

MODE

CONVERSION TIME READ DATA

WRITE

COMMUNICATIONS

(0x00) (0x00) (0x00)

STATUS DATA DATA

READ

CHANNEL

STATUS

03742-0-018

Rev. 0 | Page 23 of 32

Page 24

AD7739

CONTINUOUS CONVERSION MODE

When the mode register is being written, the ADC status byte is

RDY

cleared and the state. When the continuous conversion command is written to the mode register, the ADC starts conversion on the channel selected by the address of the mode register.

pin goes high, regardless of its previous

If an ADC conversion result has not been read before a new ADC conversion is completed, the new result will overwrite the previous one. The relevant RDY bit goes low and the

RDY

goes high for at least 163 MCLK cycles (~26.5 µs), indicating when the data register is updated, and the previous conversion data is lost.

After the conversion is complete, the relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, and the AD7739 continues converting on the next enabled channel. The part will cycle through all enabled channels until put into another mode or reset. The cycle period will be the sum of all enabled channels’ conversion times, set by the corresponding channel conversion time registers.

The RDY bit is reset when the relevant channel data register is being read. The behavior of the

pin depends on the

RDY

RDYFN bit in the I/O port register. When the RDYFN bit is 0, the

the RDYFN bit is set to 1, the

pin goes low when any channel has unread data. When

RDY

pin will go low only if all

RDY

enabled channels have unread data.

CONTINUOUS CONVERSION

SERIAL

INTERFACE

RDY

CONTINUOUS CONVERSION

SERIAL

INTERFACE

RDY

START

CH0 CONVERSION

START

READ DATA

CH0

CH1 CONVERSION

Figure 19. Continuous Conversion, CH0 and CH1, RDYFN = 0

If the data register is being read as an ADC conversion completes, the data register will not be updated with the new result (to avoid data corruption) and the new conversion data is lost.

Figure 19 shows the digital interface signal’s sequence for the continuous conversion mode with Channels 0 and 1 enabled and the RDYFN bit set to 0. The

pin goes low and the data

RDY

low and all data registers are read after all conversions are completed. Figure 21 shows the

pin when no data is read

RDY

from the AD7739.

READ DATA

CH1

CH0 CONVERSION

READ

DATA

CH1

CH0

READ DATA

CH0

CH1 CONVERSION

READ DATA

CH1

CH0 CONVERSION

READ DATA

CH0

03742-0-019

READ DATA

CH1

pin goes

CH1 CONVERSIONCH0 CONVERSION

CH0 CONVERSION

CH1 CONVERSION

CH0 CONVERSION

03742-0-020

Figure 20. Continuous Conversion, CH0 and CH1, RDYFN = 1

START CONTINUOUS CONVERSION

SERIAL

INTERFACE

RDY

CH0 CONVERSIONCH1 CONVERSIONCH0 CONVERSION CH1 CONVERSION CH0 CONVERSION

03742-0-021

Figure 21. Continuous Conversion, CH0 and CH1, No Data Read

Rev. 0 | Page 24 of 32

Page 25

AD7739

CONTINUOUS READ (CONTINUOUS CONVERSION) MODE

When the Cont RD bit in the mode register is set, the first write of 0x48 to the communications register starts the continuous read mode. As shown in Figure 22, subsequent accesses to the part sequentially read the channel status and data registers of the last completed conversion without any further configuration of the communications register being required.

Note that the continuous conversion bit in the mode register should be set when entering the continuous read mode.

Note that the last completed conversion result is being read. Therefore, the RDYFN bit in the I/O port register should be 0, and reading the result should always start before the next conversion is completed.

The AD7739 will stay in continuous read mode as long as the DIN pin is low while the

pin is low; therefore, write 0 to the

AD7739 while reading in continuous read mode. To exit continuous read mode, take the DIN pin high for at least 100 ns after a read is complete. (Write 0x80 to the AD7739 to exit continuous reading.)

Note that the continuous read mode is a dump mode reading of the channel status and data registers regardless of the dump bit value. Use the channel bits in the channel status register to check/recognize which channel data is actually being shifted out.

SCLK

DIN

DOUT

RDY

0x38

WRITE

COMM.

0x48

WRITE

MODE

0x48

WRITE COMM.

CONVERSION

ON CH0

COMPLETE

STATUS

Figure 22. Continuous Conversion, CH0 and CH1, Continuous Read

(0x00)

READ

CH0

Taking the DIN pin high does not change the Cont RD bit in the mode register. Therefore, the next write of 0x48 starts the continuous read mode again. To completely stop the continuous read mode, write to the mode register to clear the Cont RD bit.

READ

CH1

DATA

(0x00)

DATA

03742-0-022

(0x00)

DATA

READ

CH0

DATA

(0x00)

DATA

CONVERSION

ON CH1

COMPLETE

(0x00)

STATUS

READ

CH1

STATUS

(0x00)

DATA

Rev. 0 | Page 25 of 32

Page 26

AD7739

AIN(

CIRCUIT DESCRIPTION

The AD7739 is a high precision analog-to-digital converter that is intended for the measurement of wide dynamic range, low frequency signals in industrial process control, instrumentation, and PLC systems.

It contains a multiplexer, an input buffer, a sigma-delta (or charge balancing) ADC, a digital filter, a clock oscillator, a digital I/O port, and a serial communications interface.

ANALOG INPUTS

The AD7739 has nine analog input pins connected to the ADC through the internal multiplexer. The analog front end can be configured as eight single-ended inputs or four differential inputs or any combination of these (via the channel setup registers).

The AD7739 contains a wide bandwidth, fast settling time differential input buffer capable of driving the dynamic load of a high speed sigma-delta modulator. With the internal buffer enabled, the analog inputs feature high input impedance.

If chopping is enabled or when switching between channels, there is a dynamic current on analog inputs charging the internal capacitance of the multiplexer and input buffer. The capacitance is approximately 10 pF.

At the start of each conversion, there is a delay to allow the capacitance to be charged (see the Multiplexer, Conversion, and Data Output Timing section). If the analog inputs resistive source impedance does not exceed 50 kΩ, the internal capacitance is charged fast enough and the AD7739 performance is not affected at the 16-bit level.

An external RC filter connected to the analog inputs would average the multiplexer channel-to-channel switching dynamic currents to a dc current leading to a dc voltage drop across the

external input resistance. To avoid additional gain errors, offset errors, and channel-to-channel crosstalk due to this effect, low resistor values should be used in the low-pass RC filter for the AD7739. The recommended low-pass RC filter for the analog inputs is 100 Ω and 100 nF.

The average (dc) current, charging the capacitance on the multiplexer output, is related to the equation:

× V

I ≈ C

MUX

Where C approximately 10 pF , V

× FS

MUX

is the capacitance on the multiplexer output,

MUX

is the voltage difference on the

MUX

multiplexer output between two subsequent conversions, which can be up to 5 V, and F

is the channel sampling frequency,

which relates to the sum of conversion times on all subsequently sampled channels.

SIGMA-DELTA ADC

The AD7739 core consists of a charge balancing sigma-delta modulator and a digital filter. The architecture is optimized for fast, fully settled conversion. This allows for fast channel-tochannel switching while maintaining inherently excellent linearity, high resolution, and low noise.

CHOPPING

With chopping enabled, the multiplexer repeatedly reverses the ADC inputs. Every output data result is then calculated as an average of two conversions, the first with the positive and the second with the negative offset term included. This effectively removes any offset error of the input buffer and sigma-delta modulator. Figure 23 shows the channel signal chain with chopping enabled.

MULTIPLEXER

IN(+)

–)

CHOP CHOPCHOP

BUFFER

Σ-∆

MODULATOR

MCLK

Figure 23. Channel Signal Chain Diagram with Chopping Enabled

DIGITAL

FILTER

SCALING

ARITHMETIC

–

(CALIBRATIONS)

DIGITAL

INTERFACE

OUTPUT DATA AT THE SELECTED DATA RATE

03742-0-023

Rev. 0 | Page 26 of 32

Page 27

AD7739

MULTIPLEXER, CONVERSION, AND DATA OUTPUT TIMING

The specified conversion time includes one or two settling and sampling periods and a scaling time.

With chopping enabled (Figure 24), a conversion cycle starts with a settling time of 43 MCLK cycles or 44 MCLK cycles (~7 µs with a 6.144 MHz MCLK) to allow the circuits following the multiplexer to settle. The sigma-delta modulator then samples the analog signals and the digital filter processes the digital data stream. The sampling time depends on FW, i.e., on the channel conversion time register contents. After another settling of 42 MCLK cycles (~6.8 µs), the sampling time is repeated with a reversed (chopped) analog input signal. Then, during the scaling time of 163 MCLK cycles (~26.5 µs), the two results from the digital filter are averaged, scaled using the calibration registers, and written into the channel data register.

MULTIPLEXER

– CHANNEL 0

+ CHANNEL 1

With chopping disabled (Figure 25), only one sampling time is preceded by a settling time of 43 MCLK or 44 MCLK cycles and followed by a scaling time of 163 MCLK cycles.

The

pin goes high during the scaling time, regardless of its

RDY previous state. The relevant RDY bit is set in the ADC status register and in the channel status register, and the

RDY

pin goes

low when the channel data register is updated and the channel conversion cycle is finished. If in continuous conversion mode, the part will automatically continue with a conversion cycle on the next enabled channel.

Note that every channel can be configured independently for conversion time and chopping mode. The overall cycle and effective per channel data rates depend on all enabled channel settings.

– CHANNEL 1

RDY

SETTLING

TIME

Figure 24. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled

MULTIPLEXER

CHANNEL 0

RDY

Figure 25. Multiplexer and Conversion Timing— Continuous Conversion on Several Channels with Chopping Disabled

SAMPLING

TIME

SETTLING

TIME

SETTLING

TIME

CONVERSION TIME

CHANNEL 1

SAMPLING

TIME

CONVERSION TIME

SAMPLING

TIME

SCALING

TIME

SCALING

TIME

03742-0-025

03742-0-024

Rev. 0 | Page 27 of 32

Page 28

AD7739 Preliminary Technical Data

FREQUENCY RESPONSE

The sigma-delta modulator runs at ½ the MCLK frequency, which is effectively the sampling frequency. Therefore, the modulator Nyquist frequency is ¼ of the MCLK.

If chopping is enabled, the input signal is resampled by chopping. Therefore, the overall frequency response features notches close to the frequency of 1/channel conversion time.

–20

–40

–60

GAIN (dB)

–100

CHOP = 1

–80

The typical ADC frequency response plots are given in Figure 26 and Figure 27. The plots are normalized to 1/channel conversion time.

Note that these figures apply to each channel separately and are based on individual channel conversion time. The signal is effectively resampled once more in the multiplexer by switching between enabled analog inputs.

–120

0101 100

NORMALIZED INPUT FREQUENCY

(INPUT FREQUENCY × CONVERSION TIME)

03742-0-026

Figure 26. Typical ADC Frequency Response, Chopping Enabled

–20

–40

–60

GAIN (dB)

–80

–100

–120

CHOP = 0

0101 100

NORMALIZED INPUT FREQUENCY

(INPUT FREQUENCY × CONVERSION TIME)

03742-0-027

Figure 27. Typical ADC Frequency Response, Chopping Disabled

Rev. 0 | Page 28 of 32

Page 29

AD7739

ANALOG INPUT’S EXTENDED VOLTAGE RANGE

The AD7739 output data code span corresponds to the nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. The sigma-delta modulator was designed to fully cover 16% analog input overrange; outside this range, the performance might degrade more rapidly.

When the CLAMP bit in the mode register is set to 1, the channel data register will be digitally clamped to either all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range.

As shown in Table 14 and Table 15, when CLAMP = 0, the data reflects the analog input voltage outside the nominal voltage range. In this case, the SIGN and OVR bits in the channel status register should be considered along with the data register value to decode the actual conversion result.

Note that the OVR bit in the channel status register is generated digitally from the conversion result and indicates the sigmadelta modulator (nominal) overrange. The OVR bit DOES NOT indicate exceeding the AIN pin’s absolute voltage limits.

Table 14. Extended Input Voltage Range, Nominal Voltage Range ±1.25 V, 16 Bits, CLAMP = 0

Input (V) Data (hex) SIGN OVR

+1.45000 0x147B 0 1 +1.25008 0x0001 0 1 +1.25004 0x0000 0 1 +1.25000 0xFFFF 0 0 +0.00004 0x8001 0 0

0.00000 0x8000 0 0 –0.00004 0x7FFF 1 0 –1.25000 0x0000 1 0 –1.25004 0xFFFF 1 1 –1.25008 0xFFFE 1 1 –1.45000 0xEB85 1 1

Table 15. Extended Input Voltage Range, Nominal Voltage Range +1.25 V, 16 Bits, CLAMP = 0

Input (V) Data (hex) SIGN OVR

+1.45000 0x28F5 0 1 +1.25004 0x0001 0 1 +1.25002 0x0000 0 1 +1.25000 0xFFFF 0 0 +0.00002 0x0001 0 0 +0.00000 0x0000 0 0 –0.00002 0x0000 1 1

VOLTAGE REFERENCE INPUTS

The AD7739 has a differential reference input, REF IN(+) and REF IN(–). The common-mode range for these inputs is from AGND to AV

. The nominal differential reference voltage for

specified operation is 2.5 V. Both reference inputs feature dynamic load. Therefore, the reference inputs should be connected to a low impedance reference voltage source. External resistance/capacitance combinations may result in gain errors on the part.

The output noise performance outlined in Table 4 through Table 9 is for an analog input of 0 V and is unaffected by noise on the reference. Obtaining the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the AD7739. If the reference noise in the bandwidth of interest is excessive, it will degrade the performance of the AD7739.

Recommended reference voltage sources for the AD7739 include the ADR421, AD780, REF43, and REF192.

REFERENCE DETECT

The AD7739 includes on-chip circuitry to detect if the part has a valid reference for conversions. If the voltage between the REFIN(+) and REFIN(–) pins goes below the NOREF trigger voltage (0.5 V typ.) and the AD7739 is performing a conversion, the NOREF bit in the channel status register is set.

I/O PORT

The AD7739 P0 pin can be used as a general-purpose digital output or as a common analog input.

The P1 pin ( I/O pin or to synchronize the AD7739 with other devices in the

system. When the SYNC bit in the I/O port register is set and the

pin is low, the AD7739 does not process any

SYNC conversion. If it is put into single conversion mode, continuous conversion mode, or any calibration mode, the AD7739 waits

until the

SYNC

allows conversion to start from a known point in time, i.e., the rising edge of the

pin should be tied high or low.

SYNC

The digital P0 and P1 voltage is referenced to the analog supplies.

/P1) can be used as a general-purpose digital

SYNC

pin goes high and then starts operation. This

pin. When configured as input, the

SYNC

Rev. 0 | Page 29 of 32

Page 30

AD7739

CALIBRATION

The AD7739 provides zero-scale self-calibration, and zero- and full-scale system calibration capability that can effectively reduce the offset error and gain error to the order of the noise. After each conversion, the ADC conversion result is scaled using the ADC calibration registers and the relevant channel calibration registers before being written to the data register.

For unipolar ranges:

Data = ((ADC result – R × ADC ZS Cal. reg.)

× ADC FS reg./(0x20 0000) – R × Ch. ZS Cal. reg.) × Ch. FS Cal. reg./(0x20 0000)

For bipolar ranges:

Data = ((ADC result – R × ADC ZS Cal. reg.)

× ADC FS reg./(0x40 0000) + (0x80 0000) – R × Ch. ZS Cal. reg.) × Ch. FS Cal. reg./(0x20 0000)

where the ADC result is in the range of 0 to 0xFF FFFF. R = 1 for input ranges +1.25 V, ±1.25 V, +2.5 V, and ±2.5 V R = 2 for input ranges +0.625 V, and ±0.625 V

Note that the channel zero-scale calibration register has the format of a sign bit and a 22-bit channel offset value.

To start any calibration, write the relevant mode bits to the AD7739 mode register. After the calibration is complete, the contents of the corresponding calibration registers are updated, all RDY bits in the ADC status register are set, the

goes low, and the AD7739 reverts to idle mode. The calibration duration is the same as the conversion time configured on the selected channel. A longer conversion time gives less noise and yields a more exact calibration; therefore, use at least the default conversion time to initiate any calibration.

ADC Zero-Scale Self-Calibration

The ADC zero-scale self-calibration can reduce the ADC offset error in the chopping disabled mode. If repeated after a temperature change, it can also reduce the offset drift error in the chopping disabled mode.

The zero-scale self-calibration is performed on internally shorted ADC inputs. The negative analog input terminal on the selected channel is used to set the ADC zero-scale calibration common mode. Therefore, either the negative terminal of the selected differential pair or the AINCOM on the single-ended channel configuration should be driven to a proper commonmode voltage.

SYNC

ADC Full-Scale Self-Calibration

The ADC full-scale self-calibration can reduce the ADC fullscale error for the +2.5 V and ±2.5 V input range. If repeated after a temperature change, it can also reduce the full-scale drift.

The ADC full-scale self-calibration is performed with a +2.5 V input voltage range on internally generated full-scale voltage

), regardless of the input voltage range set in the channel

REF

setup register. Full-scale errors in the ±1.25 V, +1.25 V, ±0.625 V, and +0.625 V ranges are not calibrated as this would require an accurate low voltage source other than the reference.

If the 1.25 V or 0.625 V ranges are used on any channel, the ADC full-scale self-calibration is not recommended. A system full-scale calibration should be performed if accurate gains need to be achieved on these ranges.

It is recommended that the ADC full-scale calibration register be updated only as part of an ADC full-scale self-calibration for the +2.5 V and ±2.5 V input range.

Per Channel System Calibration

The per channel system calibration can reduce the system offset error and the system gain error. If repeated after a temperature change, it can also reduce the system offset and gain drifts.

If the per channel system calibrations are used, these should be initiated in the following order: a channel zero-scale system calibration, followed by a channel full-scale system calibration.

The system calibration is affected by the ADC zero-scale and full-scale calibration registers. Therefore, if both self-calibration and system calibration are used in the system, an ADC selfcalibration should be performed first, followed by a system calibration cycle.

The voltage range in the channel setup register should be set before executing the channel system calibration.

While executing a system calibration, the fully settled system zero-scale voltage signal or system full-scale voltage signal must be connected to the selected channel analog inputs.

The per channel calibration registers can be read, stored, or modified and written back to the AD7739. Note that when writing the calibration registers, the AD7739 must be in idle mode. Note that outside the specified calibration range, calibration is possible, but the performance may degrade (see the System Calibration section in Table 1).

It is recommended that the ADC zero-scale calibration register be updated only as part of an ADC zero-scale self-calibration.

Rev. 0 | Page 30 of 32

Page 31

AD7739

ADR421

10µF

0.1µF

100Ω

0.1µF

10µF

ANALOG

INPUTS

0.1µF

AINCOM

0.1µF

REFIN(+)

REFIN(-)

0.1µF

AIN0

AIN7

MUX

AD7739

BUFFER

CLOCK

GENERATOR

24-BIT

Σ-∆ ADC

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DGNDAGND

MCLKIN

MCLKOUT

RESET

SCLK

DIN

DOUT

RDY

0.1µF

6.144MHz

33pF 33pF

HOST SYSTEM

10µF

Figure 28. Typical Connections for the AD7739 Application

Rev. 0 | Page 31 of 32

Page 32

AD7739

OUTLINE DIMENSIONS

7.90

7.80

7.70

PIN 1

0.15

0.05

0.10 COPLANARITY

0.65 BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MS-153AD

121

1.20

MAX

SEATING PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09

8°

0°

0.75

0.60

0.45

Figure 29. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24)—Dimensions shown in millimeters

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model Temperature Range Package Description Package Outline

AD7739BRU –40°C to +105°C TSSOP-24 RU-24 AD7739BRU-REEL –40°C to +105°C TSSOP-24 RU-24 AD7739BRU-REEL7 –40°C to +105°C TSSOP-24 RU-24

C03742–0–5/03(0)

Rev. 0 | Page 32 of 32

Datasheet AD7739 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

AD7739—SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

TYPICAL PERFORMANCE CHARACTERISTICS

OUTPUT NOISE AND RESOLUTION SPECIFICATION

CHOPPING ENABLED

CHOPPING DISABLED

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REGISTER DESCRIPTIONS

REGISTER ACCESS

COMMUNICATIONS REGISTER

I/O PORT REGISTER

REVISION REGISTER

TEST REGISTER

ADC STATUS REGISTER

CHECKSUM REGISTER

ADC ZERO-SCALE CALIBRATION REGISTER

CHANNEL DATA REGISTERS

ADC FULL-SCALE CALIBRATION REGISTER

CHANNEL ZERO-SCALE CALIBRATION REGISTERS

CHANNEL FULL-SCALE CALIBRATION REGISTERS

CHANNEL STATUS REGISTERS

CHANNEL SETUP REGISTERS

CHANNEL CONVERSION TIME REGISTERS

MODE REGISTER

DIGITAL INTERFACE DESCRIPTION

HARDWARE

RESET

ACCESS THE AD7739 REGISTERS

SINGLE CONVERSION AND READING DATA

DUMP MODE

CONTINUOUS CONVERSION MODE

CONTINUOUS READ (CONTINUOUS CONVERSION) MODE

CIRCUIT DESCRIPTION

ANALOG INPUTS

SIGMA-DELTA ADC

CHOPPING

MULTIPLEXER, CONVERSION, AND DATA OUTPUT TIMING

FREQUENCY RESPONSE

ANALOG INPUT’S EXTENDED VOLTAGE RANGE

VOLTAGE REFERENCE INPUTS

REFERENCE DETECT

I/O PORT

CALIBRATION

ADC Zero-Scale Self-Calibration

ADC Full-Scale Self-Calibration

Per Channel System Calibration

OUTLINE DIMENSIONS

ESD CAUTION

ORDERING GUIDE