Datasheet AD7724 Datasheet (Analog Devices)

a

AVIN(+)
AVIN(–)

BVIN(+)
BVIN(–)

MZERO

GC

BIP

STBY

RESET

DVDD DVDD1 DGND AVDD AGND

ADATA

SCLK

BDATA

XTAL

OFF

XTAL1
XTAL2/MCLK

DVAL

REF1 REF2A REF2B

CLOCK

CIRCUITRY

AD7724

2.5V

REFERENCE

S-D

MODULATOR A

S-D

MODULATOR B

CONTROL

LOGIC

Dual CMOS ⌺-⌬ Modulators

AD7724

FEATURES
13 MHz Master Clock Frequency
0 V to +2.5 V or ⴞ1.25 V Input Range
Single Bit Output Stream
90 dB Dynamic Range
Power Supplies

AVDD, DVDD: 5 V␣ ⴞ 5%

DVDD1: 3 V ⴞ 5%
Logic Outputs 3 V/5 V Compatible
On-Chip 2.5 V Voltage Reference
48-Lead LQFP

GENERAL DESCRIPTION

This device consists of two seventh order sigma-delta modula­tors. Each modulator converts its analog input signal into a high
speed 1-bit data stream. The part operates from a 5 V power
supply and accepts a differential input range of 0 V to +2.5 V or

±1.25 V centered about a common-mode bias. The analog inputs

are continuously sampled by the analog modulators, eliminating
the need for external sample-and-hold circuitry. The input infor­mation is contained in the output stream as a density of ones.
The original information can be digitally reconstructed with an
appropriate digital filter.

The part provides an accurate on-chip 2.5 V reference for each
modulator. A reference input/output function is provided to
allow either the internal reference or an external system refer­ence to be used as the reference source for the modulator.

The device is offered in a 48-lead LQFP package and designed

to operate from –40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

1

AD7724–SPECIFICATIONS

f

= 13 MHz ac-coupled sine wave, REF2A = REF2B␣ =␣ 2.5 V; TA = T

MCLK

(AVDD = 5 V ⴞ 5%; DVDD = 5 V ⴞ 5%, DVDD1 = 3 V ⴞ 5%; AGND = DGND = 0 V,

to T

MIN

, unless otherwise noted.)

MAX

Parameter A Version Unit Test Conditions/Comments

STATIC PERFORMANCE When Tested with Ideal FIR Filter as in Figure 1

Integral Nonlinearity ±0.003 % FSR typ
Offset Error ±0.24 % FSR typ

Gain Error

2

±0.6 % FSR typ

Offset Error Drift ±37.69 µV/°C typ

Gain Error Drift REF2 Is an Ideal Reference, REF1 = AGND

Unipolar Mode ±37.69 µV/°C typ
Bipolar Mode ±18.85 µV/°C typ

ANALOG INPUTS

Signal Input Span (VIN(+) – VIN(–))

Bipolar Mode ±V

Unipolar Mode 0 to V

/2 V max BIP = V

REF2

REF2

V max BIP = V

IH

IL

Maximum Input Voltage AVDD V
Minimum Input Voltage 0 V
Input Sampling Capacitance 2 pF typ
Input Sampling Rate 2 f

MCLK

Differential Input Impedance 109/(8 f

MCLK

MHz

)kΩ typ

REFERENCE INPUTS

REF1 Output Voltage 2.32 to 2.68 V min/max

REF1 Output Voltage Drift 60 ppm/°C typ
REF1 Output Impedance 4 kΩ typ
Reference Buffer Offset Voltage ±12 mV max Offset Between REF1 and REF2

Using Internal Reference

REF2 Output Voltage 2.32 to 2.68 V min/max

REF2 Output Voltage Drift 60 ppm/°C typ

Using External Reference REF1 = AGND

REF2 Input Impedance 10

9

/(16 f

MCLK

)kΩ typ

External Reference Voltage Range 2.32 to 2.68 V min/max Applied to REF1 or REF2

DYNAMIC SPECIFICATIONS

Bipolar Mode BIP = V

3

When Tested with Ideal FIR Filter as in Figure 1

, VCM = 2.5 V, VIN(+) = VIN(–) = 1.25 V p-p

IH

or VIN(–) = 1.25 V, VIN(+) = 0 V to 2.5 V

Signal-to-(Noise + Distortion) 90 dB typ Input BW = 0 kHz–94.25 kHz

86 dB min
Total Harmonic Distortion –90 dB max Input BW = 0 kHz–94.25 kHz
Spurious Free Dynamic Range –90 dB max Input BW = 0 kHz–94.25 kHz

Unipolar Mode BIP = V

, VIN(–) = 0 V, VIN(+) = 0 V to 2.5 V

IL

Signal-to-(Noise + Distortion) 88 dB typ Input BW = 0 kHz–94.25 kHz
Total Harmonic Distortion –90 dB typ Input BW = 0 kHz–101.556 kHz
Spurious Free Dynamic Range –90 dB typ Input BW = 0 kHz–101.556 kHz
Intermodulation Distortion –93 dB typ

AC CMRR 96 dB typ VIN(+) = VIN(–) = 2.5 V p-p, V

= 1.25 V to

CM

3.75 V, 20 kHz

CLOCK

Square Wave

4

MCLK Duty Ratio 45 to 55 % max For Specified Operation
V
V

, MCLK High Voltage 4 V min MCLK Uses CMOS Logic

MCLKH

, MCLK Low Voltage 0.4 V max

MCLKL

Sine Wave

XTAL1 Voltage Swing 0.4 V p-p min XTAL_OFF Tied Low

4 V p-p max

LOGIC INPUTS

V

, Input High Voltage 2.4 V min

IH

, Input Low Voltage 0.8 V max

V

IL

, Input Current 10 µA max

I

INH

CIN, Input Capacitance 10 pF max

REV. A–2–

Parameter A Version Unit Test Conditions/Comments

LOGIC OUTPUTS

V

, Output High Voltage DVDD1 – 0.2 V min |I

OH

VOL, Output Low Voltage 0.4 V max |I

| ≤ 200 µA

OUT

| ≤ 1.6 mA

OUT

POWER SUPPLIES

AVDD/DVDD 4.75/5.25 V min/V max
DVDD1 2.85/5.25 V min/V max
I

(Total for AVDD, DVDD) Digital Inputs Equal to 0␣ V or DVDD

DD

Active Mode 60 mA max

Standby Mode 20 µA max

NOTES

1

Operating temperature range is as follows:␣ A Version: –40°C to +85°C.

2

Gain Error excludes reference error. The modulator gain is calibrated wrt the voltage on the REF2 pin.

3

Measurement Bandwidth = 0.5 × f

4

When a square wave clock is used, the dynamic specifications will degrade by 1 dB typically.

Specifications subject to change without notice.

; Input Level = –0.05 dB.

MCLK

AD7724

BIT STREAM

94.25kHz

FILTER 1

BANDWIDTH = 94.25kHz
TRANSITION = 304.687kHz
ATTENUATION = 120dB
COEFFICIENTS = 384

304.687kHz

120dB

DECIMATE

BY 32

94.25kHz

FILTER 2

BANDWIDTH = 94.25kHz
TRANSITION = 108.874kHz
ATTENUATION = 90dB
COEFFICIENTS = 151

108.874kHz

90dB

DECIMATE

BY 2

16-BIT

OUTPUT

Figure 1. Digital Filter (Consists of Two FIR Filters). This Filter is implemented on the AD7722.

REV. A –3–

AD7724

(AVDD = 5 V ⴞ 5%; DVDD = 5 V ⴞ 5%; DVDD1 = 3 V ⴞ 5%; AGND = DGND = 0 V, REF2A =

TIMING CHARACTERISTICS

Limit at T

Parameter (A Version) Unit Conditions/Comments

f

MCLK

t

1

t

2

t

3

t

4

t

5

t

6

t

7

NOTE
Guaranteed by design.

100 kHz min Master Clock Frequency
15 MHz max 13 MHz for Specified Performance
67 ns min Master Clock Period

0.45 × t

0.45 × t

MCLK

MCLK

15 ns min Data Hold Time After SCLK Rising Edge
10 ns min RESET Pulsewidth
10 ns min RESET Low Time Before MCLK Rising

20 × t

MCLK

REF2B = 2.5 V, unless otherwise noted)

, T

MIN

MAX

ns min Master Clock Input High Time
ns min Master Clock Input Low Time

ns max DVAL High Delay After RESET Low

I

OL

1.6mA

SCLK (O)

DATA (O)

Figure 2. Load Circuit for Access Time and Bus Relinquish Time

NOTE:
O SIGNIFIES AN OUTPUT

MCLK (I)

RESET (I)

DVAL (O)

TO

OUTPUT

PIN

C

L

50pF

I

OH

200mA

t

1

t

t

3

2

t

4

1.6V

Figure 3. Data Timing

t

6

t

5

t

7

NOTE:
I SIGNIFIES AN INPUT
O SIGNIFIES AN OUTPUT

Figure 4. RESET Timing

–4–

REV. A

AD7724

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(T

= 25°C unless otherwise noted)

A

*

DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –1 V to +1 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital Inputs to DGND . . . . . . . . –0.3 V to DVDD + 0.3 V

Digital Outputs to DGND . . . . . . . –0.3 V to DVDD + 0.3 V

VIN(+), VIN(–) to AGND . . . . . . . –0.3 V to AVDD + 0.3 V

REF1 to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

REF2 to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

REFIN to AGND . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 75°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

AVDD
AGND

AVIN(–)

NC

AVIN(+)

AGND
AVDD

NC

STBY

MZERO

RESET

NC

NC = NO CONNECT

PIN CONFIGURATION

NCNCAGND

REF2A

AGND

REF1

AD7724

TOP VIEW

(Not to Scale)

DVDD

DGND

DGND

AVDDNCREF2B

ADATA

BDATA

48 47 46 45 44 39 38 3743 42 41 40

1

PIN 1

2

IDENTIFIER
3
4
5
6
7
8
9

10
11
12

13 14 15 16 17 18 19 20 21 22 23 24

NC

XTAL1

XTAL1/MCLK

AGNDNCNC

SCLK

DVDD1

DVAL

NC

36

AVDD

35

AGND

34

BVIN(–)

33

NC

32

BVIN(+)

31

AGND

30

AVDD

29

NC

28

GC

27

BIP

26

XTAL_OFF

25

NC

Temperature Package Package

Model Range Description Option

AD7724AST –40°C to +85°C 48-Lead Plastic Thin Quad Flatpack (LQFP) ST-48

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7724 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. A

–5–

AD7724

PIN FUNCTION DESCRIPTIONS

Mnemonic Description

AVDD Analog Positive Supply Voltage, 5 V ± 5%.

AGND Ground reference point for analog circuitry.
AVIN(–), AVIN(+) Analog Input to Modulator A. In unipolar operation, the analog input range on AVIN(+) is AVIN(–) to

(AVIN(–) + VREF); for bipolar operation, the analog input range on AVIN(+) is (AVIN(–) ± VREF/2). The

absolute analog input range must lie between 0 and AVDD. The input range is continuously sampled and
processed by the analog modulator.

STBY Standby, Logic Input. When STBY is high, the device is placed in a low power mode. When STBY is low, the

device is powered up.

MZERO Digital Control Input. When MZERO is high, the modulator inputs are internally grounded i.e. tied to AGND

in unipolar mode and REF2 in bipolar mode. MZERO allows on-chip offsets to be calibrated out. MZERO is
low for normal operation.

RESET Reset Logic Input. RESET is an asynchronous input. When RESET is taken high, the sigma-delta modulator

is reset by shorting the integrator capacitors in the modulator. DVAL goes low for 20 MCLK cycles while the

modulator is being reset.
XTAL1 Input to Crystal Oscillator Amplifier. If an external clock is used, XTAL1 should be tied to AGND.
XTAL2/MCLK Clock Input. An external clock source can be applied directly to this pin with XTAL_OFF tied high. Alterna-

tively, a parallel resonant fundamental frequency crystal, in parallel with a 1 MΩ resistor, can be connected

between XTAL1 and XTAL2 with XTAL_OFF tied low. External capacitors are then required from the XTAL1

and XTAL2 pins to ground. Consult the crystal manufacturer's recommendation for the load capacitors.

A sine wave can also be used to provide the clock. A sine wave with a voltage swing between 0.4 V p-p and

4 V p-p is needed. XTAL_OFF is tied low and a 1 MΩ resistor is needed between XTAL1 and XTAL2. A

22 pF capacitor is connected in parallel with this resistor. The sine wave is ac coupled to XTAL1 using a

120 pF capacitor. The use of a sine wave to generate the clock eliminates the need for a square wave clock

source which introduces noise.

DVDD Digital Supply Voltage, 5 V ± 5%.

DGND Ground reference for the digital circuitry.
ADATA Modulator A Bit Stream. The digital bit stream from the sigma-delta modulator is output at ADATA.
BDATA Modulator B Bit Stream. The digital bit stream from the sigma-delta modulator is output at BDATA.
SCLK Serial Clock, Logic Output. The bit stream from modulator A and modulator B is valid on the rising edge of

ASCLK.

DVDD1 Digital Supply Voltage for the digital outputs. DVDD1 can have a value of 5 V ± 5% or 3 V ± 5% so that the

logic outputs can be 3 V or 5 V compatible.
DVAL Data Valid Logic Output. A logic high on DVAL indicates that the data bit stream from the AD7724 is an

accurate digital representation of the analog voltage at the input to the sigma-delta modulator. The DVAL pin

is set low for 20 MCLK cycles if the analog input is overranged.
XTAL_OFF Oscillator Enable Input. A logic high disables the crystal oscillator amplifier to allow use of an external clock

source. XTAL_OFF is set to a logic low when an external crystal is used between XTAL1 and XTAL2.
BIP Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A logic high selects

bipolar mode.
GC Digital Control Input. When GC is high, the gain error of the modulator can be calibrated.
BVIN(–), BVIN(+) Analog Input to Modulator B. In unipolar operation, the analog input range on BVIN(+) is BVIN(–) to

(BVIN(–) + VREF); for bipolar operation, the analog input range on BVIN(+) is (BVIN(–) ± VREF/2). The

absolute analog input range must lie between 0 and AVDD. The input range is continuously sampled and

processed by the analog modulator.
REF2B Reference Input/Output to Sigma-Delta Modulator B. REF2B connects to the output of an external buffer

amplifier used to drive sigma-delta modulator B. When REF2B is used as an input, REF1 must be connected

to AGND.

REF1 Reference Input/Output. REF1 connects through 3 kΩ to the output of the internal 2.5 V reference and to the

input of two buffer amplifiers that drive Σ-∆ modulator A and Σ-∆ modulator B. The pin can be overdriven

with an external 2.5 V reference.
REF2A Reference Input/Output to Sigma-Delta Modulator A. REF2A connects to the output of an external buffer

amplifier used to drive sigma-delta modulator A. When REF2A is used as an input, REF1 must be connected

to AGND.

–6–

REV. A

AD7724

TERMINOLOGY (IDEAL FIR FILTER USED WITH AD7724
[FIGURE 1])
Integral Nonlinearity

This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be con­fused with bipolar zero), a point 0.5 LSB below the first code
transition (100␣ .␣ .␣ .␣ 00 to 100␣ .␣ .␣ .␣ 01 in bipolar mode and
000␣ .␣ .␣ .␣ 00 to 000␣ .␣ .␣ .␣ 01 in unipolar mode) and full scale, a
point 0.5 LSB above the last code transition (011␣ .␣ .␣ .␣ 10 to
011␣ .␣ .␣ .␣ 11 in bipolar mode and 111␣ .␣ .␣ .␣ 10 to 111␣ .␣ .␣ .␣ 11 in
unipolar mode). The error is expressed in LSBs.

Common-Mode Rejection Ratio

The ability of a device to reject the effect of a voltage applied to
both input terminals simultaneously—often through variation of
a ground level—is specified as a common–mode rejection ratio.
CMRR is the ratio of gain for the differential signal to the gain
for the common-mode signal.

Unipolar Offset Error

Unipolar offset error is the deviation of the first code transition
from the ideal VIN(+) voltage which is (VIN(–) + 0.5 LSB)
when operating in the unipolar mode.

Bipolar Offset Error

This is the deviation of the midscale transition (111␣ .␣ .␣ .␣ 11
to 000␣ .␣ .␣ .␣ 00) from the ideal VIN(+) voltage which is (VIN(–)
–0.5 LSB) when operating in the bipolar mode.

Gain Error

The first code transition should occur at an analog value 1/2 LSB
above minus full scale. The last code transition should occur for
an analog value 1 1/2 LSB below the nominal full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.

Signal-to-(Noise + Distortion)

Signal-to-(Noise + Distortion) is the measured signal-to-noise
plus distortion ratio at the output of the ADC. The signal is the
rms magnitude of the fundamental. Noise plus distortion is the

rms sum of all of the nonfundamental signals and harmonics up
to half the Output Data Rate (f

/2), excluding dc. Signal-to-

O

(Noise + Distortion) is dependent on the number of quantiza­tion levels used in the digitization process; the more levels, the
smaller the quantization noise. The theoretical Signal-to-(Noise
+ Distortion) ratio for a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

where N is the number of bits.

Total Harmonic Distortion

THD is the ratio of the rms sum of harmonics to the rms value
of the fundamental. THD is defined as

2

2

2

2

2

+V

)

5

6

THD = 20 log

(V

+V

+V

2

+V

3

4

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,

, V5 and V6 are the rms amplitudes of the second through the

V

4

sixth harmonic.

Spurious Free Dynamic Range

Spurious free dynamic range is the difference, in dB, between
the peak spurious or harmonic component in the ADC output
spectrum (up to f

/2 and excluding dc) and the rms value of the

O

fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the output spectrum of
the FFT. For input signals whose second harmonics occur in
the stop band region of the digital filter, a spur in the noise floor
limits the SFDR.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).

REV. A

–7–

AD7724

INPUT FREQUENCY – kHz

dB

–85

–90

–115

0 20 100

40 60 80

–95

–100

–105

–110

SNR

SFDR

THD

TEMPERATURE – °C

92.0

91.5

88.0
–50 0 10050

90.0

89.5

88.5

89.0

91.0

90.5

dB

CODE

DNL ERROR – LSB

1.0

0.8

–1.0

0 20000 6 5 53540000

–0.4

–0.8

–0.6

0

–0.2

0.6

0.2

0.4

–Typical Performance Characteristics

(AVDD = DVDD = 5.0 V, TA = 25ⴗC; CLKIN = 13 MHz ac-coupled sine wave, AIN = 20 kHz, Bipolar Mode; VIN(+) = 0 V to 2.5 V, VIN(–) = 1.25 V
unless otherwise noted)

110

100

90

80

dB

70

60

50

–40 –30 0

SFDR

S/ (N+D)

–20 –10

INPUT LEVEL – dB

Figure 5. S/(N+D) and SFDR vs.
Analog Input Level

–85

–90

SNR

–95

THD

–100

dB

–105

SFDR

–110

–115

0 20 10040 60 80

VIN (+) = VIN(–) = 1.25V p-p
V

= 2.5V

CM

INPUT FREQUENCY – kHz

Figure 8. SNR, THD, and SFDR vs.
Input Frequency

84

85

AIN = 1/5 · BW

86

87

88

dB

89

90

91

92

0 50 300

100 150 200 250

OUTPUT DATA RATE – kSPS

Figure 6. S/(N+D) vs. Output Sample
Rate

84

85

AIN = 1/5 · BW

VIN (+) = VIN(–) = 1.25V p-p

86

V

= 2.5V

CM

87

88

dB

89

90

91

92

0 5 0 300

100 150 200 250

OUTPUT DATA RATE – kSPS

Figure 9. S/(N+D) vs. Output Sample
Rate

Figure 7. SNR, THD, and SFDR vs.
Input Frequency

Figure 10. SNR vs. Temperature

–94
–96

–98
–100
–102
–104

dB

–106
–108

–110
–112

–114
–116

–50 –25 100

0255075

TEMPERATURE – °C

Figure 11. THD vs. Temperature

THD

3RD

4TH

2ND

5000
4500

4000
3500
3000
2500

2000
1500

1000

FREQUENCY OF OCCURENCE

500

0

n–3 n–2 n+3n–1 n n+1 n+2

VIN(+) = VIN(–)
CLKIN = 13MHz
8k SAMPLES

CODES

Figure 12. Histogram of Output Codes
with DC Input

–8–

Figure 13. Differential Nonlinearity

REV. A

0

–10
–20
–30
–40
–50
–60
–70
–80

–90
–100
–110
–120
–130

0

dB

0

409.0268

FREQUENCY – kHz

0

–154

dB

–20

–80

–100
–120
–140

–40
–60

0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 96E+3

AIN = 90kHz
XTAL = 12.288MHz
SNR = 88.1dB
S/(N+D) = 88.1dB
SFDR = –103.7dB

90E+3

–10
–20
–30
–40
–50
–60

dB

–70
–80

–90
–100
–110
–120
–130

0

FREQUENCY – MHz

Figure 15. Modulator Output (0 Hz to MCLK/2)

1.0

0.8

0.6

0.4

0.2
0

–0.2

INL ERROR – LSB

–0.4
–0.6

–0.8
–1.0

0 20000 6 5 5 3 540000

CODE

Figure 14. Integral Nonlinearity Error

6.5

Figure 18. Modulator Output (0 to 409.0268 kHz)

AD7724

0

–20
–40

–60
–80

dB

–100
–120
–140

–154

0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3

CLKIN = 13MHz
SNR = 90.1dB
S/(N+D) = 89.2dB
SFDR = –99.5dB
THD = –96.6dB
2ND = –100.9dB
3RD = –106.0dB
4TH = –99.5dB

Figure 16. 16K Point FFT

0
–20
–40
–60
–80

dB

–100
–120
–140

–154

0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 96E+3

Figure 17. 16K Point FFT

REV. A

XTAL = 12.288MHz
SNR = 89.0dB
S/(N+D) = 87.8dB
SFDR = –94.3dB
THD = –93.8dB
2ND = –94.3dB
3RD = –108.5dB
4TH = –105.7dB

90E+3

90E+3

98E+3

–9–

0

AIN = 90kHz

–20

CLKIN = 13MHz
SNR = 89.6dB

–40

S/(N+D) = 89.6dB
SFDR = –108.0dB

–60
–80

dB

–100
–120
–140

–154

0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 98E+3

90E+3

Figure 19. 16K Point FFT

Figure 20. 16K Point FFT

AD7724

ANALOG

INPUT

R

C

VIN(+)

VIN(–)

R

C

CIRCUIT DESCRIPTION

The AD7724 employs a sigma-delta conversion technique to
convert the analog input into a digital pulse train. The analog
input is continuously sampled by a switched capacitor modulator
at twice the rate of the clock input frequency (2 f

MCLK

). The
digital data that represents the analog input is in the ones’ den­sity of the bit stream at the output of the sigma-delta modulator.
The modulator outputs the bit stream at a data rate equal to f

MCLK

.

Due to the high oversampling rate, which spreads the quantiza­tion noise from 0 to f

/2, the noise energy contained in the

MCLK

band of interest is reduced (Figure 21a). To reduce the quantiza­tion noise further, a high order modulator is employed to shape
the noise spectrum, so that most of the noise energy is shifted
out of the band of interest (Figure 21b).

QUANTIZATION NOISE

f

/2

BAND OF INTEREST

MCLK

a.

NOISE SHAPING

f

/2

BAND OF INTEREST

MCLK

b.

Figure 21. Sigma-Delta ADC

f

A

f

B

f

A

f

B

f

A

2pF

2pF

AC

GROUND

f

f

f

A

B

B

VIN(+)

VIN(–)

500V

500V

MCLK

Figure 22. Analog Input Equivalent Circuit

Since the AD7724 samples the differential voltage across its
analog inputs, low noise performance is attained with an input
circuit that provides low differential mode noise at each input.
The amplifiers used to drive the analog inputs play a critical role
in attaining the high performance available from the AD7724.

When a capacitive load is switched onto the output of an op
amp, the amplitude will momentarily drop. The op amp will try
to correct the situation and, in the process, hits its slew rate
limit. This nonlinear response, which can cause excessive ring­ing, can lead to distortion. To remedy the situation, a low-pass
RC filter can be connected between the amplifier and the input
to the AD7724 as shown in Figure 23. The external capacitor at
each input aids in supplying the current spikes created during
the sampling process. The resistor in the diagram, as well as
creating a pole for the antialiasing, isolates the op amp from the
transient nature of the load.

USING THE AD7724
ADC Differential Inputs

The AD7724 uses differential inputs to provide common-mode
noise rejection (i.e., the converted result will correspond to the
differential voltage between the two inputs). The absolute volt­age on both inputs must lie between AGND and AVDD.

In the unipolar mode, the full scale-input range (VIN(+) –
VIN(–)) is 0 V to V

full-scale analog input range is ±V

. In the bipolar mode configuration, the

REF

/2. The bipolar mode

REF

allows complementary input signals. Alternatively, VIN(–) can
be connected to a dc bias voltage to allow a single-ended input
on VIN(+) equal to V

BIAS

± V

REF

/2.

Differential Inputs

The analog input to the modulator is a switched capacitor design.
The analog input is converted into charge by highly linear sam­pling capacitors. A simplified equivalent circuit diagram of the
analog input is shown in Figure 22. A signal source driving the
analog input must be able to provide the charge onto the sam­pling capacitors every half MCLK cycle and settle to the required
accuracy within the next half cycle.

Figure 23. Simple RC Antialiasing Circuit

The differential input impedance of the AD7724 switched capaci­tor input varies as a function of the MCLK frequency, given by
the equation:

Z

= 109/(8 f

IN

MCLK

) k

Ω

Even though the voltage on the input sampling capacitors may
not have enough time to settle to the accuracy indicated by the
resolution of the AD7724, as long as the sampling capacitor
charging follows the exponential curve of RC circuits, only the
gain accuracy suffers if the input capacitor is switched away too
early.

–10–

REV. A

AD7724

f

A

f

B

f

B

4pF

f

A

f

B

f

A

f

BMCLK

REF2

f

A

4pF

SWITCHED-CAP
DAC REF

110nF

AD780

1
2

3
4

8
7

6
5

NC

+V

IN

TEMP
GND

O/P

SELECT

NC

V

OUT

TRIM

22nF

1mF

REF2

22mF

110nF

REF1

5V

NC = NO CONNECT

An alternative circuit configuration for driving the differential
inputs to the AD7724 is shown in Figure 24.

R

100V

R

100V

C

2.7nF

C

2.7nF

C

2.7nF

VIN(+)

VIN(–)

Figure 24. Differential Input with Antialiasing

A capacitor between the two input pins sources or sinks charge
to allow most of the charge needed by one input to be effectively
supplied by the other input. This minimizes undesirable charge
transfer from the analog inputs to and from ground. The series
resistor isolates the operational amplifier from the current spikes
created during the sampling process and provides a pole for
antialiasing. The 3 dB cutoff frequency of the antialias filter is
given by Equation 1, and the attenuation of the filter is given by
Equation 2.

f

= 1/(2␣ π R

3␣ dB

EXT CEXT

Attenuation = 20 log

) (1)



1/ 1+ f / f




()

3 dB



2




(2)

The choice of the filter cutoff frequency will depend on the
amount of roll-off that is acceptable in the passband of the digi­tal filter and the required attenuation at the first image frequency.

The capacitors used for the input antialiasing circuit must have
low dielectric absorption to avoid distortion. Film capacitors
such as polypropylene or polycarbonate are suitable. If ceramic
capacitors are used, they must have NPO dielectric.

Applying the Reference

The reference circuitry used in the AD7724 includes an on-chip

2.5 V bandgap reference and a reference buffer circuit. The
block diagram of the reference circuit is shown in Figure 25.

The internal reference voltage is connected to REF1 via a 3 kΩ

resistor and is internally buffered to drive the analog modulator’s
switched capacitor DAC (REF2). When using the internal refer­ence, connect 110 nF between REF1 and AGND. If the internal
reference is required to bias external circuits, use an external
precision op amp to buffer REF1.

The AD7724 can operate with its internal reference, or an
external reference can be applied in two ways. An external
reference can be connected to REF1, overdriving the internal
reference. However, an error will be introduced due to the
offset of the internal buffer amplifier. For lowest system gain
errors when using an external reference, REF1 is grounded
(disabling the internal buffer) and the external reference is con­nected to REF2.

In all cases, since the REF2 voltage connects to the analog modu­lator, a 110 nF capacitor must connect directly from REF2 to
AGND. The external capacitor provides the charge required for
the dynamic load presented at the REF2 pin (Figure 26).

Figure 26. REF2 Equivalent Circuit

The AD780 is ideal to use as an external reference with the
AD7724. Figure 27 shows a suggested connection diagram.

Figure 27. External Reference Circuit Connection

REF1

110nF

REF2

REV. A

1V

Figure 25. Reference Circuit Block Diagram

COMPARATOR

4kV

REFERENCE

BUFFER

2.5V

REFERENCE

SWITCHED-CAP
DAC REF

–11–

AD7724

CLOCK

CIRCUITRY

MCLK

25–150V

1MV

XTAL1

XTAL2

XTAL_OFF

22pF

SINEWAVE

INPUT

120pF

Input Circuits

Figures 28 and 29 show two simple circuits for bipolar mode
operation. Both circuits accept a single-ended bipolar signal
source and create the necessary differential signals at the input
to the ADC.

The circuit in Figure 28 creates a 0 V to 2.5 V signal at the
VIN(+) pins to form a differential signal around an initial bias
voltage of 1.25 V. For single-ended applications, best THD
performance is obtained with VIN(–) set to 1.25 V rather than

2.5 V. The input to the AD7724 can also be driven differen­tially with a complementary input as shown in Figure 29.

In this case, the input common-mode voltage is set to 2.5 V.
The 2.5 V p-p full-scale differential input is obtained with a

1.25 V p-p signal at each input in antiphase. This configuration
minimizes the required output swing from the amplifier circuit
and is useful for single supply applications.

12pF

–

1/2

OP275

+

1kV

1kV

12pF

–

1/2

OP275
+

1kV

1nF

1nF

DIFFERENTIAL
INPUT = 2.5V p-p

VIN(–) BIAS
VOLTAGE = 2.5V

VIN(+)

VIN(–)

AIN =

1.25V

1kV

The 1 nF capacitors at each input store charge to aid the
amplifier settling as the input is continuously switched. A
resistor in series with the drive amplifier output and the 1 nF
input capacitor may also be used to create an antialias filter.

Clock Generation

The AD7724 contains an oscillator circuit to allow a crystal or
an external clock signal to generate the master clock for the
ADC. The connection diagram for use with the crystal is shown
in Figure 30. Consult the crystal manufacturer's recommenda­tion for the load capacitors.

XTAL MCLK

1MV

Figure 30. Crystal Oscillator Connection

An external clock must be free of ringing and have a minimum
rise time of 5 ns. Degradation in performance can result as high
edge rates increase coupling that can generate noise in the sam­pling process. The connection diagram for an external clock
source (Figure 31) shows a series damping resistor connected
between the clock output and the clock input to the AD7724.
The optimum resistor will depend on the board layout and the
impedance of the trace connecting to the clock input.

OP07

+

110nF

–

110nF

REF1

REF2

R

R

Figure 28. Single-Ended Analog Input for Bipolar Mode
Operation

12pF

AIN =

60.625V

1kV

1/2

OP275

R

R

1kV

1kV

12pF

1/2

OP275

OP07

1kV

1nF

1nF

110nF

110nF

VIN(–)

DIFFERENTIAL
INPUT = 2.5V p-p

COMMON-MODE
VOLTAGE = 2.5V

VIN(+)

REF1

REF2

Figure 31. External Clock Oscillator Connection

A low phase clock should be used to generate the ADC sam­pling clock because sampling clock jitter effectively modulates
the input signal and raises the noise floor. The sampling clock
generator should be isolated from noisy digital circuits, grounded
and heavily decoupled to the analog ground plane.

A sine wave can also be used to provide the clock (Figure 32.) A
sine wave with a voltage swing between 0.4 V p-p and 4 V p-p is

needed. XTAL_OFF is tied low and a 1 MΩ resistor is needed

between XTAL1 and XTAL2. A 22 pF capacitor is connected
in parallel with this resistor. The sine wave is ac coupled to
XTAL1 using a 120 pF capacitor. The use of a sine wave to
generate the clock eliminates the need for a square wave clock
source which introduces noise.

Figure 32. Using a Sine Wave Input as a Clock Source

Figure 29. Single-Ended-to-Differential Analog Input
Circuit for Bipolar Mode Operation

–12–

REV. A

AD7724

The sampling clock generator should be referenced to the ana­log ground plane in a split ground system. However, this is not
always possible because of system constraints. In many cases,
the sampling clock must be derived from a higher frequency
multipurpose system clock that is generated on the digital
ground plane. If the clock signal is passed between its origin on
a digital plane to the AD7724 on the analog ground plane, the
ground noise between the two planes adds directly to the clock
and will produce excess jitter. The jitter can cause unwanted
degradation in the signal-to-noise ratio and also produce un­wanted harmonics.

This can be somewhat remedied by transmitting the sampling
signal as a differential one, using either a small RF transformer
or a high-speed differential driver and receiver such as PECL. In
either case, the original master system clock should be generated
from a low phase noise crystal oscillator.

Offset and Gain Calibration

The analog inputs of the AD7724 can be configured to measure
offset and gain errors. Pins MZERO and GC are used to config­ure the part. Before calibrating the device, the part should be
reset so that the modulator is in a known state at calibration.
When MZERO is taken high, the analog inputs are tied to AGND
in unipolar mode and VREF in bipolar mode. After taking
MZERO high, 1000 MCLK cycles should be allowed for the
circuitry to settle before the bit stream is read from the device.
The ideal ones density is 50% when bipolar operation is selected
and 37.5% when unipolar mode is selected.

When GC is taken high, VIN(–) is tied to ground while VIN(+)
is tied to VREF. Again, 1000 MCLK cycles should be allowed
for the circuitry to settle before the bit stream is read. The ideal
ones density is 62.5%.

The calibration results apply only for the particular analog input
mode (unipolar/bipolar) selected when performing the calibra­tion cycle. On changing to a different analog input mode, a new
calibration must be performed.

Before calibrating, ensure that the supplies have settled and that
the voltage on the analog input pins is between the supply voltages.

Standby

The part can be put into a low power standby mode by taking
STBY high. During standby, the clock to the modulators is
turned off and bias is removed from all analog circuits.

Reset

The RESET pin is used to reset the modulators to a known
state. When RESET is taken high, the integrator capacitors of
the modulator are shorted and DVAL goes low and remains low
until 20 MCLK cycles after RESET is deasserted. However, an
additional 1000 MCLK cycles should be allowed before reading
the modulator bit stream as the modulator circuitry needs to
settle after the reset.

DVAL

The DVAL pin is used to indicate that an overrange input signal
has resulted in invalid data at the modulator output. As with all
single-bit DAC high-order sigma-delta modulators, large over­loads on the inputs can cause the modulator to go unstable. The
modulator is designed to be stable with signals within the input
bandwidth that exceed full-scale by 100%. When instability is
detected by internal circuits, the modulator is reset to a stable
state and DVAL is held low for 20 clock cycles.

Grounding and Layout

Since the analog inputs are differential, most of the voltages in
the analog modulator are common-mode voltages. The excel­lent common-mode rejection of the part will remove common­mode noise on these inputs. The analog and digital supplies to
the AD7724 are independent and separately pinned out to mini­mize coupling between analog and digital sections of the device.

The printed circuit board that houses the AD7724 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes as it gives the
best shielding. Digital and analog ground planes should be
joined in only one place. If the AD7724 is the only device
requiring an AGND-to-DGND connection, the ground planes
should be connected at the AGND and DGND pins of the
AD7724. If the AD7724 is in a system where multiple devices
require AGND-to-DGND connections, the connection should
still be made at one point only, a star ground point that should
be established as close as possible to the AD7724.

Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7724 to avoid noise coupling. The power
supply lines to the AD7724 should use as large a trace as pos­sible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals such as
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board, and clock signals should
run at right angles to each other. This will reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best, but is not always possible with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes while signals are placed on the other side.

Good decoupling is important when using high resolution
ADCs. All analog and digital supplies should be decoupled to
AGND and DGND respectively, with 100 nF ceramic capaci-

tors in parallel with 10 µF tantalum capacitors. To achieve the

best from these decoupling capacitors, they should be placed as
close as possible to the device, ideally right up against the
device. In systems where a common supply voltage is used to
drive both the AVDD and DVDD of the AD7724, it is recom­mended that the system’s AVDD supply be used. This supply
should have the recommended analog supply decoupling between
the AVDD pins of the AD7724 and AGND and the recom­mended digital supply decoupling between the DVDD pins and
DGND.

REV. A

–13–

AD7724

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

48-Lead Plastic Thin Quad Flatpack

(ST-48)

0.063 (1.60)

0.030 (0.75)

0.018 (0.45)

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

MAX

0.007 (0.18)

0.004 (0.09)

0.354 (9.00) BSC SQ

48

1

12

08

13

MIN

0.019 (0.5)

78
08

TOP VIEW

(PINS DOWN)

BSC

0.011 (0.27)

0.006 (0.17)

37

24

36

25

0.276
(7.00)

BSC

SQ

0.057 (1.45)

0.053 (1.35)

C3614–0–1/00 (rev. A)

–14–

PRINTED IN U.S.A.

REV. A