Page 1
16-Bit, 1.2 MSPS
a
FEATURES
16-Bit Sigma-Delta ADC
1.2 MSPS Output Word Rate
32/16 3 Oversampling Ratio
Low-Pass and Band-Pass Digital Filter
Linear Phase
On-Chip 2.5 V Voltage Reference
Standby Mode
Flexible Parallel or Serial Interface
Crystal Oscillator
Single +5 V Supply
AV
AGND
VIN(+)
VIN(–)
UNI
HALF_PWR
STBY
MODE 1
MODE 2
SYNC
DVDD/CS
CFMT/RD
DGND/DRDY
DGND/DB0
CMOS, Sigma-Delta ADC
AD7723
FUNCTIONAL BLOCK DIAGRAM
FIR
FSI/
DB6
2.5V
REFERENCE
XTAL
CLOCK
SCO/
DB7
SDO/
DB8
DD
DGND/
DB1
AD7723
MODULATOR
DGND/
DGND/
DB2
DB3
CONTROL
LOGIC
DOE/
SFMT/
DB4
FILTER
DB5
REF2
REF1
DV
DD
DGND
XTAL_OFF
XTAL
CLKIN
DGND/DB15
DGND/DB14
SCR/DB13
SLDR/DB12
SLP/DB11
TSI/DB10
FSO/DB9
GENERAL DESCRIPTION
The AD7723 is a complete 16-bit, sigma-delta ADC. The part
operates from a +5␣ V supply. The analog input is continuously
sampled, eliminating the need for an external sample-and-hold.
The modulator output is processed by a finite impulse response
(FIR) digital filter. The on-chip filtering combined with a high
oversampling ratio reduces the external antialias requirements
to first order in most cases. The digital filter frequency response
can be programmed to be either low pass or band pass.
The AD7723 provides 16-bit performance for input bandwidths
up to 460␣ kHz at an output word rate up to 1.2 MHz. The
sample rate, filter corner frequencies and output word rate are
set by the crystal oscillator or external clock frequency.
Data can be read from the device in either serial or parallel
format. A stereo mode allows data from two devices to share a
single serial data line. All interface modes offer easy, high speed
connections to modern digital signal processors.
The part provides an on-chip 2.5␣ V reference. Alternatively, an
external reference can be used.
A power-down mode reduces the idle power consumption to
200 µW.
The AD7723 is available in a 44-lead PQFP package and is
specified over the industrial temperature range from –40°C to
+85°C.
Two input modes are provided, allowing both unipolar and
bipolar input ranges.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
Page 2
(AVDD = DVDD = +5 V 6 5%; AGND = AGND1 = AGND2 = DGND = 0 V;
1
f
AD7723–SPECIFICATIONS
= 19.2 MHz; REF2 = 2.5 V; TA = T
CLKIN
MIN
to T
; unless otherwise noted)
MAX
B Version
Parameter Test Conditions/Comments Min Typ Max Units
DYNAMIC SPECIFICATIONS
Decimate by 32
Bipolar Mode
Signal to Noise
Full Power 2.5 V Reference 87 90 dB
Half Power 86.5 89 dB
Total Harmonic Distortion
Spurious Free Dynamic Range
Unipolar Mode
Signal to Noise 87 dB
Total Harmonic Distortion
Spurious Free Dynamic Range
Bandpass Filter Mode
Bipolar Mode
Signal to Noise 76 79 dB
Decimate by 16
Bipolar Mode
Signal to Noise Measurement Bandwidth = 0.383 × F
Signal to Noise Measurement Bandwidth = 0.5 × F
Total Harmonic Distortion
Spurious Free Dynamic Range
Unipolar Mode
Signal to Noise Measurement Bandwidth = 0.383 × F
Signal to Noise Measurement Bandwidth = 0.5 × F
Total Harmonic Distortion
DIGITAL FILTER RESPONSE
Low Pass Decimate by 32
0 kHz to f
f
/66.9 –3 dB
CLKIN
f
/64 –6 dB
CLKIN
f
/51.9 to f
CLKIN
/83.5 ±0.001 dB
CLKIN
CLKIN
Group Delay 1293/2f
Settling Time 1293/f
Low Pass Decimate by 16
0 kHz to f
f
/33.45 –3 dB
CLKIN
f
/32 –6 dB
CLKIN
f
/25.95 to f
CLKIN
/41.75 ±0.001 dB
CLKIN
CLKIN
Group Delay 541/2f
Settling Time 541/f
Band Pass Decimate by 32
f
/51.90 to f
CLKIN
f
/62.95, f
CLKIN
f
/64, f
CLKIN
0 kHz to f
CLKIN
CLKIN
/32 –6 dB
CLKIN
/83.5, f
CLKIN
Group Delay 1293/2f
Settling Time 1293/f
Output Data Rate, F
O
Decimate by 32 f
Decimate by 16 f
ANALOG INPUTS
Full-Scale Input Span VIN(+) – VIN(–)
Bipolar Mode ±4/5 × V
Unipolar Mode 0 8/5 × V
2, 3
HALF_PWR = 0 or 1
f
= 10 MHz When HALF-PWR = 1
CLKIN
3 V Reference 88.5 91 dB
4
4
2.5 V Reference –92 dB
–96 –90 dB
3 V Reference –90 dB
4
4
O
–89 dB
–90 dB
2.5 V Reference 82 86 dB
3 V Reference 83 87 dB
4
2.5 V Reference –88 dB
3 V Reference –86 dB
4
2.5 V Reference –90 dB
O
78 81.5 dB
3 V Reference –88 dB
O
4
O
84 dB
81 dB
–89 dB
/2 –90 dB
CLKIN
CLKIN
/2 –90 dB
CLKIN
CLKIN
/41.75 ±0.001 dB
/33.34 –3 dB
CLKIN
/25.95 to f
/2 –90 dB
CLKIN
CLKIN
CLKIN
/32
CLKIN
/16
CLKIN
REF2
REF2
V
V
–2– REV. 0
Page 3
AD7723
B Version
Parameter Test Conditions/Comments Min Typ Max Units
ANALOG INPUTS (Continued)
Absolute Input Voltage VIN(+) and/or VIN(–) AGND AV
DD
Input Sampling Capacitance 2pF
Input Sampling Rate, f
CLKIN
19.2 MHz
CLOCK
CLKIN Duty Ratio 45 55 %
REFERENCE
REF1 Output Resistance 3kΩ
Using Internal Reference
REF2 Output Voltage 2.39 2.54 2.69 V
REF2 Output Voltage Drift 60 ppm/°C
Using External Reference
REF2 Input Impedance REF1 = AGND 4 kΩ
REF2 External Voltage Range 1.2 2.5 3.15 V
STATIC PERFORMANCE
Resolution 16 Bits
Differential Nonlinearity Guaranteed Monotonic ±0.5 ±1 LSB
Integral Nonlinearity ±2 LSB
DC CMRR 80 dB
Offset Error ±20 mV
Gain Error
5
±0.5 % FSR
LOGIC INPUTS (Excluding CLKIN)
, Input High Voltage 2.0 V
V
INH
V
, Input Low Voltage 0.8 V
INL
CLOCK INPUT (CLKIN)
V
, Input High Voltage 3.8 V
INH
V
, Input Low Voltage 0.4 V
INL
ALL LOGIC INPUTS
I
, Input Current VIN = 0 V to DV
IN
DD
±10 µA
CIN, Input Capacitance 10 pF
LOGIC OUTPUTS
, Output High Voltage |I
V
OH
VOL, Output Low Voltage |I
| = 200 µA 4.0 V
OUT
| = 1.6 mA 0.4 V
OUT
POWER SUPPLIES
AV
I
AVDD
DD
HALF_PWR = Logic Low 50 60 mA
4.75 5.25 V
HALF_PWR = Logic High 25 33 mA
DV
DD
I
DVDD
Power Consumption
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
2
Typical values for SNR apply for parts soldered directly to a printed circuit board ground plane.
3
Dynamic specifications apply for input signal frequencies from dc to 0.0240 × f
4
When using the internal reference, THD and SFDR specifications apply only to input signals above 10 kHz with a 10 µF decoupling capacitor between REF2 and
AGND2. At frequencies below 10 kHz, THD degrades to 84 dB and SFDR degrades to 86 dB.
5
Gain Error excludes Reference Error.
6
CLKIN and digital inputs static and equal to 0 or DVDD.
Specifications subject to change without notice.
6
HALF_PWR = Logic Low 25 35 mA
HALF_PWR = Logic High 15 20 mA
Standby Mode 200 µW
in decimate by 16 mode and from dc to 0.0120 × f
CLKIN
4.75 5.25 V
in decimate by 32 mode.
CLKIN
V
–3–REV. 0
Page 4
AD7723
TIMING SPECIFICATIONS
(AVDD = DVDD = +5 V 6 5%; AGND = AGND1 = DGND = 0 V; f
Logic Low or High, CFMT = Logic Low or High; TA = T
MIN
to T
= 19.2 MHz; CL = 50 pF; SFMT =
CLKIN
unless otherwise noted)
MAX
Parameter Symbol Min Typ Max Units
CLKIN Frequency F
CLKIN Period (t
CLK
= 1/f
)t
CLK
CLKIN Low Pulsewidth t
CLKIN High Pulsewidth t
CLKIN Rise Time t
CLKIN Fall Time t
FSI Setup Time t
FSI Hold Time t
FSI High Time
CLKIN to SCO Delay t
SCO Period
1
2
, SCR = 1 t
SCO Period2, SCR = 0 t
SCO Transition to FSO High Delay t
SCO Transition to FSO Low Delay t
SCO Transition to SDO Valid Delay t
SCO Transition from FSI
3
SDO Enable Delay Time t
SDO Disable Delay Time t
DRDY High Time
2
Conversion Time2 (Refer to Tables I and II) t
CLKIN to DRDY Transition t
CLKIN to DATA Valid t
CS/RD Setup Time to CLKIN t
CS/RD Hold Time to CLKIN t
Data Access Time t
Bus Relinquish Time t
SYNC Input Pulsewidth t
SYNC Low Time before CLKIN Rising t
DRDY High Delay after Rising SYNC t
DRDY Low Delay after SYNC Low t
NOTES
1
FSO pulses are gated by the release of FSI (going low).
2
Guaranteed by design.
3
Frame Sync is initiated on the falling edge of CLKIN.
Specifications subject to change without notice.
CLK
1
2
3
4
5
6
7
t
8
9
10
10
11
12
13
t
14
15
16
t
17
18
19
20
21
22
23
24
25
26
27
28
1 19.2 MHz
0.052 1 µs
0.45 × t
0.45 × t
1
1
0.55 × t
0.55 × t
1
1
5ns
5ns
05ns
05ns
1t
CLK
25 40 ns
2t
1t
CLK
CLK
05 ns
05 ns
512 ns
60 t
CLK
+ t
2
520 ns
520 ns
2t
16/32 t
CLK
CLK
35 50 ns
20 35 ns
0ns
20 ns
20 35 ns
20 35 ns
1t
CLK
0ns
25 35 ns
2049 t
CLK
I
OL
1.6mA
TO
OUTPUT
PIN
50pF
C
L
I
OH
200mA
+1.6V
Figure 1. Load Circuit for Timing Specifications
–4– REV. 0
Page 5
AD7723
CLKIN
FSI
SCO
(SFMT = 1)
(CFMT = 0)
2.3V
t
5
0.8V
t
1
t
9
t
10
t
4
t
3
t
t
6
t
8
t
9
7
t
2
Figure 2. Serial Mode Timing for Clock Input, Frame Sync Input and Serial Clock Output
32 CLKIN CYCLES
CLKIN
t
8
FSI
t
14
SCO
t
11
FSO
(SFMT = 0)
t
11
FSO
(SFMT = 1)
SDO
t
12
t
13
D15 D14 D13 D2 D1 D0 D15 D14
Figure 3. Serial Mode 1. Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output
(Refer to Table I for Control Inputs, TSI = DOE)
32 CLKIN CYCLES
CLKIN
t
8
FSI
t
SCO
(CFMT = 0)
FSO
14
t
11
t
12
t
13
SDO
D2 D1 D0 D15 D14 D13 D12 D11
D3 D2 D1 D0 D15 D14
D4
D5
Figure 4. Serial Mode 2. Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output
(Refer to Table I for Control Inputs, TSI = DOE)
–5–REV. 0
Page 6
AD7723
16 CLKIN CYCLES
CLKIN
t
8
FSI
t
SCO
(CFMT = 0)
FSO
SDO
Figure 5. Serial Mode 3. Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output
(Refer to Table I for Control Inputs, TSI = DOE)
14
t
11
t
13
D2 D1 D0 D15 D14 D13 D12 D11 D5 D4 D3 D2 D1 D0 D15 D14
t
12
Table I. Serial Interface (Mode1 = 0, Mode2 = 0)
Decimation Digital Filter SCO Frequency Output Data Control Inputs
Serial Mode Ratio (SLDR) Mode (SLP) (SCR) Rate SLDR SLP SCR
1 32 Low Pass f
1 32 Band Pass f
2 32 Low Pass f
2 32 Band Pass f
3 16 Low Pass f
CLKIN
CLKIN
/2 f
CLKIN
/2 f
CLKIN
CLKIN
f
/32 1 1 0
CLKIN
f
/32 1 0 0
CLKIN
/32 1 1 1
CLKIN
/32 1 0 1
CLKIN
f
/16 0 1 0
CLKIN
Table II. Parallel Interface
Digital Filter Decimation Output Control Inputs
Mode Ratio Data Rate MODE1 MODE2
Band Pass 32 f
Low Pass 32 f
Low Pass 16 f
DOE
t
15
SDO
/32 0 1
CLKIN
/32 1 0
CLKIN
/16 1 1
CLKIN
t
16
Figure 6. Serial Mode Timing for Data Output Enable and Serial Data Output
–6– REV. 0
Page 7
CLKIN
DRDY
AD7723
t
18
t
t
19
t
17
t
20
19
DB0–DB15
CLKIN
DRDY
RD/CS
DB0–DB15
WORD N – 1 WORD N + 1
Figure 7a. Parallel Mode Read Timing, CS and
t
19
t
22
t
t
21
22
VALID DATA
t
23
Figure 7b. Parallel Mode Read Timing, CS =
WORD N
RD
Tied Logic Low
t
18
t
19
t
21
t
24
RD
CLKIN
SYNC
DRDY
t
28
t
26
t
25
t
27
Figure 8. SYNC Timing
–7–REV. 0
Page 8
AD7723
ABSOLUTE MAXIMUM RATINGS*
(T
= +25°C unless otherwise noted)
A
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
AV
DD
DD
, AV
, AV
to AGND . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DD1
to DVDD . . . . . . . . . . . . . . . . . . . –1 V to +1 V
DD1
Model Range Description Option
AD7723BS –40°C to +85°C Plastic Quad Flatpack S-44
ORDERING GUIDE
Temperature Package Package
AGND, AGND1 to DGND . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Inputs to DGND . . . . . . . . . –0.3 V to DV
Digital Outputs to DGND . . . . . . . . –0.3 V to DV
VIN(+), VIN(–) to AGND . . . . . . . . –0.3 V to AV
REF1 to AGND . . . . . . . . . . . . . . . . –0.3 V to AV
REF2 to AGND . . . . . . . . . . . . . . . . –0.3 V to AV
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
DD
Operating Temperature Range . . . . . . . . . . – 40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 95°C/W
θ
JA
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7723 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
DGND/DB2
DGND/DB1
DGND/DB0
CFMT/RD
DGND/DRDY
DGND
MODE2
MODE1
AGND1
AGND1
AV
DD1
PIN CONFIGURATION
44-Lead PQFP Package
DD
SCO/DB7
DOE/DB4
XTAL
FSI/DB6
SFMT/DB5
AD7723
TOP VIEW
(Not to Scale)
XTAL_OFF
HALF_PWR
DGND/DB3
1
PIN 1
IDENTIFIER
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
CLKIN
SDO/DB8
DV
40 39 3841424344 36 35 3437
DD
AV
AGND
AGND
TSI/DB10
FSO/DB9
VIN(–)
VIN(+)
SLDR/DB12
SLP/DB11
REF1
AGND2
33
SCR/DB13
32
DGND/DB14
31
DGND/DB15
30
DVDD/CS
29
SYNC
28
DGND
27
STBY
26
AV
25
AGND
24
UNI
23
REF2
DD
–8– REV. 0
Page 9
AD7723
PIN FUNCTION DESCRIPTIONS
Mnemonic Pin No. Description
AV
DD1
AGND1 9, 10 Digital Logic Power Supply Ground for the Analog Modulator.
AV
DD
AGND 16, 18, 25 Power Supply Ground for the Analog Modulator.
AGND2 22 Power Supply Ground Return to the Reference Circuitry, REF2, of the Analog Modulator.
DV
DD
DGND 6, 28 Ground Reference for Digital Circuitry.
REF1 21 Reference Output. REF1 connects through 3 kΩ to the output of the internal 2.5 V reference and to
REF2 23 Reference Input. REF2 connects to the output of an internal buffer amplifier that drives the Σ−∆
VIN(+) 20 Positive Terminal of the Differential Analog Input.
VIN(–) 19 Negative Terminal of the Differential Analog Input.
UNI 24 Analog Input Range Select Input. The UNI pin selects the analog input range for either bipolar or unipo-
CLKIN 12 Clock Input. An external clock source can be applied directly to this pin with XTAL_OFF tied high.
XTAL 13 Input to Crystal Oscillator Amplifier. If an external clock is used, XTAL should be tied to AGND1.
XTAL_OFF 14 Oscillator Enable Input. A logic high disables the crystal oscillator amplifier to allow use of an exter-
MODE1/2 8, 7 Mode Control Inputs. The MODE1 and MODE2 pins choose either parallel or serial data interface
HALF_PWR 15 When set high, the power dissipation is reduced by approximately one-half and a maximum CLKIN
SYNC 29 Synchronization Logic Input. When using more than one AD7723, operated from a common master
STBY 27 Standby Logic Input. A logic high sets the AD7723 into the power-down state.
11 Digital Logic Power Supply Voltage for the Analog Modulator.
17, 26 Positive Power Supply Voltage for the Analog Modulator.
39 Digital Power Supply Voltage; +5 V ± 5%.
a buffer amplifier that drives the Σ−∆ modulator.
modulator. When REF2 is used as an input, REF1 must be connected to AGND to disable the internal buffer amplifier.
lar operation. A logic high input selects unipolar operation and a logic low selects bipolar operation.
Alternatively, a parallel resonant fundamental frequency crystal, in parallel with a 1 MΩ resistor can
be connected between the XTAL pin and the CLKIN pin with XTAL_OFF tied low. External
capacitors are then required from the CLKIN and XTAL pins to ground. Consult the crystal
manufacturer’s recommendation for the load capacitors.
nal clock source. Set low when using an external crystal between the CLKIN and XTAL pins.
operation and select the operating mode for the digital filter in parallel mode. Refer to Tables I and II.
frequency of 10 MHz applies.
clock, SYNC allows each ADC to simultaneously sample its analog input and update its output
register. A rising edge resets the AD7723 digital filter sequencer counter to zero. When the rising
edge of CLKIN senses a logic low on SYNC, the reset state is released. Because the digital filter and
sequencer are completely reset during this action, SYNC pulses cannot be applied continuously.
–9–REV. 0
Page 10
AD7723
PARALLEL MODE PIN FUNCTION DESCRIPTIONS
Mnemonic Pin No. Description
DV
/CS 30 Chip Select Logic Input.
DD
CFMT/RD 4 Read Logic Input. Used in conjunction with CS to read data from the parallel bus. The output data
bus is enabled when the rising edge of CLKIN senses a logic low level on RD if CS is also low. When
RD is sensed high, the output data bits, DB15–DB0 will be high impedance.
DGND/DRDY 5 Data Ready Logic Output. A falling edge indicates a new output word is available to be read from
the output data register. DRDY will return high upon completion of a read operation. If a read operation
does not occur between output updates, DRDY will pulse high for two CLKIN cycles before the next
output update. DRDY also indicates when conversion results are available after a SYNC sequence.
DGND/DB15 31 Data Output Bit, (MSB)
DGND/DB14 32 Data Output Bit.
SCR/DB13 33 Data Output Bit.
SLDR/DB12 34 Data Output Bit.
SLP/DB11 35 Data Output Bit.
TSI/DB10 36 Data Output Bit.
FSO/DB9 37 Data Output Bit.
SDO/DB8 38 Data Output Bit.
SCO/DB7 40 Data Output Bit.
FSI/DB6 41 Data Output Bit.
SFMT/DB5 42 Data Output Bit.
DOE/DB4 43 Data Output Bit.
DGND/DB3 44 Data Output Bit.
DGND/DB2 1 Data Output Bit.
DGND/DB1 2 Data Output Bit.
DGND/DB0 3 Data Output Bit, (LSB).
–10– REV. 0
Page 11
AD7723
SERIAL MODE PIN FUNCTION DESCRIPTIONS
Mnemonic Pin No. Description
CFMT/RD 4 Serial Clock Format Logic Input. The clock format pin selects whether the serial data, SDO, is valid
on the rising or falling edge of the serial clock, SCO. When CFMT is logic low, serial data is valid on
the falling edge of the serial clock, SCO. If CFMT is logic high, SDO is valid on the rising edge of
SCO.
DOE/DB4 43 Data Output Enable Logic Input. The DOE pin controls the three-state output buffer of the SDO
pin. The active state of DOE is determined by the logic level on the TSI pin. When the DOE logic
level equals the level on the TSI pin the serial data output, SDO, is active. Otherwise SDO will be
high impedance. SDO can be three-state after a serial data transmission by connecting DOE to FSO.
In normal operations, TSI and DOE should be tied low.
SFMT/DB5 42 Serial Data Format Logic Input. The logic level on the SFMT pin selects the format of the FSO
signal for Serial Mode 1. A logic low makes the FSO output a pulse, one SCO cycle wide at the
beginning of a serial data transmission. With SFMT set to a logic high, the FSO signal is a frame
pulse that is active low for the duration of the 16-bit transmission. For Serial Modes 2 and 3, SFMT
should be tied high.
FSI/DB6 41 Frame Synchronization Logic Input. The FSI input is used to synchronize the AD7723 serial output
data register to an external source and to allow more than one AD7723, operated from a common
master clock, to simultaneously sample its analog input and update its output register.
SCO/DB7 40 Serial Clock Output.
SDO/DB8 38 Serial Data Output. The serial data is shifted out MSB first, synchronous with the SCO. Serial
Mode 1 data transmissions last 32 SCO cycles. After the LSB is output, trailing zeros are output for
the remaining 16 SCO cycles. Serial Modes 2 and 3 data transmissions last 16 SCO cycles.
FSO/DB9 37 Frame Sync Output. FSO indicates the beginning of a word transmission on the SDO pin. Depend-
ing on the logic level of the SFMT pin, the FSO signal is either a positive pulse approximately one
SCO period wide, or a frame pulse which is active low for the duration of the 16-data bit transmission.
TSI/DB10 36 Time Slot Logic Input. The logic level on TSI sets the active state of the DOE pin. With TSI set
logic high, DOE will enable the SDO output buffer when it is a logic high, and vice versa. TSI is
used when two AD7723s are connected to the same serial data bus. When this function is not
needed, TSI and DOE should be tied low.
SLP/DB11 35 Serial Mode Low Pass/Band Pass Filter Select Input. With SLP set logic high, the low-pass filter
response is selected. A logic low selects band pass.
SLDR/DB12 34 Serial Mode Low/High Output Data Rate Select Input. With SLDR set logic high, the low data rate
is selected. A logic low selects the high data rate. The high data rate corresponds to data at the out-
put of the fourth decimation filter (Decimate by 16). The low data rate corresponds to data at the
output of the fifth decimation filter (Decimate by 32).
SCR/DB13 33 Serial Clock Rate Select Input. With SCR set logic low, the serial clock output frequency, SCO, is
equal to the CLKIN frequency. A logic high sets it equal to one-half the CLKIN frequency.
DV
/CS 30 Tie to DVDD.
DD
DGND/DB14 32 Tie to DGND.
DGND/DB15 31 Tie to DGND.
DGND/DRDY 5 Tie to DGND.
DGND/DB0 3 Tie to DGND.
DGND/DB1 2 Tie to DGND.
DGND/DB2 1 Tie to DGND.
DGND/DB3 44 Tie to DGND.
–11–REV. 0
Page 12
AD7723
TERMINOLOGY
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all of the nonfundamental signals up to
half the output data rate (F
/2), excluding dc. The ADC is
O
evaluated by applying a low noise, low distortion sine wave
signal to the input pins. By generating a Fast Fourier Transform
(FFT) plot, the SNR data can then be obtained from the output spectrum.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the harmonics to the rms
value of the fundamental. THD is defined as:
2
2
2
2
2
+V
5
6
THD = 20 log
+V
+V
V
2
3
+V
4
V
1
where V1 is the rms amplitude of the fundamental and V2, V3,
, V5 and V6 are the rms amplitudes of the second through
V
4
sixth harmonics. The THD is also derived from the FFT plot of
the ADC output spectrum.
Spurious Free Dynamic Range (SFDR)
Defined as the difference, in dB, between the peak spurious or
harmonic component in the ADC output spectrum (up to F
/2
O
and excluding dc) and the rms value of the fundamental.
Normally, the value of this specification will be determined by
the largest harmonic in the output spectrum of the FFT. For
input signals whose second harmonics occur in the stop band
region of the digital filter, the spur in the noise floor limits the
SFDR.
Passband Ripple
The frequency response variation of the AD7723 in the defined
passband frequency range.
Passband Frequency
The frequency up to which the frequency response variation is
within the passband ripple specification.
Cutoff Frequency
The frequency below which the AD7723’s frequency response
will not have more than 3 dB of attenuation.
Stopband Frequency
The frequency above which the AD7723’s frequency response
will be within its stopband attenuation.
Stopband Attenuation
The AD7723’s frequency response will not have less than 90 dB
of attenuation in the stated frequency band.
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are minus full scale, a point
0.5 LSB below the first code transition (100 . . . 00 to 100 . . . 01
in bipolar mode, 000 . . . 00 to 000 . . . 01 in unipolar mode)
and plus full scale, a point 0.5 LSB above the last code transition (011 . . . 10 to 011 . . . 11 in bipolar mode, 111 . . . 10 to
111 . . . 11 in unipolar mode). The error is expressed in LSBs.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between two adjacent codes in the ADC.
Common-Mode Rejection Ratio
The ability of a device to reject the effect of a voltage applied to
both input terminals simultaneously—often through variation of
a ground level—is specified as a common–mode rejection ratio.
CMRR is the ratio of gain for the differential signal to the gain
for the common-mode signal.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
(10 . . . 000 to 10 . . . 001) from the ideal differential voltage
(VIN(+) – VIN(–)+ 0.5 LSB) when operating in the unipolar
mode.
Bipolar Offset Error
This is the deviation of the midscale transition code (111 . . . 11
to 000 . . . 00) from the ideal differential voltage (VIN(+) –
VIN(–) – 0.5 LSB) when operating in the bipolar mode.
Gain Error
The first code transition should occur at an analog value 1/2 LSB
above –full scale. The last transition should occur for an analog
value 1 1/2 LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
–12– REV. 0
Page 13
Typical Performance Characteristics–
106
104
88
dB
96
94
92
90
100
98
102
TEMPERATURE – 8C
100–250 255075
–50
SNR
THD
2ND
3RD
SIGNAL FREQUENCY = 98kHz
MEASUREMENT BANDWIDTH = 300kHz
OUTPUT WORD RATE – kHz
115
90
50 150
dB
300 600 900
110
105
95
100
SNR
THD
SFDR
INPUT SIGNAL = 10kHz
MEASUREMENT BANDWIDTH = 0.5 3 OWR
450 750
(AVDD = DVDD = 5 V; TA = +258C; CLKIN = 19.2 MHz; External +2.5 V Reference, unless otherwise noted)
110
SIGNAL FREQUENCY = 98kHz
MEASUREMENT BANDWIDTH = 460kHz
100
AD7723
90
80
dB
70
60
50
40
–28 2–23
THD
SFDR
SNR
–18 –13 –8 –3
ANALOG INPUT LEVEL – dB
Figure 9. SNR, THD and SFDR vs. Analog Input Level
Relative to Full Scale (Output Data Rate = 1.2 MHz)
110
SIGNAL FREQUENCY = 98kHz
MEASUREMENT BANDWIDTH = 300kHz
100
90
80
dB
70
60
50
40
–28 2–23
THD
SFDR
SNR
–18 –13 –8 –3
ANALOG INPUT LEVEL – dB
Figure 10. SNR, THD and SFDR vs. Analog Input Level
Relative to Full Scale (Output Data Rate = 600 kHz)
Figure 12. SNR and THD vs. Temperature (Output Data
Rate = 600 kHz)
106
104
102
100
98
96
dB
INPUT SIGNAL = 10kHz
94
MEASUREMENT BANDWIDTH = 0.383 3 OWR
92
90
88
86
84
100 500
SFDR
1000 1500 2150
OUTPUT WORD RATE – kHz
THD
SNR
Figure 13. SNR, THD and SFDR vs. Sampling Frequency
(Decimate by 16)
102
SIGNAL FREQUENCY = 98kHz
MEASUREMENT BANDWIDTH = 460kHz
100
98
96
94
dB
92
90
88
86
84
–50
Figure 11. SNR and THD vs. Temperature (Output Data
Rate = 1.2 MHz)
TEMPERATURE – 8C
3RD
2ND
THD
SNR
100–250 255075
Figure 14. SNR, THD and SFDR vs. Sampling Frequency
(Decimate by 32)
–13–REV. 0
Page 14
AD7723
2000
VIN(+) = VIN(–)
8192 SAMPLES TAKEN
1800
1600
1400
1200
1000
800
600
400
FREQUENCY OF OCCURRENCE
200
0
32700 3271332702
32704 32706 32708 32710 32712
CODE
Figure 15. Histogram of Output Codes with DC Input
(Output Data Rate = 1.2 MHz)
5000
VIN(+) = VIN(–)
8192 SAMPLES TAKEN
4500
4000
3500
3000
2500
2000
1500
1000
FREQUENCY OF OCCURRENCE
500
0
32703 3271032704
32705 32706 32707 32708 32709
CODE
Figure 16. Histogram of Output Codes with DC Input
(Output Data Rate = 600 kHz)
1.00
67108864 SAMPLES TAKEN
DIFFERENTIAL MODE
0.80
0.60
0.40
0.20
0.00
–0.20
DNL ERROR – LSB
–0.40
–0.60
–0.80
–1.00
0
CODE
6553516384 32768 49152
Figure 18. Differential Nonlinearity (Output Data
Rate = 600 kHz)
1.00
67108864 SAMPLES TAKEN
DIFFERENTIAL MODE
0.80
0.60
0.40
0.20
0.00
–0.20
INL ERROR – LSB
–0.40
–0.60
–0.80
–1.00
0
CODE
6553516384 32768 49152
Figure 19. Integral Nonlinearity (Output Data
Rate = 1.2 MHz)
1.00
67108864 SAMPLES TAKEN
DIFFERENTIAL MODE
0.80
0.60
0.40
0.20
0.00
–0.20
DNL ERROR – LSB
–0.40
–0.60
–0.80
–1.00
0
CODE
6553516384 32768 49152
Figure 17. Differential Nonlinearity (Output Data
Rate = 1.2 MHz)
1.00
67108864 SAMPLES TAKEN
DIFFERENTIAL MODE
0.80
0.60
0.40
0.20
0.00
–0.20
INL ERROR – LSB
–0.40
–0.60
–0.80
–1.00
0
CODE
6553516384 32768 49152
Figure 20. Integral Nonlinearity (Output Data
Rate = 600 kHz)
–14– REV. 0
Page 15
AD7723
NOISE SHAPING
QUANTIZATION NOISE
DIGITAL FILTER CUTOFF FREQUENCY
f
CLKIN
/2
f
CLKIN
/2
f
CLKIN
/2
BAND OF INTEREST
BAND OF INTEREST
BAND OF INTEREST
(a)
(b)
(c)
225
200
175
150
125
100
POWER – mW
75
50
25
0
0
AI
AI
(HALF_POWER = 0)
DD
(HALF_POWER = 1)
DD
DI
DD
5 101520
CLOCK FREQUENCY – MHz
25
Figure 21. Power Consumption vs. CLKIN Frequency
0
SNR = –86.19dB
–25
–50
–75
SNR&D = –85.9dB
THD = –96.42dB
SFDR = –99.61dB
2ND HARMONIC = –100.98dB
3RD HARMONIC = –99.61dB
= 100kHz
A
IN
MEASURED BW = 460kHz
quantization noise, a high order modulator is employed to shape
the noise spectrum, so that most of the noise energy is shifted
out of the band of interest (Figure 24b).
The digital filter that follows the modulator removes the large
out-of-band quantization noise, (Figure 24c) while also reducing the data rate from f
or f
/16 at the output of the filter, depending on the state
CLKIN
at the input of the filter to f
CLKIN
CLKIN
/32
on the MODE1/2 pins in parallel interface mode or the pin
SLDR in serial interface mode. The AD7723 output data rate is
a little over twice the signal bandwidth, which guarantees that
there is no loss of data in the signal band.
Digital filtering has certain advantages over analog filtering.
Firstly, since digital filtering occurs after the A/D conversion, it
can remove noise injected during the conversion process. Analog filtering cannot remove noise injected during conversion.
Secondly, the digital filter combines low passband ripple with a
steep roll-off, while also maintaining a linear phase response.
CIRCUIT DESCRIPTION
The AD7723 ADC employs a sigma-delta conversion technique
to convert the analog input into an equivalent digital word. The
modulator samples the input waveform and outputs an equivalent digital word at the input clock frequency, f
Due to the high oversampling rate, which spreads the quantization noise from 0 to f
band of interest is reduced (Figure 24a). To further reduce the
–100
–125
POWER LEVEL RELATIVE TO FULL SCALE – dB
–150
0E+0
100E+3 200E+3
300E+3 400E+3 500E+3
FREQUENCY – Hz
600E+3
Figure 22. 16K Point FFT (Output Data Rate = 1.2 MHz)
0
–20
–40
–60
–80
–100
–120
–140
POWER LEVEL RELATIVE TO FULL SCALE – dB
–160
0E+0
50E+3 100E+3
SNR = –89.91dB
SNR&D = –89.7dB
THD = –101.16dB
SFDR = –102.1dB
2ND HARMONIC = –102.1dB
3RD HARMONIC = –110.3dB
= 50kHz
A
IN
MEASURED BW = 300kHz
150E+3 200E+3 250E+3
FREQUENCY – Hz
300E+3
Figure 23. 16K Point FFT (Output Data Rate = 600 kHz)
/2, the noise energy contained in the
CLKIN
CLKIN
.
Figure 24. Sigma-Delta ADC
The AD7723 employs four or five Finite Impulse Response
(FIR) filters in series. Each individual filter’s output data rate is
half that of the filter’s input data rate. When data is fed to the
interface from the output of the fourth filter, the output data
rate is f
/16 and the resulting Over Sampling Ratio (OSR)
CLKIN
of the converter is 16. Data fed to the interface from the output
of the fifth filter results in an output data rate of f
CLKIN
/32 and a
corresponding OSR for the converter of 32. When an Output
Data Rate (ODR) of f
/32 is selected, the digital filter re-
CLKIN
sponse can be set to either low-pass or band-pass. The bandpass response is useful when the input signal is band limited
since the resulting output data rate is half that required to convert the band when the low pass operating mode is used. To
illustrate the operation of this mode, consider a band-limited
signal as shown in Figure 25a. This signal band can be correctly
converted by selecting the (low pass) ODR = f
/16 mode, as
CLKIN
shown in Figure 25b. Note that the output data rate is a little
over twice the maximum frequency in the frequency band. Alternatively the band-pass mode can be selected as shown in Figure 25c.
The band-pass filter removes unwanted signals from dc to just
below f
/64. Rather than outputting data at f
CLKIN
output of the band-pass filter is sampled at f
CLKIN
CLKIN
/16, the
/32. This
–15–REV. 0
Page 16
AD7723
effectively translates the wanted band to a maximum frequency
of a little less than f
the output data rate reduces the work load of any following
signal processor and also allows a lower serial clock rate to be
used.
/64 as shown in Figure 25d. Halving
CLKIN
0dB
0dB
0dB
LOW PASS FILTER. OUTPUT DATA RATE = f
BAND LIMITED SIGNAL
(a)
LOW PASS FILTER RESPONSE
SAMPLE
IMAGE
f
CLKIN
f
CLKIN
ODR
CLKIN
/16
/16
/16
(b)
BAND-PASS FILTER
0dB
RESPONSE
BAND-PASS FILTER.
SAMPLE
IMAGE
f
CLKIN
/16
(c)
FREQUENCY
0dB
TRANSLATED
INPUT SIGNAL
LOW PASS FILTER. OUTPUT DATA RATE = f
ODR
SAMPLE
IMAGE
CLKIN
f
CLKIN
/16
/32
(d)
Figure 25. Band-Pass Operation
The frequency response of the three digital filter operating modes
is shown in Figures 26a, 26b, and 26c.
0dB
–100dB
–100dB
0.0 1.00.5
f
CLKIN
Figure 26b. Low-Pass Filter Decimate by 32
0dB
–100dB
0.0 1.00.5
f
CLKIN
Figure 26c. Band-Pass Filter Decimate by 32
Figure 27a shows the frequency response of the digital filter in
both low-pass and band-pass modes. Due to the sampling
nature of the converter, the pass-band response is repeated
about the input sampling frequency, f
tiples of f
. Out-of-band noise or signals coincident with
CLKIN
and at integer mul-
CLKIN
any of the filter images are aliased down to the passband. However, due to the AD7723’s high oversampling ratio, these bands
occupy only a small fraction of the spectrum, and most broadband noise is attenuated by at least 90 dB. In addition, as shown
in Figure 27b, with even a low order filter, there is significant
attenuation at the first image frequency. This contrasts with a
normal Nyquist rate converter where a very high order antialias
filter is required to allow most of the band width to be used
while ensuring sufficient attenuation at multiples of f
CLKIN
.
0.0 1.00.5
f
CLKIN
Figure 26a. Low-Pass Filter Decimate by 16
0dB
1f
CLKIN
2f
CLKIN
3f
CLKIN
Figure 27a. Digital Filter Frequency Response
OUTPUT
0dB
DATA RATE
f
CLKIN
/32
ANTIALIAS FILTER
RESPONSE
f
CLKIN
REQUIRED
ATTENUATION
Figure 27b. Frequency Response of Antialias Filter
–16– REV. 0
Page 17
AD7723
500V
500V
AD7723
CLKIN
VIN(+)
VIN(–)
AC
GROUND
2pF
2pF
FA
FB
FA
FB
F
A
F
B
F
A
F
B
VIN(+)
VIN(–)
AD7723
R
R
C
APPLYING THE AD7723
Analog Input Range
The AD7723 has differential inputs to provide common-mode
noise rejection. In unipolar mode the analog input range is 0 to
8/5 × V
± 4/5 × V
, while in bipolar mode the analog input range is
REF2
. The output code is twos complement binary in
REF2
both modes with 1 LSB = 61 µV. The ideal input/output trans-
fer characteristics for the two modes are shown in Figure 28
below. In both modes the absolute voltage on each input must
remain within the supply range AGND to AV
. The bipolar
DD
mode allows either single-ended or complementary input
signals.
011…111
011…110
000…010
000…001
000…000
111…111
111…110
100…001
100…000
–4/5 3 V
(0V)
REF2
0V
(+4/5 3 V
REF2
+4/5 3 V
)
(+8/5 3 V
– 1LSB BIPOLAR
REF2
– 1LSB) UNIPOLAR
REF2
Figure 28. Bipolar (Unipolar) Mode Transfer Function
The AD7723 will accept full-scale inband signals, however,
large scale out of band signals can overload the modulator inputs. Figure 29 shows the maximum input signal level as a function of frequency. A minimal single-pole RC antialias filter set
to f
/24 will allow full-scale input signals over the entire
CLKIN
frequency spectrum.
2.200
2.100
2.000
1.900
1.800
1.700
1.600
PEAK INPUT – V pk
1.500
1.400
1.300
V
= 2.5V
REF
0 0.50.02 0.04 0.06 0.08 0.10 0.12 0.14
INPUT SIGNAL FREQUENCY RELATIVE TO f
CLKIN
Figure 29. Peak Input Signal Level vs. Signal Frequency
Analog Input
The analog input of the AD7723 uses a switched capacitor
technique to sample the input signal. For the purpose of driving
the AD7723, an equivalent circuit of the analog inputs is shown
in Figure 30. For each half clock cycle, two highly linear sampling capacitors are switched to both inputs, converting the
input signal into an equivalent sampled charge. A signal source
driving the analog inputs must be able to source this charge,
while also settling to the required accuracy by the end of each
half-clock phase.
Figure 30. Analog Input Equivalent Circuit
Driving the Analog Inputs
To interface the signal source to the AD7723, at least one op
amp will generally be required. Choice of op amp will be critical
to achieving the full performance of the AD7723. The op amp
not only has to recover from the transient loads that the ADC
imposes on it, but must also have good distortion characteristics
and very low input noise. Resistors in the signal path will also
add to the overall thermal noise floor, necessitating the choice of
low value resistors.
Placing an RC filter between the drive source and the ADC
inputs, as shown in Figure 31, has a number of beneficial affects: transients on the op amp outputs are significantly reduced
since the external capacitor now supplies the instantaneous
charge required when the sampling capacitors are switched to
the ADC input pins and, input circuit noise at the sample images is now significantly attenuated resulting in improved overall SNR. The external resistor serves to isolate the external
capacitor from the ADC output, thus improving op amp stability while also isolating the op amp output from any remaining
transients on the capacitor. By experimenting with different
filter values, the optimum performance can be achieved for each
application. As a guideline, the RC time constant (R × C)
should be less than a quarter of the clock period to avoid nonlinear currents from the ADC inputs being stored on the external capacitor and degrading distortion. This restriction means
that this filter cannot form the main antialias filter for the ADC.
Figure 31. Input RC Network
With the unipolar input mode selected, just one op amp is required to buffer single ended input signals. However, driving
the AD7723 with complementary signals and with the bipolar
input range selected has some distinct advantages: even order
harmonics in both the drive circuits and the AD7723 front end
are attenuated; and the peak to peak input signal range on both
inputs is halved. Halving the input signal range allows some op
amps to be powered from the same supplies as the AD7723.
Although a complementary driver will require the use of two op
amps per ADC, it may avoid the need to generate additional
supplies just for these op amps.
–17–REV. 0
Page 18
AD7723
COMPARATOR
REFERENCE
BUFFER
1V
1mF
REF2
REF1
2.5V
REFERENCE
SWITCHED-CAP
DAC REFERENCED
AD7723
3kV
10nF
220nF
A
B
B
A
4pF
4pF
REF2
SWITCHED-CAP
DAC REFERENCED
CLKIN
A
F
F
F
F
B
A
B
F
F
F
F
1
2
3
4
AD780
AD7723
REF2
REF1
+5V
1mF
22nF
220nF
10nF
22mF
NC
+V
IN
TEMP
GND
O/P
SELECT
NC
V
OUT
TRIM
2.5V
NC = NO CONNECT
8
7
6
5
Figures 32 and 33 show two such circuits for driving the AD7723.
Figure 32 is intended for use when the input signal is biased
about 2.5 V while Figure 33 is used when the input signal is
biased about ground. While both circuits convert the input
signal into a complementary signal, the circuit in Figure 33
also level shifts the signal so that both outputs are biased
about 2.5 V.
Suitable op amps include the AD8047, AD8044, AD8041 and
its dual equivalent the AD8042. The AD8047 has lower input
noise than the AD8041/42 but has to be supplied from a +7.5 V/
–2.5 V supply. The AD8041/AD8042 will typically degrade
SNR from 90 dB to 88 dB but can be powered from the same
single +5 V supply as the AD7723.
R
FB
220V
AIN = 62V
BIASED
ABOUT 2.5V
R
GAIN = 2 3 RFB/(R
SOURCE
50V
R
IN
390V
10kV
SOURCE
AD8047
A1
220V
220V
A2
AD8047
+ RIN)
220nF
27V
27V
10nF
1mF
VIN(+)
220pF
AD7723
VIN(–)
REF2
REF1
Figure 32. Single-Ended to Differential Input Circuit for
Bipolar Mode Operation (Analog Input Biased About +2.5 V)
R
FB
AIN = 62V
BIASED
ABOUT
GROUND
GAIN = 2 3 R
R
BALANCE1
R
= R
REF2
= R
REF1
FB
R
SOURCE
50V
R
BALANCE1
220V
R
REF1
10kV
R
REF2
20kV
/(RIN + R
BALANCE2
3 (RIN + R
R
390V
SOURCE
3 (RIN + R
SOURCE
IN
A1
R
BALANCE2
220V
R
BALANCE2
220V
A2
)
SOURCE
)/R
FB
220V
AD8047
AD8047
220nF
27V
27V
)/(2 3 RFB)
10nF
1mF
VIN(+)
220pF
AD7723
VIN(–)
REF2
REF1
Figure 33. Single-Ended to Differential Input Circuit for
Bipolar Mode Operation (Analog Input Biased About
Ground)
Applying the Reference
The reference circuitry used in the AD7723 includes an on-chip
2.5 V bandgap reference and a reference buffer circuit. The
block diagram of the reference circuit is shown in Figure 34.
The internal reference voltage is connected to REF1 through a
3kΩ resistor and is internally buffered to drive the analog
modulator’s switched cap DAC (REF2). When using the inter-
nal reference a 1 µF capacitor is required between REF1 and
AGND to decouple the bandgap noise. If the internal reference
is required to bias external circuits, use an external precision op
amp to buffer REF1.
Figure 34. Reference Circuit Block Diagram
Where gain error or gain error drift requires the use of an external reference, the reference buffer in Figure 34 can be turned off
by grounding the REF1 pin and the external reference can be
applied directly to pin REF2. The AD7723 will accept an external reference voltage between 1.2 V to 3.15 V. By applying a 3 V
rather than a 2.5 V reference, SNR is typically improved by
about 1 dB. Where the output common-mode range of the
amplifier driving the inputs is restricted, the full-scale input
signal span can be reduced by applying a lower than 2.5 V reference. For example, a 1.25 V reference would make the bipolar
input span ±1 V, but would degrade SNR.
In all cases, since the REF2 voltage connects to the analog
modulator, a 220 nF and 10 nF capacitor must connect directly
from REF2 to AGND. The external capacitor provides the
charge required for the dynamic load presented at the REF2 pin
(See Figure 35).
Figure 35. REF2 Equivalent Input Circuit
The AD780 is ideal to use as an external reference with the
AD7723. Figure 36 shows a suggested connection diagram.
Grounding Pin 8 on the AD780 selects the 3 V output mode.
Figure 36. External Reference Circuit Connection
–18– REV. 0
Page 19
AD7723
DSP
ADDR
DECODE
DB0–15
DRDY
CS
RD
16 16
OE
D0–15
RD
INTERRUPT
ADDR
AD7723
74XX16374
Clock Generation
The AD7723 contains an oscillator circuit to allow a crystal or
an external clock signal to generate the master clock for the
ADC. The connection diagram for use with a crystal is shown in
Figure 37. Consult the manufacturer’s recommendation for the
load capacitors. To enable the oscillator circuit on board the
AD7723, XTAL_OFF should be tied low.
AD7723
XTAL CLKIN
1MV
Figure 37. Crystal Oscillator Connection
When an external clock source is being used, the internal oscillator circuit can be disabled by tying XTAL_OFF high. A low
phase noise clock should be used to generate the ADC sampling
clock because sampling clock jitter effectively modulates the
input signal and raises the noise floor. The sampling clock generator should be isolated from noisy digital circuits, grounded
and heavily decoupled to the analog ground plane.
The sampling clock generator should be referenced to the analog ground in a split ground system. However, this is not always
possible because of system constraints. In many applications,
the sampling clock must be derived from a higher frequency
multipurpose system clock that is generated on the digital
ground plane. If the clock signal is passed between its origin on
a digital ground plane to the AD7723 on the analog ground
plane, the ground noise between the two planes adds directly to
the clock and will produce excess jitter. The jitter can cause
degradation in the signal-to-noise ratio and also produce unwanted harmonics. This can be remedied somewhat by transmitting the sampling signal as a differential one, using either a
small RF transformer or a high speed differential driver and a
receiver such as PECL. In either case, the original master system clock should be generated from a low phase noise crystal
oscillator.
applied synchronous to the falling edge of CLKIN. This way, on
the next rising edge of CLKIN, SYNC is sensed low, the filter is
taken out of its reset state and multiple parts begin to gather
input samples.
Following a SYNC, the modulator and filter need time to settle
before data can be read from the AD7723. DRDY goes high
following a synchronization and it remains high until valid data
is available at the interface.
DATA INTERFACING
The AD7723 offers a choice of serial or parallel data interface
options to meet the requirements of a variety of system configurations. In parallel mode, multiple AD7723s can easily be configured to share a common data bus. Serial mode is ideal when
it is required to minimize the number of data interface lines
connected to a host processor. In either case, careful attention
to the system configuration is required to realize the high dynamic range available with the AD7723. Consult the recommendation in the Layout and Grounding section. The following
recommendations for parallel interfacing also apply for the system design when using the serial mode.
Parallel Interface
When using the AD7723, place a buffer/latch adjacent to the
converter to isolate the converter’s data lines from any noise
which may be on the data bus. Even though the AD7723 has
three state outputs, use of an isolation latch represents good
design practice.
Figure 38 shows how the parallel interface of the AD7723 can
be configured to interface with the system data bus of a microprocessor or a microcontroller such as the MC68HC16 or
8XC251. With CS and RD tied permanently low, the data output bits are always active. When DRDY goes high for two clock
cycles, the rising edge of DRDY is used to latch the conversion
data before a new conversion result is loaded into the output
data register. The falling edge of DRDY then sends an appropriate interrupt signal for interface control. Alternatively, if buffers
are used instead of latches, the falling edge of DRDY provides
the necessary interrupt when a new output word is available
from the AD7723.
SYSTEM SYNCHRONIZATION
The SYNC input provides a synchronization function for use in
parallel or serial mode. SYNC allows the user to begin gathering
samples of the analog input from a known point in time. This
allows a system using multiple AD7723s, operated from a common master clock, to be synchronized so that each ADC simultaneously updates its output register.
In a system using multiple AD7723s, a common signal to their
sync inputs will synchronize their operation. On the rising edge
of SYNC, the digital filter sequencer is reset to zero. The filter
is held in a reset state until a rising edge on CLKIN senses
SYNC low. A SYNC pulse, one CLKIN cycle long, can be
Figure 38. Parallel Interface Connection
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AD7723
AD7723
MASTER
AD7723
SLAVE
FSI
SFMT
TSI
FSI
CLKIN
DOE
CFMT
SDO
SCO
FSO
CLKIN
TSI
CFMT
SFMT
DOE
SDO
SCO
FSO
DV
DD
DV
DD
DGND
DGND
FROM
CONTROL
LOGIC
TO HOST
PROCESSOR
SERIAL INTERFACE
The AD7723’s serial data interface can operate in three modes,
depending on the application requirements. The timing diagrams in Figures 3, 4 and 5 show how the AD7723 may be used
to transmit its conversion results. Table I shows the control
inputs required to select each serial mode, and the digital filter
operating mode. The AD7723 operates solely in the master
mode providing three serial data output pins for transfer of the
conversion results. The serial data clock output, SCO, serial
data output, SDO, and frame sync output, FSO, are all synchronous with CLKIN. FSO is continuously output at the conversion
rate of the ADC.
Serial data shifts out of the SDO pin synchronous with SCO.
The FSO is used to frame the output data transmission to an
external device. An output data transmission is either 16 or 32
SCO cycles in duration (refer to Table I). Serial data shifts out
of the SDO pin, MSB first, LSB last, for a duration of 16 SCO
cycles. In Serial Mode 1, SDO outputs zeros for the last 16
SCO cycles of the 32-cycle data transmission frame.
The clock format pin, CFMT, selects the active edge of SCO.
With CFMT tied logic low, the serial interface outputs FSO and
SDO change state on the SCO rising edge and are valid on the
falling edge of SCO. With CFMT set high, FSO and SDO
change state on the falling SCO edge and are valid on the SCO
rising edge.
The Frame Sync Input, FSI, can be used if the AD7723 conversion process must be synchronized to an external source. FSI
allows the conversion data presented to the serial interface to be
a filtered and decimated result derived from a known point in
time. A common frame sync signal can be applied to two or
more AD7723s to synchronize them to a common master clock.
When FSI is applied for the first time, the digital filter sequencer
counter is reset to zero, the AD7723 interrupts the current data
transmission, reloads the output shift register, resets SCO and
transmits the conversion result. Synchronization starts immediately and the following conversions are invalid while the digital
filter settles. FSI can be applied once after power-up, or it can
be a periodic signal, synchronous to CLKIN, occurring every
32 CLKIN cycles. Subsequent FSI inputs applied every 32
CLKIN cycles do not alter the serial data transmission and do
not reset the digital filter sequencer counter. FSI is an optional
signal; if synchronization is not required, FSI can be tied to a
logic low and the AD7723 will generate FSO outputs.
In Serial Mode 1, the control input, SFMT, can be used to
select the format for the serial data transmission (refer to Figure
3). FSO is either a pulse, approximately one SCO cycle in duration, or a square wave with a period of 32 SCO cycles. With a
logic low level on SFMT, FSO pulses high for one SCO cycle at
the beginning of a data transmission frame. With a logic high
level on SFMT, FSO goes low at the beginning of a data transmission frame and returns high after 16 SCO cycles.
Note that in Serial Mode 1, FSI can be used to synchronize the
AD7723 if SFMT is set to a logic high. If SFMT is set low, the
FSI input will have no effect on synchronization.
In Serial Modes 2 and 3, SFMT should be tied high. TSI and
DOE should be tied low in these modes. The FSO is a pulse,
approximately one SCO cycle in duration, occurring at the
beginning of the serial data transmission.
Two-Channel Multiplexed Operation
Two additional serial interface control pins, DOE and TSI, are
provided to allow the serial data outputs of two AD7723s, to
easily share one serial data line when operating in Serial Mode 1.
Figure 39 shows the connection diagram. Since a serial data
transmission frame lasts 32 SCO cycles, two ADCs can share a
single data line by alternating transmission of their 16-bit output data onto one SDO pin.
Figure 39. Serial Mode 1 Connection for Two-Channel
Multiplexed Operation
The Data Output Enable pin, DOE, controls the SDO output
buffer. When the logic level on DOE matches the state of the
TSI pin, the SDO output buffer drives the serial data line, otherwise the output of the buffer goes high impedance. The serial
format pin, SFMT, is set high to choose the frame sync output
format. The clock format pin, CFMT, is set low so that serial
data is made available on SDO after the rising edge of SCO and
can be latched on the SCO falling edge.
The Master device is selected by setting TSI to a logic low and
connecting its FSO to DOE. The Slave device is selected with
its TSI pin tied high and both its FSI and DOE controlled from
the Master’s FSO. Since the FSO of the Master controls the
DOE input of both the Master and Slave, one ADC’s SDO is
active while the other is high impedance (Figure 40). When the
Master transmits its conversion result during the first 16 SCO
cycles of a data transmission frame, the low level on DOE sets
the slave’s SDO high impedance. Once the Master completes
transmitting its conversion data, its FSO goes high, triggers the
Slave’s FSI to begin its data transmission frame.
Since FSO pulses are gated by the release of FSI (going low)
and the FSI of the Slave device is held high during its data
transmission, the FSO from the Master device must be used for
connection to the host processor.
–20– REV. 0
Page 21
CLKIN
SDR
SC1
SCK
DSP56002
SDO
FSO
SCO
AD7723
FSI
t
9
SCO
t
FSO (MASTER)
DOE (MASTER & SLAVE)
FSI (SLAVE)
SDO (MASTER)
SDO (SLAVE)
t
12
t
15
D15 D14 D1 D0
D1 D0 D15 D14
t
13
t
16
11
t
t
Figure 40. Serial Mode 1 Timing for Two-Channel Multiplexed Operation
AD7723
16
15
SERIAL INTERFACE TO DSPS
In serial mode, the AD7723 can be directly interfaced to several
industry standard digital signal processors. In all cases, the
AD7723 operates as the master with the DSP operating as the
slave. The AD7723 provides its own serial clock (SCO) to
transmit the digital word on the SDO pin to the DSP. The
AD7723 also generates the frame synchronization signal that
synchronizes the transfer of the 16-bit word from the AD7723
to the DSP. Depending on the serial mode used, SCO will have
a frequency equal to CLKIN or equal to CLKIN/2. When SCO
equals 19.2 MHz, the AD7723 can be interfaced to Analog
Devices’ ADSP-2106x SHARC DSP. With a 19.2 MHz master
clock and SCO equal to CLKIN/2, the AD7723 can be interfaced with the ADSP-21xx family of DSPs, the DSP56002
and the TMS320C5x-57. When the AD7723 is used in the
HALF_PWR mode, i.e., CLKIN is less than 10 MHz, then the
AD7723 can be used with DSPs such as the TMS320C20/C25
and the DSP56000/1.
AD7723-to-ADSP-21xx Interface
Figure 41 shows the interface between the ADSP-21xx and the
AD7723. The AD7723 is operated in Mode 2 so that SCO =
CLKIN/2. For the ADSP-21xx, the bits in the serial port control register should be set up as RFSR = 1 (a frame sync is
needed for each transfer), SLEN = 15 (16-bit word lengths),
RFSW = 0 (normal framing mode for receive operations),
INVRFS = 0 (active high RFS), IRFS = 0 (external RFS) and
ISCLK = 0 (external serial clock).
(the receive data will be latched into the DSP on the falling
clock edge), LAFS = 0 (the DSP begins reading the 16-bit word
after the DSP has identified the frame sync signal rather than
the DSP reading the word at the same instant as the frame sync
signal has been identified), LRFS = 0 (RFS is active high).
The AD7723 can be used in Modes 1, 2 or 3 when interfaced to
the ADSP-2106x SHARC DSP.
AD7723-to-DSP56002 Interface
Figure 42 shows the AD7723-to-DSP56002 interface. To interface the AD7723 to the DSP56002, the ADC is operated in
Mode 2 when the ADC is operated with a 19.2 MHz clock. The
DSP56002 is configured as follows: SYN = 1 (synchronous
mode), SCD1 = 0 (RFS is an input), GCK = 0 (a continuous
serial clock is used), SCKD = 0 (the serial clock is external),
WL1 = l, WL0 = 0 (transfers will be 16 bits wide), FSL1 = 0,
FSL0 = 1 (the frame sync will be active at the beginning of each
transfer). Alternatively, the DSP56002 can be operated in asynchronous mode (SYN = 0).
In this mode, the serial clock for the receive section is input to
the SCO pin. This is accomplished by setting bit SCDO to 0
(external Rx clock).
ADSP-21xx
DR
RFS
SCLK
AD7723
SDO
FSO
SCO
Figure 41. AD7723-to-ADSP-21xx Interface
AD7723-to-SHARC Interface
The interface between the AD7723 and the ADSP-2106x
SHARC DSP is the same as shown in Figure 41 but, the DSP is
configured as follows: SLEN = 15 (16-bit word transfers),
SENDN = 0 (the MSB of the 16-bit word will be received by
the DSP first), ICLK = 0 (an external serial clock will be used),
RFSR = 0 (a frame sync is required for every word transfer),
IRFS = 0 (the receive frame sync signal is external), CKRE = 0
Figure 42. AD7723-to-DSP56002 Interface
AD7723-to-TMS320C5x Interface
Figure 43 shows the AD7723-to-TMS320C5x interface. For the
TMS320C5x, FSR and CLKR are automatically configured as
inputs. The serial port is configured as follows: FO = 0 (16-bit
word transfers), FSM = 1 (a frame sync occurs for each transfer).
TMS320C5x
DR
FSR
CLKR
AD7723
SDO
FSO
SCO
Figure 43. AD7723-to-TMS320C5x Interface
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Page 22
AD7723
+5V
10mF
100nF 100nF
100nF
10nF
10nF
10nF
10nF
10nF
10mF
220nF
10nF
1mF
REF2
AGND2
REF1
AV
DD
1
AGND1
AGND1
AGND
AGND
AV
DD
AV
DD
DV
DD
DGND
DGND
AD7723 ANALOG
GROUND PLANE
AD7723 DIGITAL
GROUND PLANE
GROUNDING AND LAYOUT
The analog and digital power supplies to the AD7723 are independent and separately pinned out to minimize coupling between analog and digital sections within the device. All the
AD7723 AGND and DGND pins should be soldered directly to
a ground plane to minimize series inductance. In addition, the
ac path from any supply pin or reference pin (REF1 and REF2)
through its decoupling capacitors to its associated ground must be
made as short as possible (Figure 44). To achieve the best decoupling, place surface mount capacitors as close as possible to the
device, ideally right up against the device pins.
All ground planes must not overlap to avoid capacitive coupling.
The AD7723’s digital and analog ground planes must be connected at one place by a low inductance path, preferably right
under the device. Typically, this connection will either be a
trace on the Printed Circuit Board of 0.5 cm wide when the
ground planes are on the same layer, or 0.5 cm wide minimum
plated through holes when the ground planes are on different
layers. Any external logic connected to the AD7723 should use
a ground plane separate from the AD7723’s digital ground
plane. These two digital ground planes should also be connected at just one place.
Separate power supplies for AV
desirable. The digital supply pin DV
a separate analog supply, but if necessary DV
power connection to AV
DD
and DVDD are also highly
DD
should be powered from
DD
may share its
DD
. Refer to the connection diagram
(Figure 44). The ferrites are also recommended to filter high
frequency signals from corrupting the analog power supply.
A minimum etch technique is generally best for ground planes
as it gives the best shielding. Noise can be minimized by paying
attention to the system layout and preventing different signals
from interfering with each other. High level analog signals
should be separated from low level analog signals, and both
should be kept away from digital signals. In waveform sampling
and reconstruction systems the sampling clock (CLKIN) is as
vulnerable to noise as any analog signal. CLKIN should be
isolated from the analog and digital systems. Fast switching
signals like clocks should be shielded with their associated
ground to avoid radiating noise to other sections of the board,
and clock signals should never be routed near the analog inputs.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7723 to shield it from noise coupling. The
power supply lines to the AD7723 should use as large a trace as
possible (preferably a plane) to provide a low impedance path
and reduce the effects of glitches on the power supply line.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
will reduce the effects of feedthrough through the board.
Figure 44. Reference and Power Supply Decoupling
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Page 23
0.037 (0.94)
0.025 (0.64)
SEATING
PLANE
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Quad Flatpack
(S-44)
0.548 (13.925)
33
0.546 (13.875)
0.398 (10.11)
0.390 (9.91)
TOP VIEW
(PINS DOWN)
0.096 (2.44)
MAX
0.8°
8°
34
AD7723
23
22
C3230–8–4/98
0.040 (1.02)
0.032 (0.81)
0.083 (2.11)
0.077 (1.96)
0.040 (1.02)
0.032 (0.81)
44
1
0.033 (0.84)
0.029 (0.74)
12
11
0.016 (0.41)
0.012 (0.30)
PRINTED IN U.S.A.
–23–REV. 0
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