Datasheet AD7712EB, AD7712SQ, AD7712AR, AD7712AQ, AD7712AN Datasheet (Analog Devices)

LC2MOS

a

FEATURES
Charge Balancing ADC

24 Bits No Missing Codes

ⴞ0.0015% Nonlinearity
High Level and Low Level Analog Input Channels
Programmable Gain for Both Inputs

Gains from 1 to 128

Differential Input for Low Level Channel
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Internal/External Reference Option
Single or Dual Supply Operation
Low Power (25 mW typ) with Power-Down Mode

(100 ␮W typ)

APPLICATIONS
Process Control
Smart Transmitters
Portable Industrial Instruments

AIN1(+)
AIN1(–)

AIN2

TP

Signal Conditioning ADC

FUNCTIONAL BLOCK DIAGRAM

REF

AV

DD

AV

DD

VOLTAGE

ATTENUATION

AD7712

DGND

AGND

DV

DD

4.5mA

M
U
X

V

REF

IN (–)

PGA

A = 1 – 128

SS

V

IN (+)

BIAS

CHARGE-BALANCING A/D

CONVERTER

AUTO-ZEROED

S–D

MODULATOR

SERIAL INTERFACE

CONTROL
REGISTER

MODE SDATA SCLK

TFSRFS

2.5V REFERENCE

CLOCK

GENERATION

REGISTER

AD7712*

REF OUT

A0

SYNC

STANDBY

MCLK
IN

MCLK
OUT

DIGITAL

FILTER

OUTPUT

DRDY

GENERAL DESCRIPTION

The AD7712 is a complete analog front end for low frequency
measurement applications. The device has two analog input
channels and accepts either low level signals directly from a

transducer or high level (±4 × V

) signals and outputs a serial

REF

digital word. It employs a sigma-delta conversion technique to
realize up to 24 bits of no missing codes performance. The low
level input signal is applied to a proprietary programmable gain
front end based around an analog modulator. The high level
analog input is attenuated before being applied to the same
modulator. The modulator output is processed by an on-chip
digital filter. The first notch of this digital filter can be pro­grammed via the on-chip control register allowing adjustment of
the filter cutoff and settling time.

Normally, one of the channels will be used as the main channel
with the second channel used as an auxiliary input to periodi­cally measure a second voltage. The part can be operated from a
single supply (by tying the V

pin to AGND) provided that the

SS

input signals on the low level analog input are more positive
than –30 mV. By taking the V
vert signals down to –V

REF

pin negative, the part can con-

SS

on this low level input. This low level
input, as well as the reference input, features differential input
capability.

The AD7712 is ideal for use in smart, microcontroller-based
systems. Input channel selection, gain settings and signal polar­ity can be configured in software using the bidirectional serial

*Protected by U.S. Patent No. 5,134,401.

port. The AD7712 also contains self-calibration, system calibra­tion and background calibration options and also allows the user
to read and to write the on-chip calibration registers.

CMOS construction ensures low power dissipation and a hard­ware programmable power-down mode reduces the standby

power consumption to only 100 µW typical. The part is avail-

able in a 24-lead, 0.3 inch wide, plastic and hermetic dual-in­line package (DIP) as well as a 24-lead small outline (SOIC)
package.

PRODUCT HIGHLIGHTS

1. The low level analog input channel allows the AD7712 to
accept input signals directly from a strain gage or transducer,
removing a considerable amount of signal conditioning. To
maximize the flexibility of the part, the high level analog

input accepts signals of ±4 × V

/GAIN.

REF

2. The AD7712 is ideal for microcontroller or DSP processor
applications with an on-chip control register that allows
control over filter cutoff, input gain, channel selection, signal
polarity and calibration modes.

3. The AD7712 allows the user to read and to write the on-chip
calibration registers. This means that the microcontroller has
much greater control over the calibration procedure.

4. No Missing Codes ensures true, usable, 23-bit dynamic

range coupled with excellent ±0.0015% accuracy. The effects

of temperature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.

REV. E

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD7712–SPECIFICATIONS

(AVDD = +5␣ V ⴞ 5%; DVDD = +5␣ V ⴞ 5%; VSS = 0␣ V or –5 V ⴞ 5%; REF IN(+) = +2.5␣ V;

REF IN(–) = AGND; MCLK IN = 10␣ MHz unless otherwise stated. All specifications T

MIN

to T

unless otherwise noted.)

MAX

Parameter A, S Versions

1

Units Conditions/Comments

STATIC PERFORMANCE

No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches ≤ 60 Hz

22 Bits min For Filter Notch = 100 Hz
18 Bits min For Filter Notch = 250 Hz
15 Bits min For Filter Notch = 500 Hz
12 Bits min For Filter Notch = 1 kHz

Output Noise See Tables I & II Depends on Filter Cutoffs and Selected Gain

Integral Nonlinearity @ +25°C ±0.0015 % FSR max Filter Notches ≤ 60 Hz

T

to T

MIN

Positive Full-Scale Error
Full-Scale Drift

Unipolar Offset Error
Unipolar Offset Drift

Bipolar Zero Error
Bipolar Zero Drift

MAX

5

2

5

2

5

2, 3

±0.003 % FSR max Typically ±0.0003%

See Note 4 Excluding Reference

1 µV/°C typ Excluding Reference. For Gains of 1, 2

0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

See Note 4

0.5 µV/°C typ For Gains of 1, 2

0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128

See Note 4

0.5 µV/°C typ For Gains of 1, 2

0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128

Gain Drift 2 ppm/°C typ

Bipolar Negative Full-Scale Error

T

to T

MIN

MAX

Bipolar Negative Full-Scale Drift

2

@ +25°C ±0.003 % FSR max Excluding Reference

5

±0.006 % FSR max Typically ±0.0006%
1 µV/°C typ Excluding Reference. For Gains of 1, 2

0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

ANALOG INPUTS/REFERENCE INPUTS

Normal-Mode 50 Hz Rejection
Normal-Mode 60 Hz Rejection
AIN1/REF IN

DC Input Leakage Current
T

to T

MIN

MAX

Sampling Capacitance
Common-Mode Rejection (CMR) 100 dB min At DC
Common-Mode 50 Hz Rejection
Common-Mode 60 Hz Rejection
Common-Mode Voltage Range

Analog Inputs

8

Input Sampling Rate, f
AIN1 Input Voltage Range

AIN2 Input Voltage Range

AIN2 DC Input Impedance 30 kΩ

AIN2 Gain Error

AIN2 Gain Drift 1 ppm/°C typ Additional Drift Contributed by Resistor Attenuator

AIN2 Offset Error

11

11

6

S

6

6

@ +25°C

6

6

7

9

9

100 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 × f
100 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 × f

6

10 pA max
1 nA max
20 pF max

150 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 × f
150 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 × f

VSS to AV

DD

V min to V max

See Table III

0 to +V

REF

±V

REF

0 to + 4 × V
±4 × V

REF

10

V max Unipolar Input Range (B/U Bit of Control Register = 1)
V max Bipolar Input Range (B/U Bit of Control Register = 0)

REF

10

V max Unipolar Input Range (B/U Bit of Control Register = 1)
V max Bipolar Input Range (B/U Bit of Control Register = 0)

For Normal Operation. Depends on Gain Selected

For Normal Operation. Depends on Gain Selected

±0.05 % typ Additional Error Contributed by Resistor Attenuator

10 mV max Additional Error Contributed by Resistor Attenuator

NOTCH

NOTCH

NOTCH

NOTCH

AIN2 Offset Drift 20 µV/°C typ

Reference Inputs

REF IN(+) – REF IN(–) Voltage

Input Sampling Rate, f

NOTES

1

Temperature range is as follows: A Version, –40°C to +85°C; S Version –55°C to +125°C. See also Note 18.

2

Applies after calibration at the temperature of interest.

3

Positive full-scale error applies to both unipolar and bipolar input ranges.

4

These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration
or background calibration.

5

Recalibration at any temperature or use of the background calibration mode will remove these drift errors.

6

These numbers are guaranteed by design and/or characterization.

7

This common-mode voltage range is allowed provided that the input voltage on AIN1(+) and AIN1(–) does not exceed AV

8

The AIN1 analog input presents a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum recommended
source resistance depends on the selected gain (see Tables IV and V).

9

The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2
input is with respect to AGND. The absolute voltage on the AIN1 input should not go more positive than AVDD + 30 mV or more negative than VSS – 30 mV.

10

V

= REF IN(+) – REF IN(–).

REF

11

This error can be removed using the system calibration capabilities of the AD7712. This error is not removed by the AD7712’s self-calibration features. The offset
drift on the AIN2 input is 4 times the value given in the STATIC PERFORMANCE section.

12

The reference input voltage range may be restricted by the input voltage range requirement on the V

S

12

+2.5 to +5 V min to V max For Specified Performance. Part Is Functional with

f

CLK IN

/256

Lower V

input.

BIAS

Voltages

REF

+ 30 mV and VSS – 30 mV.

DD

–2– REV. E

AD7712

Parameter A, S Versions

1

Units Conditions/Comments

REFERENCE OUTPUT

Output Voltage 2.5 V nom

Initial Tolerance ±1 % max
Drift 20 ppm/°C typ
Output Noise 30 µV typ pk-pk Noise; 0.1 Hz to 10 Hz Bandwidth

Line Regulation (AVDD) 1 mV/V max
Load Regulation 1.5 mV/mA max Maximum Load Current 1 mA
External Current 1 mA max

INPUT

13

– 0.85 × V

DD

REF

See V

Input Section

BIAS

V

BIAS

Input Voltage Range AV

or AVDD – 3.5 V max Whichever Is Smaller; +5 V/–5 V or +10 V/0 V

or AVDD – 2.1 V max Whichever Is Smaller; +5 V/0 V Nominal AVDD/V

Nominal AVDD/V

V

+ 0.85 × V

SS

or VSS + 3 V min Whichever Is Greater; +5 V/–5 V or +10 V/0 V

REF

See V

BIAS

Nominal AVDD/V

or VSS + 2.1 V min Whichever Is Greater; +5 V/0 V Nominal AVDD/V

V

Rejection 65 to 85 dB typ Increasing with Gain

BIAS

SS

SS

Input Section

SS

SS

LOGIC INPUTS

Input Current ±10 µA max

All Inputs except MCLK IN

V

, Input Low Voltage 0.8 V max

INL

V

, Input High Voltage 2.0 V min

INH

MCLK IN Only

V

, Input Low Voltage 0.8 V max

INL

V

, Input High Voltage 3.5 V min

INH

LOGIC OUTPUTS

VOL, Output Low Voltage 0.4 V max I
VOH, Output High Voltage 4.0 V min I

Floating State Leakage Current ±10 µA max

Floating State Output Capacitance

14

9 pF typ

= 1.6 mA

SINK

SOURCE

= 100 µA

TRANSDUCER BURNOUT

Current 4.5 µA nom
Initial Tolerance ±10 % typ
Drift 0.1 %/°C typ

SYSTEM CALIBRATION

AIN1

Positive Full-Scale Calibration Limit
Negative Full-Scale Calibration Limit
Offset Calibration Limit
Input Span

15

16, 17

AIN2

Positive Full-Scale Calibration Limit
Negative Full-Scale Calibration Limit
Offset Calibration Limit
Input Span

NOTES

13

The AD7712 is tested with the following V

with AVDD = +5 V and VSS = –5 V, V

14

Guaranteed by design, not production tested.

15

After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will

output all 0s.

16

These calibration and span limits apply provided the absolute voltage on the AIN1 analog inputs does not exceed AVDD + 30 mV or does not go more negative

than VSS – 30 mV.

17

The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

15

17

BIAS

15

15

15

15

BIAS

= 0 V.

(1.05 × V
–(1.05 × V
–(1.05 × V

0.8 × V
(2.1 × V

(4.2 × V
–(4.2 × V
–(4.2 × V

3.2 × V
(8.4 × V

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128)

REF

voltages. With AVDD = +5 V and VSS = 0 V, V

= +2.5 V; with AVDD = +10 V and VSS = 0 V, V

BIAS

= +5 V and

BIAS

REV. E

–3–

AD7712–SPECIFICATIONS

WARNING!

ESD SENSITIVE DEVICE

Parameter A, S Versions

POWER REQUIREMENTS

Power Supply Voltages

AVDD Voltage
DVDD Voltage
AV

DD

18

19

– V

Voltage +10.5 V max For Specified Performance

SS

+5 to +10 V nom ±5% for Specified Performance
+5 V nom ±5% for Specified Performance

Power Supply Currents

AVDD Current 4 mA max
DV

Current 4.5 mA max

DD

VSS Current 1.5 mA max VSS = –5 V

Power Supply Rejection

20

Positive Supply (AVDD and DVDD) See Note 21 dB typ
Negative Supply (VSS) 90 dB typ

Power Dissipation

Normal Mode 45 mW max AVDD = DVDD = +5 V, VSS = 0 V; Typically 25 mW
Normal Mode 52.5 mW max AV
Standby (Power-Down) Mode

NOTES

18

The AD7712 is specified with a 10 MHz clock for AV

than 10.5 V.

19

The ±5% tolerance on the DV

20

Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will

exceed 120 dB with filter notches of 10 Hz, 30 Hz or 60 Hz.

21

PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ. These numbers can be improved

(to 95 dB typ) by deriving the V

22

Using the hardware STANDBY pin. Standby power dissipation using the software standby bit (PD) of the Control Register is 8 mW typ.

Specifications subject to change without notice.

22

input is allowed provided that DVDD does not exceed AVDD by more than 0.3 V.

DD

voltage (via Zener diode or reference) from the AVDD supply.

BIAS

200 µW max AV

1

Units Conditions/Comments

Rejection w.r.t. AGND; Assumes V

= DV

DD

DD

voltages of +5 V ± 5%. It is specified with an 8 MHz clock for AV

DD

= +5␣ V, VSS = –5 V; Typically 30 mW

DD

= DV

= +5␣ V, V

DD

= 0 V or –5 V; Typically 100 µW

SS

Is Fixed

BIAS

voltages greater than 5.25 V and less

DD

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C, unless otherwise noted)

A

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

AV

DD

to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

AV

DD

to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V

AV

DD

to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

DV

DD

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

DV

DD

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

V

SS

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

V

SS

AIN1 Input Voltage to AGND . . V

– 0.3 V to AVDD + 0.3 V

SS

Reference Input Voltage to AGND

. . . . . . . . . . . . . . . . . . . . . . . . . V

– 0.3 V to AVDD + 0.3 V

SS

ORDERING GUIDE

Model Temperature Range Package Options*

AD7712AN –40°C to +85°C N-24
AD7712AR –40°C to +85°C R-24
AD7712AQ –40°C to +85°CQ-24
AD7712SQ –55°C to +125°CQ-24

EVAL-AD7712EB Evaluation Board

*N = Plastic DIP, Q = Cerdip; R = SOIC.

REF OUT to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V to AV

DD

Digital Input Voltage to DGND . . . . . –0.3 V to AVDD + 0.3 V

Digital Output Voltage to DGND . . . –0.3 V to DV

+ 0.3 V

DD

Operating Temperature Range

Commercial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro­static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.

–4–

REV. E

(DVDD = +5␣ V ⴞ 5%; AVDD = +5␣ V or +10 V3 ⴞ 5%; VSS = 0 V or –5 V ⴞ 5%; AGND = DGND =

MIN

1, 2

, T

0 V; f

MAX

=10␣ MHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)

CLKIN

TIMING CHARACTERISTICS

Limit at T

Parameter (A, S Versions) Units Conditions/Comments

4, 5

f

CLK IN

Master Clock Frequency: Crystal Oscillator or
Externally Supplied

400 kHz min AV

= +5 V ± 5%

DD

10 MHz max For Specified Performance

= +5.25 V to +10.5 V

DD

t

CLK IN LO

t

CLK IN HI

6

t

r

6

t

f

t

1

8 MHz AV

0.4 × t

0.4 × t

CLK IN

CLK IN

ns min Master Clock Input Low Time; t

ns min Master Clock Input High Time
50 ns max Digital Output Rise Time; Typically 20 ns
50 ns max Digital Output Fall Time; Typically 20 ns
1000 ns min SYNC Pulsewidth

Self-Clocking Mode

t

2

t

3

t

4

t

5

t

6

7

t

7

7

t

8

t

9

t

10

t

14

t

15

t

16

t

17

t

18

t

19

0 ns min DRDY to RFS Setup Time; t
0 ns min DRDY to RFS Hold Time
2 × t

CLK IN

ns min A0 to RFS Setup Time
0 ns min A0 to RFS Hold Time
4 × t
4 × t
t

CLK IN

t

CLK IN/2

t

CLK IN

3 × t

+ 20 ns max RFS Low to SCLK Falling Edge

CLK IN

+ 20 ns max Data Access Time (RFS Low to Data Valid)

CLK IN

/2 ns min SCLK Falling Edge to Data Valid Delay

+ 30 ns max

/2 ns nom SCLK High Pulsewidth

/2 ns nom SCLK Low Pulsewidth

CLK IN

50 ns min A0 to TFS Setup Time
0 ns min A0 to TFS Hold Time
4 × t
4 × t

+ 20 ns max TFS to SCLK Falling Edge Delay Time

CLK IN

CLK IN

ns min TFS to SCLK Falling Edge Hold Time
0 ns min Data Valid to SCLK Setup Time
10 ns min Data Valid to SCLK Hold Time

CLK IN

CLK IN

= 1/f

= 1/f

AD7712

2

CLK IN

CLK IN

–5–REV. E

AD7712

TOP VIEW

(Not to Scale)

24
23
22
21
20
19
18
17
16
15
14
13

1
2
3
4
5
6
7
8

9
10
11
12

AD7712

AV

DD

V

SS

TP

STANDBY

AIN1(–)

MCLK IN

MCLK OUT

A0

AIN1(+)

MODE

SCLK

SYNC

V

BIAS

REF IN(–)

REF IN(+)

REF OUT

AIN2

DGND
DV

DD

SDATA

DRDY

AGND

TFS

RFS

Limit at T

MIN

, T

MAX

Parameter (A, S Versions) Units Conditions/Comments

External Clocking Mode

f

SCLK

t

20

t

21

t

22

t

23

7

t

24

7

t

25

t

26

t

27

t

28

8

t

29

t

30

8

t

31

t

32

t

33

t

34

t

35

t

36

NOTES

1

Guaranteed by design, not production tested. Sample tested during initial release and after any redesign or process change that may affect this parameter. All input
signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

See Figures 11 to 14.

3

The AD7712 is specified with a 10 MHz clock for AV
than 10.5 V.

4

CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7712 is not in STANDBY mode. If no clock is present in this case, the
device can draw higher current than specified and possibly become uncalibrated.

5

The AD7712 is production tested with f

6

Specified using 10% and 90% points on waveform of interest.

7

These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

8

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are
the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

Specifications subject to change without notice.

f

/5 MHz max Serial Clock Input Frequency

CLK IN

0 ns min DRDY to RFS Setup Time
0 ns min DRDY to RFS Hold Time
2 × t

CLK IN

ns min A0 to RFS Setup Time

0 ns min A0 to RFS Hold Time
4 × t

CLK IN

ns max Data Access Time (RFS Low to Data Valid)

10 ns min SCLK Falling Edge to Data Valid Delay

2 × t
2 × t
2 × t

t

CLK IN

+ 20 ns max

CLK IN

CLK IN

CLK IN

ns min SCLK High Pulse Width
ns min SCLK Low Pulse Width

+ 10 ns max SCLK Falling Edge to DRDY High

10 ns min SCLK to Data Valid Hold Time

+ 10 ns max

t

CLK IN

10 ns min RFS/TFS to SCLK Falling Edge Hold Time
5 × t

/2 + 50 ns max RFS to Data Valid Hold Time

CLK IN

0 ns min A0 to TFS Setup Time
0 ns min A0 to TFS Hold Time
4 × t
2 × t

CLK IN

– SCLK High ns min Data Valid to SCLK Setup Time

CLK IN

ns min SCLK Falling Edge to TFS Hold Time

30 ns min Data Valid to SCLK Hold Time

voltages of +5 V ± 5%. It is specified with an 8 MHz clock for AV

DD

at 10 MHz (8 MHz for AVDD < +5.25 V). It is guaranteed by characterization to operate at 400 kHz.

CLK IN

voltages greater than 5.25 V and less

DD

1.6mA

TO OUTPUT

PIN

100pF

200mA

+2.1V

Figure 1. Load Circuit for Access Time and Bus Relinquish
Time

–6–

PIN CONFIGURATION

DIP AND SOIC

REV. E

AD7712

PIN FUNCTION DESCRIPTION

Pin Mnemonic Function

1 SCLK Serial Clock. Logic Input/Output depending on the status of the MODE pin. When MODE is high, the

device is in its self-clocking mode and the SCLK pin provides a serial clock output. This SCLK becomes
active when RFS or TFS goes low and it goes high impedance when either RFS or TFS returns high or when
the device has completed transmission of an output word. When MODE is low, the device is in its external
clocking mode and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to the AD7712 in smaller batches of data.

2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal or external clock. A crystal can

be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a
CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10 MHz.

3 MCLK OUT When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.

4 A0 Address Input. With this input low, reading and writing to the device is to the control register. With this input

high, access is to either the data register or the calibration registers.

5 SYNC Logic Input which allows for synchronization of the digital filters when using a number of AD7712s. It resets

the nodes of the digital filter.

6 MODE Logic Input. When this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its

external clocking mode.

7 AIN1(+) Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input

is connected to an output current source which can be used to check that an external transducer has burned out
or gone open circuit. This output current source can be turned on/off via the control register.

8 AIN1(–) Analog Input Channel 1. Negative input of the programmable gain differential analog input.
9 STANDBY Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power

consumption to less than 50 µW.

10 TP Test Pin. Used when testing the device. Do not connect anything to this pin.

11 V

12 AV

13 V

SS

DD

BIAS

14 REF IN(–) Reference Input. The REF IN(–) can lie anywhere between AV

15 REF IN(+) Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–).

16 REF OUT Reference Output. The internal +2.5 V reference is provided at this pin. This is a single-ended output

17 AIN2 Analog Input Channel 2. High level analog input which accepts an analog input voltage range of ±4 ×

18 AGND Ground reference point for analog circuitry.
19 TFS Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial

20 RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the

Analog Negative Supply, 0 V to –5 V. Tied to AGND for single supply operation. The input voltage on AIN1
should not go > 30 mV negative w.r.t. V

for correct operation of the device.

SS

Analog Positive Supply Voltage, +5 V to +10 V.

Input Bias Voltage. This input voltage should be set such that V

> VSS where V

× V

REF

and VSS. Thus, with AV
–5 V, it can be tied to AGND, while with AV

is REF IN(+) – REF IN(–). Ideally, this should be tied halfway between AV

REF

= +5 V and VSS = 0 V, it can be tied to REF OUT; with AVDD = +5 V and VSS =

DD

= +10 V, it can be tied to +5 V.

DD

+ 0.85 × V

BIAS

and VSS provided REF IN(+) is greater

DD

< AVDD and V

REF

BIAS

– 0.85

DD

than REF IN(–).

REF IN(+) can lie anywhere between AV

and VSS.

DD

which is referred to AGND.

V

/GAIN. At the nominal V

REF

of +2.5 V and a gain of 1, the AIN2 input voltage range is ±10 V.

REF

data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active
after TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data word
is written to the part.

self-clocking mode, the SCLK and SDATA lines both become active after RFS goes low. In the external
clocking mode, the SDATA line becomes active after RFS goes low.

2

–7–REV. E

AD7712

Pin Mnemonic Function

21 DRDY Logic output. A falling edge indicates that a new output word is available for transmission. The DRDY pin

will return high upon completion of transmission of a full output word. DRDY is also used to indicate
when the AD7712 has completed its on-chip calibration sequence.

22 SDATA Serial Data. Input/Output with serial data being written to either the control register or the calibration

registers and serial data being accessed from the control register, calibration registers or the data register.
During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is
low). During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low.
The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.

23 DV

DD

24 DGND Ground reference point for digital circuitry.

Digital Supply Voltage, +5 V. DVDD should not exceed AVDD by more than 0.3 V in normal operation.

TERMINOLOGY

INTEGRAL NONLINEARITY

This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end­points of the transfer function are zero-scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi­tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
above the last code transition (111 . . . 110 to 111 . . . 111). The
error is expressed as a percentage of full scale.

POSITIVE FULL-SCALE ERROR

Positive full-scale error is the deviation of the last code transi­tion (111 . . . 110 to 111 . . . 111) from the ideal input full-scale
voltage. For AIN1(+), the ideal full-scale input voltage is
(AIN1(–) + V

scale voltage is +4 × V

/GAIN – 3/2 LSBs); for AIN2, the ideal full-

REF

/GAIN – 3/2 LSBs. Positive full-scale

REF

error applies to both unipolar and bipolar analog input ranges.

UNIPOLAR OFFSET ERROR

Unipolar offset error is the deviation of the first code transition
from the ideal voltage. For AIN1(+), the ideal input voltage is
(AIN1(–) + 0.5 LSB); for AIN2, the ideal input is 0.5 LSB
when operating in the unipolar mode.

BIPOLAR ZERO ERROR

This is the deviation of the midscale transition (0111 . . . 111
to 1000 . . . 000) from the ideal input voltage. For AIN1(+), the
ideal input voltage is (AIN1(–) – 0.5 LSB); for AIN2, the ideal
input is –0.5 LSB when operating in the bipolar mode.

BIPOLAR NEGATIVE FULL-SCALE ERROR

This is the deviation of the first code transition from the ideal
input voltage. For AIN1(+), the ideal input voltage is (AIN1(–)

/GAIN + 0.5 LSB); for AIN2, the ideal input voltage is

– V

REF

(–4 × V

/GAIN + 0.5 LSB) when operating in the bipolar

REF

mode.

POSITIVE FULL-SCALE OVERRANGE

Positive full-scale overrange is the amount of overhead available
to handle input voltages on AIN1(+) input greater than
(AIN1(–) + V

/GAIN (for example, noise peaks or excess voltages due to

V

REF

/GAIN) or on the AIN2 of greater than +4 ×

REF

system gain errors in system calibration routines) without intro­ducing errors due to overloading the analog modulator or to
overflowing the digital filter.

NEGATIVE FULL-SCALE OVERRANGE

This is the amount of overhead available to handle voltages on
AIN1(+) below (AIN1(–) – V

–4 × V

/GAIN without overloading the analog modulator or

REF

/GAIN) or on AIN2 below

REF

overflowing the digital filter. Note that the analog input will
accept negative voltage peaks on AIN1(+) even in the unipolar
mode provided that AIN1(+) is greater than AIN1(–) and
greater than V

OFFSET CALIBRATION RANGE

– 30␣ mV.

SS

In the system calibration modes, the AD7712 calibrates its offset
with respect to the analog input. The offset calibration range
specification defines the range of voltages that the AD7712 can
accept and still accurately calibrate offset.

FULL-SCALE CALIBRATION RANGE

This is the range of voltages that the AD7712 can accept in the
system calibration mode and still correctly calibrate full-scale.

INPUT SPAN

In system calibration schemes, two voltages applied in sequence
to the AD7712’s analog input define the analog input range.
The input span specification defines the minimum and maxi­mum input voltages from zero to full-scale that the AD7712
can accept and still accurately calibrate gain.

–8–

REV. E

AD7712

CONTROL REGISTER (24 BITS)

A write to the device with the A0 input low writes data to the control register. A read to the device with the A0 input low accesses the
contents of the control register. The control register is 24-bits wide and when writing to the register 24 bits of data must be written
otherwise the data will not be loaded to the control register. In other words, it is not possible to write just the first 12-bits of data into
the control register. If more than 24 clock pulses are provided before TFS returns high, then all clock pulses after the 24th clock
pulse are ignored. Similarly, a read operation from the control register should access 24 bits of data.

MSB

MD2 MD1 MD0 G2 G1 G0 CH PD WL X BO B/U

FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0

X = Don’t Care.

Operating Mode

MD2 MD1 MD0 Operating Mode

0 0 0 Normal Mode. This is the normal mode of operation of the device whereby a read to the device accesses

data from the data register. This is the default condition of these bits after the internal power on reset.

0 0 1 Activate Self-Calibration. This activates self-calibration on the channel selected by CH. This is a one-step

calibration sequence, and when complete, the part returns to Normal Mode (with MD2, MD1, MD0 of
the control registers returning to 0, 0, 0). The DRDY output indicates when this self-calibration is complete.
For this calibration type, the zero-scale calibration is done internally on shorted (zeroed) inputs and the
full-scale calibration is done on V

0 1 0 Activate System Calibration. This activates system calibration on the channel selected by CH. This is a

two-step calibration sequence, with the zero-scale calibration done first on the selected input channel and
DRDY indicating when this zero-scale calibration is complete. The part returns to Normal Mode at the
end of this first step in the two-step sequence.

0 1 1 Activate System Calibration. This is the second step of the system calibration sequence with full-scale

calibration being performed on the selected input channel. Once again, DRDY indicates when the full-
scale calibration is complete. When this calibration is complete, the part returns to Normal Mode.

1 0 0 Activate System Offset Calibration. This activates system offset calibration on the channel selected by

CH. This is a one-step calibration sequence and, when complete, the part returns to Normal Mode with
DRDY indicating when this system offset calibration is complete. For this calibration type, the zero-scale
calibration is done on the selected input channel and the full-scale calibration is done internally on V

1 0 1 Activate Background Calibration. This activates background calibration on the channel selected by CH. If

the background calibration mode is on, then the AD7712 provides continuous self-calibration of the
reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence,
extending the conversion time and reducing the word rate by a factor of six. Its major advantage is that
the user does not have to worry about recalibrating the device when there is a change in the ambient
temperature. In this mode, the shorted (zeroed) inputs and V
continuously monitored and the calibration registers of the device are automatically updated.

1 1 0 Read/Write Zero-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents

of the zero-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high
writes data to the zero-scale calibration coefficients of the channel selected by CH. The word length for
reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control
register. Therefore, when writing to the calibration register, 24 bits of data must be written, otherwise the
new data will not be transferred to the calibration register.

1 1 1 Read/Write Full-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of

the full-scale calibration coefficients of the channel selected by CH. A write to the device with A0 high
writes data to the full-scale calibration coefficients of the channel selected by CH. The word length for
reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control
register. Therefore, when writing to the calibration register, 24 bits of data must be written, otherwise the
new data will not be transferred to the calibration register.

REF

.

, as well as the analog input voltage, are

REF

LSB

REF

2

.

–9–REV. E

AD7712

PGA Gain

G2 Gl G0 Gain

0 0 0 1 (Default Condition After the Internal Power-On Reset)
00 1 2
01 0 4
01 1 8
10 0 16
10 1 32
11 0 64
1 1 1 128

Channel Selection

CH Channel

0 AIN1 Low Level Input (Default Condition After the Internal Power-On Reset)
1 AIN2 High Level Input

Power-Down
PD

0 Normal Operation (Default Condition After the Internal Power-On Reset)
1 Power-Down

Word Length
WL Output Word Length

0 16-Bit (Default Condition After Internal Power-On Reset)
1 24-Bit

Burnout Current
BO

0 Off (Default Condition After Internal Power-On Reset)
1On

Bipolar/Unipolar Selection (Both Inputs)
B/U

0 Bipolar (Default Condition After Internal Power-On Reset)
1 Unipolar

Filter Selection (FS11–FS0)

The on-chip digital filter provides a Sinc3 (or (Sinx/x)3) filter response. The 12 bits of data programmed into these bits determine
the filter cutoff frequency, the position of the first notch of the filter and the data rate for the part. In association with the gain selec­tion, it also determines the output noise (and hence the effective resolution) of the device.

The first notch of the filter occurs at a frequency determined by the relationship: filter first notch frequency = (f
where code is the decimal equivalent of the code in bits FS0 to FS11 and is in the range 19 to 2,000. With the nominal f
10 MHz, this results in a first notch frequency range from 9.76 Hz to 1.028 kHz. To ensure correct operation of the AD7712, the
value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device.

Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I and II and Figure 2 show the effect of
the filter notch frequency and gain on the effective resolution of the AD7712. The output data rate (or effective conversion time) for
the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at
50 Hz, then a new word is available at a 50 Hz rate or every 20 ms. If the first notch is at 1 kHz, a new word is available every 1 ms.

The settling time of the filter to a full-scale step input change is worst case 4 × 1/(output data rate). This settling time is to 100% of

the final value. For example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input change is
80 ms max. If the first notch is at 1 kHz, the settling time of the filter to a full-scale input step is 4 ms max. This settling time can be

reduced to 3 × l/(output data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step
input takes place with SYNC low, the settling time will be 3 × l/(output data rate). If a change of channels takes place, the settling
time is 3 × l/(output data rate) regardless of the SYNC input.

The –3 dB frequency is determined by the programmed first notch frequency according to the relationship: filter –3 dB frequency

= 0.262 × first notch frequency.

CLK IN

/512)/code

of

CLK IN

–10–

REV. E

AD7712

Tables I and II show the output rms noise for some typical notch and –3 dB frequencies. The numbers given are for the bipolar
input ranges with a V
noise from the part comes from two sources. First, there is the electrical noise in the semiconductor devices used in the implementa­tion of the modulator (device noise). Secondly, when the analog input signal is converted into the digital domain, quantization noise
is added. The device noise is at a low level and is largely independent of frequency. The quantization noise starts at an even lower
level but rises rapidly with increasing frequency to become the dominant noise source. Consequently, lower filter notch settings
(below 60 Hz approximately) tend to be device noise dominated while higher notch settings are dominated by quantization noise.
Changing the filter notch and cutoff frequency in the quantization noise dominated region results in a more dramatic improvement
in noise performance than it does in the device noise dominated region as shown in Table I. Furthermore, quantization noise is
added after the PGA, so effective resolution is independent of gain for the higher filter notch frequencies. Meanwhile, device noise is
added in the PGA and, therefore, effective resolution suffers a little at high gains for lower notch frequencies.

At the lower filter notch settings (below 60 Hz), the no missing codes performance of the device is at the 24-bit level. At the higher
settings, more codes will be missed until at 1 kHz notch setting, no missing codes performance is only guaranteed to the 12-bit level.
However, since the effective resolution of the part is 10.5 bits for this filter notch setting, this no missing codes performance should
be more than adequate for all applications.

The effective resolution of the device is defined as the ratio of the output rms noise to the input full scale. This does not remain
constant with increasing gain or with increasing bandwidth. Table II shows the same table as Table I except that the output is now

expressed in terms of effective resolution (the magnitude of the rms noise with respect to 2 × V

is possible to do post filtering on the device to improve the output data rate for a given –3 dB frequency and also to further reduce
the output noise (see Digital Filtering section).

of +2.5 V. These numbers are typical and are generated with an analog input voltage of 0 V. The output

REF

/GAIN, i.e., the input full scale). It

REF

Table I. Output Noise vs. Gain and First Notch Frequency

2

First Notch of
Filter and O/P –3␣ dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of
Data Rate

10␣ Hz
25␣ Hz
30␣ Hz
50␣ Hz
60␣ Hz
100␣ Hz
250␣ Hz
500␣ Hz
1␣ kHz

NOTES

1

The default condition (after the internal power-on reset) for the first notch of filter is 60 Hz.

2

For these filter notch frequencies, the output rms noise is primarily dominated by device noise and as a result is independent of the value of the reference voltage.
Therefore, increasing the reference voltage will give an increase in the effective resolution of the device (i.e., the ratio of the rms noise to the input full scale is
increased since the output rms noise remains constant as the input full scale increases).

3

For these filter notch frequencies, the output rms noise is dominated by quantization noise and as a result is proportional to the value of the reference voltage.

1

Frequency 1248163264128

2

2

2

2

2

3

3

3

3

2.62␣ Hz 1.0 0.78 0.48 0.33 0.25 0.25 0.25 0.25

6.55␣ Hz 1.8 1.1 0.63 0.5 0.44 0.41 0.38 0.38

7.86␣ Hz 2.5 1.31 0.84 0.57 0.46 0.43 0.4 0.4

13.1 Hz 4.33 2.06 1.2 0.64 0.54 0.46 0.46 0.46

15.72 Hz 5.28 2.36 1.33 0.87 0.63 0.62 0.6 0.56

26.2 Hz 13 6.4 3.7 1.8 1.1 0.9 0.65 0.65

65.5 Hz 130 75 25 12 7.5 4 2.7 1.7

131 Hz 0.6 × 10
262 Hz 3.1 × 10

3

3

0.26 × 10

1.6 × 10

Typical Output RMS Noise (␮V)

3

140 70 35 25 15 8

3

0.7 × 10

3

0.29 × 10

3

180 120 70 40

Table II. Effective Resolution vs. Gain and First Notch Frequency

1

First Notch of

Effective Resolution

(Bits)

Filter and O/P –3␣ dB Gain of Gain of Gain of Gain of Gain of Gain of Gain of Gain of
Data Rate Frequency 1248163264128

10␣ Hz 2.62␣ Hz 22.5 21.5 21.5 21 20.5 19.5 18.5 17.5
25␣ Hz 6.55␣ Hz 21.5 21 21 20 19.5 18.5 17.5 16.5
30␣ Hz 7.86␣ Hz 21 21 20.5 20 19.5 18.5 17.5 16.5
50␣ Hz 13.1␣ Hz 20 20 20 20 19 18.5 17.5 16.5
60␣ Hz 15.72␣ Hz 20 20 20 19.5 19 18 17 16
100␣ Hz 26.2␣ Hz 18.5 18.5 18.5 18.5 18 17.5 17 16
250␣ Hz 65.5␣ Hz 15 15.5 15.5 15.5 15.5 15.5 15 14.5
500␣ Hz 131␣ Hz 13 13 13 13 13 12.5 12.5 12.5
1␣ kHz 262␣ Hz 10.5 10.5 11 11 11 10.5 10 10

NOTE

1

Effective resolution is defined as the magnitude of the output rms noise with respect to the input full scale (i.e., 2 × V
a V

of +2.5 V and resolution numbers are rounded to the nearest 0.5 LSB.

REF

/GAIN). The above table applies for

REF

–11–REV. E

AD7712

1000

10

0.1
10 1000 10000

100

1

100

NOTCH FREQUENCY – Hz

OUTPUT NOISE – mV

GAIN OF 16
GAIN OF 32

GAIN OF 64
GAIN OF 128

Figures 2a and 2b give information similar to that outlined in Table I. In these plots, the output rms noise is shown for the full range
of available cutoffs frequencies rather than for some typical cutoff frequencies as in Tables I and II. The numbers given in these plots

are typical values at +25°C.

10000

GAIN OF 1

1000

100

10

OUTPUT NOISE – mV

1

0.1
10 1000 10000

100

NOTCH FREQUENCY – Hz

GAIN OF 2
GAIN OF 4
GAIN OF 8

Figure 2a. Plot of Output Noise vs. Gain and Notch

Frequency (Gains of 1 to 8)

CIRCUIT DESCRIPTION

The AD7712 is a sigma-delta A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those in industrial control or pro­cess control applications. It contains a sigma-delta (or charge
balancing) ADC, a calibration microcontroller with on-chip
static RAM, a clock oscillator, a digital filter and a bidirectional
serial communications port.

The part contains two analog input channels, one programmable
gain differential input and one programmable gain high level
single-ended input. The gain range on both inputs is from 1 to

128. For the AIN1 input, this means that the input can accept
unipolar signals of between 0 mV to +20 mV and 0 mV to

+2.5 V or bipolar signals in the range from ±20 mV to ±2.5 V

when the reference input voltage equals +2.5 V. The input volt-

age range for the AIN2 input is ±4 × V

/GAIN and is ±10 V with

REF

the nominal reference of +2.5 V and a gain of 1. The input
signal to the selected analog input channel is continuously
sampled at a rate determined by the frequency of the master
clock, MCLK IN, and the selected gain (see Table III). A
charge balancing A/D converter (Sigma-Delta Modulator) con­verts the sampled signal into a digital pulse train whose duty
cycle contains the digital information. The programmable gain
function on the analog input is also incorporated in this sigma­delta modulator with the input sampling frequency being modi­fied to give the higher gains. A sinc
processes the output of the sigma-delta modulator and updates

3

digital low-pass filter

the output register at a rate determined by the first notch fre­quency of this filter. The output data can be read from the serial
port randomly or periodically at any rate up to the output regis­ter update rate. The first notch of this digital filter (and hence its
–3 dB frequency) can be programmed via an on-chip control
register. The programmable range for this first notch frequency
is from 9.76 Hz to 1.028 kHz, giving a programmable range for
the –3 dB frequency of 2.58 Hz to 269 Hz.

Figure 2b. Plot of Output Noise vs. Gain and Notch

Frequency (Gains of 16 to 128)

The basic connection diagram for the part is shown in Figure 3.
This shows the AD7712 in the external clocking mode with both
the AV

and DVDD pins of the AD7712 being driven from the

DD

analog +5 V supply. Some applications will have separate sup­plies for both AV

and DVDD, and in some of these cases, the

DD

analog supply will exceed the +5 V digital supply (see Power
Supplies and Grounding section).

ANALOG

+5V SUPPLY

DIFFERENTIAL

ANALOG INPUT

SINGLE-ENDED
ANALOG INPUT

ANALOG

GROUND

DIGITAL

GROUND

DV

10mF

DD

0.1mF

AIN1(+)
AIN1(–)

AIN2

STANDBY

AGND
V

SS

DGND

REF OUT
REF IN(+)
V

BIAS

REF IN(–)

AV

DV

DD

AD7712

DD

DRDY

SDATA

SCLK

MODE

SYNC

MCLK OUT

MCLK IN

0.1mF

TFS

RFS

A0

DATA
READY

TRANSMIT
(WRITE)

RECEIVE
(READ)

SERIAL
DATA

SERIAL
CLOCK

ADDRESS
INPUT

+5V

Figure 3. Basic Connection Diagram

–12–

REV. E

AD7712

V

IN

DIFFERENTIAL

AMPLIFIER

COMPARATOR

–FS

DAC

+FS

The AD7712 provides a number of calibration options which
can be programmed via the on-chip control register. A calibra­tion cycle may be initiated at any time by writing to this control
register. The part can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. Other system components may also be included in
the calibration loop to remove offset and gain errors in the input
channel using the system calibration mode. Another option is a
background calibration mode where the part continuously per­forms self-calibration and updates the calibration coefficients.
Once the part is in this mode, the user does not have to worry
about issuing periodic calibration commands to the device or
asking the device to recalibrate when there is a change in the
ambient temperature or power supply voltage.

The AD7712 gives the user access to the on-chip calibration
registers allowing the microprocessor to read the device’s cali­bration coefficients and also to write its own calibration coeffi­cients to the part from prestored values in E

2

PROM. This gives
the microprocessor much greater control over the AD7712’s
calibration procedure. It also means that the user can verify that
the device has performed its calibration correctly by comparing the
coefficients after calibration with prestored values in E

2

PROM.

The AD7712 can be operated in single supply systems provided
that the analog input voltage on the AIN1 input does not go
more negative than –30 mV. For larger bipolar signals on the
AIN1 input, a V

of –5 V is required by the part. For battery

SS

operation or low power systems, the AD7712 offers a standby
mode (controlled by the STANDBY pin) that reduces idle

power consumption to typically 100 µW.

Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC:

SNR = (6.02 × number of bits + 1.76) dB,

a 1-bit ADC or comparator yields an SNR of 7.78 dB.

The AD7712 samples the input signal at a frequency of 39 kHz or
greater (see Table III). As a result, the quantization noise is
spread over a much wider frequency than that of the band of
interest. The noise in the band of interest is reduced still further
by analog filtering in the modulator loop, which shapes the
quantization noise spectrum to move most of the noise energy to
frequencies outside the bandwidth of interest. The noise perfor­mance is thus improved from this 1-bit level to the performance
outlined in Tables I and II and in Figure 2.

The output of the comparator provides the digital input for the
1-bit DAC, so that the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital data
that represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the compara­tor. It can be retrieved as a parallel binary data word using a
digital filter.

Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first order sigma­delta ADC is shown in Figure 5. This contains only a first order
low-pass filter or integrator. It also illustrates the derivation of
the alternative name for these devices: Charge Balancing ADCs.

2

THEORY OF OPERATION

The general block diagram of a sigma-delta ADC is shown in
Figure 4. It contains the following elements:

1. A sample-hold amplifier.

2. A differential amplifier or subtracter.

3. An analog low-pass filter.

4. A 1-bit A/D converter (comparator).

5. A 1-bit DAC.

6. A digital low-pass filter.

S/H AMP

ANALOG

LOW-PASS

FILTER

DAC

COMPARATOR

DIGITAL

FILTER

DIGITAL DATA

Figure 4. General Sigma-Delta ADC

In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, whose output samples the differ­ence signal at a frequency many times that of the analog signal
sampling frequency (oversampling).

Figure 5. Basic Charge-Balancing ADC

It consists of a differential amplifier (whose output is the differ­ence between the analog input and the output of a 1-bit DAC),
an integrator and a comparator. The term charge balancing,
comes from the fact that this system is a negative feedback loop
that tries to keep the net charge on the integrator capacitor at
zero by balancing charge injected by the input voltage with
charge injected by the 1-bit DAC. When the analog input is
zero, the only contribution to the integrator output comes from
the 1-bit DAC. For the net charge on the integrator capacitor to
be zero, the DAC output must spend half its time at +FS and
half its time at –FS. Assuming ideal components, the duty cycle
of the comparator will be 50%.

When a positive analog input is applied, the output of the 1-bit
DAC must spend a larger proportion of the time at +FS, so the
duty cycle of the comparator increases. When a negative input
voltage is applied, the duty cycle decreases.

The AD7712 uses a second-order sigma-delta modulator and a
digital filter that provides a rolling average of the sampled out­put. After power-up, or if there is a step change in the input
voltage, there is a settling time that must elapse before valid
data is obtained.

–13–REV. E

AD7712

Input Sample Rate

The modulator sample frequency for the device remains at

/512 (19.5 kHz @ f

f

CLK IN

= 10 MHz) regardless of the

CLK IN

selected gain. However, gains greater than ×1 are achieved by a

combination of multiple input samples per modulator cycle and
a scaling of the ratio of reference capacitor to input capacitor.
As a result of the multiple sampling, the input sample rate of
the device varies with the selected gain (see Table III). The

effective input impedance is 1/C × f

pling capacitance and f

is the input sample rate.

S

where C is the input sam-

S

Table III. Input Sampling Frequency vs. Gain

Gain Input Sampling Frequency (fS)

1f

22 × f
44 × f
88 × f
16 8 × f
32 8 × f
64 8 × f
128 8 × f

/256 (39 kHz @ f

CLK IN

/256 (78 kHz @ f

CLK IN

/256 (156 kHz @ f

CLK IN

/256 (312 kHz @ f

CLK IN

/256 (312 kHz @ f

CLK IN

/256 (312 kHz @ f

CLK IN

/256 (312 kHz @ f

CLK IN

/256 (312 kHz @ f

CLK IN

CLK IN

CLK IN

CLK IN

CLK IN

CLK IN

CLK IN

CLK IN

CLK IN

= 10 MHz)

= 10 MHz)

= 10 MHz)
= 10 MHz)
= 10 MHz)
= 10 MHz)
= 10 MHz)

= 10 MHz)

DIGITAL FILTERING

The AD7712’s digital filter behaves like a similar analog filter,
with a few minor differences.

First, since digital filtering occurs after the A-to-D conversion
process, it can remove noise injected during the conversion
process. Analog filtering cannot do this.

On the other hand, analog filtering can remove noise superim­posed on the analog signal before it reaches the ADC. Digital
filtering cannot do this, and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. To alleviate this problem, the AD7712 has over­range headroom built into the sigma-delta modulator and digital
filter which allows overrange excursions of 5% above the analog
input range. If noise signals are larger than this, consideration
should be given to analog input filtering, or to reducing the
input channel voltage so that its full scale is half that of the
analog input channel full scale. This will provide an overrange
capability greater than 100% at the expense of reducing the
dynamic range by 1 bit (50%).

Filter Characteristics

The cutoff frequency of the digital filter is determined by the
value loaded to bits FS0 to FS11 in the control register. At the
maximum clock frequency of 10 MHz, the minimum cutoff
frequency of the filter is 2.58 Hz while the maximum program­mable cutoff frequency is 269 Hz.

Figure 6 shows the filter frequency response for a cutoff fre­quency of 2.62 Hz, which corresponds to a first filter notch
frequency of 10 Hz. This is a (sinx/x)

3

) that provides >100 dB of 50 Hz and 60 Hz rejection.

sinc

3

response (also called

Programming a different cutoff frequency via FS0–FS11 does
not alter the profile of the filter response; it changes the fre­quency of the notches as outlined in the Control Register
section.

0
–20
–40
–60
–80

–100
–120
–140

GAIN – dBs

–160
–180
–200
–220
–240

10

0

FREQUENCY – Hz

6050403020

Figure 6. Frequency Response of AD7712 Filter

Since the AD7712 contains this on-chip, low-pass filtering,
there is a settling time associated with step function inputs, and
data on the output will be invalid after a step change until the
settling time has elapsed. The settling time depends upon the
notch frequency chosen for the filter. The output data rate
equates to this filter notch frequency, and the settling time of
the filter to a full-scale step input is four times the output data
period. In applications using both input channels, the settling
time of the filter must be allowed to elapse before data from the
second channel is accessed.

Post Filtering

The on-chip modulator provides samples at a 19.5 kHz output
rate. The on-chip digital filter decimates these samples to pro­vide data at an output rate that corresponds to the programmed
first notch frequency of the filter. Since the output data rate
exceeds the Nyquist criterion, the output rate for a given band­width will satisfy most application requirements. However,
there may be some applications which require a higher data rate
for a given bandwidth and noise performance. Applications that
need this higher data rate will require some post filtering follow­ing the digital filter of the AD7712.

For example, if the required bandwidth is 7.86 Hz but the
required update rate is 100 Hz, the data can be taken from the
AD7712 at the 100 Hz rate giving a –3 dB bandwidth of

26.2 Hz. Post filtering can be applied to this to reduce the
bandwidth and output noise, to the 7.86 Hz bandwidth level,
while maintaining an output rate of 100 Hz.

Post filtering can also be used to reduce the output noise from
the device for bandwidths below 2.62 Hz. At a gain of 128, the
output rms noise is 250 nV. This is essentially device noise or
white noise, and since the input is chopped, the noise has a flat
frequency response. By reducing the bandwidth below 2.62 Hz,
the noise in the resultant passband can be reduced. A reduction

in bandwidth by a factor of two results in a √2 reduction in the

output rms noise. This additional filtering will result in a longer
settling time.

–14–

REV. E

AD7712

Antialias Considerations

The digital filter does not provide any rejection at integer mul-

tiples of the modulator sample frequency (n × 19.5 kHz, where

n = 1, 2, 3 . . . ). This means that there are frequency bands,

±f

3 dB

wide (f

is cutoff frequency selected by FS0 to FS11)

3 dB

where noise passes unattenuated to the output. However, due to
the AD7712’s high oversampling ratio, these bands occupy only
a small fraction of the spectrum and most broadband noise is
filtered. In any case, because of the high oversampling ratio a
simple, RC, single pole filter is generally sufficient to attenuate
the signals in these bands on the analog input and thus provide
adequate antialiasing filtering.

If passive components are placed in front of the AIN1 input of
the AD7712, care must be taken to ensure that the source imped­ance is low enough so as not to introduce gain errors in the sys-

tem. The dc input impedance for the AIN1 input is over 1 GΩ.

The input appears as a dynamic load that varies with the clock
frequency and with the selected gain (see Figure 7). The input
sample rate, as shown in Table III, determines the time allowed
for the analog input capacitor, C

, to be charged. External

IN

impedances result in a longer charge time for this capacitor, and
this may result in gain errors being introduced on the analog
inputs. Table IV shows the allowable external resistance/
capacitance values such that no gain error to the 16-bit level
is introduced while Table V shows the allowable external
resistance/capacitance values such that no gain error to the
20-bit level is introduced. Both inputs of the differential input
channels (AIN1) look into similar input circuitry.

R

INT

AIN

(7kV TYP)

C

INT

(11.5pF TYP)

SWITCHING FREQUENCY DEPENDS ON
f

AND SELECTED GAIN

CLKIN

IMPEDANCE

V

BIAS

HIGH
>1GV

Table IV. Typical External Series Resistance That Will Not
Introduce 16-Bit Gain Error

External Capacitance (pF)

Gain 0 50 100 500 1000 5000

1 184 kΩ 45.3 kΩ 27.1 kΩ 7.3 kΩ 4.1 kΩ 1.1 kΩ
2 88.6 kΩ 22.1 kΩ 13.2 kΩ 3.6 kΩ 2.0 kΩ 560 Ω
4 41.4 kΩ 10.6 kΩ 6.3 kΩ 1.7 kΩ 970 Ω 270 Ω

8–128 17.6 kΩ 4.8 kΩ 2.9 kΩ 790 Ω 440 Ω

120 Ω

Table V. Typical External Series Resistance That Will Not
Introduce 20-Bit Gain Error

External Capacitance (pF)

Gain 0 50 100 500 1000 5000

1 145 kΩ 34.5 kΩ 20.4 kΩ 5.2 kΩ 2.8 kΩ 700 Ω
2 70.5 kΩ 16.9 kΩ 10 kΩ 2.5 kΩ 1.4 kΩ 350 Ω
4 31.8 kΩ 8.0 kΩ 4.8 kΩ 1.2 kΩ 670 Ω 170 Ω
8–128 13.4 kΩ 3.6 kΩ 2.2 kΩ 550 Ω 300 Ω 80 Ω

The numbers in the above tables assume a full-scale change on
the analog input. In any case, the error introduced due to longer
charging times is a gain error which can be removed using the
system calibration capabilities of the AD7712 provided that the
resultant span is within the span limits of the system calibration
techniques for the AD7712.

The AIN2 input contains a resistive attenuation network as
outlined in Figure 8. The typical input impedance on this input

is 44 kΩ. As a result, the AIN2 input should be driven from a

low impedance source.

AIN2

33kV

11kV

MODULATOR

CIRCUIT

2

Figure 7. AIN1 Input Impedance

V

BIAS

Figure 8. AIN2 Input Impedance

–15–REV. E

AD7712

ANALOG INPUT FUNCTIONS
Analog Input Ranges

The analog inputs on the AD7712 provide the user with consid­erable flexibility in terms of analog input voltage ranges. One of
the inputs is a differential, programmable gain, input channel
which can handle either unipolar or bipolar input signals. The
common-mode range of this input is from V

to AVDD provided

SS

that the absolute value of the analog input voltage lies between

– 30 mV and AVDD + 30 mV. The second analog input is a

V

SS

single-ended, programmable gain, high level input that accepts

analog input ranges of 0 to +4 × V

/GAIN or ±4 × V

REF

/GAIN.

REF

The dc input leakage current on the AIN1 input is 10 pA maxi-

mum at 25°C (±1 nA over temperature). This results in a dc

offset voltage developed across the source impedance. However,
this dc offset effect can be compensated for by a combination of
the differential input capability of the part and its system cali­bration mode. The dc input current on the AIN2 input depends
on the input voltage. For the nominal input voltage range of

±10 V, the input current is ±225 µA typ.

Burnout Current

The AIN1(+) input of the AD7712 contains a 4.5 µA current

source that can be turned on/off via the control register. This
current source can be used in checking that a transducer has not
burned out or gone open circuit before attempting to take mea­surements on that channel. If the current is turned on and is
allowed flow into the transducer and a measurement of the
input voltage on the AIN1 input is taken, it can indicate that the
transducer is not functioning correctly. For normal operation,
this burnout current is turned off by writing a 0 to the BO bit in
the control register.

Bipolar/Unipolar Inputs

The two analog inputs on the AD7712 can accept either unipo­lar or bipolar input voltage ranges. Bipolar or unipolar options
are chosen by programming the B/U bit of the control register.
This programs both channels for either unipolar or bipolar
operation. Programming the part for either unipolar or bipolar
operation does not change any of the input signal conditioning;
it simply changes the data output coding. The data coding is
binary for unipolar inputs and offset binary for bipolar inputs.

The AIN1 input channel is differential and, as a result, the
voltage to which the unipolar and bipolar signals are referenced
is the voltage on the AIN1(–) input. For example, if AIN1(–) is
+1.25 V and the AD7712 is configured for unipolar operation
with a gain of 1 and a V

of +2.5 V, the input voltage range

REF

on the AIN1(+) input is +1.25 V to +3.75 V. If AIN1(–) is
+1.25 V and the AD7712 is configured for bipolar mode with a
gain of 1 and a V

of +2.5 V, the analog input range on the

REF

AIN1(+) input is –1.25 V to +3.75 V. For the AIN2 input, the
input signals are referenced to AGND.

REFERENCE INPUT/OUTPUT

The AD7712 contains a temperature compensated +2.5 V refer-

ence which has an initial tolerance of ±1%. This reference volt-

age is provided at the REF OUT, pin and it can be used as the
reference voltage for the part by connecting the REF OUT pin
to the REF IN(+) pin. This REF OUT pin is a single-ended
output, referenced to AGND, which is capable of providing up

to 1 mA to an external load. In applications where REF OUT
is connected directly to REF IN(+), REF IN(–) should be tied
to AGND to provide the nominal +2.5 V reference for the
AD7712.

The reference inputs of the AD7712, REF IN(+) and
REF IN(–), provide a differential reference input capability. The
common-mode range for these differential inputs is from V

. The nominal differential voltage, V

AV

DD

(REF IN(+) –

REF

to

SS

REF IN(–)), is +2.5 V for specified operation, but the reference
voltage can go to +5 V with no degradation in performance
provided that the absolute value of REF IN(+) and REF IN(–)
does not exceed its AV

and VSS limits and the V

DD

BIAS

input

voltage range limits are obeyed. The part is also functional with

voltages down to 1 V but with degraded performance as

V

REF

the output noise will, in terms of LSB size, be larger. REF
IN(+) must always be greater than REF IN(–) for correct opera­tion of the AD7712.

Both reference inputs provide a high impedance, dynamic load
similar to the AIN1 analog inputs. The maximum dc input

leakage current is 10 pA (±1 nA over temperature) and source

resistance may result in gain errors on the part. The reference
inputs look like the AIN1 analog input (see Figure 7). In this
case, R
sample rate is f
of 1 to 8 C

is 5 kΩ typ and C

INT

INT

/256 and does not vary with gain. For gains

CLK IN

is 20 pF; for a gain of 16 it is 10 pF; for a gain of

varies with gain. The input

INT

32 it is 5 pF; for a gain of 64 it is 2.5 pF; and for a gain of 128 it
is 1.25 pF.

The digital filter of the AD7712 removes noise from the refer­ence input just as it does with the analog input, and the same
limitations apply regarding lack of noise rejection at integer
multiples of the sampling frequency. The output noise perfor­mance outlined in Tables I and II assumes a clean reference. If
the reference noise in the bandwidth of interest is excessive, it
can degrade the performance of the AD7712. Using the on-chip
reference as the reference source for the part (i.e., connecting
REF OUT to REF IN) results in somewhat degraded output
noise performance from the AD7712 for portions of the noise
table that are dominated by the device noise. The on-chip refer­ence noise effect is eliminated in ratiometric applications where
the reference is used to provide its excitation voltage for the
analog front end. The connection scheme shown in Figure 9
between the REF OUT and REF IN pins of the AD7712 is rec­ommended when using the on-chip reference. Recommended
reference voltage sources for the AD7712 include the AD780
and AD680 2.5 V references.

REF OUT REF IN(+)

AD7712

REF IN(–)

Figure 9. REF OUT/REF IN Connection

–16–

REV. E

AD7712

V

Input

BIAS

The V

input determines at what voltage the internal analog

BIAS

circuitry is biased. It essentially provides the return path for
analog currents flowing in the modulator, and as such it should
be driven from a low impedance point to minimize errors.

For maximum internal headroom, the V
set halfway between AV
AV

and (V

DD

+ 0.85 × V

BIAS

headroom the circuit has at the upper end, while the difference
between V

and (V

SS

and VSS. The difference between

BIAS

DD

) determines the amount of

REF

– 0.85 × V

REF

voltage should be

BIAS

) determines the amount
of headroom the circuit has at the lower end. Care should be
taken in choosing a V
prescribed limits. For single +5 V operation, the selected V
voltage must ensure that V

or VSS or that the V

AV

DD

voltage to ensure that it stays within

BIAS

± 0.85 × V

BIAS

voltage itself is greater than V

BIAS

does not exceed

REF

BIAS

SS

+ 2.1 V and less than AVDD – 2.1 V. For single +10 V operation

or dual ±5 V operation, the selected V

that V
the V
AV
and V

± 0.85 × V

BIAS

voltage itself is greater than VSS + 3 V or less than

BIAS

– 3 V. For example, with AVDD = +4.75 V, VSS = 0 V

DD

= +2.5 V, the allowable range for the V

REF

+2.125 V to +2.625 V. With AV

= +5 V, the range for V

V

REF

= +4.75 V, VSS = –4.75 V and V

AV

DD

does not exceed AVDD or VSS or that

REF

DD

is +4.25 V to +5.25 V. With

BIAS

voltage must ensure

BIAS

voltage is

BIAS

= +9.5 V, VSS = 0 V and

= +2.5 V, the V

REF

BIAS

range is –2.625 V to +2.625 V.

The V
ply rejection performance of the AD7712. If the V
tracks the AV
from the AV
ternal Zener diode, connected between the AV
as the source for the V
AV

voltage does have an effect on the AVDD power sup-

BIAS

supply, it improves the power supply rejection

DD

supply line from 80 dB to 95 dB. Using an ex-

DD

voltage gives the improvement in

power supply rejection performance.

DD

BIAS

DD

voltage

BIAS

line and V

BIAS,

USING THE AD7712
SYSTEM DESIGN CONSIDERATIONS

The AD7712 operates differently from successive approximation
ADCs or integrating ADCs. Since it samples the signal continu­ously, like a tracking ADC, there is no need for a start convert
command. The output register is updated at a rate determined
by the first notch of the filter and the output can be read at any
time, either synchronously or asynchronously.

Clocking

The AD7712 requires a master clock input, which may be an
external TTL/CMOS compatible clock signal applied to the
MCLK IN pin with the MCLK OUT pin left unconnected.
Alternatively, a crystal of the correct frequency can be con­nected between MCLK IN and MCLK OUT, in which case the
clock circuit will function as a crystal controlled oscillator. For
lower clock frequencies, a ceramic resonator may be used in­stead of the crystal. For these lower frequency oscillators, exter­nal capacitors may be required on either the ceramic resonator
or on the crystal.

The input sampling frequency, the modulator sampling fre­quency, the –3 dB frequency, output update rate and calibration
time are all directly related to the master clock frequency,

Reducing the master clock frequency by a factor of two

f

CLK IN.

will halve the above frequencies and update rate and will double
the calibration time.

The current drawn from the DVDD power supply is also directly
related to f
the DV

DD

power supply.

AV

DD

. Reducing f

CLK IN

current but will not affect the current drawn from the

by a factor of two will halve

CLK IN

System Synchronization

If multiple AD7712s are operated from a common master clock,
they can be synchronized to update their output registers simul­taneously. A falling edge on the SYNC input resets the filter
and places the AD7712 into a consistent, known state. A com­mon signal to the AD7712s’ SYNC inputs will synchronize their
operation. This would normally be done after each AD7712 has
performed its own calibration or has had calibration coefficients
loaded to it.

The SYNC input can also be used to reset the digital filter in
systems where the turn-on time of the digital power supply
(DVDD) is very long. In such cases, the AD7712 will start oper­ating internally before the DV
operating level, +4.75 V. With a low DV

line has reached its minimum

DD

voltage, the

DD

AD7712’s internal digital filter logic does not operate correctly.
Thus, the AD7712 may have clocked itself into an incorrect
operating condition by the time that DV

has reached its cor-

DD

rect level. The digital filter will be reset upon issue of a calibra­tion command (whether it is self-calibration, system calibration
or background calibration) to the AD7712. This ensures correct
operation of the AD7712. In systems where the power-on de­fault conditions of the AD7712 are acceptable, and no calibra­tion is performed after power-on, issuing a SYNC pulse to the
AD7712 will reset the AD7712’s digital filter logic. An R, C on
the SYNC line, with R, C time constant longer than the DV

DD

power-on time, will perform the SYNC function.

Accuracy

Sigma-delta ADCs, like VFCs and other integrating ADCs, do
not contain any source of nonmonotonicity and inherently offer
no missing codes performance. The AD7712 achieves excellent
linearity by the use of high quality, on-chip silicon dioxide ca­pacitors, which have a very low capacitance/voltage coefficient.
The device also achieves low input drift through the use of
chopper stabilized techniques in its input stage. To ensure
excellent performance over time and temperature, the AD7712
uses digital calibration techniques that minimize offset and gain
error.

Autocalibration

Autocalibration on the AD7712 removes offset and gain errors
from the device. A calibration routine should be initiated on the
device whenever there is a change in the ambient operating
temperature or supply voltage. It should also be initiated if there
is a change in the selected gain, filter notch or bipolar/unipolar
input range. However, if the AD7712 is in its background cali­bration mode, the above changes are all automatically taken care
of (after the settling time of the filter has been allowed for).

The AD7712 offers self-calibration, system calibration and
background calibration facilities. For calibration to occur on the
selected channel, the on-chip microcontroller must record the
modulator output for two different input conditions. These are
“zero-scale” and “full-scale” points. With these readings, the
microcontroller can calculate the gain slope for the input to
output transfer function of the converter. Internally, the part
works with a resolution of 33 bits to determine its conversion
result of either 16 bits or 24 bits.

2

–17–REV. E

AD7712

The AD7712 also provides the facility to write to the on-chip
calibration registers, and in this manner the span and offset for
the part can be adjusted by the user. The offset calibration regis­ter contains a value which is subtracted from all conversion
results, while the full-scale calibration register contains a value
which is multiplied by all conversion results. The offset calibra­tion coefficient is subtracted from the result prior to the multi­plication by the full-scale coefficient. In the first three modes
outlined here, the DRDY line indicates that calibration is com­plete by going low. If DRDY is low before (or goes low during)
the calibration command, it may take up to one modulator cycle
before DRDY goes high to indicate that calibration is in
progress. Therefore, the DRDY line should be ignored for up
to one modulator cycle after the last bit of the calibration com­mand is written to the control register.

Self-Calibration

In the self-calibration mode with a unipolar input range, the
zero-scale point used in determining the calibration coefficients
is with both inputs shorted (i.e., AIN1(+) = AIN1(–) =

for AIN1 and AIN2 = V

V

BIAS

point is V

. The zero-scale coefficient is determined by con-

REF

for AIN2 ) and the full-scale

BIAS

verting an internal shorted inputs node. The full-scale coeffi­cient is determined from the span between this shorted inputs
conversion and a conversion on an internal V

node. The self-

REF

calibration mode is invoked by writing the appropriate values (0,
0, 1) to the MD2, MD1 and MD0 bits of the control register. In
this calibration mode, the shorted inputs node is switched in to
the modulator first and a conversion is performed; the V

REF

node is then switched in, and another conversion is performed.
When the calibration sequence is complete, the calibration
coefficients updated and the filter resettled to the analog input
voltage, the DRDY output goes low. The self-calibration proce­dure takes into account the selected gain on the PGA.

For bipolar input ranges in the self-calibrating mode, the
sequence is very similar to that just outlined. In this case, the
two points that the AD7712 calibrates are midscale (bipolar
zero) and positive full scale.

System Calibration

System calibration allows the AD7712 to compensate for system
gain and offset errors as well as its own internal errors. System
calibration performs the same slope factor calculations as self­calibration but uses voltage values presented by the system to
the AIN inputs for the zero and full-scale points. System cali­bration is a two-step process. The zero-scale point must be
presented to the converter first. It must be applied to the con­verter before the calibration step is initiated and remain stable
until the step is complete. System calibration is initiated by
writing the appropriate values (0, 1, 0) to the MD2, MD1 and
MD0 bits of the control register. The DRDY output from the
device will signal when the step is complete by going low. After
the zero-scale point is calibrated, the full-scale point is applied
and the second step of the calibration process is initiated by
again writing the appropriate values (0, 1, 1) to MD2, MD1 and
MD0. Again the full-scale voltage must be set up before the
calibration is initiated, and it must remain stable throughout the
calibration step. DRDY goes low at the end of this second step
to indicate that the system calibration is complete. In the

unipolar mode, the system calibration is performed between the
two endpoints of the transfer function; in the bipolar mode, it is
performed between midscale and positive full scale.

This two-step system calibration mode offers another feature.
After the sequence has been completed, additional offset or gain
calibrations can be performed by themselves to adjust the zero
reference point or the system gain. This is achieved by perform­ing the first step of the system calibration sequence (by writing
0, 1, 0 to MD2, MD1, MD0). This will adjust the zero-scale or
offset point but will not change the slope factor from what was
set during a full system calibration sequence.

System calibration can also be used to remove any errors from
an antialiasing filter on the analog input. A simple R, C anti­aliasing filter on the front end may introduce a gain error on the
analog input voltage but the system calibration can be used to
remove this error.

System Offset Calibration

System offset calibration is a variation of both the system cali­bration and self-calibration. In this case, the zero-scale point
for the system is presented to the AIN input of the converter.
System offset calibration is initiated by writing 1, 0, 0 to MD2,
MD1, MD0. The system zero-scale coefficient is determined by
converting the voltage applied to the AIN input, while the full­scale coefficient is determined from the span between this AIN
conversion and a conversion on V

. The zero-scale point

REF

should be applied to the AIN input for the duration of the cali­bration sequence. This is a one-step calibration sequence with
DRDY going low when the sequence is completed. In the uni­polar mode, the system offset calibration is performed between
the two endpoints of the transfer function; in the bipolar mode,
it is performed between midscale and positive full scale.

Background Calibration

The AD7712 also offers a background calibration mode where
the part interleaves its calibration procedure with its normal
conversion sequence. In the background calibration mode, the
same voltages are used as the calibration points as are used in
the self-calibration mode, i.e., shorted inputs and V

REF

. The
background calibration mode is invoked by writing 1, 0, 1 to
MD2, MD1, MD0 of the control register. When invoked, the
background calibration mode reduces the output data rate of the
AD7712 by a factor of six while the –3 dB bandwidth remains
unchanged. Its advantage is that the part is continually perform­ing calibration and automatically updating its calibration coeffi­cients. As a result, the effects of temperature drift, supply
sensitivity and time drift on zero- and full-scale errors are auto­matically removed. When the background calibration mode is
turned on, the part will remain in this mode until bits MD2,
MD1 and MD0 of the control register are changed. With back­ground calibration mode on, the first result from the AD7712
will be incorrect as the full-scale calibration will not have been
performed. For a step change on the input, the second output
update will have settled to 100% of the final value.

Table VI summarizes the calibration modes and the calibration
points associated with them. It also gives the duration from
when the calibration is invoked to when valid data is available to
the user.

–18–

REV. E

AD7712

AD7712

0.1mF 0.1mF10mF

ANALOG
SUPPLY

DIGITAL +5V
SUPPLY

AV

DD

DV

DD

Table VI. Calibration Truth Table

Cal Type MD2, MD1, MD0 Zero-Scale Cal Full-Scale Cal Sequence Duration

Self-Cal 0, 0, 1 Shorted Inputs V

REF

System Cal 0, 1, 0 AIN – Two Step 4 × 1/Output Rate
System Cal 0, 1, 1 – AIN Two Step 4 × 1/Output Rate

System Offset Cal 1, 0, 0 AIN V
Background Cal 1, 0, 1 Shorted Inputs V

REF

REF

One Step 9 × 1/Output Rate

One Step 9 × 1/Output Rate
One Step 6 × 1/Output Rate

2

Span and Offset Limits

Whenever a system calibration mode is used, there are limits on
the amount of offset and span that can be accommodated. The
range of input span in both the unipolar and bipolar modes for

AIN1 has a minimum value of 0.8 × V
mum value of 2.1 × V

/GAIN. For AIN2, both numbers are a

REF

/GAIN and a maxi-

REF

factor of four higher.

The amount of offset which can be accommodated depends on
whether the unipolar or bipolar mode is being used. This offset
range is limited by the requirement that the positive full-scale

calibration limit is ≤ 1.05 × V
the offset range plus the span range cannot exceed 1.05 × V
GAIN for AIN1. If the span is at its minimum (0.8 × V
GAIN) the maximum the offset can be is (0.25 × V

/GAIN for AIN1. Therefore,

REF

/GAIN)

REF

REF

REF

/

for AIN1. For AIN2, both ranges are multiplied by a factor of
four.

In the bipolar mode, the system offset calibration range is again
restricted by the span range. The span range of the converter in
bipolar mode is equidistant around the voltage used for the zero­scale point, thus the offset range plus half the span range cannot

exceed (1.05 × V

/GAIN, the offset span cannot move more than ±(0.05 ×

V

REF

/GAIN) before the endpoints of the transfer function ex-

V

REF

ceed the input overrange limits ±(1.05 × V
If the span range is set to the minimum ±(0.4 × V

the maximum

/GAIN) for AIN1. If the span is set to 2 ×

REF

/GAIN) for AIN1.

REF

allowable offset range is ±(0.65

× V

/GAIN),

REF

REF

/GAIN)
for AIN1. Once again, for AIN2, both ranges are multiplied
by a factor of four.

POWER-UP AND CALIBRATION

On power-up, the AD7712 performs an internal reset which sets
the contents of the control register to a known state. However,
to ensure correct calibration for the device a calibration routine
should be performed after power-up.

The power dissipation and temperature drift of the AD7712 are
low and no warm-up time is required before the initial calibra­tion is performed. However, if an external reference is being
used, this reference must have stabilized before calibration is
initiated.

Drift Considerations

The AD7712 uses chopper stabilization techniques to minimize
input offset drift. Charge injection in the analog switches and dc
leakage currents at the sampling node are the primary sources of
offset voltage drift in the converter. The dc input leakage cur­rent is essentially independent of the selected gain. Gain drift
within the converter depends primarily upon the temperature
tracking of the internal capacitors. It is not affected by leakage
currents.

Measurement errors due to offset drift or gain drift can be elimi­nated at any time by recalibrating the converter or by operating
the part in the background calibration mode. Using the system
calibration mode can also minimize offset and gain errors in the
signal conditioning circuitry. Integral and differential linearity
errors are not significantly affected by temperature changes.

POWER SUPPLIES AND GROUNDING

Since the analog inputs and reference input are differential,
most of the voltages in the analog modulator are common-mode
voltages. V
currents flowing in the analog modulator. As a result, the V

/

provides the return path for most of the analog

BIAS

input should be driven from a low impedance to minimize errors
due to charging/discharging impedances on this line. When the
internal reference is used as the reference source for the part,
AGND is the ground return for this reference voltage.

The analog and digital supplies to the AD7712 are independent
and separately pinned out to minimize coupling between the
analog and digital sections of the device. The digital filter will
provide rejection of broadband noise on the power supplies,
except at integer multiples of the modulator sampling frequency.
The digital supply (DV
supply (AV

) by more than 0.3 V in normal operation. If sepa-

DD

) must not exceed the analog positive

DD

rate analog and digital supplies are used, the recommended
decoupling scheme is shown in Figure 10. In systems where

= +5 V and DVDD = +5 V, it is recommended that AV

AV

DD

and DVDD are driven from the same +5 V supply, although each
supply should be decoupled separately as shown in Figure 10. It
is preferable that the common supply is the system’s analog +5 V
supply.

It is also important that power is applied to the AD7712 before
signals at REF IN, AIN or the logic input pins in order to avoid
excessive current. If separate supplies are used for the AD7712
and the system digital circuitry, then the AD7712 should be
powered up first. If it is not possible to guarantee this, then
current limiting resistors should be placed in series with the
logic inputs.

Figure 10. Recommended Decoupling Scheme

BIAS

DD

–19–REV. E

AD7712

DIGITAL INTERFACE

The AD7712’s serial communications port provides a flexible
arrangement to allow easy interfacing to industry-standard
microprocessors, microcontrollers and digital signal processors.
A serial read to the AD7712 can access data from the output
register, the control register or from the calibration registers. A
serial write to the AD7712 can write data to the control register
or the calibration registers.

Two different modes of operation are available, optimized for
different types of interface where the AD7712 can act either as
master in the system (it provides the serial clock) or as slave (an
external serial clock can be provided to the AD7712). These
two modes, labelled self-clocking mode and external clocking
mode, are discussed in detail in the following sections.

Self-Clocking Mode

The AD7712 is configured for its self-clocking mode by tying
the MODE pin high. In this mode, the AD7712 provides the
serial clock signal used for the transfer of data to and from the
AD7712. This self-clocking mode can be used with processors
that allow an external device to clock their serial port including
most digital signal processors and microcontrollers such as the
68HC11 and 68HC05. It also allows easy interfacing to serial
parallel conversion circuits in systems with parallel data commu­nication, allowing interfacing to 74XX299 Universal Shift regis­ters without any additional decoding. In the case of shift registers,
the serial clock line should have a pull-down resistor instead of
the pull-up resistor shown in Figure 11 and Figure 12.

Read Operation

Data can be read from either the output register, the control
register or the calibration registers. A0 determines whether the
data read accesses data from the control register or from the
output/calibration registers. This A0 signal must remain valid
for the duration of the serial read operation. With A0 high, data
is accessed from either the output register or from the calibra­tion registers. With A0 low, data is accessed from the control
register.

The function of the DRDY line is dependent only on the output
update rate of the device and the reading of the output data
register. DRDY goes low when a new data word is available in

the output data register. It is reset high when the last bit of data
(either 16th bit or 24th bit) is read from the output register. If
data is not read from the output register, the DRDY line will
remain low. The output register will continue to be updated at
the output update rate but DRDY will not indicate this. A read
from the device in this circumstance will access the most recent
word in the output register. If a new data word becomes avail­able to the output register while data is being read from the
output register, DRDY will not indicate this and the new data
word will be lost to the user. DRDY is not affected by reading
from the control register or the calibration registers.

Data can only be accessed from the output data register when
DRDY is low. If RFS goes low with DRDY high, no data trans-
fer will take place. DRDY does not have any effect on reading
data from the control register or from the calibration registers.

Figure 11 shows a timing diagram for reading from the AD7712
in the self-clocking mode. This read operation shows a read
from the AD7712’s output data register. A read from the con­trol register or calibration registers is similar, but in these cases
the DRDY line is not related to the read function. Depending
on the output update rate, it can go low at any stage in the
control/calibration register read cycle without affecting the read
and its status should be ignored. A read operation from either
the control or calibration registers must always read 24 bits of
data from the respective register.

Figure 11 shows a read operation from the AD7712. For the
timing diagram shown, it is assumed that there is a pull-up
resistor on the SCLK output. With DRDY low, the RFS input is
brought low. RFS going low enables the serial clock of the
AD7712 and also places the MSB of the word on the serial data
line. All subsequent data bits are clocked out on a high to low
transition of the serial clock and are valid prior to the following
rising edge of this clock. The final active falling edge of SCLK
clocks out the LSB, and this LSB is valid prior to the final ac­tive rising edge of SCLK. Coincident with the next falling edge
of SCLK, DRDY is reset high. DRDY going high turns off the
SCLK and the SDATA outputs. This means that the data hold
time for the LSB is slightly shorter than for all other bits.

DRDY (O)

A0 (I)

RFS (I)

SCLK (O)

SDATA (O)

t

2

t

4

t

6

t

t

8

7

MSB LSB

t

9

t

10

Figure 11. Self-Clocking Mode, Output Data Read Operation

–20–

t

3

t

5

THREE-STATE

REV. E

AD7712

Write Operation

Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the DRDY line and the write operation does not have any effect
on the status of DRDY. A write operation to the control register
or the calibration register must always write 24 bits to the
respective register.

Figure 12 shows a write operation to the AD7712. A0 deter­mines whether a write operation transfers data to the control
register or to the calibration registers. This A0 signal must remain
valid for the duration of the serial write operation. The falling
edge of TFS enables the internally generated SCLK output.
The serial data to be loaded to the AD7712 must be valid on
the rising edge of this SCLK signal. Data is clocked into the
AD7712 on the rising edge of the SCLK signal with the MSB
transferred first. On the last active high time of SCLK, the LSB
is loaded to the AD7712. Subsequent to the next falling edge of
SCLK, the SCLK output is turned off. (The timing diagram of
Figure 12 assumes a pull-up resistor on the SCLK line.)

External Clocking Mode

The AD7712 is configured for its external clocking mode by
tying the MODE pin low. In this mode, SCLK of the AD7712
is configured as an input, and an external serial clock must be
provided to this SCLK pin. This external clocking mode is
designed for direct interface to systems which provide a serial
clock output which is synchronized to the serial data output,
including microcontrollers such as the 80C51, 87C51, 68HC11
and 68HC05 and most digital signal processors.

Read Operation

As with the self-clocking mode, data can be read from either the
output register, the control register or the calibration registers.
A0 determines whether the data read accesses data from the
control register or from the output/calibration registers. This A0
signal must remain valid for the duration of the serial read

operation. With A0 high, data is accessed from either the output
register or from the calibration registers. With A0 low, data is
accessed from the control register.

The function of the DRDY line is dependent only on the output
update rate of the device and the reading of the output data
register. DRDY goes low when a new data word is available in
the output data register. It is reset high when the last bit of data
(either 16th bit or 24th bit) is read from the output register. If
data is not read from the output register, the DRDY line will
remain low. The output register will continue to be updated at
the output update rate, but DRDY will not indicate this. A read
from the device in this circumstance will access the most recent
word in the output register. If a new data word becomes avail­able to the output register while data is being read from the
output register, DRDY will not indicate this and the new data
word will be lost to the user. DRDY is not affected by reading
from the control register or the calibration register.

Data can only be accessed from the output data register when
DRDY is low. If RFS goes low while DRDY is high, no data
transfer will take place. DRDY does not have any effect on reading
data from the control register or from the calibration registers.

Figures 13a and 13b show timing diagrams for reading from the
AD7712 in the external clocking mode. Figure 13a shows a
situation where all the data is read from the AD7712 in one read
operation. Figure 13b shows a situation where the data is read
from the AD7712 over a number of read operations. Both read
operations show a read from the AD7712’s output data register.
A read from the control register or calibration registers is similar,
but in these cases the DRDY line is not related to the read func­tion. Depending on the output update rate, it can go low at any
stage in the control/calibration register read cycle without affect­ing the read and its status should be ignored. A read operation
from either the control or calibration registers must always read
24 bits of data from the respective register.

2

A0 (I)

t

14

TFS (I)

t

SCLK (O)

SDATA (O)

16

t

18

MSB LSB

t

9

t

10

t

19

Figure 12. Self-Clocking Mode, Control/Calibration Register Write Operation

–21–REV. E

t

15

t

17

AD7712

Figure 13a shows a read operation from the AD7712 where
RFS remains low for the duration of the data word transmission.
With DRDY low, the RFS input is brought low. The input
SCLK signal should be low between read and write operations.
RFS going low places the MSB of the word to be read on the
serial data line. All subsequent data bits are clocked out on a
high to low transition of the serial clock and are valid prior to
the following rising edge of this clock. The penultimate falling
edge of SCLK clocks out the LSB and the final falling edge
resets the DRDY line high. This rising edge of DRDY turns off
the serial data output.

Figure 13b shows a timing diagram for a read operation where
RFS returns high during the transmission of the word and re­turns low again to access the rest of the data word. Timing
parameters and functions are very similar to that outlined for

DRDY (O)

t

20

A0 (I)

t

22

RFS (I)

SCLK (I)

t

25

t

24

SDATA (O) LSBMSB

Figure 13a, but Figure 13b has a number of additional times to
show timing relationships when RFS returns high in the middle
of transferring a word.

RFS should return high during a low time of SCLK. On the
rising edge of RFS, the SDATA output is turned off. DRDY
remains low and will remain low until all bits of the data word
are read from the AD7712, regardless of the number of times
RFS changes state during the read operation. Depending on the
time between the falling edge of SCLK and the rising edge of
RFS, the next bit (BIT N + 1) may appear on the databus be­fore RFS goes high. When RFS returns low again, it activates
the SDATA output. When the entire word is transmitted, the
DRDY line will go high, turning off the SDATA output as per
Figure 13a.

t

21

t

23

t

26

t

27

t

t

29

28

THREE-STATE

Figure 13a. External Clocking Mode, Output Data Read Operation

DRDY (O)

t

20

A0 (I)

t

22

RFS (I)

t

SCLK (I)

SDATA (O)

26

t

24

t

25

MSB BIT N

t

27

t

30

THREE-STATE

Figure 13b. External Clocking Mode, Output Data Read Operation (

t

t

31

RFS

Returns High During Read Operation)

24

BIT N+1

t

25

–22–

REV. E

AD7712

Write Operation

Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the DRDY line, and the write operation does not have any effect
on the status of DRDY. A write operation to the control regis­ter or the calibration register must always write 24 bits to the
respective register.

Figure 14a shows a write operation to the AD7712 with TFS
remaining low for the duration of the write operation. A0 deter­mines whether a write operation transfers data to the control
register or to the calibration registers. This A0 signal must
remain valid for the duration of the serial write operation. As
before, the serial clock line should be low between read and
write operations. The serial data to be loaded to the AD7712
must be valid on the high level of the externally applied SCLK
signal. Data is clocked into the AD7712 on the high level of this

A0 (I)

t

32

TFS (I)

t

26

SCLK (I)

t

36

SDATA (I)

t

35

MSB

SCLK signal with the MSB transferred first. On the last active
high time of SCLK, the LSB is loaded to the AD7712.

Figure 14b shows a timing diagram for a write operation to the
AD7712 with TFS returning high during the write operation
and returning low again to write the rest of the data word. Tim­ing parameters and functions are very similar to that outlined for
Figure 14a, but Figure 14b has a number of additional times to
show timing relationships when TFS returns high in the middle
of transferring a word.

Data to be loaded to the AD7712 must be valid prior to the
rising edge of the SCLK signal. TFS should return high during
the low time of SCLK. After TFS returns low again, the next bit
of the data word to be loaded to the AD7712 is clocked in on
next high level of the SCLK input. On the last active high time
of the SCLK input, the LSB is loaded to the AD7712.

t

33

t

34

t

27

LSB

2

Figure 14a. External Clocking Mode, Control/Calibration Register Write Operation

A0 (I)

t

32

TFS (I)

t

30

t

36

BIT N BIT N+1

t

35

SCLK (I)

SDATA (I)

MSB

t

26

t

t

35

27

Figure 14b. External Clocking Mode, Control/Calibration Register Write Operation (
Write Operation)

t

36

TFS

Returns High During

–23–REV. E

AD7712

NO

YES

BRING

RFS LOW

33

REVERSE

ORDER OF BITS

BRING

RFS HIGH

POLL DRDY

CONFIGURE &

INITIALIZE mC/mP

SERIAL PORT

DRDY

LOW?

BRING

RFS, TFS HIGH

READ

SERIAL BUFFER

START

SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE

In many applications, the user may not require the facility of
writing to the on-chip calibration registers. In this case, the
serial interface to the AD7712 in external clocking mode can be
simplified by connecting the TFS line to the A0 input of the
AD7712 (see Figure 15). This means that any write to the de­vice will load data to the control register (since A0 is low while
TFS is low) and any read to the device will access data from the
output data register or from the calibration registers (since A0 is
high while RFS is low). It should be noted that in this arrange­ment the user does not have the capability of reading from the
control register.

RFS

FOUR INTER-

FACE LINES

SDATA

SCLK

TFS

A0

AD7712

Figure 15. Simplified Interface with

TFS

Connected to A0

Another method of simplifying the interface is to generate the
TFS signal from an inverted RFS signal. However, generating
the signals the opposite way around (RFS from an inverted
TFS) will cause writing errors.

MICROCOMPUTER/MICROPROCESSOR INTERFACING

The AD7712’s flexible serial interface allows for easy interface
to most microcomputers and microprocessors. Figure 16 shows
a flowchart diagram for a typical programming sequence for
reading data from the AD7712 to a microcomputer while Figure
17 shows a flowchart diagram for writing data to the AD7712.
Figures 18, 19 and 20 show some typical interface circuits.

The flowchart of Figure 16 is for continuous read operations
from the AD7712 output register. In the example shown, the
DRDY line is continuously polled. Depending on the micropro­cessor configuration, the DRDY line may come to an interrupt
input in which case the DRDY will automatically generate an
interrupt without being polled. The reading of the serial buffer
could be anything from one read operation up to three read
operations (where 24 bits of data are read into an 8-bit serial
register). A read operation to the control/calibration registers is
similar, but in this case the status of DRDY can be ignored. The
A0 line is brought low when the RFS line is brought low when
reading from the control register.

The flowchart also shows the bits being reversed after they have
been read in from the serial port. This depends on whether the
microprocessor expects the MSB of the word first or the LSB of
the word first. The AD7712 outputs the MSB first.

Figure 16. Flowchart for Continuous Read Operations to

the AD7712

The flowchart for Figure 17 is for a single 24-bit write operation
to the AD7712 control or calibration registers. This shows data
being transferred from data memory to the accumulator before
being written to the serial buffer. Some microprocessor systems
will allow data to be written directly to the serial buffer from
data memory. The writing of data to the serial buffer from the
accumulator will generally consist of either two or three write
operations, depending on the size of the serial buffer.

The flowchart also shows the option of the bits being reversed
before being written to the serial buffer. This depends on
whether the first bit transmitted by the microprocessor is the
MSB or the LSB. The AD7712 expects the MSB as the first bit
in the data stream. In cases where the data is being read or
being written in bytes and the data has to be reversed, the bits
will have to be reversed for every byte.

–24–

REV. E

AD7712

START

CONFIGURE &

INITIALIZE mC/mP

SERIAL PORT

BRING

RFS, TFS & A0 HIGH

LOAD DATA FROM

ADDRESS TO

ACCUMULATOR

REVERSE

ORDER OF

BITS

BRING

TFS & A0 LOW

WRITE DATA FROM
ACCUMULATOR TO

SERIAL BUFFER

BRING

TFS & A0 HIGH

END

33

Figure 17. Flowchart for Single Write Operation to the
AD7712

AD7712 to 8051 Interface

Figure 18 shows an interface between the AD7712 and the
8XC51 microcontroller. The AD7712 is configured for its exter­nal clocking mode while the 8XC51 is configured in its Mode 0
serial interface mode. The DRDY line from the AD7712 is
connected to the Port P1.2 input of the 8XC51 so the DRDY
line is polled by the 8XC51. The DRDY line can be connected
to the INT1 input of the 8XC51 if an interrupt driven system is
preferred.

DV

DD

SYNC
RFS
TFS

DRDY

A0
SDATA

SCLK
MODE

AD7712

8XC51

P1.0
P1.1
P1.2
P1.3
P3.0
P3.1

Table VII shows some typical 8XC51 code used for a single
24-bit read from the output register of the AD7712. Table VIII
shows some typical code for a single write operation to the con­trol register of the AD7712. The 8XC51 outputs the LSB first
in a write operation while the AD7712 expects the MSB first, so
the data to be transmitted has to be rearranged before being
written to the output serial register. Similarly, the AD7712 out­puts the MSB first during a read operation while the 8XC51
expects the LSB first. Therefore, the data which is read into the
serial buffer needs to be rearranged before the correct data word
from the AD7712 is available in the accumulator.

Table VII. 8XC51 Code for Reading from the AD7712

MOV SCON,#00010001B; Configure 8051 for MODE 0

Operation

MOV IE,#00010000B; Disable All Interrupts
SETB 90H; Set P1.0, Used as RFS
SETB 91H; Set P1.1, Used as TFS
SETB 93H; Set P1.3, Used as A0
MOV R1,#003H; Sets Number of Bytes to Be Read in

A Read Operation

MOV R0,#030H; Start Address for Where Bytes Will

Be Loaded

MOV R6,#004H; Use P1.2 as DRDY
WAIT:
NOP;
MOV A,P1; Read Port 1
ANL A,R6; Mask Out All Bits Except DRDY
JZ READ; If Zero Read
SJMP WAIT; Otherwise Keep Polling
READ:
CLR 90H; Bring RFS Low
CLR 98H; Clear Receive Flag
POLL:
JB 98H, READ1 Tests Receive Interrupt Flag
SJMP POLL
READ 1:
MOV A,SBUF; Read Buffer
RLC A; Rearrange Data
MOV B.0,C; Reverse Order of Bits
RLC A; MOV B.1,C; RLC A; MOV B.2,C;
RLC A; MOV B.3,C; RLC A; MOV B.4,C;
RLC A; MOV B.5,C; RLC A; MOV B.6,C;
RLC A; MOV B.7,C;
MOV A,B;
MOV @R0,A; Write Data to Memory
INC R0; Increment Memory Location
DEC R1 Decrement Byte Counter
MOV A,R1
JZ END Jump if Zero
JMP WAIT Fetch Next Byte
END:
SETB 90H Bring RFS High
FIN:
SJMP FIN

2

Figure 18. AD7712 to 8XC51 Interface

–25–REV. E

AD7712

AD7712

SDATA

SCLK

A0

RFS

TFS

DR

SCLK

MODE

A0

DRDY

ADSP-2105

DT

DMWR

TFS

RFS

DV

DD

D

Q

Q

74HC74

Table VIII. 8XC51 Code for Writing to the AD7712

MOV SCON,#00000000B; Configure 8051 for MODE 0

Operation & Enable Serial Reception
MOV IE,#10010000B; Enable Transmit Interrupt
MOV IP,#00010000B; Prioritize the Transmit Interrupt
SETB 91H; Bring TFS High
SETB 90H; Bring RFS High
MOV R1,#003H; Sets Number of Bytes to Be Written

in a Write Operation
MOV R0,#030H; Start Address in RAM for Bytes
MOV A,#00H; Clear Accumulator
MOV SBUF,A; Initialize the Serial Port
WAIT:
JMP WAIT; Wait for Interrupt
INT ROUTINE:
NOP; Interrupt Subroutine
MOV A,R1; Load R1 to Accumulator
JZ FIN; If Zero Jump to FIN
DEC R1; Decrement R1 Byte Counter
MOV A,@R; Move Byte into the Accumulator
INC R0; Increment Address
RLC A; Rearrange Data—From LSB First

to MSB First
MOV B.0,C; RLC A; MOV B.1,C; RLC A;
MOV B.2,C; RLC A; MOV B.3,C; RLC A;
MOV B.4,C; RLC A; MOV B.5,C; RLC A;
MOV B.6,C; RLC A: MOV B.7,C; MOV A,B;
CLR 93H; Bring A0 Low
CLR 91H; Bring TFS Low
MOV SBUF,A; Write to Serial Port
RETI; Return from Subroutine
FIN:
SETB 91H; Set TFS High
SETB 93H; Set A0 High
RETI; Return from Interrupt Subroutine

DV

DD

SYNC

RFS

TFS
DRDY

A0

AD7712

SCLK
SDATA
MODE

68HC11

PC0

PC1
PC2
PC3

SCK
MISO
MOSI

SS

DV

DD

Figure 19. AD7712 to 68HC11 Interface

AD7712 to ADSP-2105 Interface

An interface circuit between the AD7712 and the ADSP-2105
microprocessor is shown in Figure 20. In this interface, the
AD7712 is configured for its self-clocking mode while the RFS
and TFS pins of the ADSP-2105 are configured as inputs and
the ADSP-2105 serial clock line is also configured as an input.
When the ADSP-2105’s serial clock is configured as an input it
needs a couple of clock pulses to initialize itself correctly before
accepting data. Therefore, the first read from the AD7712 may
not read correct data. In the interface shown, a read operation
to the AD7712 accesses either the output register or the calibra­tion registers. Data cannot be read from the control register. A
write operation always writes to the control or calibration
registers.

DRDY is used as the frame synchronization pulse for read op­erations from the output register and it is decoded with A0 to
drive the RFS inputs of both the AD7712 and the ADSP-2105.
The latched A0 line drives the TFS inputs of both the AD7712
and the ADSP-2105 as well as the AD7712 A0 input.

AD7712 to 68HC11 Interface

Figure 19 shows an interface between the AD7712 and the
68HC11 microcontroller. The AD7712 is configured for its
external clocking mode while the SPI port is used on the
68HC11 which is in its single chip mode. The DRDY line from
the AD7712 is connected to the Port PC0 input of the 68HC11
so the DRDY line is polled by the 68HC11. The DRDY line
can be connected to the IRQ input of the 68HC11 if an inter­rupt driven system is preferred. The 68HC11 MOSI and MISO
lines should be configured for wired-or operation. Depending
on the interface configuration, it may be necessary to provide
bidirectional buffers between the 68HC11’s MOSI and MISO
lines.

The 68HC11 is configured in the master mode with its CPOL
bit set to a logic zero and its CPHA bit set to a logic one. With a
10 MHz master clock on the AD7712, the interface will operate
with all four serial clock rates of the 68HC11.

–26–

Figure 20. AD7712 to ADSP-2105 Interface

REV. E

AD7712

APPLICATIONS
4–20 mA LOOP

The AD7712’s high level input can be used to measure the current
in 4–20 mA loop applications as shown in Figure 21. In this
case, the system calibration capabilities of the AD7712 can be
used to remove the offset caused by the 4 mA flowing through

4–20mA

LOOP

ANALOG +5V SUPPLY

AVDDDV

AV

AIN1(+)

AIN1(–)

AIN2

ATTENUATION

500V

AD7712

AGND

DD

DD

4.5mA

M

U
X

VOLTAGE

DGND

REF

IN (–)

PGA

A = 1 – 128

V

SS

REF

IN (+)

the 500 Ω resistor. The AD7712 can handle an input span as
low as 3.2 × V

(= 8 V with a V

REF

of +2.5 V) even though the

REF

nominal input voltage range for the input is 10 V. Therefore, the
full span of the A/D converter can be used for measuring the
current between 4 mA and 20 mA.

V

BIAS

CHARGE-BALANCING A/D

CONVERTER

AUTO-ZEROED

S–D

MODULATOR

SERIAL INTERFACE

CONTROL
REGISTER

MODE SDATA SCLK A0

TFSRFS

REF OUT

2.5V REFERENCE

DIGITAL

FILTER

CLOCK

GENERATION

OUTPUT

REGISTER

DRDY

SYNC

STANDBY

MCLK IN
MCLK OUT

2

Figure 21. 4–20 mA Loop Measurement Using the AD7712

–27–REV. E

AD7712

0.210
(5.33)

MAX

0.200 (5.05)

0.125 (3.18)

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Plastic DIP (N-24)

1.275 (32.30)

1.125 (28.60)

24

112

PIN 1

0.022 (0.558)

0.014 (0.356)

0.100 (2.54)
BSC

13

0.070 (1.77)

0.045 (1.15)

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

Cerdip (Q-24)

0.005 (0.13) MIN

24

1

PIN 1

0.023 (0.58)

0.014 (0.36)

1.280 (32.51) MAX

0.100 (2.54)
BSC

0.098 (2.49) MAX

13

0.310 (7.87)

0.220 (5.59)

12

0.060 (1.52)

0.015 (0.38)

0.070 (1.78)

0.030 (0.76)

0.150
(3.81)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.320 (8.13)

0.290 (7.37)

158

08

0.195 (4.95)

0.115 (2.93)

C1656d–0–7/98

0.015 (0.38)

0.008 (0.20)

24

0.0118 (0.30)

0.0040 (0.10)

1

PIN 1

0.6141 (15.60)

0.5985 (15.20)

0.0500
(1.27)

BSC

SOIC (R-24)

0.0192 (0.49)

0.0138 (0.35)

13

12

0.2992 (7.60)

0.1043 (2.65)

0.0926 (2.35)

SEATING
PLANE

0.2914 (7.40)

0.4193 (10.65)

0.3937 (10.00)

0.0125 (0.32)

0.0091 (0.23)

0.0291 (0.74)

0.0098 (0.25)

0.0500 (1.27)

88
08

0.0157 (0.40)

3 458

PRINTED IN U.S.A.

–28–

REV. E