Datasheet AD7709EB, AD7709ARU Datasheet (Analog Devices)

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

a

AD7709

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

16-Bit - ADC with

Switchable Current Sources

FUNCTIONAL BLOCK DIAGRAM

V

DD

IEXC1

8I

IEXC2

8I

IOUT1

IOUT2

IEXC3

I

OSCILLATOR

AND

PLL

XTAL2REFIN1(–) REFIN2(–)REFIN1(+) REFIN2(+) XTAL1

DOUT

RESET

RDY

CS

SCLK

DIN

SERIAL

INTERFACE

AND

CONTROL

LOGIC

BUF

PGA

MUX

I/O PORT

V

DD

16-BIT - ADC

AIN1

AIN2
AIN3/P3
AIN4/P4

AINCOM

AD7709

V

DD

GND

PWRGND

P1/SW1 P2/SW2

I = 25A

FEATURES
16-Bit - ADC
Programmable Gain Front End
Simultaneous 50 Hz and 60 Hz Rejection at 20 Hz

Update Rate

VREF Select

™ Allows Absolute and Ratiometric

Measurement Capability

ISOURCE Select

™
16-Bit No Missing Codes
13-Bit p-p Resolution @ 20 Hz, 20 mV Range
16-Bit p-p Resolution @ 20 Hz, 2.56 V Range

INTERFACE
3-Wire Serial
SPI™, QSPI™, MICROWIRE™ and DSP-Compatible
Schmitt Trigger on SCLK

POWER
Specified for Single 3 V and 5 V Operation
Normal: 1.25 mA Typ @ 3 V
Power-Down: 7 A (32.768 kHz Crystal Running)

ON-CHIP FUNCTIONS
Rail-to-Rail Input Buffer and PGA
Selectable Reference Inputs
Three Switchable, Ratioed Current Sources for V

BE

Measurements
4-Bit Digital I/O Port
Low-Side Power Switches

APPLICATIONS
Sensor Measurement
Temperature Measurement
Pressure Measurements
Weigh Scales
Portable Instrumentation
4 to 20 mA Loops

GENERAL DESCRIPTION

The AD7709 is a complete analog front end for low frequency
measurement applications. It contains a 16-bit ⌺-⌬ ADC, selectable
reference inputs, three switchable matched excitation current
sources, low-side power switches and a digital I/O port. The
16-bit channel with PGA accepts fully differential, unipolar,
and

bipolar input signal ranges from 1.024 ⫻ REFIN/128 to

1.024 ⫻ REFIN. It can be configured as two fully differential
input channels or four pseudo-differential input channels. Signals
can be converted directly from a transducer without the need for
signal conditioning.

The device operates from a 32.768 kHz crystal with an on-chip
PLL generating the required internal operating frequency. The
output data rate from the part is software programmable. The
p-p

resolution from the part varies with the programmed gain

and output data rate.

The part operates from a single 3 V or 5 V supply. When
operating from 3 V supplies, the power dissipation for the part
is 3.75 mW. The AD7709 is housed in a 24-lead TSSOP package.

ISOURCE Select and VREF Select are trademarks of Analog Devices, Inc.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

REV. 0

AD7709

–2–

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 6

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 8

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9

TYPICAL PERFORMANCE CHARACTERISTICS . . . . 10

ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . 11

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Σ-∆ ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

NOISE PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . 13

ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Communications Register . . . . . . . . . . . . . . . . . . . . . . . . 14

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ADC Data Result Register . . . . . . . . . . . . . . . . . . . . . . . . 18

CONFIGURING THE AD7709 . . . . . . . . . . . . . . . . . . . . . 19

DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MICROCOMPUTER/MICROPROCESSOR

INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

AD7709-to-68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 21

AD7709-to-8051 Interface . . . . . . . . . . . . . . . . . . . . . . . . 21

AD7709-to-ADSP-2103/ADSP-2105 Interface . . . . . . . . 21

CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 22

Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 23

Bipolar/Unipolar Configuration . . . . . . . . . . . . . . . . . . . . 23

Data Output Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . 26

3-Wire RTD Configurations . . . . . . . . . . . . . . . . . . . . . . 27

Smart Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 28

REV. 0

–3–

AD7709

SPECIFICATIONS

(VDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V; XTAL1/XTAL2 =

32.768 kHz Crystal; all specifications T

MIN

to T

MAX

, unless otherwise noted.)

Parameter AD7709A, B Unit Test Conditions

ADC CHANNEL SPECIFICATION

Output Update Rate 5.4 Hz min 0.732 ms Increments

105 Hz max

ADC CHANNEL

No Missing Codes

2

16 Bits min 20 Hz Update Rate

Resolution 13 Bits p-p ±20 mV Range, 20 Hz Update Rate

16 Bits p-p ±2.56 V Range, 20 Hz Update Rate

Output Noise and Update Rates See Tables II to V
Integral Nonlinearity

2

±30 ppm of FSR max Typically 2 ppm

FSR

REFIN

GAIN

=

×2 1 024.

Offset Error ±3 µV typ
Offset Error Drift vs. Temperature ±10 nV/°C typ
Full-Scale Error

3

±0.2 % of FS typ
Gain Drift vs. Temperature ±0.5 ppm/°C typ
Power Supply Rejection (PSR) 85 dB typ Input Range = ±2.56 V

100 dB typ on ±20 mV Range

ANALOG INPUTS

Differential Input Voltage Ranges

±×1 024. REFIN

GAIN

V nom REFIN = REFIN(+) – REFIN(–)

GAIN = 1 to 128

ADC Range Matching ±2 µV typ Input Voltage = 19 mV on All Ranges
Absolute AIN1–AIN4 Voltage Limits

2

GND + 100 mV V min

V

DD

– 100 mV V max

AIN1–AIN4 Analog Input Current

DC Input Current

2

±1 nA max

DC Input Current Drift ±5 pA /°C typ

Absolute AINCOM Voltage Limits

2

GND – 30 mV V min

V

DD

+ 30 mV V max

AINCOM Analog Input Current Pseudo-Differential Mode of Operation

DC Input Current ±125 nA/V typ Input Current Varies with Input Range
DC Input Current Drift ±2 pA/V/°C typ

Normal-Mode Rejection

2, 4

@ 50 Hz 100 dB min

50 Hz ± 1 Hz, 16.65 Hz Update Rate, SF = 82

@ 60 Hz 100 dB min 60 Hz ± 1 Hz, 20 Hz Update Rate, SF = 68

Common-Mode Rejection

@ DC 100 dB typ Input Range = ±2.56 V, AIN = 1 V

110 dB typ on ±20 mV Range

@ 50 Hz

2

100 dB min 50 Hz ± 1 Hz, Range = ± 2.56 V, AIN = 1 V

@ 60 Hz

2

100 dB min 60 Hz ± 1 Hz, Range = ± 2.56 V, AIN = 1 V

REFERENCE INPUTS
(REFIN1 and REFIN2)

REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–)
REFIN Voltage Range

2

1 V min

V

DD

V max

Absolute REFIN Voltage Limits

2

GND – 30 mV V min

V

DD

+ 30 mV V max

Average Reference Input Current 0.5 µA/V typ
Average Reference Input Current Drift ±0.01 nA/V/°C typ
Normal-Mode Rejection

2, 4

@ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF = 82
@ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF = 68

Common-Mode Rejection

@ DC 110 dB typ Input Range = ±2.56 V, AIN = 1 V
@ 50 Hz 110 dB typ 50 Hz ± 1 Hz, Range = 2.56 V, AIN = 1 V
@ 60 Hz 110 dB typ 60 Hz ± 1 Hz, Range = 2.56 V, AIN = 1 V

REV. 0

–4–

AD7709–SPECIFICATIONS

Parameter AD7709A, B Unit Test Conditions

EXCITATION CURRENT SOURCES

(IEXC1, IEXC2, and IEXC3)

Output Current

IEXC1, IEXC2 200 µA nom
IEXC3 25 µA nom

Initial Tolerance at 25°C ± 10 % typ
Drift 20 ppm/°C typ
Initial Current Matching at 25°C ±2.5 % max B Grade, No Load

(between IEXC1 and IEXC2) ±2.5 % typ A Grade, No Load

Drift Matching

(between IEXC1 and IEXC2) 20 ppm/°C typ

Initial Current Matching at 25°C ±5 % max B Grade, No Load

(between 8 ⫻ IEXC3 and
IEXC1/IEXC2) ± 5 % typ A Grade, No Load

Drift Matching

(between 8 ⫻ IEXC3 and
IEXC1/IEXC2) 20 ppm/°C typ

Line Regulation V

DD

= 5 V ± 5%

IEXC1, IEXC2 1.25 µA/V typ A, B Grades

2.6 µA/V max B Grade

IEXC3 1 µA/V max B Grade

1 µA/V typ A Grade

Load Regulation 300 nA/V typ
Output Compliance V

DD

– 0.6 V max

GND –30 mV V min

LOW-SIDE POWER SWITCHES

(SW1 and SW2)

R

ON

3 Ω typ VDD = 5 V, A and B Grade
5 Ω max B Grade

4.5 Ω typ VDD = 3 V, A and B Grade
7 Ω max B Grade

Allowable Current

2

20 mA max Continuous Current per Switch

LOGIC INPUTS

All Inputs Except SCLK and XTAL1

2

V

INL

, Input Low Voltage 0.8 V max VDD = 5 V

0.4 V max V

DD

= 3 V

V

INH

, Input High Voltage 2.0 V min VDD = 3 V or 5 V

SCLK Only (Schmitt-Triggered Input)

2

V

T(+)

1.4/2 V min/V max VDD = 5 V

V

T(–)

0.8/1.4 V min/V max VDD = 5 V

V

T(+)

– V

T(–)

0.3/0.85 V min/V max VDD = 5 V

V

T(+)

0.95/2 V min/V max VDD = 3 V

V

T(–)

0.4/1.1 V min/V max VDD = 3 V

V

T(+)

– V

T(–)

0.3/0.85 V min/V max VDD = 3 V

XTAL1 Only

2

V

INL

, Input Low Voltage 0.8 V max VDD = 5 V

V

INH

, Input High Voltage 3.5 V min VDD = 5 V

V

INL

, Input Low Voltage 0.4 V max VDD = 3 V

V

INH

, Input High Voltage 2.5 V min VDD = 3 V

Input Currents (except XTAL) ±2 µA max V

IN

= V

DD

–70 µA max VIN = GND, Typically –40 µA @ 5 V and

–20 µA at 3 V; Weak Pull-Ups on the
Logic Inputs

Input Capacitance 10 pF typ All Digital Inputs

LOGIC OUTPUTS (Excluding XTAL2)

V

OH

, Output High Voltage

2

VDD – 0.6 V min VDD = 3 V, I

SOURCE

= 100 µA

V

OL

, Output Low Voltage

2

0.4 V max VDD = 3 V, I

SINK

= 100 µA

V

OH

, Output High Voltage

2

4 V min VDD = 5 V, I

SOURCE

= 200 µA

V

OL

, Output Low Voltage

2

0.4 V max VDD = 5 V, I

SINK

= 1.6 mA

Floating-State Leakage Current ±10 µA max
Floating-State Output Capacitance ±10 pF typ
Data Output Coding Binary Unipolar Mode

Offset Binary Bipolar Mode

(continued)

REV. 0

Parameter AD7709A, B Unit Test Conditions

I/O PORT

V

INL

, Input Low Voltage

2

0.8 V max VDD = 5 V

0.4 V max V

DD

= 3 V

V

INH

, Input High Voltage

2

2.0 V min VDD = 3 V or 5 V

Input Currents ±2 µA max V

IN

= V

DD

–70 µA max VIN = GND, Typically –40 µA @ VDD = 5 V

and –20 µA at V

DD

= 3 V; Weak Pull-Ups on

the Logic Inputs
Input Capacitance 10 pF typ All Digital Inputs
V

OH

, Output High Voltage

2

VDD – 0.6 V min VDD = 3 V, I

SOURCE

= 100 µA

V

OL

, Output Low Voltage

2

0.4 V max VDD = 3 V, I

SINK

= 100 µA

V

OH

, Output High Voltage

2

4 V min VDD = 5 V, I

SOURCE

= 200 µA

V

OL

, Output Low Voltage

2

0.4 V max VDD = 5 V, I

SINK

= 1.6 mA

Floating-State Output Leakage Current ±10 µA max
Floating-State Output Capacitance ±10 pF typ

START-UP TIME

From Power-On 300 ms typ
From Standby Mode 1 ms typ OSCPD = 0
From Power-Down Mode 300 ms typ OSCPD = 1

POWER REQUIREMENTS

Power Supply Voltage

VDD – GND 2.7/3.6 V min/max VDD = 3 V nom

4.75/5.25 V min/max V

DD

= 5 V nom

Power Supply Currents

I

DD

Current 1.5 mA max VDD = 3 V, 1.25 mA typ

1.75 mA max V

DD

= 5 V, 1.45 mA typ

I

DD

(Low Power Mode) 7 µA max B Grade, VDD = 3 V, Standby Mode

7 µA typ A Grade, V

DD

= 3 V, Standby Mode

1.5 µA max B Grade, V

DD

= 3 V, Power-Down Mode

1.5 µA typ A Grade, V

DD

= 3 V, Power-Down Mode

26 µA max B Grade, V

DD

= 5 V, Standby Mode

26 µA typ A Grade, V

DD

= 5 V, Standby Mode

6.5 µA max B Grade, V

DD

= 5 V, Power-Down Mode

6.5 µA typ A Grade, V

DD

= 5 V, Power-Down Mode

I

DD

for One Conversion Second 107

5

µA typ VDD = 3 V, Standby Mode

134

5

µA typ VDD = 5 V, Standby Mode

NOTES

1

Temperature Range –40°C to +85°C.

2

Guaranteed by design and/or characterization data on production release.

3

Full-scale error applies to both positive and negative full scale.

4

Simultaneous 50 Hz and 60 Hz rejection is achieved using 19.79 Hz update rate. Normal mode rejection in this case is 60 dB min.

5

When the part is placed in power-down mode for a single conversion/second, at an update rate of 19.79 Hz, the current consumption is higher compared to when the
part is placed in standby mode as the crystal oscillator takes approximately 100 ms to begin clocking. The device will therefore use full current for the conversion
time and the 100 ms period required for the oscillator to begin clocking. However, if the conversion rate is lower, the current consumption will be reduced so that it
is worthwhile to use the power-down rather than the standby mode.

Specifications subject to change without notice.

AD7709

–5–

REV. 0

AD7709

–6–

TIMING CHARACTERISTICS

1, 2

Limit at T

MIN

, T

MAX

Parameter (A, B Version) Unit Conditions/Comments

t

1

30.5176

µs

typ Crystal Oscillator Period

t

2

50 ns min RESET Pulsewidth

Read Operation

t

3

0 ns min RDY to CS Setup Time

t

4

0 ns min CS Falling Edge to SCLK Active Edge Setup Time

3

t

5

4

0 ns min SCLK Active Edge to Data Valid Delay

3

60 ns max VDD = 4.75 V to 5.25 V
80 ns max V

DD

= 2.7 V to 3.6 V

t

5A

4, 5

0 ns min CS Falling Edge to Data Valid Delay
60 ns max V

DD

= 4.75 V to 5.25 V

80 ns max V

DD

= 2.7 V to 3.6 V

t

6

100 ns min SCLK High Pulsewidth

t

7

100 ns min SCLK Low Pulsewidth

t

8

0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time

3

t

9

6

10 ns min Bus Relinquish Time after SCLK Inactive Edge

3

80 ns max

t

10

100 ns max SCLK Active Edge to RDY High

3, 7

Write Operation

t

11

0 ns min CS Falling Edge to SCLK Active Edge Setup Time

3

t

12

30 ns min Data Valid to SCLK Edge Setup Time

t

13

25 ns min Data Valid to SCLK Edge Hold Time

t

14

100 ns min SCLK High Pulsewidth

t

15

100 ns min SCLK Low Pulsewidth

t

16

0 ns min CS Rising Edge to SCLK Edge Hold Time

NOTES

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

See Figures 2 and 3.

3

SCLK active edge is falling edge of SCLK.

4

These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V

OL

or VOH limits.

5

This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.

6

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo­lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the
part and as such are independent of external bus loading capacitances.

7

RDY returns high after a read of the ADC. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur
close to the next output update.

(VDD = 2.7 V to 3.6 V or VDD = 4.75 V to 5.25 V; GND = 0 V; X

TAL

= 32.768 kHz; Input Logic 0 = 0 V,

Logic 1 = VDD unless otherwise noted.)

REV. 0

AD7709

–7–

I

SINK

(1.6mA WITH VDD = 5V
100A WITH V

DD

= 3V)

1.6V

I

SOURCE

(200A WITH VDD = 5V

100A WITH V

DD

= 3V)

TO OUTPUT

PIN

50pF

Figure 1. Load Circuit for Timing Characterization

t

12

t

13

t

14

t

15

t

11

t

16

MSB

LSB

CS

SCLK

DIN

Figure 2. Write Cycle Timing Diagram

t

5

t

5A

t

4

t

6

t

3

t

9

MSB

LSB

CS

SCLK

t

8

t

10

t

7

DOUT

RDY

Figure 3. Read Cycle Timing Diagram

REV. 0

AD7709

–8–

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7709 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

1

AD7709

GND

V

DD

XTAL2

XTAL1

RDY

DOUT

DIN

RESET

SCLK

CS

P1/SW1

PWRGND

IOUT1

IOUT2

REFIN1(+)

REFIN1(–)

AIN1

AIN2

AIN3/P3

AIN4/P4

AINCOM

P2/SW2

REFIN2(+)

REFIN2(–)

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

PWRGND to AGND . . . . . . . . . . . . . . –20 mV to +20 mV

Analog Input Voltage to GND . . . . . –0.3 V to V

DD

+ 0.3 V

Reference Input Voltage to GND . . . –0.3 V to V

DD

+ 0.3 V

Total AIN/REFIN Current (Indefinite) . . . . . . . . . . 30 mA

Digital Input Voltage to GND . . . . . . . –0.3 V to V

DD

+ 0.3 V

Digital Output Voltage to GND . . . . –0.3 V to V

DD

+ 0.3 V

Operating Temperature Range . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

TSSOP Package

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . 97.9°C/W

θ

JC

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 14°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD7709ARU –40°C to +85°C TSSOP RU-24
AD7709BRU –40°C to +85°C TSSOP RU-24
EVAL-AD7709EB Evaluation Board

REV. 0

AD7709

–9–

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 IOUT1 Output for Internal Excitation Current Source. Either current source IEXC1, IEXC2, IEXC3 or a combina-

tion of the current sources can be switched to this output.

2 IOUT2 Output for Internal Excitation Current Source. Either current source IEXC1, IEXC2, IEXC3 or a combina-

tion of the current sources can be switched to this output.

3 REFIN1(+) Positive Reference Input. REFIN1(+) can lie anywhere between V

DD

and GND + 1 V. The nominal refer-

ence

voltage (REFIN1(+) – REFIN1(–)) is 2.5 V, but the part is functional with a reference range from 1 V to VDD.
4 REFIN1(–) Negative Reference Input. This reference input can lie anywhere between GND and VDD – 1 V.
5 AIN1 Analog Input. Programmable gain input which can be used as a pseudo-differential input when used with

AINCOM or as the positive input of a fully-differential input pair when used with AIN2.

6 AIN2 Analog Input. Programmable gain input which can be used as a pseudo-differential input when used with

AINCOM or as the negative input of a fully-differential input pair when used with AIN1.

7 AIN3/P3 Analog Input/Digital Port Bit. Programmable gain input which can be used as a pseudo-differential input

when used with AINCOM or as the positive input of a fully-differential input pair when used with AIN4.
This pin can also be programmed as a general purpose digital input bit.

8 AIN4/P4 Analog Input/Digital Port Bit. Programmable gain input which can be used as a pseudo-differential input

when used with AINCOM or as the negative input of a fully-differential input pair when used with AIN3.

This pin can also be programmed as a general purpose digital input bit.
9 AINCOM All analog inputs are referenced to this input when configured in pseudo-differential input mode.
10 REFIN2(+) Positive Reference Input. REFIN2(+) can lie anywhere between V

DD

and GND + 1 V. The nominal reference

voltage (REFIN2(+) – REFIN2(–)) is 2.5 V, but the part is functional with a reference range from 1 V to V

DD

.
11 REFIN2(–) Negative Reference Input. This reference input can lie anywhere between GND and VDD – 1 V.
12 P2/SW2 Dual-Purpose Pin. It can act as a general purpose output (P2) bit or as a low-side power switch (SW2) to

PWRGND.
13 PWRGND Ground Point for the Low-Side Power Switches SW2 and SW1. PWRGND must be tied to GND.
14 P1/SW1 Dual-Purpose Pin. It can act as a general-purpose output (P1) bit or as a low-side power switch (SW1) to

PWRGND.
15 RESET

Digital Input Used to Reset the ADC to Its Power-On-Reset Status. This pin has a weak pull-up internally to VDD.
16 SCLK Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt triggered input making

the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted

in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being

transmitted to or from the AD7709 in smaller batches of data. A weak pull-up to V

DD

is provided on the

SCLK input.
17 CS Chip Select Input. This is an active low logic input used to select the AD7709. CS can be used to select the

AD7709 in systems with more than one device on the serial bus or as a frame synchronization signal in com-

municating with the device. CS can be hardwired low allowing the AD7709 to operate in 3-wire mode with

SCLK, DIN and DOUT used to interface with the device. A weak pull-up to VDD is provided on the CS input.
18 RDY RDY is a Logic Low Status Output from the AD7709. RDY is low if the ADC has valid data in its data

register. This output returns high on completion of a read operation from the data register. If data is not

read, RDY will return high prior to the next update indicating to the user that a read operation should

not be initiated.
19 DOUT Serial Data Output Accessing the Output Shift Register of the AD7709. The output shift register can contain

data from any of the on-chip data or control registers.
20 DIN Serial Data Input Accessing the Input Shift Register on the AD7709. Data in this shift register is transferred to

the control registers within the ADC, the selection bits of the Communications register selecting which

control register. A weak pull-up to V

DD

is provided on the DIN input.
21 GND Ground Reference Point for the AD7709.
22 V

DD

Supply Voltage, 3 V or 5 V Nominal.
23 XTAL2 Output from the 32.768 kHz Crystal Oscillator Inverter.
24 XTAL1 Input to the 32.768 kHz Crystal Oscillator Inverter.

REV. 0

AD7709–Typical Performance Characteristics

–10–

200

3276732766 32768 3277032769

600

500

400

300

700

CODE

OCCURRENCE

32771

100

0

TPC 3. Noise Histogram

OSCILLATOR

VDD = 5V
T

A

= 25C

TIME BASE = 100ms/DIV
TRACE 1 = TRACE 2 = 2V/DIV

V

DD

TPC 4. Typical Oscillator Power-Up

32767

1000 200 400300

32771

32770

32769

32768

32772

READING NUMBER

CODE READ

500

32766

32765

32764

600 700 800 900 1000

VDD = 5V

INPUT RANGE = 20mV
UPDATE RATE = 19.79Hz

V

REF

= 2.5V

T

A

= 25 C

TPC 1. Typical Noise Plot on ±20 mV Input Range

2.5

0

1.0 3.02.52.01.5 3.5 5.04.54.0

2.0

1.5

1.0

0.5

3.0

V

REF

– Vo lt s

RMS NOISE – V

20mV RANGE

2.56V RANGE

VDD = 5V
V

REF

= 2.5V

INPUT RANGE = 2.56V
UPDATE RATE = 19.79Hz
T

A

= 25C

TPC 2. RMS Noise vs. Reference Input

REV. 0

AD7709

–11–

ADC CIRCUIT INFORMATION
Overview

The AD7709 incorporates a ⌺-⌬ ADC channel with on-chip digital
filtering intended for the measurement of wide dynamic range, low
frequency signals such as those in weigh-scale, strain-gauge,
pressure transducer, or temperature measurement applications.

ΣΣ

ΣΣ

Σ-

∆∆

∆∆

∆

ADC

This channel can be programmed to have one of eight input
voltage ranges from ±20 mV to ±2.56 V. This channel can be
configured as either two fully differential inputs (AIN1/AIN2
and AIN3/AIN4) or four pseudo-differential input channels
(AIN1/AINCOM, AIN2/AINCOM, AIN3/AINCOM and
AIN4/AINCOM). Buffering the input channel means that the
part can accommodate significant source impedances on the
analog input and that R, C filtering (for noise rejection or RFI
reduction) can be placed on the analog inputs if required.

The ADC employs a sigma-delta conversion technique to realize
up to 16 bits of no-missing-codes performance. The sigma-delta
modulator converts the sampled input signal into a digital pulse
train whose duty cycle contains the digital information. A Sinc

3

programmable low-pass filter is then employed to decimate the
modulator output data stream to give a valid data conversion
result at programmable output rates from 5.35 Hz (186.77 ms)
to 105.03 Hz (9.52 ms). A chopping scheme is also employed to
minimize ADC channel offset errors. A block diagram of the
ADC input channel is shown in Figure 4.

The sampling frequency of the modulator loop is many times
higher than the bandwidth of the input signal. The integrator in
the modulator shapes the quantization noise (which results from
the analog-to-digital conversion) so that the noise is pushed
toward one-half of the modulator frequency. The output of the
sigma-delta modulator feeds directly into the digital filter. The
digital filter then band-limits the response to a frequency signifi­cantly lower than one-half of the modulator frequency. In this
manner, the 1-bit output of the comparator is translated into a
bandlimited, low noise output from the AD7709 ADC. The
AD7709 filter is a low-pass, Sinc

3

or (SIN(x)/x)3 filter whose
primary function is to remove the quantization noise introduced
at the modulator. The cutoff frequency and decimated output
data rate of the filter are programmable via the SF word loaded
to the filter register.

A chopping scheme is employed where the complete signal chain
is chopped, resulting in excellent dc offset and offset drift speci­fications, and is extremely beneficial in applications where drift,
noise rejection, and optimum EMI rejection are important fac­tors. With chopping the ADC repeatedly reverses its inputs. The
decimated digital output words from the Sinc3 filters therefore
have a positive offset and negative offset term included. As a
result, a final summing stage is included so that each output
word from the filter is summed and averaged with the previous

filter output to produce a new valid output result to be written
to the ADC data register.

The input chopping is incorporated into the input multiplexer
while the output chopping is accomplished by an XOR gate at
the output of the modulator. The chopped modulator bit stream
is applied to a Sinc

3

filter. The programming of the Sinc3 deci­mation factor is restricted to an 8-bit register SF, the actual
decimation factor is the register value times 8. The decimated
output rate from the Sinc

3

filter (and the ADC conversion rate)

will therefore be:

f

SF

f

ADC MOD

=×

×











×

1
318

where

f

ADC

is the ADC update rate.

SF is the decimal equivalent of the word loaded to the
filter register.

f

MOD

is the modulator sampling rate of 32.768 kHz.

Programming the filter register determines the update rate for the
ADC. The chop rate of the channel is half the output data rate.

The frequency response of the filter H(f ) is as follows:

1

8

8

1
2

2

3

SF

SF f/ f

f/f

f/f

f/f

MOD

MOD

OUT

OUT

×

×

×××

×











×

×

××

×











sin ( )

sin ( )

sin ( )

sin ( )

π

π

π

π

where

f

MOD

= 32,768 Hz

SF = value programmed into Filter Register.

f

OUT

= f

MOD

/(SF ⫻ 8 ⫻ 3)

The following shows plots of the filter frequency response for the
SF words shown in Table I. The overall frequency response is the
product of a Sinc

3

and a sinc response. There are Sinc3 notches

at integer multiples of 3 ⫻ f

ADC

and there are sinc notches at odd

integer multiples of f

ADC

/2. The 3 dB frequency for all values of SF

obeys the following equation:

fdB f

ADC

3024

()

=×.

The signal chain is chopped as shown in Figure 4. The chop
frequency is:

f

f

CHOP

ADC

=











2

SINC3 FILTER

MUX

BUF

PGA

-

MOD

XOR

ANALOG

INPUT

DIGITAL
OUTPUT

1

8  SF



3

(

(8  SF )

3 



1
2

AIN + V

OS

AIN – V

OS

f

CHOP

f

IN

f

MOD

f

CHOP

f

ADC

)

Figure 4. ADC Channel Block Diagram

REV. 0

AD7709

–12–

As shown in the block diagram, the Sinc3 filter outputs alternately
contain +VOS and –VOS, where VOS is the respective channel offset.
This offset is removed by performing a running average of 2.
This average by 2 means that the settling time to any change in
programming of the ADC will be twice the normal conversion
time, while an asynchronous step change on the analog input
will not be fully reflected until the third subsequent output.

t

f

t

SETTLE

ADC

ADC

=











=×

2

2

The allowable range for SF is 13 to 255, with a default of 69
(45H). The corresponding conversion rates, conversion times
and settling times are tabulated in Table I. Note that the con­version time increases by 0.732 ms for each increment in SF.

FREQUENCY – Hz

0

–140

–200

0

650

50

100

150 200 250 300 350 400

450 500 550 600

700

ATTENUATION – dB

–20

–120

–160

–180

–60

–100

–40

–80

SF = 13
OUTPUT DATA RATE = 105Hz
INPUT BANDWIDTH = 25.2Hz
FIRST NOTCH = 52.5Hz
50Hz REJECTION = –23.6dB, 50Hz  1Hz REJECTION = –20.5dB
60Hz REJECTION = –14.6dB, 60Hz  1Hz REJECTION = –13.6dB

Figure 5. Filter Profile with SF = 13

FREQUENCY – Hz

0

–80

–160

0 10010

ATTENUATION – dB

20 30 40 50 60 70 80 90

–20

–40

–120

–140

–60

–100

SF = 82
OUTPUT DATA RATE = 16.65Hz
INPUT BANDWIDTH = 4Hz
50Hz REJECTION = –171dB, 50Hz  1Hz REJECTION = –100dB
60Hz REJECTION = –58dB, 60Hz  1Hz REJECTION = –53dB

Figure 6. Filter Profile with SF = 82

Table I. ADC Conversion and Settling Times for Various
SF Words

SF Data Update Rate Settling Time
Word f

ADC

(Hz) t

SETTLE

(ms)

13 105.3 19.04
69 (Default) 19.79 101.07
255 5.35 373.54

Normal-mode rejection is the major function of the digital filter
on the AD7709. The normal mode 50 ± 1 Hz rejection with an
SF word of 82 is typically –100 dB. The 60 ± 1 Hz rejection with
SF = 68 is typically –100 dB. Simultaneous 50 Hz and 60 Hz
rejection of better than 60 dB is achieved with an SF of 69.
Choosing an SF word of 69 places notches at both 50 Hz and
60 Hz. Figures 5 to 8 show the filter rejection for a selection
of SF words.

FREQUENCY – Hz

0

–80

–160

0 100

10

ATTENUATION – dB

20 30 40 50 60 70 80 90

–20

–40

–120

–140

–60

–100

SF = 69
OUTPUT DATA RATE = 19.8Hz
INPUT BANDWIDTH = 4.74Hz
FIRST NOTCH = 9.9Hz
50Hz REJECTION = –66dB, 50Hz  1Hz REJECTION = –60dB
60Hz REJECTION = –117dB, 60Hz  1Hz REJECTION = –94dB

Figure 7. Filter Profile with Default SF = 69 Giving Filter
Notches at Both 50 Hz and 60 Hz

FREQUENCY – Hz

0

–80

–160

0 10010

ATTENUATION – dB

20 30 40 50 60 70 80 90

–20

–40

–120

–140

–60

–100

SF = 255
OUTPUT DATA RATE = 5.35Hz
INPUT BANDWIDTH = 1.28Hz
50Hz REJECTION = –93dB, 50Hz  1Hz REJECTION = –93dB
60Hz REJECTION = –74dB, 60Hz  1Hz REJECTION = –68dB

Figure 8. Filter Profile with SF = 255

REV. 0

AD7709

–13–

NOISE PERFORMANCE

Tables II and III show the output rms noise and output peak-to­peak resolution in bits (rounded to the nearest 0.5 LSB) for a
selection of output update rates. The numbers are typical and
generated at a differential input voltage of 0 V. The output up­date rate is selected via the SF7–SF0 bits in the Filter Register.
It is important to note that the peak-to-peak resolution figures
represent the resolution for which there will be no code flicker
within a six-sigma limit. The output noise comes from two
sources. The first is the electrical noise in the semiconductor
devices (device noise) used in the implementation of the modula­tor. Secondly, when the analog input is converted into the digital
domain, quantization noise is added. The device noise is at a low

DIN

ADC STATUS REGISTER

(8 BITS)

CONFIGURATION REGISTER

(24 BITS)

FILTER REGISTER

(8 BITS)

ADC DATA REGISTER

(16 BITS)

REGISTER

SELECT

DECODER

DOUT

DOUT

DOUT

DOUT

DOUT

DIN

DIN

WEN

R/W STBY

OSCPD 0 0 A1 A0

Figure 9. On-Chip Registers

level and is independent of frequency. The quantization noise starts
at an even lower level but rises rapidly with increasing frequency
to become the dominant noise source.

The numbers in the tables

are given for the bipolar input ranges.

For the unipolar ranges

the rms noise numbers will be the same

as the bipolar range, but

the peak-to-peak resolution is now based

on half the signal range,

which effectively means losing 1 bit of resolution.

ON-CHIP REGISTERS

The AD7709 is controlled and configured via a number of on-chip
registers as shown in Figure 9 and described in more detail in the
following pages. In the following descriptions, Set implies a Logic 1
state and Cleared implies a Logic 0 state, unless otherwise stated.

Table II. Typical Output RMS Noise vs. Input Range and Update Rate for the AD7709. Output RMS Noise in V

SF Data Update

Input Range

Word Rate (Hz) 20 mV 40 mV 80 mV 160 mV 320 mV 640 mV 1.28 V 2.56 V

13 105.3 1.50 1.50 1.60 1.75 3.50 4.50 6.70 11.75
69 19.79 0.60 0.65 0.65 0.65 0.65 0.95 1.40 2.30
255 5.35 0.35 0.35 0.37 0.37 0.37 0.51 0.82 1.25

Table III. Peak-to-Peak Resolution vs. Input Range and Update Rate for the AD7709. Peak-to-Peak Resolution in Bits

SF Data Update

Input Range

Word Rate (Hz) 20 mV 40 mV 80 mV 160 mV 320 mV 640 mV 1.28 V 2.56 V

13 105.3 12 13 14 15 15 15.5 16 16
69 19.79 13 14 15 16 16 16 16 16
255 5.35 14 15 16 16 16 16 16 16

REV. 0

AD7709

–14–

Communications Register (A1, A0 = 0, 0)

The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the
Communications Register. The data written to the Communications Register determines whether the next operation is a read or
write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write
operation to the selected register is complete, the interface returns to where it expects a write operation to the Communications
Register. This is the default state of the interface, and on power-up or after a RESET, the AD7709 is in this default state waiting for
a write operation to the Communications Register. In situations where the interface sequence is lost, a write operation of at least 32
serial clock cycles with DIN high, returns the AD7709 to this default state by resetting the part. Table IV outlines the bit designations for
the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the Communications Register.
CR7 denotes the first bit of the data stream.

7RC6RC5RC4RC3RC2RC1RC0RC

NEW )0(

/R W )0()0(YBTS)0(DPCSO)0(RRE)0(0)0(1A)0(A

Table IV. Communications Register Bit Designations

Bit Bit
Location Name Description

CR7 WEN Write Enable Bit. A 0 must be written to this bit so the write operation to the Communications Register

actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register.
It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next
seven bits will be loaded to the Communications Register.

CR6 R/W A zero in this bit location indicates that the next operation will be a write to a specified register. A one in

this position indicates that the next operation will be a read from the designated register.

CR5 STBY Standby Bit Location

A one in this location places the AD7709 in low power mode.
A zero in this location powers up the AD7709.

CR4 OSCPD Oscillator Power-Down Bit

If this bit is set, placing the AD7709 in standby mode will stop the crystal oscillator also, reducing the
power consumed by the part to a minimum. The oscillator will require 300 ms to begin oscillating when
the ADC is taken out of power-down mode. If this bit is cleared, the oscillator is not stopped when the
ADC is placed in power-down mode. When the ADC is taken out of power-down mode, the oscillator
does not require the 300 ms start-up time.

CR3–CR2 0 These bits must be programmed with a logic 0 for correct operation.

CR1–CR0 A1–A0 Register Address Bits. These address bits are used to select which of the AD7709’s registers are being

accessed during this serial interface communication.

Table V. Register Selection Table

A1 A0 Register

0 0 Communications Register during a Write Operation
0 0 Status Register during a Read Operation
0 1 Configuration Register
1 0 Filter Register
1 1 ADC Data Register

REV. 0

AD7709

–15–

Status Register (A1, A0 = 0, 0; Power-On Reset = 00 Hex)

The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica­tions Register selecting the next operation to be a read and load bits A1–A0 with 0, 0. Table VI outlines the bit designations for the
Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit
of the data stream. The number in brackets indicates the power-on/reset default status of that bit.

Table VI. Status Register Bit Designations

Bit Bit
Location Name Description

SR7 RDY Ready Bit for ADC

Set when data is written to the ADC data register. The RDY bit is cleared automatically after the ADC data
register has been read or a period of time before the data register is updated with a new conversion result.

SR6 0 This bit is automatically cleared.

SR5 0 This bit is automatically cleared.

SR4 0 This bit is automatically cleared.

SR3 ERR ADC Error Bit. This bit is set at the same time as the RDY bit.

Set to indicate that the result written to the ADC data register has been clamped to all zeros or all ones.
Error sources include Overrange, Underrange. Cleared by a write to the mode bits to initiate a conversion.

SR2 0 This bit is automatically cleared.

SR1 STBY Standby Bit Indication

When this bit is set, the AD7709 is in power down mode. This bit is cleared when the ADC is powered up.

SR0 LOCK PLL Lock Status Bit

Set if the PLL has locked onto the 32.768 kHz crystal oscillator clock. If the user is worried about exact
sampling frequencies etc., the LOCK bit should be interrogated and the result discarded if the LOCK bit
is zero.

7RS6RS5RS4RS3RS2RS1RS0RS

)0(YDR)0(0)0(0)0(0)0(RRE)0(0)0(YBTS)0(KCOL

REV. 0

AD7709

–16–

Table VII. Configuration Register Bit Designations

Bit Bit
Location Name Description

CONFIG23 PSW2 Power Switch 2 Control Bit

Set by user to enable Power switch SW2/P2 to PWRGND. Cleared by user to enable use as a standard I/O pin.
When the ADC is in standby mode, the power switches are open.

CONFIG22 PSW1 Power Switch 1 Control Bit

Set by user to enable Power switch SW1/P1 to PWRGND. Cleared by user to enable use as a standard I/O pin.
When the ADC is in standby mode, the power switches are open.

CONFIG21 I3EN1 IEXC3 Current Source Enable Bit

CONFIG20 I3EN0 IEXC3 Current Source Enable Bit

CONFIG19 I2EN1 IEXC2 Current Source Enable Bit

CONFIG18 I2EN0 IEXC2 Current Source Enable Bit

CONFIG17 I1EN1 IEXC1 Current Source Enable Bit

Configuration Register (A1, A0 = 0, 1; Power-On-Reset = 000007 Hex)

The configuration register is a 24-bit register from which data can either be read or to which data can be written. This register is used
to select the input channel and configure the input range, excitation current sources and I/O port. Table VII outlines the bit designa­tions for this register. CONFIG23 through CONFIG0 indicate the bit location, CONFIG denoting the bits are in the configuration
register. CONFIG23 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of
that bit. A write to the configuration register has immediate effect and does not reset the ADC. Therefore, if a current source is
switched while the ADC is converting, the user will have to wait for the full settling time of the sinc

3

filter before obtaining a fully settled

output. This equates to three outputs.

I3EN1 I3EN0 Function

0 0 IEXC3 Current Source OFF
0 1 IEXC3 Current Source routed to the IOUT1 pin.
1 0 IEXC3 Current Source routed to the IOUT2 pin.
1 1 Reserved

I2EN1 I2EN0 Function

0 0 IEXC2 Current Source OFF
0 1 IEXC2 Current Source routed to the IOUT1 pin.
1 0 IEXC2 Current Source routed to the IOUT2 pin.
1 1 Reserved

7GIFNOC6GIFNOC5GIFNOC4GIFNOC3GIFNOC2GIFNOC1GIFNOC0GIFNOC

)0(LESFER)0(2HC)0(1HC)0(0HC)0(INU)1(2NR)1(1NR)1(0NR

51GIFNOC41GIFNOC31GIFNOC21GIFNOC11GIFNOC01GIFNOC9GIFNOC8GIFNOC

)0(GID4P)0(GID3P)0(NE2P)0(0NE1P)0(TAD4P)0(TAD3P)0(TAD2P)0(TAD1P

32GIFNOC22GIFNOC12GIFNOC02GIFNOC91GIFNOC81GIFNOC71GIFNOC61GIFNOC

)0(2WSP)0(1WSP)0(1NE3I)0(0NE3I)0(1NE2I)0(0NE2I)0(1NE1I)0(0NE1I

REV. 0

AD7709

–17–

Bit Bit
Location Name Description

CONFIG16 I1EN0 IEXC1 Current Source Enable Bit

CONFIG15 P4DIG Digital Input Enable Set by user to enable pin AIN4/P4 as a digital input. A weak pull-up resistor is

activated in this state. Cleared by user to configure pin AIN4/P4 as an analog input.

CONFIG14 P3DIG Digital Input Enable Set by user to enable pin AIN3/P3 as a digital input. A weak pull-up resistor is

activated in this state. Cleared by user to configure pin AIN3/P3 as an analog input.

CONFIG13 P2EN SW2/P2 Digital Output Enable Bit

Set by user to enable P2 as a regular digital output pin. Cleared by user to three-state the P2 output.
PSW2 takes precedence over P2EN.

CONFIG12 P1EN SW1/P1 Digital Output Enable Bit

Set by user to enable P1 as a regular digital output pin. Cleared by user to three-state the P1 output.
PSW1 takes precedence over P1EN.

CONFIG11 P4DAT Digital Input Port Data Bit

P4DAT is read only and will return a zero if P4DIG equals zero. If P4 is enabled as a digital input,
the readback value indicates the status of pin P4.

CONFIG10 P3DAT Digital Input Port Data Bit

P3DAT is read only and will return a zero if P3DIG equals zero. If P3 is enabled as a digital input,
the readback value indicates the status of pin P3.

CONFIG9 P2DAT Digital Output Port Data Bit

P2 is a digital output only. When the port is active as an output (P2EN = 1), the value written to this
data bit appears at the output port. Reading P2DAT will return the last value written to the P2DAT bit.

CONFIG8 P1DAT Digital Output Port Data Bit

P1 is a digital output only. When the port is active as an output (P1EN = 1), the value written to this
data bit appears at the output port. Reading P1DAT will return the last value written to the P1DAT bit.

CONFIG7 REFSEL ADC Reference Input Select

Cleared by the user to select REFIN1(+) and REFIN1(–) as the ADC reference.
Set by the user to select REFIN2(+) and REFIN2(–) as the ADC reference.

CONFIG6 CH2 ADC Input Channel Selection Bit. It is used in conjunction with CH1 and CH0 as shown below.

CONFIG5 CH1 ADC Input Channel Selection Bit. It is used in conjunction with CH2 and CH0 as shown below.

CONFIG4 CH0 ADC Input Channel Selection Bit. It is used in conjunction with CH2 and CH1 as shown below.

The Buffer column indicates if the analog inputs are buffered or unbuffered. This determines the common-mode input range
on each input. If the input is unbuffered (AINCOM), the common-mode input includes ground.

I1EN1 I1EN0 Function

0 0 IEXC1 Current Source OFF
0 1 IEXC1 Current Source routed to the IOUT1 pin.
1 0 IEXC1 Current Source routed to the IOUT2 pin.
1 1 Reserved

Table VII. Configuration Register Bit Designations (continued)

CH2 CH1 CH0 Positive Input Negative Input Buffer

0 0 0 AIN1 AINCOM Positive Analog Input
0 0 1 AIN2 AINCOM Positive Analog Input
0 1 0 AIN3 AINCOM Positive Analog Input
0 1 1 AIN4 AINCOM Positive Analog Input
1 0 0 AIN1 AIN2 Positive and Negative Analog Inputs
1 0 1 AIN3 AIN4 Positive and Negative Analog Inputs
1 1 0 AINCOM AINCOM None
1 1 1 AIN2 AIN2 Positive and Negative Analog Inputs

REV. 0

AD7709

–18–

Table VIII. Filter Register Bit Designations

Table IX. Update Rate vs. SF WORD

SF (dec) SF (Hex) f

ADC

(Hz) t

ADC

(ms)

13 0D 105.3 9.52
69 45 19.79 50.34
255 FF 5.35 186.77

RN2 RN1 RN0 Selected ADC Input Range (VREF = 2.5 V)

00 0 ± 20 mV
00 1 ± 40 mV
01 0 ± 80 mV
01 1 ± 160 mV
10 0 ± 320 mV
10 1 ± 640 mV
11 0 ± 1.28 V
11 1 ± 2.56 V

Table VII. Configuration Register Bit Designations (continued)

Bit Bit
Location Name Description

CONFIG3 UNI Unipolar/Bipolar Operation Selection Bit Set by the user to enable unipolar operation. In this mode,

the device uses straight binary output coding i.e., zero differential input will generate a result of
0000h and a fullscale differential input will generate a code of FFFFh. Cleared by the user to enable
pseudo-bipolar operation. The device uses offset binary coding i.e. a negative fullscale differential
input will result in a code of 0000h, a zero differential input will generate a code of 8000h while a
positive fullscale differential input will result in a code of FFFFh.

CONFIG2 RN2 This bit is used in conjunction with RN1 and RN0 to select the analog input range as shown below.

CONFIG1 RN1 This bit is used in conjunction with RN2 and RN0 to select the analog input range as shown below.

CONFIG0 RN0 This bit is used in conjunction with RN2 and RN1 to select the analog input range as shown below.

Filter Register (A1, A0 = 1, 0; Power-On Reset = 45 Hex)

The Filter Register is an 8-bit register from which data can be
read or to which data can be written. This register determines
the amount of averaging performed by the sinc filter. Table VIII
outlines the bit designations for the Filter Register. FR7 through
FR0 indicate the bit location, FR denoting the bits are in the
Filter Register. FR7 denotes the first bit of the data stream. The
number in brackets indicates the power-on/reset default status
of that bit. The number in this register is used to set the decima­tion factor and thus the output update rate for the ADC. The
filter register cannot be written to by the user while the ADC is
active. The update rate is calculated as follows:

f

SF

f

ADC MOD

=×

×

×

1
318

where

f

ADC

= ADC Output Update Rate.

f

MOD

= Modulator Clock Frequency = 32.768 kHz.

SF = Decimal Value Written to SF Register.

7RF6RF5RF4RF3RF2RF1RF0RF

)0(7FS)1(6FS)0(5FS)0(4FS)0(3FS)0(2FS)0(1FS)0(0FS

The allowable range for SF is 13dec to 255dec. Examples of SF
values and corresponding conversion rate (f

ADC

) and time (t

ADC

)
are shown in Table IX. It should also be noted that the ADC
input channel is chopped to minimize offset errors. This means
that the time for a single conversion or the time to the first con­version result is 2 ⫻ t

ADC

.

ADC Data Result Register (A1, A0 = 1, 1; Power-On Reset =
0000 Hex)

The conversion result is stored in the ADC data register (DATA).
This register is 16-bits wide. This is a read only register. On
completion of a read from this register, the RDY bit in the
status register is cleared.

REV. 0

AD7709

–19–

CONFIGURING THE AD7709

The four user-accessible registers on the AD7709 are accessed
via the serial interface. Communication with any of these
registers is initiated by first writing to the Communications
Register. The AD7709 begins converting on power up without
the need to write to

the registers. The default conditions are used
i.e., the AD7709 operates at a 19.79 Hz update rate which offers
50 Hz and 60 Hz rejection.

Figure 10 outlines a flow diagram of the sequence used to con­figure all registers after a power-up or reset on the AD7709.
The flowchart shows two methods of determining when it is
valid to read the data register. The first method is hardware
polling of the RDY pin and the second method involves software
interrogation of the RDY bit in the status register. The flowchart
details all the necessary programming steps required to initialize
the ADC and read data from the ADC channel following a
power-on or reset. The steps can be broken down as follows:

1. Configure and initialize the microcontroller or microproces-

sor serial port.

2. Initialize the AD7709 by configuring the following registers:

a)

Filter Register to configure the update rate for the channel.

The AD7709 must be placed in standby mode before the
Filter Register can be written to.

b)Configuration Register to select the input channel to be

converted, its input range and reference. This register is also
used to configure internal current sources, power switches
and I/O port.

Both of these operations consist of a write to the communi­cations register to specify the next operation as a write to a
specified register. Data is then written to this register. When
each sequence is complete, the ADC defaults to waiting for
another write to the communications register to specify the
next operation.

3. When configuration is complete, the user needs to determine
when it is valid to read the data from the data register. This is
accomplished either by polling the RDY pin (hardware polling)
or by interrogating the RDY bit in the STATUS register
(software

polling). Both are shown in Figure 10.

POLL RDY PIN

HARDWARE

POLLING

START

SOFTWARE

POLLING

POWER-ON/RESET FOR AD7709

CONFIGURE AND INITIALIZE C/P SERIAL PORT

WRITE TO COMMUNICATIONS REGISTER SETTING

UP NEXT OPERATION TO BE A WRITE TO THE
FILTER REGISTER (WRITE 22H TO REGISTER)

WRITE TO FILTER REGISTER CONFIRMING

THE REQUIRED UPDATE RATE

WRITE TO COMMUNICATIONS REGISTER SETTING

UP NEXT OPERATION TO BE A WRITE TO THE

CONFIGURATION REGISTER

(WRITE 01H TO REGISTER)

READ DATA FROM OUTPUT REGISTER

WRITE TO COMMUNICATIONS REGISTER SETTING

UP NEXT OPERATION TO BE A READ FROM THE

STATUS REGISTER (WRITE 40H TO REGISTER)

WRITE TO COMMUNICATIONS REGISTER SETTING

UP NEXT OPERATION TO BE A READ FROM THE

DATA REGISTER (WRITE 43H TO REGISTER)

WRITE TO COMMUNICATIONS REGISTER SETTING

UP NEXT OPERATION TO BE A READ FROM THE

DATA REGISTER (WRITE 43H TO REGISTER)

READ 16-BIT DATA RESULT

READ 16-BIT DATA RESULT

READ STATUS REGISTER

ANOTHER

READ

RDY

LOW?

ANOTHER

READ

CHANNEL

CHANGE

RDY = 1

END

END

SOFTWARE

POLLING

HARDWARE

POLLING

NO

YES

YES

YES

NO

YES

NO

YES

NO

YES

NO

WRITE TO CONFIGURATION REGISTER TO SELECT

THE INPUT CHANNEL, INPUT RANGE, AND

REFERENCE. CURRENT SOURCES AND I/O PORT

CAN ALSO BE CONFIGURED

CHANNEL

CHANGE

Figure 10. Flowchart for Initializing and Reading Data from the AD7709

REV. 0

AD7709

–20–

DIGITAL INTERFACE

As previously outlined, the AD7709’s programmable functions
are controlled using a set of on-chip registers. Data is written to
these registers via the part’s serial interface and read access to
the on-chip registers is also provided by this interface. All com­munications to the part must start with a write operation to the
Communications Register. After power-on or

RESET

, the device
expects a write to its Communications Register. The data writ­ten to this register determines whether the next operation to the
part is a read or a write operation and also determines to which
register this read or write operation occurs. Therefore, write
access to any of the other registers on the part starts with a write
operation to the Communications Register followed by a write
to the selected register. A read operation from any other register
on the part (including the output data register) starts with a
write operation to the Communications Register followed by a
read operation from the selected register.

The AD7709’s serial interface consists of five signals, CS, SCLK,
DIN, DOUT, and RDY. The DIN line is used for transferring
data into the on-chip registers while the DOUT line is used for
accessing data from the on-chip registers. SCLK is the serial
clock input for the device and all data transfers (either on DIN
or DOUT) take place with respect to this SCLK signal. The
RDY line is used as a status signal to indicate when data is ready
to be read from the AD7709’s data register. RDY goes low when a
new data word is available in the output register. It is reset high
when a read operation from the data register is complete. It also
goes high prior to the updating

of the output register to indicate

when not to read from the device

to ensure that a data read is not

attempted while the register is being updated. CS is used to
select the device. It can be used to decode the AD7709 in sys­tems where a number of parts are connected to the serial bus.

Figures 2 and 3 show timing diagrams for interfacing to the
AD7709 with CS used to decode the part. Figure 3 is for a read
operation from the AD7709’s output shift register while Figure
2 shows a write operation to the input shift register. It is possible
to read the same data twice from the output register even though
the RDY line returns high after the first read operation. Care must
be taken, however, to ensure that the read operations have been
completed before the next output update is about to take place.

The AD7709 serial interface can operate in 3-wire mode by
tying the CS input low. In this case, the SCLK, DIN, and
DOUT lines are used to communicate with the AD7709 and the
status of the RDY bit can be obtained by interrogating the
STATUS Register. This scheme is suitable for interfacing to
microcontrollers. If CS is required as a decoding signal, it can
be generated from a port bit. For microcontroller interfaces, it is
recommended that the SCLK idles high between data transfers.

The AD7709 can also be operated with CS used as a frame
synchronization signal. This scheme is suitable for DSP inter­faces. In this case, the first bit (MSB) is effectively clocked out
by CS since CS would normally occur after the falling edge of
SCLK in DSPs. The SCLK can continue to run between data
transfers provided the timing numbers are obeyed.

The serial interface can be reset by exercising the RESET input
on the part. It can also be reset by writing a series of 1s on the
DIN input. If a Logic 1 is written to the AD7709 DIN line for
at least 32 serial clock cycles the serial interface is reset. This
ensures that in 3-wire systems, if the interface gets lost either via
a software error or by some glitch in the system, it can be reset
back to a known state. This state returns the interface to where
the AD7709 is expecting a write operation to its Communica­tions Register. This operation resets the contents of all registers to
their power-on reset values.

Some microprocessor or microcontroller serial interfaces have a
single serial data line. In this case, it is possible to connect the
AD7709’s DOUT and DIN lines together and connect them to the
single data line of the processor. A 10 kΩ pull-up resistor should
be used on this single data line. In this case, if the interface gets
lost, because the read and write operations share the same line
the procedure to reset it back to a known state is somewhat
different than previously described. It requires a read operation
of 24 serial clocks followed by a write operation where a Logic 1
is written for at least 32 serial clock cycles to ensure that the
serial interface is back into a known state.

MICROCOMPUTER/MICROPROCESSOR INTERFACING

The AD7709’s flexible serial interface allows for easy interface to
most microcomputers and microprocessors. The flowchart of Figure
10 outlines the sequence that should be followed when interfacing
a microcontroller or microprocessor to the AD7709. Figures 11,
12, and 13 show some typical interface circuits. The serial interface
on the AD7709 is capable of operating from just three wires and is
compatible with SPI interface protocols. The 3-wire operation makes
the part ideal for isolated systems where minimizing the number of
interface lines minimizes the number of opto-isolators required in
the system. The serial clock input is a Schmitt-triggered input to
accommodate slow edges from optocouplers. The rise and fall times
of other digital inputs to the AD7709 should be no longer than 1 µs.

Some of the registers on the AD7709 are 8-bit registers, which
facilitates easy interfacing to the 8-bit serial ports of microcontrollers.
The Data Register on the AD7709 is 16 bits and the CONFIG
register is 24-bits, but data transfers to these registers can consist of
multiple 8-bit transfers to the serial port of the microcontroller. DSP
processors and microprocessors generally transfer 16 bits of data in a
serial data operation. Some of these processors, such as the ADSP-2105,
have the facility to program the amount of cycles in a serial transfer.
This allows the user to tailor the number of bits in any transfer to
match the register length of the required register in the AD7709.

Even though some of the registers on the AD7709 are only eight
bits in length, communicating with two of these registers in
successive write operations can be handled as a single 16-bit
data transfer if required. For example, if the Filter Register is to
be updated, the processor must first write to the Communications
Register (saying that the next operation is a write to the Filter
Register) and then write eight bits to the Filter Register. If
required, this can all be done in a single 16-bit transfer because
once the eight serial clocks of the write operation to the Commu­nications Register have been completed, the part immediately
sets itself up for a write operation to the Filter Register.

REV. 0

AD7709

–21–

AD7709-to-68HC11 Interface

Figure 11 shows an interface between the AD7709 and the 68HC11
microcontroller. The diagram shows the minimum (3-wire) inter­face with CS on the AD7709 hard-wired low. In this scheme,
the RDY bit of the Status Register is monitored to determine
when the Data Register is updated. An alternative scheme, which
increases the number of interface lines to four, is to monitor
the RDY output line from the AD7709. The monitoring of the
RDY line can be done in two ways. First, RDY can be connected
to one of the 68HC11’s port bits (such as PC0), which is con­figured as an input. This port bit is then polled to determine
the status of RDY. The second scheme is to use an interrupt
driven system, in which case the RDY output is connected to the
IRQ input of the 68HC11. For interfaces that require control of the
CS input on the AD7709, one of the port bits of the 68HC11
(such as PC1), which is configured as an output, can be used to
drive the CS input.

The 68HC11 is configured in the master mode with its CPOL
bit set to a Logic 1 and its CPHA bit set to a Logic 1. When the
68HC11 is configured like this, its SCLK line idles high between
data transfers. The AD7709 is not capable of full duplex opera­tion. If the AD7709 is configured for a write operation, no data appears
on the DOUT lines even when the SCLK input is active. Simi­larly, if the AD7709 is configured for a read operation, data
presented to the part on the DIN line is ignored even when
SCLK is active.

68HC11

V

DD

AD7709

SS

SCK

MISO

MOSI

RESET

DOUT

DIN

CS

SCLK

V

DD

Figure 11. AD7709-to-68HC11 Interface

AD7709-to-8051 Interface

An interface circuit between the AD7709 and the 8XC51 microcon­troller is shown in Figure 12. The diagram shows the minimum
number of interface connections with CS on the AD7709 hard­wired low. In the case of the 8XC51 interface, the minimum
number of interconnects is just two. In this scheme, the RDY
bit of the Status Register is monitored to determine when the
Data Register is updated. The alternative scheme, which increases
the number of interface lines to three, is to monitor the RDY output
line from the AD7709. The monitoring of the RDY line can be
done in two ways. First, RDY can be connected to one of the
8XC51’s port bits (such as P1.0) which is configured as an input.
This port bit is then polled to determine the status of RDY.

8XC51

V

DD

AD7709

P3.0

P3.1

RESET

DIN

SCLK

CS

DOUT

V

DD

10k

Figure 12. AD7709-to-8XC51 Interface

The second scheme is to use an interrupt-driven system, in which
case the RDY output is connected to the INT1 input of the
8XC51. For interfaces that require control of the CS input on
the AD7709, one of the port bits of the 8XC51 (such as P1.1),
which is configured as an output, can be used to drive the CS
input. The 8XC51 is configured in its Mode 0 serial interface
mode. Its serial interface contains a single data line. As a result,
the DOUT and DIN pins of the AD7709 should be connected
together with a 10 kΩ pull-up resistor. The serial clock on the
8XC51 idles high between data transfers. The 8XC51 outputs
the LSB first in a write operation, while the AD7709 expects the
MSB first so the data to be transmitted has to be rearranged
before being written to the output serial register. Similarly, the
AD7709 outputs the MSB first during a read operation while
the 8XC51 expects the LSB first. Therefore, the data read into
the serial buffer needs to be rearranged before the correct data
word from the AD7709 is available in the accumulator.

ADSP-2103/
ADSP-2105

V

DD

AD7709

RFS

SCLK

RESET

DOUT

DIN

SCLK

CS

TFS

DR

DT

Figure 13. AD7709-to-ADSP-2103/ADSP-2105 Interface

AD7709-to-ADSP-2103/ADSP-2105 Interface

Figure 13 shows an interface between the AD7709 and the
ADSP-2103/ADSP-2105 DSP processor. In the interface shown,
the RDY bit of the Status Register is again monitored to
determine when the Data Register is updated. The alternative
scheme is to use an interrupt-driven system, in which case the

REV. 0

AD7709

–22–

RDY output is connected to the IRQ2 input of the ADSP-2103/
ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105
is set up for alternate framing mode. The RFS and TFS pins
of the ADSP-2103/ADSP-2105 are configured as active low
outputs and the ADSP-2103/ADSP-2105 serial clock line, SCLK,
is also configured as an output. The CS for the AD7709 is active
when either the RFS or TFS outputs from the ADSP-2103/
ADSP-2105 are active. The serial clock rate on the ADSP-2103/
ADSP-2105 should be limited to 3 MHz to ensure correct opera­tion with the AD7709.

CIRCUIT DESCRIPTION

The AD7709 is a

⌺-⌬

A/D converter with on-chip digital filter­ing, intended for the measurement of wide dynamic range, low
frequency signals such as those in weigh scale, pressure, tempera­ture, industrial control or process control applications. It employs
a sigma-delta conversion technique to realize up to 16 bits of
no-missing-codes performance. The sigma-delta modulator
converts the sampled input signal into a digital pulse train whose
duty cycle contains the digital information. A Sinc

3

programmable
low-pass filter is then employed to decimate the modulator output
data stream to give a valid data conversion result at program­mable output rates from 5.35 Hz (186.77 ms) to 105.03 Hz
(9.52 ms). A Chopping scheme is also employed to minimize
ADC offset and offset and gain drift errors. The

channel is

buffered and can be programmed for one of eight input

ranges

from ±20 mV to ±2.56 V. The input channels can be configured
for either fully differential inputs or pseudo-differential input
channels via the CH2, CH1, and CH0 bits in the Configu

ration

register. Buffering the input channel allows the part to handle

sig­nificant source impedances on the analog input, allowing
R/C filtering (for noise rejection or RFI reduction) to be placed
on the analog inputs if required. These input channels are intended
for converting signals directly from sensors without the need for
external signal conditioning. Other functions contained on-chip
that augment the operation of the ADC include software config­urable

current sources, switchable reference inputs and low side

power switches.

The basic connection diagram for the AD7709 is shown in
Figure 14. An AD780/REF195, precision 2.5 V reference, provides
the reference source for the part. A quartz crystal or ceramic
resonator provides the 32.768 kHz master clock source for the
part. In some cases, it will be necessary to connect capacitors on
the crystal or resonator to ensure that it does not oscillate at overtones
of its fundamental operating frequency. The values of capacitors
will vary depending on the manufacturer’s specifications.

Analog Input Channels

The main ADC has five associated analog input pins (labeled
AIN1 to AIN4 and AINCOM) which can be configured as two
fully differential input channels (AIN1-AIN2 and AIN3-AIN4)
or four pseudo-differential input channels (AIN1-AINCOM,
AIN2-AINCOM, AIN3-AINCOM, and AIN4-AINCOM).
Channel selection bits CH2, CHI, and CH0 in the Configura­tion

Register detail the different configurations. When the analog
input channel is switched, the settling time of the part must
elapse before a new valid word is available from the ADC.

IOUT1

AIN3/P3

AINCOM

AIN1

IOUT2

AIN4/P4

REFIN1(–)

AIN2

REFIN1(+)

REFIN2(–)

REFIN2(+)

RESET

CS

DOUT

DIN

SCLK

P2/SW2

P1/SW1

XTAL1

XTAL2

5V

CHIP
SELECT

RECEIVE
(READ)

SERIAL
CLOCK

32.768kHz
CRYSTAL

PWRGND

GND

AD780/

REF195

VINV

OUT

GND

V

DD

ANALOG 5V

SUPPLY

0.1F

10F

0.1F

10F

ANALOG 5V

SUPPLY

AD7709

SERIAL DATA
(WRITE)

Figure 14. Basic Connection Diagram

The output of the ADC multiplexer feeds into a high-impedance
input stage of the buffer amplifier. As a result, the ADC inputs can
handle significant source impedances and are tailored for direct
connection to external resistive-type sensors like strain gauges or
Resistance Temperature Detectors (RTDs).

The absolute input voltage range on the ADC inputs when buff­ered (AIN1 to AIN4) is restricted to a range between GND +
100 mV and V

DD

– 100 mV. Care must be taken in setting up
the common-mode voltage and input voltage range so that these
limits are not exceeded; otherwise there will be a degradation in
linearity and noise performance.

The absolute input voltage range on the ADC inputs when
unbuffered (AINCOM) includes the range between GND – 30 mV
to VDD + 30 mV as a result of being unbuffered. The negative
absolute input voltage limit does allow the possibility of monitoring
small true bipolar signals with respect to GND.

REV. 0

AD7709

–23–

Programmable Gain Amplifier

The output from the buffer on the ADC is applied to the input
of the on-chip programmable gain amplifier (PGA). The PGA
can be programmed through eight different unipolar and bipolar
ranges. The PGA gain range is programmed via the range bits
in the Configuration register. With an external 2.5 V reference
applied the unipolar ranges are 0 mV to 20 mV, 0 mV to 40 mV,
0 mV

to 80 mV, 0 mV to 160 mV, 0 mV to 320

mV

, 0 mV to

640 mV, 0 V

to 1.28 V and 0 to 2.56 V while bipolar ranges are

±20 mV,

±40 mV, ±80 mV, ±160 mV, ± 320 mV, ± 640 mV,

±1.28 V and

±2.56 V.

These are the ranges that should appear at

the input to the on-chip PGA.

Typical matching across ranges is shown in Figure 15. Here, the
ADC is configured in fully-differential, bipolar mode with an
external 2.5 V reference, while an analog input voltage of just
greater than 19 mV is forced on its analog inputs. The ADC
continuously converts the dc voltage at an update rate of 5.35 Hz,
i.e., SF = FF Hex. 800 conversion results in total are gathered.
The first 100 results gathered with the ADC operating in the
±20 mV. The ADC range is then switched to ±40 mV and 100
more results are gathered, and so on until the last 100 samples
are gathered with the ADC configured in the ±2.5 V range. From
Figure 15, the variation in the sample mean through each range,
i.e., the range matching, is seen to be on the order of 2 µV.

0 100 200 300 400 500 600 700 800

SAMPLE COUNT

ADC INPUT VOLTAGE – mV

19.372

19.371

19.370

19.369

19.368

19.367

19.366

19.365

19.364

ADC RANGE

20mV

40mV

80mV

160mV

320mV

640mV

1.28V

2.56V

Figure 15. ADC Range Matching

Bipolar/Unipolar Configuration

The analog inputs on the AD7709 can accept either unipolar or
bipolar input voltage ranges. Bipolar input ranges does not imply
that the part can handle negative voltages with respect to system
GND. Unipolar and bipolar signals on the AIN(+) input on
the

ADC are referenced to the voltage on the respective AIN(–)
input. AIN(+) and AIN(–) refer to the signals seen by the
modulator that come from the output of the multiplexer as shown
in Figures 16 and 17.

FULLY-DIFFERENTIAL

FULLY-DIFFERENTIAL

AIN(+)

AIN(–)

AIN1

AIN2

AIN3

AIN4

AIN1

AIN2

AIN3

AIN4

MUX

ADC CHANNEL

Figure 16. Fully-Differential Mode of Operation

AIN3AIN3

AIN4AIN4

AIN1/AINCOM

PSEUDO-DIFFERENTIAL

INPUT

AIN(–)

AIN(+)

AIN1

AIN1

AIN2

AIN2

AINCOM

AINCOM

ADC CHANNEL

MUX

AIN2/AINCOM

AIN3/AINCOM

AIN4/AINCOM

PSEUDO-DIFFERENTIAL

INPUT

Figure 17. Pseudo-Differential Mode of Operation

For example, if AIN(–) is 2.5 V and the ADC is configured for
an analog input range of 0 mV to 20 mV, the input voltage range
on the AIN(+) input is 2.5 V to 2.52 V. If AIN(–) is 2.5 V and
the AD7709 is configured for an analog input range of ±1.28 V,
the analog input range on the AIN(+) input is 1.22 V to 3.78 V
(i.e., 2.5 V ±1.28 V). Bipolar or unipolar options are chosen by
programming the UNI bit in the Configuration register. This
programs the ADC for either unipolar or bipolar operation.
Programming for either unipolar or bipolar operation does not
change any of the input signal conditioning; it simply changes
the data output coding.

Data Output Coding

When the ADC is configured for unipolar operation, the output
coding is natural (straight) binary with a zero differential input
voltage resulting in a code of 000 . . . 000, a midscale voltage
resulting in a code of 100 . . . 000, and a full-scale input voltage
resulting in a code of 111 . . . 111. The output code for any analog
input voltage on the ADC can be represented as follows:

Code

AIN GAIN

V

N

REF

=

××

()

×

()

2

1 024.

where:

AIN is the analog input voltage.

GAIN is the PGA gain, i.e., 1 on the 2.56 V range and 128 on

the 20 mV range.

N = 16

REV. 0

AD7709

–24–

When the ADC is configured for bipolar operation, the coding
is offset binary with a negative full-scale voltage resulting in a
code of 000 . . . 000, a zero differential voltage resulting in a
code of 100 . . . 000, and a positive full-scale voltage resulting in
a code of 111 . . . 111. The output code from the ADC for any
analog input voltage can be represented as follows:

Code AIN GAIN V

N

REF

=× × ×

()

()

+

[]

−

2 1 024 1

1

/.

where:

AIN is the analog input voltage.
GAIN in the PGA gain, i.e., 1 on the ±2.56 V range and 128

on the ±20 mV range.

N = 16

Excitation Currents

The AD7709 also contains three software configurable constant
current-sources. IEXC1 and IEXC2 provide 200 µA of current
while IEXC3 provides 25 µA of current. All source current
from V

DD

that is directed to either the IOUT1 or IOUT2 pins of
the device. These current sources are controlled via bits in the
Configuration register. The configuration bits enable the current
sources and they can be configured to source current individually
to both pins or a combination of currents, i.e., 400 µA, 225 µA, or
425 µA to either of the selected output pins. These current sources
can be used to excite external resistive bridge or RTD sensors.

Crystal Oscillator

The AD7709 is intended for use with a 32.768 kHz watch crys­tal. A PLL internally locks onto a multiple of this frequency to
provide a stable 4.194304 MHz clock for the ADC. The modu­lator sample rate is the same as the crystal oscillator frequency.

The start-up time associated with 32.768 kHz crystals is typi­cally 300 ms. The OSCPD bit in the Communications register
can be used to prevent the oscillator from powering down when
the AD7709 is placed in power-down mode. This avoids having
to wait 300 ms after exiting power-down to start a conversion at
the expense of raising the power-down current.

Reference Input

The AD7709 has a fully-differential reference input capability
for the channel. On the channel, the reference inputs can be
REFIN1(+) and REFIN1(–) or REFIN2(+) and REFIN2(–).
They provide a differential reference input capability. The com­mon-mode range for these differential inputs is from GND to V

DD

.
The reference input is unbuffered and therefore excessive R-C
source impedances will introduce gain errors. The nominal
reference voltage, VREF, ((REFIN1(+) – REFIN1(–) or
(REFIN2(+) – REFIN2(–)), for specified operation is 2.5 V, but
the AD7709 is functional with reference voltages from 1 V to V

DD

.
In applications where the excitation (voltage or current) for the
transducer on the analog input also drives the reference voltage
for the part, the effect of the low frequency noise in the excita­tion source will be removed as the application is ratiometric. If

the AD7709 is used in a nonratiometric application, a low
noise reference should be used. Recommended reference volt­age sources for the AD7709 include the AD780, REF43, and
REF192. It should also be noted that the reference inputs provide
a high impedance, dynamic load. Because the input impedance
of each reference input is dynamic, resistor/capacitor combina­tions on these inputs can cause dc gain errors, depending on the
output impedance of the source that is driving the reference inputs.
Reference voltage sources like those recommended above (e.g.,
AD780), will typically have low output impedances and are therefore
tolerant to having decoupling capacitors on the REFIN(+)

without
introducing gain errors in the system. Deriving the reference input
voltage across an external resistor, as shown in Figure 18, will mean
that the reference input sees a significant external source impedance.
External decoupling on the REFIN pins would not be recommended
in this type of circuit configuration.

Reset Input

The RESET input on the AD7709 resets all the logic, the digital
filter, and the analog modulator while all on-chip registers are reset
to their default state. RDY is driven high and the AD7709 ignores
all communications to any of its registers while the RESET
input is low. When the RESET input returns high, the AD7709
operates with its default setup conditions and it is necessary to
set up all registers after a RESET command.

Power-Down Mode

Loading 0 to the STBY bit in the ADC communications register
places the AD7709 in device power-down mode. The AD7709
retains the contents of all its on-chip registers (including the data
register) while in power-down mode.

The device power-down mode does not affect the digital interface,
but it does affect the status of the RDY pin. Putting the AD7709
into power-down mode will reset the RDY line high. Placing the
part in power-down mode reduces the total current to 26 µA
typical when the part is operated at 5 V with the oscillator run­ning during power-down mode. With the oscillator shut down,
the total I

DD

is 1.5 µA typical at 3 V and 6.5 µA typical at 5 V.

Grounding and Layout

Since the analog inputs and reference inputs on the ADC are
differential, most of the voltages in the analog modulator are
common-mode voltages. The excellent common-mode rejection
of the part will remove common-mode noise on these inputs.
The digital filter will provide rejection of broadband noise on
the power supply, except at integer multiples of the modulator
sampling frequency. The digital filter also removes noise from
the analog and reference inputs, provided these noise sources do
not saturate the analog modulator. As a result, the AD7709 is
more immune to noise interference than a conventional high­resolution converter. However, because the resolution of the
AD7709 is so high, and the noise levels from the AD7709 so
low, care must be taken with regard to grounding and layout.

REV. 0

AD7709

–25–

The printed circuit board that houses the AD7709 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. A minimum etch
technique is generally best for ground planes as it gives the best
shielding.

It is recommended that the AD7709’s GND pin be tied to the
AGND plane of the system. In any layout, it is important that the
user keep in mind the flow of currents in the system ensuring
that the return paths for all currents are as close as possible to
the paths the currents took to reach their destinations. Avoid
forcing digital currents to flow through the AGND sections of
the layout.

The PWRGND pin is tied internally to GND on the AD7709.
The PWRGND pad internally has a resistance of less then 50 mΩ
to the PWRGND pin, while the resistance back to the GND
pad is >3 Ω. This means that 19.5 mA of the maximum speci­fied current (20 mA) will flow to PWRGND with the remaining

0.5 mA flowing to GND. PWRGND and GND should be tied
together at the AD7709 and it is important to minimize the
resistance on the ground return lines.

Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7709 to prevent noise coupling. The power
supply lines to the AD7709 should use as wide a trace as possible
to provide low impedance paths and reduce the effects of glitches
on the power supply line. Fast switching signals like clocks
should be shielded with digital ground to avoid radiating noise
to other sections of the board, and clock signals should never be
run near the analog inputs. Avoid crossover of digital and analog
signals. Traces on opposite sides of the board should run at right
angles to each other. This will reduce the effects of feedthrough
through the board. A microstrip technique is by far the best, but is not
always possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground planes while
signals are placed on the solder side.

Good decoupling is important when using high-resolution ADCs.
The supply should be decoupled with 10 µF tantalum in parallel
with 0.1 µF capacitors to GND. To achieve the best from these
decoupling components, they have to be placed as close as possible
chips should be decoupled with 0.1 µF ceramic capacitors to DGND.

APPLICATIONS

The AD7709 provides a low-cost, high-resolution analog-to­digital function. Because the analog-to-digital function is provided
by a sigma-delta architecture, it makes the part more immune to
noisy environments, making it ideal for use in sensor measure­ment and industrial and process control applications. Given the
architecture used in the AD7709, where the signal chain is
chopped and the device is factory-calibrated at final test, field
calibration is not needed due to the extremely low offset and
gain drifts exhibited by this converter. It also provides a pro­grammable gain amplifier and a digital filter. Thus, it provides
far more system-level functionality than off-the-shelf integrating
ADCs without the disadvantage of having to supply a high-quality
integrating capacitor. In addition, using the AD7709 in a system

allows the system designer to achieve a much higher level of reso­lution because noise performance of the AD7709 is significantly
better than that of integrating ADCs.

The on-chip PGA allows the AD7709 to handle an analog input
voltage range as low as 10 mV full-scale with V

REF

= 1.25 V. The
differential inputs of the part allow this analog input range to
have an absolute value anywhere between GND + 100 mV and
V

DD

– 100 mV. It allows the user to connect the transducer
directly to the input of the AD7709. The programmable gain
front end on the AD7709 allows the part to handle unipolar
analog input ranges from 0 mV to 20 mV to 0 V to 2.5 V and
bipolar inputs of ±20 mV to ±2.5 V. Because the part operates
from a single supply, these bipolar ranges are with respect to a
biased-up differential input.

Pressure Measurement

One typical application of the AD7709 is pressure measure­ment. Figure 18 shows the AD7709 used with a pressure
transducer, the BP01 from Sensym. The pressure transducer is
arranged in a bridge network and gives a differential output
voltage between its OUT(+) and OUT(–) terminals. With
rated full-scale pressure (in this case 300 mmHg) on the trans­ducer, the differential output voltage is 3 mV/V of the input
voltage (i.e., the voltage between its IN(+) and IN(–) terminals).

Assuming a 5 V excitation voltage, the full-scale output range
from the transducer is 15 mV. The excitation voltage for the
bridge can be used to directly provide the reference for the ADC
as the reference input range includes the supply. Alternatively, a
suitable resistor divider can be implemented that allows the full
dynamic range of the input to be utilized in this application.
This implementation is fully ratiometric, so variations in the
excitation voltage do not introduce errors in the system. Choos­ing resistor values of 10 kΩ and 6 kΩ as per Figure 18 give a

1.875 V reference voltage for the AD7709 when the excitation
voltage is 5 V.

AD7709

IN+

OUT+

OUT–

IN–

10k

EXCITATION VOLTAGE = 5V

V

DD

AIN1

AIN2

REFIN1(+)

P1

PWRGND

GND

REFIN2(–)

6k

Figure 18. Pressure Measurement Using AD7709

Using the part with a programmed gain of 128 results in the
full-scale input span of the AD7709 being 15 mV, which corre­sponds with the output span from the transducer.

REV. 0

AD7709

–26–

A second key advantage to using the AD7709 in transducer­based applications is that the on-chip low-side power switch can
be fully utilized in low power applications. The low-side power
switch is connected in series with the cold side of the bridge. In
normal operation, the switch is closed and measurements can be
taken from the bridge. In applications where power is of con­cern, the AD7709 can be put in low power mode substantially
reducing the power burned in the application. In addition to
this, the power switch can be opened while in low power mode
thus avoiding the unnecessary burning of power in the front end
transducer. When taken back out of power-down and the power
switch is closed, the user should ensure that the front end cir­cuitry is fully settled before attempting a read from the AD7709.

The circuit in Figure 19 shows a method that utilizes three
pseudo-differential input channels on the AD7709 to temperature­compensate a pressure transducer.

5V

OUT(+)

OUT(–)

IN(–)

IN(+)

I1

I2

PRESSURE

BRIDGE

XTAL1

XTAL2

IOUT1

6.25k

V

DD

REFIN(+)

REFIN(–)

AIN2

AIN1

AIN3

AINCOM

GND

AD7709

250

Figure 19. Temperature-Compensating a Pressure
Transducer

In this application, pseudo-differential input channel AIN1/AINCOM
is used to measure the bridge output while pseuo-differential

channels
AIN2/AINCOM and AIN3/AINCOM measure the voltage
across the bridge. The voltage measured across the bridge will vary
proportionally with temperature, and the delta

in this voltage can be

used to temperature-compensate the output

of the pressure bridge.

Temperature Measurement

The AD7709 is also useful in temperature measurement appli­cations, Figure 20 shows an RTD temperature measurement
application.

REFIN(–)

IOUT1

5V

6.25k

AIN2

AIN1

AD7709

REFIN(+)

IOUT2

V

DD

GND PWRGND

DRDY

SCLK

DIN

DOUT

CS

XTAL1

XTAL2

R

REF

RL1

RL2

RL3

RL4

R

CM

RTD

200A

CONTROLLER

Figure 20. 4-Wire RTD Temperature Measurement
Using the AD7709

In this application, the transducer is an RTD (Resistive Tem­perature Device), a PT100. The arrangement is a 4-lead RTD
configuration. There are voltage drops across the lead resistances
RL1 and RL4, but these simply shift the common-mode voltage.
There is no voltage drop across lead resistances RL2 and RL3 as
the input current to the AD7709 is very low, looking into a high
input impedance buffer. R

CM

is included to shift the analog
input voltage to ensure that it lies within the common-mode
range (GND + 100 mV to V

DD

– 100 mV) of the ADC. In the

application shown, the on-chip 200 µA current source provides
the excitation current for the PT100 and also generates the reference
voltage for the AD7709 via the 6.25 kΩ resistor. Variations in
the excitation current do not affect the circuit as both the input
voltage and the reference voltage vary ratiometrically with the exci­tation

current. However, the 6.25 kΩ resistor must

have a low

temperature coefficient to avoid errors in the reference

voltage

over temperature.

REV. 0

AD7709

–27–

Figure 21 shows a further enhancement to the circuit shown in
Figure 20. Generally dc excitation has been accepted as the
normal method of exciting resistive-based sensors like RTDs
(Resistance Temperature Detectors) in temperature measure­ment applications.

IOUT1

IOUT2

V

DD

AIN2

AIN1

AIN3

AIN4

AD7709

REFIN(+)

MUX1

R

REF

A A

BUF
AND
PGA

200A

I1

EMF1

RESISTIVE

T

RANSDUCER

EMF2

P1

P2

REFIN(–)

Figure 21. Low Resistance Measurement

With dc excitation, the excitation current through the sensor
must be large enough so that the smallest temperature/resis­tance change to be measured results in a voltage change that
is larger than the system noise, offset, and drift of the system.
The purpose of switching the excitation source is to eliminate
dc-induced errors. DC errors (EMF1 and EMF2) due to para­sitic thermocouples produced by differential metal connections
(solder and copper track) within the circuit are also eliminated
when using this switching arrangement. This excitation is a
form of synchronous detection where the sensor is excited with
an alternating excitation source and the ADC only measures
information in the same phase as the excitation source.

The switched polarity current source is developed using the on­chip current sources and external phase control switches (A and A)
driven by the AD7709’s logic outputs P1 and P2. During the
conversion process the AD7709 takes two conversion results, one
on each phase. During Phase 1 the on-chip current source is directed
to IOUT1 and flows top to bottom through the sensor and
switch controlled by A. In Phase 2, the current source is directed
to IOUT2

and flows in the opposite direction through the sensor

and through

switch controlled by A. In all cases the current flows

in the same direction through the reference resistor to develop the
reference voltage for the ADC. All measurements are ratiometri­cally derived.The results of both conversions are combined
within the microcontroller to produce one output measurement
representing the resistance or temperature of the transducer. For
example, if the RTD output during Phase 1 is 10 mV, a 1 mV
circuit-induced dc error exists due to parasitic thermocouples, the
ADC measures 11 mV. During the second phase, the excitation
current is reversed and the ADC measures –10 mV from the
RTD and again sees 1 mV dc error, giving an ADC output of
–9 mV during this phase. These measurements are processed
in the controller (11 mV – (–9 mV)/2 = 10 mV) thus removing
the dc-induced errors within the system.

In the circuit shown in Figure 20, the resistance measurement is
made using ratiometric techniques. Resistor R

REF

, which develops
the ADC reference, must be stable over temperature to prevent
reference-induced errors in the measurement output.

3-Wire RTD Configurations

To fully optimize a 3-wire RTD configuration, two identically
matched current sources are required. The AD7709, which
contains two well-matched 200 µA current sources, is ideally
suited to these applications. One possible 3-wire configuration
using the AD7709 is outlined in Figure 22.

REFIN(–)

IOUT1

GND

5V

6.25k

AIN2

AIN1

AD7709

RL3

R

CM

REFIN(+)

IOUT2

V

DD

DRDY

SCLK

DIN

DOUT

CS

XTAL1

XTAL2

RL2

RTD

200A

200A

RL1

CONTROLLER

Figure 22. 3-Wire RTD Configuration Using the AD7709

In this 3-wire configuration, the lead resistances will result in
errors if only one current source is used as the 200 µA will flow
through RL1, developing a voltage error between AIN1 and
AIN2. In the scheme outlined below, the second RTD current
source is used to compensate for the error introduced by the
200 µA flowing through RL1. The second RTD current flows
through RL2. Assuming RL1 and RL2 are equal (the leads
would normally be of the same material and of equal length),
and IOUT1 and IOUT2 match, the error voltage across RL2
equals the error voltage across RL1 and no error voltage is
developed between AIN1 and AIN2. Twice the voltage is developed
across RL3 but, since this is a common-mode voltage, it will not
introduce errors. RCM is included so the current flowing through
the combination of RL3 and RCM develops enough voltage that the
analog input voltage seen by the AD7709 is within the common

­mode range of the ADC. The reference voltage for the AD7709
is also generated using one of these matched current sources.

This reference voltage is developed across the 6.25 kΩ resistor as
shown, and applied to the differential reference inputs of the AD7709.
This scheme ensures that the analog input voltage span remains
ratiometric to the reference voltage. Any errors in the analog
input voltage due to the temperature drift of the RTD

current
source is compensated for by the variation in the reference voltage.
The typical drift matching between the two RTD current

sources

is less than 20 ppm/°C. The voltage on either I

OUT

pin can go to

within 0.6 V of the V

DD

supply.

The AD7709 also includes a 25 µA current source that can be used
along with the two 200 µA current sources for VBE measurement
where a 17:1 ratio is required from the current sources.

REV. 0

–28–

C02700–.8–10/01(0)

PRINTED IN U.S.A.

AD7709

MICROCONTROLLER

V

CC

GND

REFOUT2

REFIN

10F

0.1F

V

DD

AIN1

AIN2

CS

DOUT

SCLK

DIN

GND

REFIN(+)

REFIN(–)

0.1F

REFOUT1

CLOCK

LATCH

DATA

4.7F

COM

C1 C2 C3

AD7709

AD421

BOOST

V

CC

LV

0.01F

1k

1000pF

LOOP

POWER

10F

3.3V

1.25V

DN25D

0.01F

LOOP

RTN

COMP

DRIVE

VARIABLES

AIN3

AIN4

Figure 23. Smart Transmitter Employing the AD7709

Smart Transmitters

Smart transmitters are another key design-in area for the AD7709.
The sigma-delta converter, single supply operation, 3-wire interface
capabilities, and small package size are all of benefit in smart
transmitters. Here, the entire smart transmitter must operate
from the 4 mA-to-20 mA loop. Tolerances in the loop mean that

the amount of current available to power the transmitter is as low
as 3.5 mA. Figure 23 shows a block diagram of a smart transmitter
which includes the AD7709.

Not shown in Figure 23 is the isolated power source required to
power the front end.

24-Lead Plastic TSSOP

(RU-24)

24

13

121

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

0.311 (7.90)

0.303 (7.70)

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0256 (0.65)
BSC

0.0433 (1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

8
0

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).