Page 1
16-Bit, 250 kSPS PulSAR
FEATURES
16-bit resolution with no missing codes
Throughput: 250 kSPS @ 5 V
INL: ±4 LSB max
S/(N + D): 92 dB @ 20 kHz
THD: –106 dB @ 20 kHz
Pseudo-differential analog input range:
0 V to V
with V
REF
No pipeline delay
Single-supply operation: 2.7 V or 5 V
Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible
Supply Current: 540 µA @ 2.7 V/100 kSPS,
800 µA @ 5 V/100 kSPS
Standby current: 1 nA
8-lead MSOP package
nd
Improved 2
Source to LTC1864 and LTC1864L
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
up to VDD
REF
ADC in MSOP
AD7694
APPLICATION DIAGRAM
1V TO VDD 2.5V TO 5V
REF
GND
Figure 1.
VDD
SCK
SDO
CNV
AD7685
AD7694
3-WIRE SPI
INTERFACE
AD7686
05003-001
0 TO V
REF
IN+
IN–
AD7694
Table 1. MSOP, QFN (LFCSP)/SOT-23, 16-Bit PulSAR ADC
Type 100 kSPS 250 kSPS 500 kSPS
True Differential AD7684 AD7687 AD7688
Pseudo
AD7683
Differential/Unipolar
Unipolar AD7680
GENERAL DESCRIPTION
The AD7694 is a 16-bit, charge redistribution, successive
approximation, PulSAR™ analog-to-digital converter (ADC)
that operates from a single power supply, VDD, between 2.7 V
to 5.25 V. It contains a low power, high speed, 16-bit sampling
ADC with no missing codes (B grade), an internal conversion
clock, and a serial, SPI-compatible interface port. The part also
contains a low noise, wide bandwidth, short aperture delay
track-and-hold circuit. On the CNV rising edge, it samples an
analog input, IN+, between 0 V to REF with respect to a ground
sense, IN−. The reference voltage, REF, is applied externally and
can be set up to the supply voltage.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.
Its power scales linearly with throughput.
The AD7694 is housed in an 8-lead MSOP package with an
operating temperature specified from −40°C to +85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
Page 2
AD7694
TABLE OF CONTENTS
Specifications..................................................................................... 3
Typical C o n n e ction Di ag r a m ................................................... 13
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Te r m in o l o g y ...................................................................................... 8
Typical Performance Characteristics............................................. 9
Application Information................................................................ 12
Circuit Information.................................................................... 12
Converter Operation.................................................................. 12
Transfe r F u ncti o n s ...................................................................... 12
REVISION HISTORY
7/04—Revision 0: Initial Version
Analog Input............................................................................... 13
Driver Amplifier Choice............................................................ 13
Voltage Reference Input ............................................................ 14
Power Supply............................................................................... 14
Supplying the ADC from the Reference.................................. 14
Digital Interface.......................................................................... 14
Layout .......................................................................................... 15
Evaluating the AD7694’s Performance.................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Rev. 0 | Page 2 of 16
Page 3
AD7694
SPECIFICATIONS
VDD = 2.7 V to 5.25 V; V
Table 2.
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
RESOLUTION 16 16 Bits
ANALOG INPUT
Voltage Range IN+ − IN− 0 V
Absolute Input Voltage IN+ −0.1 VDD + 0.1 −0.1 VDD + 0.1 V
IN− −0.1 0.1 −0.1 0.1 V
Leakage Current at 25°C Acquisition phase 1 1 nA
Input Impedance See the Analog Input section.
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 +6 −4 +4 LSB
Transition Noise REF = VDD = 5 V 0.5 0.5 LSB
Gain Error1, T
MIN
to T
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error1, T
MIN
to T
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity
THROUGHPUT
Conversion Rate VDD = 4.75 V to 5.25 V 0 250 0 250 kSPS
VDD = 2.7 V to 4.75 V 0 150 0 150 kSPS
AC ACCURACY
Signal-to-Noise fIN = 20 kHz, V
f
Spurious-Free Dynamic Range fIN = 20 kHz −100 −106 dB
Total Harmonic Distortion fIN = 20 kHz −100 −106 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz, V
f
= VDD; TA = –40°C to +85°C, unless otherwise noted.
REF
MAX
MAX
±2 ±30 ±2 ±15 LSB
±0.7 ±3.5 ±0.7 ±3.5 mV
VDD = 5 V ±5%
= 5 V 90 88 92 dB
REF
= 20 kHz, V
IN
= 20 kHz, V
IN
= 2.5 V 86 87 dB
REF
= 5 V 89 88 92 dB
REF
= 2.5 V 86 87 dB
REF
REF
0 V
REF
V
±0.05 ±0.05 LSB
2
1
See section. These specifications do include full temperature range variation, but do not include the error contribution from the external reference. Terminology
2
All specifications in dB refer to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. 0 | Page 3 of 16
Page 4
AD7694
VDD = 2.7 V to 5.25 V; V
Table 3.
Parameter Conditions Min Typ Max Unit
REFERENCE
Voltage Range 1 VDD V
Load Current 250 kSPS, V
SAMPLING DYNAMICS
−3 dB Input Bandwidth 9 MHz
DIGITAL INPUTS
Logic Levels
V
IL
VDD = 2.7 V 0.45 V
V
IH
VDD = 3.3 V 1.9 V
I
IL
I
IH
DIGITAL OUTPUTS
Data Format Serial, 16 bits straight binary
Pipeline Delay
V
OL
V
OH
POWER SUPPLIES
VDD Specified performance 2.7 5.25 V
Operating Current
VDD VDD = 5 V, 100 kSPS throughput 0.8 1.2 mA
VDD = 2.7 V, 100 kSPS throughput 540 960 µA
Standby Current
1, 2
TEMPERATURE RANGE
Specified Performance T
= VDD; TA = –40°C to +85°C, unless otherwise noted.
REF
− V
= V
IN+
IN−
/2 = 2.5 V 50 µA
REF
VDD = 4.75 V 0.8 V
VDD = 5.25 V 3.15 V
−1 +1 µA
−1 +1 µA
I
= +500 µA 0.4 V
SINK
I
= −500 µA VDD − 0.3 V
SOURCE
VDD = 5 V, 25°C
to T
MIN
MAX
Conversion results available immediately
after completed conversion
1 50 nA
−40 +85
°C
1
With all digital inputs forced to VDD or GND, as required.
2
During acquisition phase.
Rev. 0 | Page 4 of 16
Page 5
AD7694
TIMING SPECIFICATIONS
VDD = 4.75 V to 5.25 V; TA = −40°C to +85°C, unless otherwise stated.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
Time between Conversions t
SCK Period t
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t
CNV Low to SDO, D15 MSB Valid t
CNV High to SDO High Impedance t
CONV
CYC
SCK
SCKL
SCKH
HSDO
DSDO
EN
DIS
3.2 µs
4 µs
50 ns
20 ns
20 ns
5 ns
20 ns
60 ns
60 ns
VDD = 2.7 V to 4.75 V; T
−40°C to +85°C, unless otherwise stated.
A =
Table 5.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
Time between Conversions t
SCK Period t
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t
CNV Low to SDO, D15 MSB Valid t
CNV High to SDO High Impedance t
CONV
CYC
SCK
SCKL
SCKH
HSDO
DSDO
EN
DIS
4.66 µs
6.66 µs
125 ns
50 ns
50 ns
5 ns
50 ns
120 ns
120 ns
Rev. 0 | Page 5 of 16
Page 6
AD7694
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Inputs
IN+1, IN−1 GND − 0.3 V to VDD + 0.3 V
or ±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD to GND −0.3 V to +7 V
Digital Inputs to GND −0.3 V to VDD + 0.3 V
Digital Outputs to GND −0.3 V to VDD + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 200°C/W (MSOP-8)
θJC Thermal Impedance 44°C/W (MSOP-8)
Lead Temperature Range
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1
See the Analog Input section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500µAI
TO SDO
Figure 2. Load Circuit for Digital Interface Timing
50pF
C
L
500µAI
V
IL
t
DELAY
V
OH
V
OL
Figure 3. Voltage Reference Levels for Timing
OL
1.4V
OH
V
IH
t
DELAY
V
V
OH
OL
05003-002
05003-003
Rev. 0 | Page 6 of 16
Page 7
AD7694
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REF
1
2
IN+
AD7694
TOP VIEW
IN–
3
(Not to Scale)
4
GND
Figure 4. 8-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type1Function
1 REF AI
Reference Input Voltage. The REF range is from 1 V to VDD. It is referred to the GND pin. This pin should be
decoupled closely to the pin with a ceramic capacitor of a few µF.
2 IN+ AI
Analog Input. It is referred to in IN−. The voltage range, i.e., the difference between IN+ and IN−, is 0 V
to V
.
REF
3 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground.
4 GND P Power Supply Ground.
5 CNV DI Convert Input. On its leading edge, it initiates the conversions. It enables the SDO pin when low.
6 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
7 SCK DI Serial Data Clock Input. When CNV is low, the conversion result is shifted out by this clock.
8 VDD P Power Supply.
VDD
8
7
SCK
SDO
6
5
CNV
05003-004
1
AI = analog input; DI = digital input; DO = digital output; and P = power.
Rev. 0 | Page 7 of 16
Page 8
AD7694
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale to positive full scale.
The point used as negative full scale occurs ½ LSB before the
first code transition. Positive full scale is defined as a level 1 ½
LSB beyond the last code transition. The deviation is measured
from the middle of each code to the true straight line (see
Figure 19).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level 1/2 LSB above analog
ground (38.1 µV for the 0 V to 5 V range). The offset error is the
deviation of the actual transition from that point.
Gain Error
The last transition (from 111...10 to 111...11) should occur for
an analog voltage 1 ½ LSB below the nominal full scale
(4.999886 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset has been adjusted out.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N + D) by the following formula
ENOB = (S/[N + D]
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (S/[N + D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is the time between the rising edge of the CNV input and the
time the input signal is held for conversion.
− 1.76)/6.02
dB
Transient Response
The time required for the ADC to accurately acquire its input
after a full-scale step function is applied.
Rev. 0 | Page 8 of 16
Page 9
AD7694
TYPICAL PERFORMANCE CHARACTERISTICS
4
3
POSITIVE INL = +0.68 LSB
NEGATIVE INL = –1.14 LSB
2.0
1.5
POSITIVE DNL = +0.59 LSB
NEGATIVE DNL = –0.56 LSB
2
1
0
INL (LSB)
–1
–2
–3
–4
0 3276816384 49152 65536
CODE
Figure 5. Integral Nonlinearity vs. Code
12000
10000
8000
6000
COUNTS
4000
2000
001 00
0
24E0 24E1 24E2 24E3 24E4 24E5 24E6 24E7 24E8
108568
10003
CODE IN HEX
VDD = REF = 5V
12500
0
Figure 6. Histogram of a DC Input at the Code Center
05003-005
05003-006
1.0
0.5
0
DNL (LSB)
–0.5
–1.0
–1.5
–2.0
0 3276816384 49152 65536
CODE
Figure 8. Differential Nonlinearity vs. Code
8000
7000
6000
5000
4000
COUNTS
3000
2000
1000
0027
0
251B 251C 251D 251E 251F 2520 2521 2522 2523 2524 2525 2526
65487
32418
28148
2133
CODE IN HEX
VDD = REF = 2.5V
2808
50
100
Figure 9. Histogram of a DC Input at the Code Center
05003-008
05003-009
0
–20
–40
–60
–80
–100
–120
–140
AMPLITUDE (dB OF FULL SCALE)
–160
–180
0 20 40 60 80 100 120
FREQUENCY (kHz)
16384 POINT FFT
VDD = REF = 5V
f
= 250kSPS
S
f
= 20.43kHz
IN
SNR = 92.5dB
THD = –109.9dB
SFDR = –111.0dB
Figure 7. FFT Plot
05003-007
Rev. 0 | Page 9 of 16
0
–20
–40
–60
–80
–100
–120
–140
AMPLITUDE (dB OF FULL SCALE)
–160
–180
0 10203040506070
FREQUENCY (kHz)
16384 POINT FFT
VDD = REF = 2.5V
f
= 150kSPS
S
f
= 20.43kHz
IN
SNR = 88.5dB
THD = –102.7dB
SFDR = –105.1dB
Figure 10. FFT Plot
05003-010
Page 10
AD7694
100
17
1200
95
SNR
90
SNR, S/[N+D] (dB)
S/[N+D]
85
80
2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE VOLTAGE (V)
ENOB
Figure 11. SNR, S/(N + D), and ENOB vs. Reference Voltage
100
95
90
85
S/[N+D] (dB)
80
75
70
0 50 100 150 200
V
= 2.5V, –1dB
REF
FREQUENCY (kHz)
V
REF
V
= 5V, –10dB
REF
Figure 12. S/[N + D] vs. Freq uency
= 5V, –1dB
16
15
14
13
ENOB (Bits)
05003-011
05003-012
1000
800
600
400
OPERATING CURRENT (µA)
200
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY (V)
f
= 100kSPS
S
Figure 14. Operating Current vs. Supply
900
800
700
600
500
400
300
OPERATING CURRENT (µA)
200
100
0
–55 125105856545255–15–35
VDD = 5V,
f
= 100kSPS
S
TEMPERATURE (°C)
VDD = 2.7V,
f
= 100kSPS
S
Figure 15. Operating Current vs. Temperature
05003-014
05003-015
–80
V
= 2.5V, –1dB
–85
–90
–95
V
= 5V, –1dB
–100
THD (dB)
–105
–110
–115
0 40 80 120 160 200
REF
FREQUENCY (kHz)
REF
Figure 13. THD vs. Frequency
05003-013
Rev. 0 | Page 10 of 16
1000
750
500
250
POWER-DOWN CURRENT (nA)
0
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
Figure 16. Power-Down Current vs. Temperature
05003-016
Page 11
AD7694
6
4
2
0
OFFSET ERROR
–2
–4
OFFSET ERROR, GAIN ERROR (LSB)
–6
–55 125105856545255–15–35
TEMPERATURE (°C)
Figure 17. Offset and Gain Error vs. Temperature
GAIN ERROR
05003-017
Rev. 0 | Page 11 of 16
Page 12
AD7694
APPLICATION INFORMATION
IN+
REF
GND
16,384C
16,384C
SWITCHES CONTROL
SW+MSB
LSB
4C 2C C C32,768C
COMP
4C 2C C C32,768C
SW–MSB
LSB
CONTROL
LOGIC
CNV
BUSY
OUTPUT CODE
IN–
Figure 18. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7694 is a low power, single-supply, 16-bit ADC using a
successive approximation architecture. It is capable of converting 250,000 samples per second (250 kSPS) and powers
down between conversions. When operating at 100 SPS, for
example, it consumes typically 4 µW, ideal for battery-powered
applications.
The AD7694 provides the user with on-chip track-and-hold and
does not exhibit any pipeline delay or latency, making it ideal
for multiple, multiplexed channel applications.
The AD7694 is specified from 2.7 V to 5.25 V. It is housed in a
8-lead MSOP. The AD7694 is an improved second source to
LTC1864 and LTC1864L. For even better performance, the
AD7685 should be considered.
CONVERTER OPERATION
The AD7694 is a successive approximation ADC based on a
charge redistribution DAC. Figure 18 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase begins. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the GND
input. Thus, the differential voltage between the inputs, IN+ and
IN−, captured at the end of the acquisition phase applies to the
comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between
GND and REF, the comparator input varies by binary weighted
/2, V
voltage steps (V
REF
REF
/4...V
/65536). The control logic
REF
05003-018
toggles these switches, starting with the MSB, in order to bring
the comparator back into a balanced condition. After the
completion of this process, the part returns to the acquisition
phase and the control logic generates the ADC output code.
Because the AD7694 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7694 is shown in
Figure 19 and Table 8.
111...111
111...110
111...101
ADC CODE (STRAIGHT BINARY)
000...010
000...001
000...000
–FS
–FS + 1 LSB
–FS + 0.5 LSB
ANALOG INPUT
Figure 19. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Analog Input
= 5 V
Description
V
REF
FSR – 1 LSB 4.999924 V FFFF2
Midscale + 1 LSB 2.500076 V 8001
Midscale 2.5 V 8000
Midscale – 1 LSB 2.499924 V 7FFF
–FSR + 1 LSB 76.3 µV 0001
–FSR 0 V 00003
Digital Output Code
Hexadecimal
2
This is also the code for an overranged analog input (V
V
– V
).
REF
GND
3
This is also the code for an underranged analog input (V
+
+FS – 1.5 LSB
FS – 1 LSB
IN+
IN+
– V
– V
above
IN–
IN–
below V
05003-019
GND
).
Rev. 0 | Page 12 of 16
Page 13
AD7694
(NOTE 1)
REF
2.2 TO 10µF
(NOTE 2)
100nF
2.7V TO 5.25V
33Ω
0 TO V
REF
(NOTE 3)
NOTE 1: SEE REFERENCE SECTION FOR REFERENCE SELECTION.
NOTE 2: C
NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION.
NOTE 4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
REF
2.7nF
(NOTE 4)
Figure 20. Typical Application Diagram
TYPICAL CONNECTION DIAGRAM
Figure 20 shows an example of the recommended application
diagram for the AD7694.
ANALOG INPUT
Figure 21 shows an equivalent circuit of the AD7694 input
structure. The two diodes, D1 and D2, provide ESD protection
for the analog inputs, IN+ and IN−. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 0.3 V, because this will cause these diodes to
become forward-biased and start conducting current. However,
these diodes can handle a forward-biased current of 130 mA,
maximum. For instance, these conditions could eventually
occur when the input buffer’s (U1) supplies are different from
VDD. In such a case, an input buffer with a short-circuit current
limitation can be used to protect the part.
VDD
IN+
OR IN–
GND
D1
C
PIN
D2
Figure 21. Equivalent Analog Input Circuit
R
This analog input structure allows the sampling of the
differential signal between IN+ and IN−. By using this
differential input, small signals common to both inputs are
rejected. For instance, by using IN− to sense a remote signal
ground, ground potential differences between the sensor and
the local ADC ground are eliminated. During the acquisition
phase, the impedance of the analog input IN+ can be modeled
as a parallel combination of the capacitor C
formed by the series connection of R
the pin capacitance. R
is typically 600 Ω and is a lumped
IN
and CIN. C
IN
component made up of some serial resistors and the onresistance of the switches. C
is typically 30 pF and is mainly
IN
C
IN
IN
and the network
PIN
is primarily
PIN
05003-021
IN+
IN–
REF
GND
AD7694
VDD
SCK
SDO
CNV
3-WIRE INTERFACE
05003-020
the ADC sampling capacitor. During the conversion phase,
where the switches are opened, the input impedance is limited
. RIN and CIN make a 1-pole, low-pass filter that reduces
to C
PIN
undesirable aliasing effects and limits the noise.
When the source impedance of the driving circuit is low, the
AD7694 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance.
DRIVER AMPLIFIER CHOICE
Although the AD7694 is easy to drive, the driver amplifier
needs to meet the following requirements:
• The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7694. Note that the
AD7694 has a noise much lower than most of the other
16-bit ADCs and, therefore, can be driven by a noisier op
amp while preserving the same or better system performance. The noise coming from the driver is filtered by the
AD7694 analog input circuit 1-pole, low-pass filter made
by R1 and C2 or by the external filter, if one is used.
• For ac applications, the driver needs to have a THD
performance suitable to that of the AD7694. Figure 13
gives the THD versus frequency that the driver
should exceed.
• For multichannel multiplexed applications, the driver
amplifier and the AD7694 analog input circuit must be able
to settle for a full-scale step of the capacitor array at a
16-bit level (0.0015%). In the amplifier’s data sheet, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
Rev. 0 | Page 13 of 16
Page 14
AD7694
Table 9. Recommended Driver Amplifiers
Amplifier Typical Application
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8605, AD8615 5 V single-supply and low power
AD8519 Small, low power, and low frequency
AD8031 High frequency and low power
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7694, with its low operating
current, can be supplied directly using the reference circuit, as
shown in Figure 23. The reference line can be driven by either
• The system power supply directly
• A reference voltage with enough current output capability,
such as the
ADR43x
VOLTAGE REFERENCE INPUT
The AD7694 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (e.g., an
unbuffered reference voltage like the low temperature drift
ADR43x reference or a reference buffer using the AD8031 or
the
AD8605), a 10 µF (X5R, 0805 size) ceramic chip capacitor is
appropriate for optimum performance.
If desired, smaller reference decoupling capacitor values down
to 2.2 µF can be used with a minimal impact on performance,
especially DNL.
POWER SUPPLY
The AD7694 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 22. This makes the part
ideal for a low sampling rate (even a few Hz) and low batterypowered applications.
10,000
1,000
A)
µ
100
VDD = 5V
• A reference buffer, such as the
AD8031, that can also filter
the system power supply, as shown in Figure 23
5V OR 3V
5V
10kΩ
OR
3V
1µF
NOTE 1: OPTIONAL REFERENCE BUFFER AND FILTER
Figure 23. Example of an Application Circuit
AD8031
(NOTE 1)
5V OR 3V
2.2
TO
10µF
10Ω
REF VDD
AD7694
1µF
05003-023
DIGITAL INTERFACE
The AD7694 is compatible with SPI, QSPI, digital hosts, and
DSPs, e.g., Blackfin® ADSP-BF53x or ADSP-219x. The connection diagram is shown in Figure 24 and the corresponding
timing diagram is shown in Figure 25.
A rising edge on CNV initiates a conversion and forces SDO to
high impedance. When the conversion is complete, the AD7694
enters the acquisition phase and powers down. When CNV goes
low, the MSB is output onto SDO. The remaining data bits are
then clocked by subsequent SCK falling edges. The data is valid
on both SCK edges.
10
1
OPERATING CURRENT (
0.1
0.01
10 100 1k 10k 100k 1M
Figure 22. Operating Current vs. Sampling Rate
SAMPLING RATE (SPS)
VDD = 2.7V
05003-022
Rev. 0 | Page 14 of 16
CONVERT
CNV
AD7694
SDO
SCK
Figure 24. Connection Diagram
DATA IN
CLK
DIGITAL HOST
05003-024
Page 15
AD7694
t
CYC
CNV
t
CONV
ACQUISITION
SCK
SDO
*SDO REMAINS LOW IF FURTHER SCK CLOCKS ARE APPLIED WHILE CNV IS LOW
CONVERSION
1 2 3 14 15 16*
t
t
EN
D15 D14 D13 D1 D0
Figure 25. Serial Interface Timing
LAYOUT
The printed circuit board that houses the AD7694 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7694 with all its analog signals on the left side and all its
digital signals on the right side eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7694 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog section. In such a case, it
should be joined underneath the AD7694s.
HSDO
t
ACQ
ACQUISITION
t
SCK
t
SCKL
t
SCKH
t
DSDO
t
DIS
05003-025
The AD7694 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. That is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and by connecting these pins with wide, low
impedance traces.
Finally, the power supply, VDD, of the AD7694 should be
decoupled with a ceramic capacitor, typically 100 nF. This
capacitor should be placed close to the AD7694 and connected
using short and large traces to provide low impedance paths
and reduce the effect of glitches on the power supply lines.
EVALUATING THE AD7694’S PERFORMANCE
Other recommended layouts for the AD7694 are outlined in the
evaluation board for the AD7694 (
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the
EVAL-AD7694). The
EVAL-CONTROL BRD2.
Rev. 0 | Page 15 of 16
Page 16
AD7694
OUTLINE DIMENSIONS
3.00
BSC
85
3.00
BSC
PIN 1
0.65 BSC
0.15
0.00
0.38
0.22
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA
BSC
4
SEATING
PLANE
4.90
1.10 MAX
0.23
0.08
8°
0°
0.80
0.60
0.40
Figure 26. 8-Lead Micro Small Outline Package [MSOP]
(RM-8)
Dimensions Shown in Millimeters
ORDERING GUIDE
Models Integral Nonlinearity Temperature Range Package (Option) Transport Media, Quantity Branding
AD7694ARM ±6 LSB max –40°C to +85°C MSOP (RM-8) Tube, 50 C2H
AD7694ARMRL7 ±6 LSB max –40°C to +85°C MSOP (RM-8) Reel, 1,000 C2H
AD7694BRM ±4 LSB max –40°C to +85°C MSOP (RM-8) Tube, 50 C2J
AD7694BRMRL7 ±4 LSB max –40°C to +85°C MSOP (RM-8) Reel, 1,000 C2J
EVAL-AD7694CB1 Evaluation Board
EVAL-CONTROL BRD22 Controller Board
EVAL-CONTROL BRD32 Controller Board
1
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.
2
These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in CB designators.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05003–0–7/04(0)
Rev. 0 | Page 16 of 16
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