Datasheet AD7693 Datasheet (ANALOG DEVICES)

16-Bit, ±0.5 LSB, 500 kSPS PulSAR®

V

FEATURES

16-bit resolution with no missing codes
Throughput: 500 kSPS
INL/DNL: ±0.25 LSB typ, ±0.5 LSB max (±8 ppm of FSR)
Dynamic range: 96.5 dB
SINAD: 96 dB @ 1 kHz
THD: −120 dB @ 1 kHz
True differential analog input range: ±V

0 V to V

with V

REF

up to VDD on both inputs

REF

No pipeline delay
Single-supply 5 V operation with

1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible
Daisy-chain multiple ADCs, selectable busy indicator
Power dissipation: 40 nJ/conversion

40 μW @ 5 V/1 kSPS
4 mW @ 5 V/100 kSPS

18 mW @ 5 V/500 kSPS
Standby current: 1 nA
10-lead package: MSOP (MSOP-8 size) and

3 mm × 3 mm QFN (LFCSP) (SOT-23 size)
Pin-for-pin compatible with the 16-bit AD7687 and AD7688

and the 18-bit AD7690 and AD7691

APPLICATIONS

Battery-powered equipment
Data acquisitions
Seismic data acquisition systems
DVMs
Instrumentation
Medical instruments

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 65536

16384 32768 49152

Figure 1. Integral Nonlinearity vs. Code

POSITIVE INL = +0.17LSB
NEGATIVE INL = –0. 17LSB

CODE

REF

Differential ADC in MSOP/QFN

AD7693

APPLICATION DIAGRAM

+2.5V TO +5V

±10V, ±5V, ...

ADA4941-1

Table 1. MSOP, QFN (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC

100

Type

kSPS

18-Bit AD7691 AD7690

16-Bit True

AD7684 AD7687 AD7688

Differential
16-Bit Pseudo AD7683 AD7685 AD7686 ADA4841-x
Differential/

AD7680 AD7694

Unipolar
14-Bit AD7940 AD7942 AD7946 ADA4841-x

GENERAL DESCRIPTION

The AD7693 is a 16-bit, successive approximation analog-to­digital converter (ADC) that operates from a single power supply,
VDD. It contains a low power, high speed, 16-bit sampling ADC
with no missing codes, an internal conversion clock, and a
versatile serial interface port. The reference voltage, V
applied externally and can be set up to the supply voltage, VDD.
On the CNV rising edge, it samples the voltage difference
between the IN+ and IN− pins. The voltages on these pins
swing in opposite phase between 0 V and V

Its power scales linearly with throughput.
Using the SDI input, the SPI-compatible serial interface also

features the ability to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.

The AD7693 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.

06394-001

REF

IN+

AD7693

IN–

GND

Figure 2.

250
kSPS

+5

VDD

VIO

SDI

SCK

SDO

CNV

+1.8V TO VDD

3- OR 4-WIRE
INTERFACE
(SPI, DAISY CHAIN, CS)

400 kSPS
to
500 kSPS

AD7693

about V

REF

ADC
Driver

ADA4941-1
ADA4841-x

ADA4941-1
ADA4841-x

, is

REF

/2.

REF

6394-002

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2011 Analog Devices, Inc. All rights reserved.

AD7693

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Application Diagram........................................................................ 1

General Description......................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions........................... 7

Terminology...................................................................................... 8

Typical Performance Characteristics............................................. 9

Theory of Operation ......................................................................12

Circuit Information.................................................................... 12

Converter Operation.................................................................. 12

Typical Connection Diagram ...................................................13

Analog Inputs..............................................................................14

Driver Amplifier Choice ........................................................... 14

Single-Ended-to-Differential Driver ....................................... 15

Voltage Reference Input ............................................................ 15

Power Supply............................................................................... 15

Supplying the ADC from the Reference.................................. 16

Digital Interface.......................................................................... 16

CS

Mode, 3-Wire Without Busy Indicator ............................. 17

CS

Mode, 3-Wire with Busy Indicator.................................... 18

CS

Mode, 4-Wire Without Busy Indicator ............................. 19

CS

Mode, 4-Wire with Busy Indicator.................................... 20

Chain Mode Without Busy Indicator...................................... 21

Chain Mode with Busy Indicator............................................. 22

Application Hints ...........................................................................23

Layout .......................................................................................... 23

Evaluating AD7693 Performance............................................. 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

6/11—Rev. 0 to Rev. A

Changes to Resolution Parameter and Common-Mode Input

Range Parameter in Table 2............................................................. 3

Changes to Figure 6 and Table 6..................................................... 7

Updated Outline Dimensions....................................................... 24

Changes to Ordering Guide.......................................................... 24

12/06—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD7693

SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 2.

Parameter Conditions/Comments Min Typ Max Unit

RESOLUTION 16 Bits
ANALOG INPUT

Voltage Range IN+ − (IN−) −V
Absolute Input Voltage IN+, IN− −0.1 V
Common-Mode Input Range IN+, IN− V
Analog Input CMRR fIN = 250 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance1

THROUGHPUT

Conversion Rate 0 500 kSPS
Transient Response Full-scale step 400 ns

ACCURACY

No Missing Codes 16 Bits
Integral Linearity Error −0.5 ±0.25 +0.5 LSB2
Differential Linearity Error −0.5 ±0.25 +0.5 LSB
Transition Noise REF = VDD = 5 V 0.35 LSB
Gain Error3 −20 ±0.5 +20 LSB
Gain Error Temperature Drift ±0.3 ppm/°C
Zero Error3 −5 ±0.5 +5 LSB
Zero Temperature Drift ±0.3 ppm/°C
Power Supply Sensitivity

AC ACCURACY4

Dynamic Range 96 96.5 dB5
Signal-to-Noise fIN = 1 kHz 95.5 96 dB
f
f
f
Signal-to-(Noise + Distortion) fIN = 1 kHz 95.5 96 dB
f
f
Total Harmonic Distortion fIN = 1 kHz −120 −108 dB
f
f
Spurious-Free Dynamic Range fIN = 1 kHz 120 dB
f
f
Intermodulation Distortion6 115 dB

1

See the Analog Inputs section.

2

LSB means least significant bit. With the ±5 V input range, one LSB is 152.6 μV.

3

See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.

4

With V

= 5 V, unless otherwise noted.

REF

5

All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

6

f

= 21.4 kHz and f

IN1

= 18.9 kHz, with each tone at −7 dB below full scale.

IN2

= VDD, all specifications T

REF

VDD = 5 V ± 5%

= 10 kHz 95.5 dB

IN

= 100 kHz 93 dB

IN

= 1 kHz, V

IN

= 10 kHz 95.5 dB

IN

= 100 kHz 90 dB

IN

= 10 kHz −113 dB

IN

= 100 kHz −92 dB

IN

= 10 kHz 114 dB

IN

= 100 kHz 93.5 dB

IN

= 2.5 V 93 dB

REF

to T

MIN

+V

REF

/2 – 0.1 V

REF

, unless otherwise noted.

MAX

/2 V

REF

V

REF

+ 0.1 V

REF

/2 + 0.1 V

REF

±1 ppm

Rev. A | Page 3 of 24

AD7693

VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 3.

Parameter Conditions/Comments Min Typ Max Unit

REFERENCE

Voltage Range 0.5 VDD + 0.3 V
Load Current 500 kSPS, REF = 5 V 100 μA

SAMPLING DYNAMICS

−3 dB Input Bandwidth 9 MHz
Aperture Delay VDD = 5V 2.5 ns

DIGITAL INPUTS

Logic Levels

VIL −0.3 +0.3 × VIO V
VIH 0.7 × VIO VIO + 0.3 V
IIL −1 +1 μA
IIH −1 +1 μA

DIGITAL OUTPUTS

Data Format

Pipeline Delay1
VOL I
VOH I

POWER SUPPLIES

VDD Specified performance 4. 5 5.5 V
VIO Specified performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V
Standby Current

2, 3

VDD and VIO = 5 V, 25°C 1 50 nA
Power Dissipation 100 SPS throughput 5 μW
100 kSPS throughput 4 mW
500 kSPS throughput 18 21.5 mW
Energy per Conversion 40 nJ

TEMPERATURE RANGE4

Specified Performance T

1

Conversion results available immediately after completed conversion.

2

With all digital inputs forced to VIO or GND as required.

3

During acquisition phase.

4

Contact an Analog Devices sales representative for the extended temperature range.

= VDD, all specifications T

REF

Serial 16 bits, twos

MIN

to T

, unless otherwise noted.

MAX

complement

= +500 μA 0.4 V

SINK

= −500 μA VIO − 0.3 V

SOURCE

to T

MIN

−40 +85 °C

MAX

Rev. A | Page 4 of 24

AD7693

TIMING SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 4.

1

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width (CS Mode)

SCK Period (CS Mode)
SCK Period (Chain Mode) t

VIO Above 4.5 V 17 ns
VIO Above 3 V 18 ns
VIO Above 2.7 V 19 ns

VIO Above 2.3 V 20 ns
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t

VIO Above 4.5 V 14 ns

VIO Above 3 V 15 ns

VIO Above 2.7 V 16 ns

VIO Above 2.3 V 17 ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO Above 4.5 V 15 ns

VIO Above 2.7 V 18 ns

VIO Above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with Busy Indicator) t

VIO Above 4.5 V 15 ns

VIO Above 2.3 V 26 ns

1

See Figure 3 and Figure 4 for load conditions.

= VDD, all specifications T

REF

MIN

t
t

t

t
t
t

to T

CONV

ACQ

CYC

CNVH

SCK

SCK

SCKL

SCKH

HSDO

DSDO

EN

DIS

SSDICNV

HSDICNV

SSCKCNV

HSCKCNV

SSDISCK

HSDISCK

DSDOSDI

, unless otherwise noted.

MAX

0.5 1.6 μs

400 ns

2.0 μs
10 ns

15 ns

7 ns

7 ns

4 ns

25 ns

15 ns

0 ns
5 ns

10 ns

4 ns

4 ns

Rev. A | Page 5 of 24

AD7693

T

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs

IN+,1 IN−1

GND − 0.3 V to VDD + 0.3 V

or ±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages

VDD, VIO to GND −0.3 V to +7 V

VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance (MSOP-10) 200°C/W
θJC Thermal Impedance (MSOP-10) 44°C/W
Lead Temperature Range JEDEC J-STD-20

1

See the Analog Inputs section.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

O SDO

50pF

C

L

500µA I

500µA I

OL

1.4V

OH

6394-003

Figure 3. Load Circuit for Digital Interface Timing

30% VIO

t

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

12V IF VI O ABOVE 2. 5V, VIO – 0.5V IF VIO BEL OW 2.5V .

20.8V IF V IO ABOVE 2.5V, 0.5V IF VI O BELOW 2.5V.

Figure 4. Voltage Levels for Timing

70% VIO

t

1

2

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

1

2

06394-004

Rev. A | Page 6 of 24

AD7693

G

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

REF

VDD

IN+

IN–

GND

1

2

AD7693

3

TOP VIEW

(Not to Scale)

4

5

VIO

10

SDI

9

SCK

8

SDO

7

6

CNV

06394-005

Figure 5. 10-Lead MSOP Pin Configuration

1REF

2VDD

AD7693

3IN+

TOP VIEW

4IN–

(Not to Scale)

5

ND

NOTES

1. THE EXPOSED PAD IS CONNECTED
TO GND. THIS CONNECTION I S NOT

REQUIRED TO MEET THE ELECTRICAL
PERFORMANCES.

Figure 6. 10-Lead QFN (LFCSP) Pin Configuration

10 VIO

9SDI

8SCK

7SDO

6CNV

05793-006

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1 REF AI

Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This

pin should be decoupled closely to the pin with a 10 μF capacitor.
2 VDD P Power Supply.
3 IN+ AI
4 IN− AI
5 GND P
6 CNV DI

Differential Positive Analog Input.

Differential Negative Analog Input.

Power Supply Ground.

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions

and selects the interface mode of the part: chain or CS

read when CNV is high. In CS

mode, the SDO pin is enabled when CNV is low.

mode. In chain mode, the data should be

7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI

Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this

clock.
9 SDI DI

Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC

as follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a

data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line.

The digital data level on SDI is output on SDO with a delay of 16 SCK cycles.

mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV

CS

can enable the serial output signals when low and if SDI or CNV is low when the conversion is

complete, the busy indicator feature is enabled.
10 VIO P

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,

2.5 V, 3 V, or 5 V).

EPAD

Exposed Pad. The exposed pad is connected to GND. This connection is not required to meet

the electrical performances. The exposed pad is only on the 10-Lead QFN (LFCSP).

1

AI = analog input, DI = digital input, DO = digital output, and P = power.

Rev. A | Page 7 of 24

AD7693

TERMINOLOGY

Least Significant Bit (LSB)

The LSB is the smallest increment that can be represented by a
converter. For a differential analog-to-digital converter with N
bits of resolution, the LSB expressed in volts is

V

2

LSB

(V) =

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 26).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.

Zero Error

Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.

Gain Error

The first transition (from 100 ... 00 to 100 ... 01) should occur at
a level ½ LSB above nominal negative full scale (−4.999847 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999771 V for the ±5 V range.) The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition
from the difference between the ideal levels.

Aperture Delay

Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.

2

REF

N

Transi ent Res p ons e

Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:

ENOB = (SINAD

and is expressed in bits.

− 1.76)/6.02

dB

Rev. A | Page 8 of 24

AD7693

–

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 65536

16384 32768 49152

Figure 7. Integral Nonlinearity vs. Code

POSITIVE INL = +0.17LSB
NEGATIVE INL = –0. 17LSB

CODE

= VDD, TA = 25C.

REF

06394-007

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 65536

16384 32768 49152

POSITIVE DNL = +0. 22LSB
NEGATIVE DNL = –0.22L SB

CODE

06394-010

Figure 10. Differential Nonlinearity vs. Code

300000

258774

250000

200000

150000

COUNTS

100000

50000

00 00

0

67

1905

8 9 ABC

CODE IN HEX

441

6394-008

Figure 8. Histogram of a DC Input at the Code Center

0

–20

–40

–60

–80

–100

–120

–140

AMPLITUDE ( dB of Full Scal e)

–160

–180

02

40 6020 16014012010080 180

FREQUENCY (kHz)

f

= 500kSPS

S

f

= 0.95kHz

IN

SNR = 96.4dB
THD = –121dB
SFDR = 124dB
SINAD = 96.4dB

00

06394-009

160000

140000

120000

100000

80000

COUNTS

60000

40000

20000

00 0

0

7

Figure 11. Histogram of a DC Input at the Code Transition

100

99

98

97

96

95

SNR (dB)

94

93

92

91

90

–10 –8 –6 –4 –2 0

Figure 9. FFT Plot

135054

126066

00

89ABCD

CODE IN HEX

SNR

THD

INPUT LEVEL (dB)

Figure 12. SNR, THD vs. Input Level

80

–85

–90

–95

–100

–105

–110

–115

–120

–125

–130

6394-011

THD (dB)

6394-012

Rev. A | Page 9 of 24

AD7693

–

–

–

100

99

98

97

96

95

94

SNR, SINAD (dB)

93

92

91

90

2.0 2.53.03.54.04.55.0 5.5

SNR, SINAD

ENOB

REFERENCE VOL TAGE (V)

Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage

20.0

19.5

19.0

18.5

18.0

17.5

17.0

16.5

16.0

15.5

15.0

80

–85

–90

–95

–100

–105

THD (dB)

ENOB (Bits)

06394-013

–110

–115

–120

–125

–130

2.0 5.5

2.53.03.54.04.55.0

REFERENCE VOL TAGE (V)

SFDR

THD

Figure 16. THD, SFDR vs. Reference Voltage

130

125

120

115

110

105

100

95

90

85

80

SFDR (dB)

06394-016

100

99

98

97

96

95

94

SNR, SINAD (dB)

93

92

91

90

–55 –35 –15 5 25 45 65 85 105 125

SNR, SINAD

ENOB

TEMPERATURE ( °C)

Figure 14. SNR, SINAD, and ENOB vs. Temperature

100

98

96

94

92

90

88

SNR, SINAD (dB)

86

84

82

80

0 50 100 150 200

VIN = –10dBFS

= –1dBFS

V

IN

FREQUENCY (kHz)

Figure 15. SINAD vs. Frequency

20.0

19.5

19.0

18.5

18.0

17.5

17.0

16.5

16.0

15.5

15.0

100

= 5V

V

DD

–105

–110

–115

ENOB (Bits)

06394-014

THD (dB)

–120

–125

–130

–55 –35 –15 5 25 45 65 85 105 125

SFDR

THD

TEMPERATURE (°C)

130

125

120

115

110

105

100

SFDR (dB)

06394-017

Figure 17. THD, SFDR vs. Temperature

80

–85

–90

–95

–100

–105

THD (dB)

–110

–115

–120

–125

–130

0 50 100 150 200

06394-015

= –1dBFS

V

IN

VIN = –10dBFS

FREQUENCY (kHz)

06394-018

Figure 18. THD vs. Frequency

Rev. A | Page 10 of 24

AD7693

1000

800

600

f

= 100kSPS

S

VDD

1000

800

600

400

OPERATING CURRENT (µA)

200

VIO

0

4.50 4. 75 5. 00 5. 25

SUPPLY (V)

Figure 19. Operating Currents vs. Supply

1000

f

= 100kSPS

S

800

600

400

OPERATING CURRENT (µA)

200

0

–55 –35 –15 –5 25 45 65 85 105 125

VDD

VIO

TEMPERATURE (°C)

Figure 20. Operating Currents vs. Temperature

5.50

400

POWER-DOW N CURRENT (nA)

200

VDD + VIO

0
–55 125105856545255–15–35

06394-019

TEMPERATURE (°C)

06394-022

Figure 22. Power-Down Currents vs. Temperature

1.0

0.5

ZERO ERROR

0

GAIN ERROR

–0.5

ZERO, GAIN ERROR (LSB)

–1.0

–55 –35 –15 5 25 45 65 85 105 125

06394-020

TEMPERATURE ( °C)

06394-023

Figure 23. Zero Error and Gain Error vs. Temperature

10k

1k

100

10

1

OPERATING CURRENT (µA)

0.1

0.01
10 1M100k10k1k100

VDD

VIO

SAMPLING RAT E (SPS)

Figure 21. Operating Currents vs. Sample Rate

06394-021

Rev. A | Page 11 of 24

DELAY (ns)

DSDO

t

25

20

15

10

5

0

Figure 24. t

VDD = 5V, 85° C

VDD = 5V, 25°C

SDO CAPACITI VE LOAD (pF)

Delay vs. Capacitance Load and Supply

DSDO

1200 20406080100

6394-031

AD7693

+

THEORY OF OPERATION

IN

SWITCHES CO NTROL

SW+MSB

LSB

REF

GND

16,384C

16,384C

4C 2C C C32,768C

COMP

4C 2C C C32,768C

SW–MSB

LSB

CONTROL

LOGIC

CNV

BUSY

OUTPUT CODE

IN–

Figure 25. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7693 is a fast, low power, single-supply, precise, 16-bit
ADC using a successive approximation architecture.

The AD7693 is capable of converting 500,000 samples per
second (500 kSPS) and powers down between conversions.
When operating at 1 kSPS, for example, it consumes 40 μW
typically, ideal for battery-powered applications.

The AD7693 provides the user with an on-chip track-and-hold
and does not exhibit pipeline delay or latency, making it ideal
for multiple multiplexed channel applications.

The AD7693 is specified from 4.5 V to 5.5 V and can be
interfaced to any 1.8 V to 5 V digital logic family. It is housed in
a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines
space savings and allows flexible configurations.

It is pin-for-pin compatible with the 16-bit AD7687 and

AD7688 and with the 18-bit AD7690 and AD7691.

CONVERTER OPERATION

The AD7693 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors, which are
connected to the two comparator inputs.

6394-024

During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.

Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
IN+ and IN− inputs captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary-weighted voltage steps (V

REF

/2, V

REF

/4 ... V

/32,768).

REF

The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part returns to the
acquisition phase, and the control logic generates the ADC
output code and a busy signal indicator.

Because the AD7693 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.

Rev. A | Page 12 of 24

AD7693

V

Transfer Functions

The ideal transfer characteristic for the AD7693 is shown in
Figure 26 and Tabl e 7.

011...111

011...110

011...101

ADC CODE (TWO S COMPLEM ENT)

100...010

100...001

100...000

–FSR

–FSR + 1LSB

–FSR + 0.5LSB

+FSR – 1.5LSB

ANAL OG INP UT

+FSR – 1LSB

Figure 26. ADC Ideal Transfer Function

1

REF

33Ω

2.7nF

4

33Ω

2.7nF

4

10µF

2

Figure 27. Typical Application Diagram with Multiple Supplies

0TO V

ADA4841-2

TO 0

REF

ADA4841-2

V+

V+

REF

3

V–

V+

3

V–

1

SEE REFERENCE SE CTION FOR REFERENCE SELECTIO N.

2

C

IS USUALLY A 10µF CERAMIC CAPACITOR (X5R) .

REF

3

SEE TABLE 8 F OR ADDITI ONAL RECOMM ENDED AMPLIFIERS.

4

OPTIONAL FILTER. SEE ANALOG INPUT SECTION.

5

SEE THE DIG ITAL INTERFACE SECT ION FOR MOST CONVE NIENT INTERFACE MODE.

IN+

IN–

6394-025

REF

GND

AD7693

Table 7. Output Codes and Ideal Input Voltages

Description

V

REF

= 5 V

FSR − 1 LSB +4.999847 V 0x7FFF1
Midscale + 1 LSB +152.6 μV 0x0001
Midscale 0 V 0x0000
Midscale − 1 LSB −152.6 μV 0xFFFF

−FSR + 1 LSB −4.999847 V 0x8001

−FSR −5 V 0x80002

1

This is also the code for an overranged analog input (V

2

This is also the code for an underranged analog input (V

Analog Input

Digital Output
Code (Hex)

− V

above V

IN+

IN−

− V

IN+

TYPICAL CONNECTION DIAGRAM

Figure 27 shows an example of the recommended connection
diagram for the AD7693 when multiple supplies are available.

5V

1.8V TO VDD

3- OR 4-WIRE INTERFACE

5

6394-026

VDD

VIO

100nF

100nF

SDI

SCK

SDO

CNV

below V

IN−

− V

REF

GND

GND

).

).

Rev. A | Page 13 of 24

AD7693

V

–

ANALOG INPUTS

Figure 28 shows an equivalent circuit of the input structure of
the AD7693.

The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal does not exceed the supply rails by more
than 0.3 V because this causes the diodes to become forward
biased and to start conducting current. These diodes can handle
a forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur when the input buffer’s
(U1) supplies are different from VDD. In such a case, for
example, an input buffer with a short circuit, the current
limitation can be used to protect the part.

DD

IN+

OR IN–

GND

D1

C

PIN

D2

R

Figure 28. Equivalent Analog Input Circuit

The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.

100

95

90

85

80

75

70

CMRR (dB)

65

60

55

50

1 10 100 1000 10000

FREQUENCY (kHz)

Figure 29. Analog Input CMRR vs. Frequency

During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination
of the capacitor, C
connection of R
R

is typically 600 Ω and is a lumped component made up of

IN

, and the network formed by the series

PIN

and CIN. C

IN

is primarily the pin capacitance.

PIN

serial resistors and the on resistance of the switches. C
typically 30 pF and is mainly the ADC sampling capacitor.

During the conversion phase, where the switches are opened,
the input impedance is limited to C

. RIN and CIN make a 1-pole,

PIN

low-pass filter that reduces undesirable aliasing effects and
limits the noise.

When the source impedance of the driving circuit is low, the
AD7693 can be driven directly. Large source impedances
significantly affect the ac performance, especially total

C

IN

IN

VREF = 5V

06394-027

06394-028

is

IN

Rev. A | Page 14 of 24

harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency.

80

VDD = 5V

–85

–90

–95

–100

–105

THD (dB)

–110

–115

–120

–125

–130

0 102030405060708090

250Ω

100Ω

50Ω

33Ω

FREQUENCY (kHz)

6394-047

Figure 30. THD vs. Analog Input Frequency and Source Resistance

DRIVER AMPLIFIER CHOICE

Although the AD7693 is easy to drive, the driver amplifier must
meet the following requirements:

• The noise generated by the driver amplifier needs to be

kept as low as possible to preserve the SNR and transition
noise performance of the AD7693. The noise coming from
the driver is filtered by the AD7693 analog input circuit’s
1-pole, low-pass filter made by R
external filter, if one is used. Because the typical noise of
the AD7693 is 56 μV rms, the SNR degradation due to the
amplifier is

⎛
⎜

SNR

LOSS

=

⎜

log20

⎜

2

⎜

56

⎜
⎝

where:

f

is the input bandwidth in megahertz of the AD7693

−3 dB

(9 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in
buffer configuration).

e

is the equivalent input noise voltage of the op amp,

N

in nV/√Hz.

• For ac applications, the driver should have a THD

performance commensurate with the AD7693.

• For multichannel multiplexed applications, the driver

amplifier and the AD7693 analog input circuit must settle
for a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the amplifier’s data sheet, settling at

0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.

and CIN or by the

IN

π

dB3

2

56

π

2

++

)(

−−

2

)(

NefNef

dB3

NN

2

⎞
⎟

⎟
⎟
⎟

⎟
⎠

AD7693

±

Table 8. Recommended Driver Amplifiers

Amplifier Typical Application

ADA4941-1 Very low noise, low power single to differential
ADA4841-x Very low noise, small, and low power
AD8655 5 V single supply, low noise
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8605, AD8615 5 V single supply, low power

SINGLE-ENDED-TO-DIFFERENTIAL DRIVER

For applications using a single-ended analog signal, either
bipolar or unipolar, the
driver allows for a differential input into the part. The
schematic is shown in Figure 31.

R1 and R2 set the attenuation ratio between the input range and
the ADC range (V
the desired input resistance, signal bandwidth, antialiasing and
noise contribution. For example, for the ±10 V range with a 4 kΩ
impedance, R2 = 1 kΩ and R1 = 4 kΩ.

R3 and R4 set the common mode on the IN− input, and R5 and
R6 set the common mode on the IN+ input of the ADC. The
common mode should be set close to V
supply is desired, it can be set slightly above V
some headroom for the
for the ±10 V range with a single supply, R3 = 8.45 kΩ, R4 =

11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ.

R5

R3

100nF

100nF

10V, ±5V, ...

R1

Figure 31. Single-Ended-to-Differential Driver Circuit

ADA4941-1 single-ended-to-differential

). R1, R2, and CF are chosen depending on

REF

/2; however, if single

REF

/2 to provide

REF

ADA4941-1 output stage. For example,

R6

R4

2.7nF

2.7nF

10µF

IN+

IN–

+5.2V

R2

C

33Ω

33Ω

ADA4941

F

REF

AD7693

GND

+5V REF

+5.2V

VDD

06394-029

If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using low temperature drift ADR43x and ADR44x
references.

If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially DNL.

Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.

POWER SUPPLY

The AD7693 uses two power supply pins: a core supply, VDD,
and a digital input/output interface supply, VIO. VIO allows
direct interface with any logic between 1.8 V and VDD. To
reduce the supplies needed, the VIO and VDD pins can be tied
together. The AD7693 is independent of power supply sequencing
between VIO and VDD. Additionally, it is very insensitive to
power supply variations over a wide frequency range, as shown
in Figure 32.

100

95

90

85

80

75

PSRR (dB)

70

65

60

55

50

1 10 100 1000 10000

FREQUENCY (kHz)

Figure 32. PSRR vs. Frequency

The AD7693 powers down automatically at the end of each
conversion phase; therefore, the operating currents and power
scale linearly with the sampling rate (refer to Figure 21). This
makes the part ideal for low sampling rates (even of a few hertz)
and low battery-powered applications.

VREF = 5V

06394-030

VOLTAGE REFERENCE INPUT

The AD7693 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.

When REF is driven by a very low impedance source (for
example, a reference buffer using the AD8031 or the AD8605),
a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate
for optimum performance.

Rev. A | Page 15 of 24

AD7693

SUPPLYING THE ADC FROM THE REFERENCE

For simplified applications, the AD7693, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 33. The reference line can be driven by

• The system power supply directly

• A reference voltage with enough current output capability,

such as the ADR43x

• A reference buffer, such as the AD8031, which can also

filter the system power supply, as shown in Figure 33.

5V

10kΩ

5V

1µF

1

OPTIONAL REFE RENCE BUFFER AND FILTER.

AD8031

Figure 33. Example of an Application Circuit

5V

10Ω

10µF 1µF

1

AD7693

VIOREF VDD

06394-032

DIGITAL INTERFACE

Generally, a user is interested in either minimizing the wiring
complexity of a multichannel ADC system or communicating
with the parts via a specific interface standard. Although the
ADC has only four digital pins (CNV, SCK, SDI, and SDO), it
offers a significantly flexible serial interface, including
compatibility with SPI, QSPI, digital hosts, and DSPs (such as
Blackfin® ADSP-BF53x or ADSP-219x). By configuring the
ADC into one of six modes, virtually any serial interface
scenario can be accommodated.

For wiring efficiency, the best way to configure a multichannel,
simultaneous-sampling system is to use the 3-wire chain mode.
This system is easily created by cascading multiple (M) ADCs
into a shift register structure. The CNV and CLK pins are
common to all ADCs, and the SDO of one part feeds the SDI of
the next part in the chain. The 3-wire interface is simply the
CNV, SCK, and SDO of the last ADC in the chain. For a system
containing M- and N-bit converters, the user needs to provide
M × N SCK transitions to read back all of the data. This 3-wire
interface is also ideally suited for isolated applications.

Additional flexibility is provided by optionally configuring the
ADCs to provide a busy indication. Without a busy indication,
the user must externally timeout the maximum ADC
conversion time before commencing readback. This
configuration is described in the Chain Mode Without Busy
Indicator section. With the busy indication enabled, external
timer circuits are not required because the SDO at the end of
the chain provides a low-to-high transition (that is, a start bit)
when all of the chain members have completed their
conversions and are ready to transmit data. However, one
additional SCK is required to flush the SDO busy indication

prior to reading back the data. This configuration is described
in the Chain Mode with Busy Indicator section.

The primary limitations of 3-wire chain mode are that all ADCs
are simultaneously sampled and the user cannot randomly
select an individual ADC for readback. This can be overcome
only by increasing the number of wires (for example, one chip
select wire per ADC). To operate with this increased
functionality, the part must be used in

CS

Mode. CS mode is
separated into two categories (3-wire and 4-wire) whereby
flexibility is traded off for wiring complexity. In

CS

4-wire
mode, the user has independent control over the sampling
operation (via CNV) and the chip select operation (via SDI) for
each ADC. In

CS

3-wire mode, SDI is unused (tied high) and
CNV is used to both sample the input and chip select the part
when needed. As with chain mode, the parts can optionally be
configured to provide a busy indication, but at the expense of
one additional SCK when reading back the data. So in total
there are four

CS

modes: 3-wire and 4-wire modes, each with

busy and without busy.
There is no elaborate writing of configuration words into the

part via the SDI pin. The mode in which the part operates is
defined by ensuring a specific relationship between the CNV,
SDI, and SCK inputs at key times. To select

CS

mode, ensure
that SDI is high at the rising edge of CNV; otherwise, chain
mode will be selected. Once in

CS

mode, selecting the part for
readback before the conversion is complete (by bringing either
SDI or CNV low) instructs the part to provide a busy indicator,
a high-to-low impedance transition on SDO, to tell the user
when the conversion has finished. If the part is selected after the
conversion has finished, SDO outputs the MSB when it is
selected. In chain mode, the busy indicator, a low-to-high
transition on SDO, is selected based on the state of SCK at the
rising edge of CNV. If SCK is high, the busy indicator is
enabled; otherwise, the busy indicator is not enabled.

The following sections provide specifics for each of the different
serial interface modes. Note that in the following sections, the
timing diagrams indicate digital activity (SCK, CNV) during
conversion. However, due to the possibility of performance
degradation, digital activity should only occur during the first
quarter of the conversion phase because the AD7693 provides
error correction circuitry that can correct for an incorrect bit
during this time. The user should initiate the busy indicator if
desired during this time. It is also possible to corrupt the sample
by having SCK or SDI transitions near the sampling instant.
Therefore, it is recommended to keep the digital pins quiet for
approximately 30 ns before and 10 ns after the rising edge of
CNV. The exception is when the device is in the chain mode
with busy configuration, where SDI is tied to CNV, because this
scenario does not yield a corrupted sample. To this extent, it is
recommended, to use a discontinuous SCK whenever possible to
avoid any potential performance degradation.

Rev. A | Page 16 of 24

AD7693

V

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 34, and the corresponding timing is given in
Figure 35.

With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the

impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This could be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be

mode, and forces SDO to high

CS

returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to
avoid the generation of the busy signal indicator. When the
conversion is complete, the AD7693 enters the acquisition
phase and powers down. When CNV goes low, the MSB is
output onto SDO. The remaining data bits are clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the

th

16

SCK falling edge or when CNV goes high (whichever

occurs first), SDO returns to high impedance.

CONVERT

SDI = 1

CNV

SCK

SDO

t

CNVH

t

CONV

CONVERSIONACQUISITI ON

Figure 35.

IO

AD7693

Figure 34.

CNV

SDOSDI

SCK

CS

Mode, 3-Wire Without Busy Indicator

DIGITAL HOST

DATA IN

CLK

06394-033

Connection Diagram (SDI High)

t

CYC

t

ACQ

ACQUISITI ON

t

SCK

t

SCKL

123 141516

t

HSDO

t

EN

D15 D14 D13 D1 D0

CS

Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)

t

DSDO

t

SCKH

t

DIS

06394-034

Rev. A | Page 17 of 24

AD7693

V

CS MODE, 3-WIRE WITH BUSY INDICATOR

This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host having an interrupt input.

The connection diagram is shown in Figure 36, and the
corresponding timing is given in Figure 37.

With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high

CS

mode, and forces SDO to high

IO

CNV

AD7693

SCK

SDOSDI

impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7693 then
enters the acquisition phase and powers down. The data bits are
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge will allow a faster reading rate, provided it has an
acceptable hold time. After the optional 17

th

SCK falling edge or
when CNV goes high (whichever occurs first), SDO returns to
high impedance.

If multiple AD7693s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.

CONVERT

VIO

DIGITAL HOST

DATA IN

IRQ

SDI = 1

CNV

SCK

SDO

t

CNVH

t

CONV

CONVERSIONACQUISITION

Figure 37.

Figure 36.

CLK

CS

Mode, 3-Wire with Busy Indicator

6394-035

Connection Diagram (SDI High)

t

CYC

t

ACQ

ACQUISITI ON

t

SCK

t

SCKL

123 151617

t

HSDO

t

D15 D14 D1 D0

CS

Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)

DSDO

t

SCKH

t

DIS

6394-036

Rev. A | Page 18 of 24

AD7693

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when multiple AD7693s are
connected to an SPI-compatible digital host.

A connection diagram example using two AD7693s is shown in
Figure 38, and the corresponding timing is given in Figure 39.

With SDI high, a rising edge on CNV initiates a conversion,
selects the

mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion

mode, and forces SDO to high impedance. In this

CS

time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7693 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the

th

16

SCK falling edge or when SDI goes high (whichever occurs
first), SDO returns to high impedance and another AD7693 can
be read.

CS2
CS1
CONVERT

CNV

SCK

Figure 38.

SDOSDI

CS

Mode, 4-Wire Without Busy Indicator Connection Diagram

CNV

AD7693AD7693

SDOSDI

SCK

DIGITAL HOST

DATA IN
CLK

6394-037

t

CYC

CNV

t

ACQ

ACQUISITION

17 1816

D0 D16 D15

t

DIS

6394-038

t

SSDICNV

SDI(CS1)

SDI(CS2)

SCK

SDO

t

HSDICNV

t

CONV

CONVERS IONACQUISITION

t

SCK

t

SCKL

t

DSDO

14 15

t

SCKH

D1

123 303132

t

t

EN

HSDO

D15 D14 D13 D1 D0

CS

Figure 39.

Mode, 4-Wire Without Busy Indicator Serial Interface Timing

Rev. A | Page 19 of 24

AD7693

CS MODE, 4-WIRE WITH BUSY INDICATOR

This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host with an interrupt input and it
is desired to keep CNV, which is used to sample the analog
input, independent of the signal used to select the data reading.
This requirement is particularly important in applications
where low jitter on CNV is desired.

The connection diagram is shown in Figure 40, and the
corresponding timing is given in Figure 41.

With SDI high, a rising edge on CNV initiates a conversion,
selects the
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,

CS

mode, and forces SDO to high impedance. In this

CNV

AD7693

SCK

SDOSDI

but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7693
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge will allow a faster reading rate, provided it has an
acceptable hold time. After the optional 17

th

SCK falling edge,
or when SDI goes high (whichever occurs first), SDO returns to
high impedance.

CS1
CONVERT

VIO

DIGITAL HOST

DATA IN

IRQ

CNV

t

SDI

SCK

SDO

SSDICNV

t

HSDICNV

CONVERSIONACQUISITI ON

Figure 40.

t

CONV

t

EN

Figure 41.

CLK

CS

Mode, 4-Wire with Busy Indicator Connection Diagram

t

CYC

t

ACQ

ACQUISITI ON

t

SCK

t

SCKL

1 2 3 15 16 17

t

HSDO

t

DSDO

D15 D14 D1 D0

CS

Mode, 4-Wire with Busy Indicator Serial Interface Timing

t

SCKH

06394-039

t

DIS

06394-040

Rev. A | Page 20 of 24

AD7693

CHAIN MODE WITHOUT BUSY INDICATOR

This mode can be used to daisy-chain multiple AD7693s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.

A connection diagram example using two AD7693s is shown in
Figure 42, and the corresponding timing is given in Figure 43.

When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data

readback. When the conversion is complete, the MSB is output
onto SDO and the AD7693 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge will allow a faster
reading rate and consequently more AD7693s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate can be reduced due to the total
readback time.

CONVERT

CNV

AD7693

A

SCK

SDOSDI

CNV

AD7693

B

SCK

DIGITAL HOST

SDOSDI

DATA IN

CLK

6394-041

Figure 42. Chain Mode Without Busy Indicator Connection Diagram

SDIA = 0

CNV

SCK

t

HSCKCNV

SDOA = SDI

SDO

t

CONV

CONVERSIONACQUISITION

t

t

SSCKCNV

1 2 3 30 31 32

t

t

EN

B

t

HSDO

t

DSDO

B

SSDISCK

DA15 DA14 DA13

DB15 DB14 DB13 DA1DB1DB0DA15 DA14

SCKL

t

Figure 43. Chain Mode Without Busy Indicator Serial Interface Timing

14 15

HSDISCK

t

CYC

ACQUISITI ON

t

SCK

DA1

t

t

SCKH

ACQ

DA0

17 1816

DA0

06394-042

Rev. A | Page 21 of 24

AD7693

CHAIN MODE WITH BUSY INDICATOR

This mode can also be used to daisy-chain multiple AD7693s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register.

A connection diagram example using three AD7693s is shown
in Figure 44, and the corresponding timing is given in Figure 45.

When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have

completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7693 ADC labeled C in Figure 44) is
driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7693 then enters the acquisition phase and powers
down. The data bits stored in the internal shift register are
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N + 1 clocks are required to
readback the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate and consequently more AD7693s in the
chain, provided the digital host has an acceptable hold time.

CONVERT

CNV = SDI

ACQUISITI ON

SCK

t

HSCKCNV

SDOA = SDI

= SDI

SDO

B

SDO

A

B

C

C

CNV

AD7693

A

SCK

t

CONV

CONVERSION

t

SSCKCNV

t

EN

t

DSDOSDI

t

DSDOSDI

CNV

SDOSDI

AD7693

B

SCK

SDOSDI

CNV

AD7693

C

SCK

SDOSDI

DIGITAL HOST

DATA IN

IRQ

CLK

06394-043

Figure 44. Chain Mode with Busy Indicator Connection Diagram

t

CYC

t

ACQ

ACQUISITION

t

t

SCKH

123 35 47 48

t

SSDISCK

DA15 DA14 DA13

t

HSDO

t

DSDO

DB15 DB14 DB13 DA1DB1DB0DA15 DA14

DC15 DC14 DC13 DA1DA0DC1DC0D

SCK

415

t

HSDISCK

DA1

t

SCKL

17 3416

DA0

19 31 3218

33

DA0

1DB0DA15DB15 DB14

D

B

14

A

t

DSDOSDI

t

DSDOSDI

t

49

DSDOSDI

Figure 45. Chain Mode with Busy Indicator Serial Interface Timing

06394-044

Rev. A | Page 22 of 24

AD7693

APPLICATION HINTS

LAYOUT

The printed circuit board that houses the AD7693 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7693, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.

Avoid running digital lines under the device because these
couple noise onto the die unless a ground plane under the
AD7693 is used as a shield. Fast switching signals, such as CNV
or clocks, should not run near analog signal paths. Crossover of
digital and analog signals should be avoided.

At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the AD7693s.

The AD7693 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.

Finally, the power supplies VDD and VIO of the AD7693
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7693 and connected using short, wide
traces to provide low impedance paths and reduce the effect of
glitches on the power supply lines.

An example of a layout following these rules is shown in
Figure 46 and Figure 47.

Figure 46. Example Layout of the AD7693 (Top Layer)

06394-045

EVALUATING AD7693 PERFORMANCE

Other recommended layouts for the AD7693 are outlined
in the documentation of the evaluation board for the AD7693
(EVAL-AD7693CB). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the

EVAL-CONTROL BRD3.

Figure 47. Example Layout of the AD7693 (Bottom Layer)

6394-046

Rev. A | Page 23 of 24

AD7693

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

6

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

0.10

1

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 48.10-Lead Mini Small Outline Package [MSOP]

3.10

3.00 SQ

2.90

5.15

4.90

4.65

5

15° MAX

6°
0°

0.23

0.13

0.30

0.15

1.10 MAX

(RM-10)

Dimensions shown in millimeters

2.48

2.38

2.23

0.70

0.55

0.40

0.50 BSC

091709-A

PIN 1 INDEX

AREA

0.80

0.75

0.70

SEATING

PLANE

TOP VIEW

0.30

0.25

0.20

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

6

EXPOSED

PAD

5

BOTTOM VIEW

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

10

1.74

1.64

1.49

1

N

1

P

I

R

C

I

A

O

T

N

I

D

)

5

1

.

R

0

(

121009-A

Figure 49. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Notes Temperature Range Package Description Package Option Branding Ordering Quantity

AD7693BCPZRL −40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 C4Y Reel, 5,000
AD7693BCPZRL7 −40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 C4Y Reel, 1,500
AD7693BRMZ −40°C to +85°C 10-Lead MSOP RM-10 C4Y Tube, 50
AD7693BRMZRL7 −40°C to +85°C 10-Lead MSOP RM-10 C4Y Reel, 1,000
EVAL-AD7693CBZ
EVAL-CONTROL BRD2 3 Controller Board
EVAL-CONTROL BRD3 3 Controller Board

1

Z = RoHS Compliant Part.

2

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.

3

These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05793-0-6/11(A)

2

Evaluation Board

Rev. A | Page 24 of 24