Datasheet AD7691 Datasheet (ANALOG DEVICES)

18-Bit, 1.5 LSB INL, 250 kSPS PulSAR

V

Data Sheet

FEATURES

18-bit resolution with no missing codes
Throughput: 250 kSPS
INL: ±0.75 LSB typical, ±1.5 LSB maximum (±6 ppm of FSR)
Dynamic range: 102 dB typical @ 250 kSPS
Oversampled dynamic range: 125 dB @1 kSPS
Noise-free code resolution: 20 bits @ 1 kSPS
Effective resolution: 22.7 bits @ 1 kSPS
SINAD: 101.5 dB typical @ 1 kHz
THD: −125 dB typical @ 1 kHz
True differential analog input range: ±V

0 V to V

with V

REF

up to VDD on both inputs

REF

No pipeline delay
Single-supply 2.3 V to 5 V operation with

1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Ability to daisy-chain multiple ADCs
Optional busy indicator feature
Power dissipation

1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS

1.4 μW @ 2.5 V/100 SPS
Standby current: 1 nA
10-lead packages: MSOP (MSOP-8 size) and

3 mm × 3 mm QFN (LFCSP) (SOT-23 size)

Pin-for-pin compatible with the18-bit AD7690 and

16-bit AD7693, AD7688, and AD7687

APPLICATIONS

Battery-powered equipment
Data acquisitions
Seismic data acquisition systems
Instrumentation
Medical instruments

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

0 262144

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

65536 131072 196608

CODE

Figure 1. Integral Nonlinearity vs. Code, 5 V

REF

POSIT IVE INL = 0.43LSB
NEGATIVE INL = –0. 62LSB

06146-025

Differential ADC in MSOP/QFN

AD7691

APPLICATION DIAGRAM

+0.5V TO VDD

±10V, ±5V, ...

ADA4941

Table 1. MSOP, QFN (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR® ADC

Type

18-Bit True
Differential

16-Bit True
Differential

16-Bit
Pseudo
Differential

14-Bit
Pseudo
Differential

100
kSPS

AD7691 AD7690

AD7684 AD7687 AD7688

AD7680
AD7683

AD7940 AD7942 AD7946 ADA4841-1

250
kSPS

AD7685
AD7694

GENERAL DESCRIPTION

The AD7691 is an 18-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single power supply, VDD, between 2.3 V and 5 V. It
contains a low power, high speed, 18-bit sampling ADC with no
missing codes, an internal conversion clock, and a versatile
serial interface port. On the CNV rising edge, it samples the
voltage difference between the IN+ and IN− pins. The voltages
on these pins swing in opposite phases between 0 V and REF.
The reference voltage, REF, is applied externally and can be set
up to the supply voltage.

The part’s power scales linearly with throughput.
The SPI-compatible serial interface also features the ability,

using the SDI input, to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.

The AD7691 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2012 Analog Devices, Inc. All rights reserved.

+2.5V TO +5

IN+

IN–

SDI

SCK

SDO

GND

CNV

AD7691

Figure 2.

400 kSPS to
500 kSPS

AD7693
AD7686 AD7980 ADA4841-x

VIO

REF

VDD

+1.8V TO VDD

3- OR 4-WIRE
INTERFACE
(SPI, DAISY CHAIN, CS)

≥1000
kSPS

AD7982
AD7984

ADA4941-1

ADC
Driver

ADA4941-1
ADA4841-x

ADA4841-x

6146-001

AD7691 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Application Diagram........................................................................ 1

General Description......................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

Timing Specifications ..................................................................5

Absolute Maximum Ratings............................................................ 7

Thermal Resistance...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions........................... 8

Typical Performance Characteristics............................................. 9

Terminology.................................................................................... 13

Theory of Operation ......................................................................14

Circuit Information.................................................................... 14

Converter Operation.................................................................. 14

Typical Connection Diagram ...................................................15

Analog Inputs..............................................................................15

Driver Amplifier Choice ........................................................... 16

Single-to-Differential Driver ....................................................16

Voltage Reference Input ............................................................ 16

Power Supply............................................................................... 17

Supplying the ADC from the Reference.................................. 17

Digital Interface.......................................................................... 17

CS

Mode, 3-Wire Without Busy Indicator ............................. 18

CS

Mode, 3-Wire with Busy Indicator.................................... 19

CS

Mode, 4-Wire Without Busy Indicator ............................. 20

CS

Mode, 4-Wire with Busy Indicator.................................... 21

Chain Mode Without Busy Indicator...................................... 22

Chain Mode with Busy Indicator............................................. 23

Application Hints ...........................................................................24

Layout .......................................................................................... 24

Evaluating the AD7691 Performance...................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

REVISION HISTORY

3/12—Rev. B to Rev. C

Change to Table 9........................................................................... 14

Changes to Ordering Guide.......................................................... 25

7/11—Rev. A to Rev. B

Changes to Common-Mode Input Range Min Parameter ......... 3

Added EPAD Note to Figure 6 and Table 8................................... 8

Updated Outline Dimensions....................................................... 25

11/07—Rev. 0 to Rev. A

Deleted QFN Package in Development References.......Universal

Changes to Features, Applications, Figure 1 and Figure 2.......... 1

Changes to Accuracy, Table 2.......................................................... 3

Changes to Power Dissipation, Table 3.......................................... 4

Added Thermal Resistance Section ............................................... 7

Changes to Figure 22...................................................................... 11

Changes to Format......................................................................... 12

Changes to Terminology Section.................................................. 13

Changes to Format and Figure 29 ................................................15

Inserted Figure 31........................................................................... 15

Changes to Format......................................................................... 17

Changes to Figure 44...................................................................... 22

Changes to Figure 46...................................................................... 23

Updated QFN Outline Dimensions............................................. 25

Changes to Ordering Guide.......................................................... 25

7/06—Revision 0: Initial Version

Rev. C | Page 2 of 28

Data Sheet AD7691

SPECIFICATIONS

VDD = 2.3 V to 5.25 V, VIO = 2.3 V to VDD, V

Table 2.

Parameter Conditions/Comments Min Typ Max Unit

RESOLUTION 18 Bits
ANALOG INPUT

Voltage Range, V

IN

Absolute Input Voltage IN+, IN− −0.1 V
Common-Mode Input Range IN+, IN− V
Analog Input CMRR fIN = 250 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance1

THROUGHPUT

Conversion Rate VDD = 4.5 V to 5.25 V 0 250 kSPS
VDD = 2.3 V to 4.5 V 0 180 kSPS
Transient Response Full-scale step 1.8 s

ACCURACY

No Missing Codes 18 Bits
Integral Linearity Error −1.5 ±0.75 +1.5 LSB2
Differential Linearity Error −1 ±0.5 +1.25 LSB2
Transition Noise REF = VDD = 5 V 0.75 LSB2
Gain Error3 VDD = 4.5 V to 5.25 V −40 ±2 +40 LSB2
VDD = 2.3 V to 4.5 V −80 ±2 +80 LSB2
Gain Error Temperature Drift ±0.3 ppm/°C
Zero Error3 VDD = 4.5 V to 5.25 V −0.8 ±0.1 +0.8 mV
VDD = 2.3 V to 4.5 V −3.5 ±0.7 +3.5 mV
Zero Temperature Drift ±0.3 ppm/°C
Power Supply Sensitivity

AC ACCURACY4

Dynamic Range V
Oversampled Dynamic Range5 f
Signal-to-Noise fIN = 1 kHz, V
f
Spurious-Free Dynamic Range fIN = 1 kHz, V
Total Harmonic Distortion fIN = 1 kHz, V
Signal-to-(Noise + Distortion) fIN = 1 kHz, V
f
Intermodulation Distortion6 115 dB

1

See the Analog Inputs section.

2

LSB means least significant bit. With the ±5 V input range, one LSB is 38.15 µV.

3

See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.

4

All ac accuracy specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

5

Dynamic range obtained by oversampling the ADC running at a throughput fS of 250 kSPS, followed by postdigital filtering with an output word rate fO.

6

f

= 21.4 kHz and f

IN1

= 18.9 kHz, with each tone at −7 dB below full scale.

IN2

= VDD, all specifications T

REF

IN+ − (IN−) −V

VDD = 5 V ± 5%

= 5 V 101 102 dB

REF

= 1 kSPS 125 dB

IN

= 5 V 100 101.5 dB

REF

= 1 kHz, V

IN

= 1 kHz, V

IN

= 2.5 V 95 96.5 dB

REF

= 5 V −125 dB

REF

= 5 V −118 dB

REF

= 5 V 100 101.5 dB

REF

= 2.5 V 95 96.5 dB

REF

MIN

to T

, unless otherwise noted.

MAX

+V

REF

/2 − 0.1 V

REF

/2 V

REF

REF

+ 0.1 V

REF

/2 + 0.1 V

REF

±0.25 LSB2

V

Rev. C | Page 3 of 28

AD7691 Data Sheet

VDD = 2.3 V to 5.25 V, VIO = 2.3 V to VDD, V

Table 3.

Parameter Conditions/Comments Min Typ Max Unit

REFERENCE

Voltage Range 0.5 VDD + 0.3 V
Load Current 250 kSPS, REF = 5 V 60 µA

SAMPLING DYNAMICS

−3 dB Input Bandwidth 2 MHz
Aperture Delay VDD = 5 V 2.5 ns

DIGITAL INPUTS

Logic Levels

VIL −0.3 +0.3 × VIO V
VIH 0.7 × VIO VIO + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA

DIGITAL OUTPUTS

Data Format Serial 18-bit, twos complement
Pipeline Delay1

VOL I
VOH I

= +500 µA 0.4 V

SINK

= −500 µA VIO − 0.3 V

SOURCE

POWER SUPPLIES

VDD Specified performance 2.3 5.25 V
VIO Specified performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V
Standby Current

2, 3

VDD and VIO = 5 V, TA = 25°C 1 50 nA
Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.4 µW
VDD = 2.5 V, 100 kSPS throughput 1.35 mW
VDD = 2.5 V, 180 kSPS throughput 2.4 mW
VDD = 5 V, 100 kSPS throughput 4.24 5 mW
VDD = 5 V, 250 kSPS throughput 10.6 12.5 mW
Energy per Conversion 50 nJ/sample

TEMPERATURE RANGE4

Specified Performance T

1

Conversion results are available immediately after completed conversion.

2

With all digital inputs forced to VIO or GND as required.

3

During acquisition phase.

4

Contact an Analog Devices, Inc., sales representative for the extended temperature range.

MIN

to T

= VDD, all specifications T

REF

−40 +85 °C

MAX

MIN

to T

, unless otherwise noted.

MAX

Rev. C | Page 4 of 28

Data Sheet AD7691

TIMING SPECIFICATIONS

VDD = 4.5 V to 5.25 V, VIO = 2.3 V to VDD, V

Table 4.

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width (CS Mode)

SCK Period (CS Mode)
SCK Period (Chain Mode) t

VIO Above 4.5 V 17 ns
VIO Above 3 V 18 ns
VIO Above 2.7 V 19 ns

VIO Above 2.3 V 20 ns
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t

VIO Above 4.5 V 14 ns

VIO Above 3 V 15 ns

VIO Above 2.7 V 16 ns

VIO Above 2.3 V 17 ns
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)

VIO Above 4.5 V 15 ns

VIO Above 2.7 V 18 ns

VIO Above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with Busy Indicator) t

VIO Above 4.5 V 15 ns

VIO Above 2.3 V 26 ns

1

See Figure 3 and Figure 4 for load conditions.

= VDD, all specifications T

REF

to T

MIN

CONV

ACQ

CYC

t

CNVH

t

SCK

SCK

SCKL

SCKH

HSDO

DSDO

t

EN

t

25 ns

DIS

t

SSDICNV

t

HSDICNV

SSCKCNV

HSCKCNV

SSDISCK

HSDISCK

DSDOSDI

, unless otherwise noted.1

MAX

0.5 2.2 µs

1.8 µs

4 µs

10 ns

15 ns

7 ns

7 ns

4 ns

15 ns

0 ns
5 ns

10 ns

3 ns

4 ns

Rev. C | Page 5 of 28

AD7691 Data Sheet

VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, V

Table 5.

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode) t

VIO Above 3 V 29 ns
VIO Above 2.7 V 35 ns

VIO Above 2.3 V 40 ns
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t

VIO Above 3 V 24 ns

VIO Above 2.7 V 30 ns

VIO Above 2.3 V 35 ns
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)

VIO Above 2.7 V 18 ns

VIO Above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with Busy Indicator) t

1

See Figure 3 and Figure 4 for load conditions.

500µA I

TO SDO

50pF

C

L

500µA I

Figure 3. Load Circuit for Digital Interface Timing

OL

OH

= VDD, all specifications T

REF

1.4V

06146-002

MIN

CONV

ACQ

CYC

t

CNVH

t

SCK

SCK

SCKL

SCKH

HSDO

DSDO

t

EN

t

DIS

t

SSDICNV

t

HSDICNV

SSCKCNV

HSCKCNV

SSDISCK

HSDISCK

DSDOSDI

to T

, unless otherwise noted.1

MAX

0.5 3.7 µs

1.8 ns

5.5 µs
10 ns

25 ns

12 ns

12 ns

5 ns

25 ns

30 ns

0 ns
5 ns

8 ns

8 ns

10 ns

36

30% VIO

t

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

1

2V IF VI O ABOVE 2. 5V, VIO – 0.5V IF VIO BEL OW 2.5V.

2

0.8V IF V IO ABOVE 2.5V, 0.5V IF VI O BELOW 2.5V.

Figure 4. Voltage Levels for Timing

70% VIO

t

1

2

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

2

1

06146-003

Rev. C | Page 6 of 28

Data Sheet AD7691

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Analog Inputs (IN+, IN−)1

REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages

VDD, VIO to GND −0.3 V to +7 V

VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Lead Temperature Range JEDEC J-STD-20

1

See the Analog Inputs section.

GND − 0.3 V to VDD + 0.3 V
or ±130 mA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θJA θJC Unit

10-Lead MSOP 200 44 °C/W
10-Lead QFN (LFCSP) 43.4 6.5 °C/W

ESD CAUTION

Rev. C | Page 7 of 28

AD7691 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

REF

VDD

IN+

IN–

GND

1

2

AD7691

3

TOP VIEW

(Not to Scale)

4

5

VIO

10

SDI

9

SCK

8

SDO

7

CNV

6

06146-004

Figure 5. 10-Lead MSOP Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1 REF AI

Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin.

This pin should be decoupled closely to the pin with a 10 µF capacitor.
2 VDD P Power Supply.
3 IN+ AI

4 IN− AI

5 GND P
6 CNV DI

Differential Positive Analog Input. Referenced to IN−. The input range for IN+ is between 0 V and V

centered about V

/2 and must be driven 180° out of phase with IN−.

REF

Differential Negative Analog Input. Referenced to IN+. The input range for IN− is between 0 V and V

centered about V

/2 and must be driven 180° out of phase with IN+.

REF

Power Supply Ground.

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and

selects the interface mode of the part, either chain or CS

low. In chain mode, the data should be read when CNV is high.
7 SDO DO
8 SCK DI
9 SDI DI

Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.

Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.

Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to

daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on

SDI is output on SDO with a delay of 18 SCK cycles.

mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable

CS

the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the busy

indicator feature is enabled.
10 VIO P

Input/Output Interface Digital Power. Nominally at the same supply as the host interface

(1.8 V, 2.5 V, 3 V, or 5 V ).
EPAD

Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints, it is

recommended that the pad be soldered to the ground plane.

1

AI = analog input, DI = digital input, DO = digital output, and P = power.

1REF

2VDD

AD7691

3IN+

TOP VIEW

4IN–

(Not to Scale)

5GND

NOTES

1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALL Y. FO R INCREASED REL IABILI TY OF
THE SOL DER JOINTS , IT I S RECOMMENDED THAT
THE PAD BE SO LDERED TO THE GRO UND PLANE.

10 VI O

9SDI

8SCK

7SDO

6 CNV

Figure 6. 10-Lead QFN (LFCSP) Pin Configuration

mode. In CS mode, it enables the SDO pin when

06146-005

,

REF

,

REF

Rev. C | Page 8 of 28

Data Sheet AD7691

TYPICAL PERFORMANCE CHARACTERISTICS

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

0 262144

65536 131072 196608

POSIT IVE INL = 0.39LSB
NEGATIVE INL = –0. 73LSB

CODE

Figure 7. Integral Nonlinearity vs. Code 2.5 V

80k

2904

69769

28527

CODE IN HEX

27770

70k

60k

50k

40k

COUNTS

30k

20k

10k

0

0

25

26

0

26 27 28 29 2A 2B 2C 2D 2E 2F

VDD = REF = 5V
σ = 0.76LSB

2062

14

Figure 8. Histogram of a DC Input at the Code Center, 5 V

1.0

0.5

0

DNL (LSB)

–0.5

–1.0

0 262144

06146-026

65536 131072 196608

POSITIVE DNL = 0. 37LSB
NEGATIVE DNL = –0.33L SB

CODE

06146-029

Figure 10. Differential Nonlinearity vs. Code, 5 V

45k

40k

35k

30k

25k

20k

COUNTS

15k

10k

5k

0

0

06146-027

01229

0

2423 25 26 28 29 2B2A 2C 2D 2F2E 30 31

2997

501

27

38068

24411

14362

CODE IN HEX

28179

17460

VDD = REF = 2.5V
σ = 1.42LSB

4055

910

78 9 0

06146-030

Figure 11. Histogram of a DC Input at the Code Center, 2.5 V

–100

–120

–140

AMPLITUDE (dB of Full Scal e)

–160

–180

–20

–40

–60

–80

0

0

20 40 60 80 100 120

FREQUENCY (kHz)

32768 POINT FFT
VDD = REF = 5V

f

= 250kSPS

S

f

= 2kHz

IN

SNR = 101.4dB
THD = –120.1dB
2ND HARMONIC = –140. 7dB
3RD HARMONIC = –120. 3dB

06146-028

Figure 9. 2 kHz FFT Plot, 5 V

AMPLITUDE (dB of Full Scal e)

–20

–40

–60

–80

–100

–120

–140

–160

–180

0

0

2010 30 40 50 60 70 80 90

FREQUENCY (kHz)

32768 POINT FFT
VDD = REF = 2.5V

f

= 180kSPS

S

f

= 2kHz

IN

SNR = 96.4dB
THD = –120.3dB
2ND HARMONIC = –132.5d B
3RD HARMONIC = –121.2d B

06146-031

Figure 12. 2 kHz FFT Plot, 2.5 V

Rev. C | Page 9 of 28

AD7691 Data Sheet

–

–

–

104

102

100

98

96

94

SNR, SINAD (dB)

92

90

88

86

2.3 5.34.7 5.0

2.6 2.9 3.2 3.5 3.8 4.1 4.4

REFERENCE VOL TAGE (V)

Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage

SNR

ENOB

SINAD

18

17

16

ENOB (Bits)

15

14

06146-032

105

–110

–115

THD

–120

THD, SFDR (d B)

–125

–130

–135

2.3 5.3

2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0

SFDR

REFERENCE VOL TAGE (V)

06146-038

Figure 16. THD, SFDR vs. Reference Voltage

105

V

= 5V

REF

100

V

= 2.5V

REF

95

SNR (dB)

90

85

80

–35–155 25456585105

–55 125

TEMPERATURE (° C)

Figure 14. SNR vs. Temperature

105

100

95

90

85

SINAD (dB)

80

75

V

REF

V

= 5V, –10dB

= 2.5V, –1d B

REF

V

REF

V

= 2.5V, –10d B

REF

= 5V, –1dB

90

–100

–110

THD (dB)

–120

–130

–55 125

–35–155 25456585105

06146-033

V

= 5V

REF

V

= 2.5V

REF

TEMPERATURE (° C)

06146-039

Figure 17. THD vs. Temperature

60

–70

THD (dB)

–80

–90

–100

–110

–120

V

= 2.5V, –1d B

REF

V

REF

= 5V, –10dB

V

REF

V

= 2.5V, –10d B

REF

= 5V, –1dB

70

0 125

25 50 75 100

FREQUENCY (kHz)

Figure 15. SINAD vs. Frequency

06146-037

–130

0 125

25 50 75 100

FREQUENCY (kHz)

Figure 18. THD vs. Frequency

06146-040

Rev. C | Page 10 of 28

Data Sheet AD7691

–

105

102

SNR 5V

99

96

SNR 2.5V

90

–95

–100

–105

6

GAIN ERROR

4

2

93

SNR (dB)

90

87

84

81

–10 0

THD 5V

THD 2.5V

–8 –6 –4 –2

INPUT LEVEL (dB)

Figure 19. SNR, THD vs. Input Level

1000

750

500

250

OPERATING CURRENT (µA)

0

–55 –35 –15 5 25 45 65 85 105 125

VDD = 5V

VDD = 2.5V

VIO

TEMPERATURE (° C)

Figure 20. Operating Current vs. Temperature

f

=100kSPS

S

–110

–115

–120

–125

–130

0

THD (dB)

–2

OFFSET, GAIN ERROR (LSB)

–4

OFFSET ERROR

–6

–55 125

–35–155 25456585105

06146-041

TEMPERATURE (° C)

06146-044

Figure 22. Zero Error, Gain Error vs. Temperature

1000

750

500

250

POWER-DOW N CURRENT (nA)

VDD + VIO

0

–55 –35 –15 5 25 45 65 85 105 125

6146-042

Figure 23. Power-Down Current vs. Temperature

TEMPERATURE (° C)

6146-047

1000

f

=100kSPS

S

750

500

250

OPERATING CURRENT (µA)

0

2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3

VDD

VIO

SUPPLY (V)

Figure 21. Operating Current vs. Supply

6146-043

Rev. C | Page 11 of 28

DELAY (ns)

DSDO

t

25

20

15

10

5

0

Figure 24. t

VDD = 5V, 85° C

VDD = 5V, 25°C

SDO CAPACITI VE LOAD (pF)

Delay vs. Capacitance Load and Supply

DSDO

1200 20406080100

6146-034

AD7691 Data Sheet

95

90

85

80

PSRR (dB)

75

70

65

1 10000

10 100 1000

FREQUENCY (kHz)

06146-035

Figure 25. PSSR vs. Frequency

90

85

80

75

70

65

CMRR (dB)

60

55

50

45

40

1 10000

10 100 1000

FREQUENCY (kHz)

V

REF

= VDD = 5V

06146-036

Figure 26. Analog Input CMRR vs. Frequency

Rev. C | Page 12 of 28

Data Sheet AD7691

TERMINOLOGY

Least Significant Bit (LSB)

The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For an analog-to-digital
converter with N bits of resolution, the LSB expressed in volts is

V

LSB2)V( =

INpp

N

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 28).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.

Zero Error

Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.

Gain Error

The first transition (from 100 . . . 00 to 100 . . . 01) should occur
at a level ½ LSB above nominal negative full scale (−4.999981 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999943 V for the ±5 V range). The gain
error is the deviation in LSBs (or % of full-scale range) of the
difference between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels. The closely related full-scale error, which is
expressed also in LSBs or % of full-scale range, includes the
contribution from the zero error.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:

ENOB = (SINAD

− 1.76)/6.02

dB

and is expressed in bits.

Noise-Free Code Resolution

It is the number of bits beyond which it is impossible to resolve
individual codes distinctly. It is calculated as

Noise-Free Code Resolution = log

(2N/Peak-to-Peak Noise)

2

and is expressed in bits.

Effective Resolution

It is calculated as

Effective Resolution = log

(2N/RMS Input Noise)

2

and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.

Aperture Delay

Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.

Transi ent Res p ons e

Transient response is the time required for the ADC to acquire
its input accurately after a full-scale step function is applied.

Rev. C | Page 13 of 28

AD7691 Data Sheet

+

THEORY OF OPERATION

IN

SWITCHES CO NTROL

SW+MSB

LSB

REF

GND

65,536C

65,536C

4C 2C C C131,072C

COMP

4C 2C C C131,072C

SW–MSB

LSB

CONTRO L

LOGIC

BUSY

OUTPUT CODE

CNV

IN–

Figure 27. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7691 is a fast, low power, single-supply, precise, 18-bit
ADC using a successive approximation architecture.

The part is capable of converting 250,000 samples per second
(250 kSPS) and powers down between conversions. When
operating at 1 kSPS, for example, it consumes 50 µW typically,
which is ideal for battery-powered applications.

The AD7691 provides the user with an on-chip track-and-hold
and does not exhibit pipeline delay or latency, making it ideal
for multiple multiplexed channel applications.

The AD7691 is specified from 2.3 V to 5.25 V and can be
interfaced to any 1.8 V to 5 V digital logic family. It is housed in
a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines
space savings and allows flexible configurations.

The part is pin-for-pin compatible with the 18-bit AD7690 as
well as the 16-bit AD7687 and AD7688.

CONVERTER OPERATION

The AD7691 is a successive approximation ADC based on a
charge redistribution DAC. Figure 27 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary-weighted capacitors, which are
connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by

/2, V

binary-weighted voltage steps (V

REF

REF

/4 ... V

/262,144).

REF

Rev. C | Page 14 of 28

6146-024

The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part returns to the
acquisition phase, and the control logic generates the ADC
output code and a busy signal indicator.

Because the AD7691 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.

Transfer Functions

The ideal transfer characteristic for the AD7691 is shown in
Figure 28 and Tabl e 9.

011...111

011...110

011...101

ADC CODE (T WOS COMPL EMENT )

100...010

100...001

100...000

–FSR

–FSR + 1LSB

–FSR + 0.5L SB

+FSR – 1.5L SB

ANALOG INPUT

+FSR – 1LS B

06146-006

Figure 28. ADC Ideal Transfer Function

Table 9. Output Codes and Ideal Input Voltages

Description

Analog Input
V

= 5 V

REF

Digital Output
Code (Hex)

FSR − 1 LSB +4.999962 V 0x1FFFF1
Midscale + 1 LSB +38.15 µV 0x00001
Midscale 0 V 0x00000
Midscale − 1 LSB −38.15 µV 0x3FFFF

−FSR + 1 LSB −4.999962 V 0x20001

−FSR −5 V 0x200002

1

This is also the code for an overranged analog input (V

2

This is also the code for an underranged analog input (V

− V

above V

IN+

IN−

− V

IN+

below V

IN−

− V

REF

GND

GND

).

).

Data Sheet AD7691

V

TYPICAL CONNECTION DIAGRAM

Figure 29 shows an example of the recommended connection diagram for the AD7691 when multiple supplies are available.

REF

1

15Ω

2.7nF

4

15Ω

2.7nF

4

10µF

2

IN+

IN–

0 TO V

ADA4841-2

V

REF

ADA4841-2

V+

V+

REF

3

V–

V+

TO 0

3

V–

1

SEE VOLT AGE REFERENCE INPUT SECTION FOR RE FERENCE SELECTION.

2

C

IS USUALLY A 10µF CERAMIC CAPACITOR (X5R) .

REF

3

SEE TABLE 9 F OR ADDITI ONAL RECOMM ENDED AMPLIF IERS.

4

OPTIONAL FILTER. SEE ANALOG INPUT SECTION.

5

SEE THE DIG ITAL INTERFACE SECTION FOR MOST CONVE NIENT INT ERFACE MODE.

Figure 29. Typical Application Diagram with Multiple Supplies

ANALOG INPUTS

Figure 30 shows an equivalent circuit of the input structure of
the AD7691.

The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal does not exceed the supply rails by more
than 0.3 V because this causes the diodes to become forward
biased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur if the input buffer (U1)
supplies are different from VDD. In such a case (for example, an
input buffer with a short circuit), the current limitation can be
used to protect the part.

DD

IN+

OR IN–

GND

D1

C

PIN

D2

R

Figure 30. Equivalent Analog Input Circuit

The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.

During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination
of the capacitor, C
connection of R

is typically 3 kΩ and is a lumped component composed of

R

IN

, and the network formed by the series

PIN

and CIN. C

IN

is primarily the pin capacitance.

PIN

serial resistors and the on resistance of the switches. C
typically 30 pF and is mainly the ADC sampling capacitor.

C

IN

IN

06146-007

is

IN

REF

GND

VDD

AD7691

100nF

100nF

VIO

SDI

SCK

SDO

CNV

During the conversion phase, where the switches are opened,
the input impedance is limited to C
1-pole, low-pass filter that reduces undesirable aliasing effects
and limits noise.

When the source impedance of the driving circuit is low, the
AD7691 can be driven directly. Large source impedances
significantly affect the ac performance, especially total harmonic
distortion (THD). The dc performances are less sensitive to
the input impedance. The maximum source impedance
depends on the amount of THD that can be tolerated.

The THD degrades as a function of the source impedance and
the maximum input frequency as shown in Figure 31.

–80

V

–85

–90

–95

–100

–105

THD (dB)

–110

–115

–120

–125

–130

09

Figure 31. THD vs. Analog Input Frequency and Source Resistance

5V

1.8V TO V DD

3- OR 4-WIRE INTERFACE

= VDD 5V

REF

250Ω

100Ω

15Ω

50Ω

10 20 30 40 50 60 70 80 0

FREQUENCY (kHz)

5

06146-008

. RIN and CIN make a

PIN

33Ω

06146-009

Rev. C | Page 15 of 28

AD7691 Data Sheet

DRIVER AMPLIFIER CHOICE

Although the AD7691 is easy to drive, the driver amplifier must
meet the following requirements:

The noise generated by the driver amplifier needs to be kept as

low as possible to preserve the SNR and transition noise
performance of the AD7691. The noise coming from the
driver is filtered by the AD7691 analog input circuit’s
1-pole, low-pass filter made by R
external filter, if one is used. The SNR degradation due to
the amplifier is as follows:

=

SNR

LOSS

⎛
⎜

⎜

log20

⎜
⎜

NADC

⎝

π

2

−

dB3

2

where:

V

is the noise of the ADC, in V, given by the following:

NADC

V

INpp

10

SNR

20

22

V =

NADC

f

is the input bandwidth, in MHz, of the AD7691 (2 MHz)

−3 dB

or the cutoff frequency of the input filter, if one is used.
N is the noise gain of the amplifier (for example, 1 in
buffer configuration).

and eN− are the equivalent input noise voltage densities

e

N+

of the op amps connected to IN+ and IN−, in nV/√Hz.
This approximation can be used when the resistances around

the amplifier are small. If larger resistances are used, their
noise contributions should also be root-sum-squared.

For ac applications, the driver should have a THD performance

commensurate with the AD7691.

For multichannel multiplexed applications, the driver amplifier

and the AD7691 analog input circuit must settle for a full­scale step onto the capacitor array at an 18-bit level
(0.0004%, 4 ppm). In the amplifier’s data sheet, settling at

0.1% to 0.01% is more commonly specified. This may
differ significantly from the settling time at an 18-bit level
and should be verified prior to driver selection.

Table 10. Recommended Driver Amplifiers

Amplifier Typical Application

ADA4941-1

Very low noise, low power single-ended-to-

differential

ADA4841-x Very low noise, small, and low power
AD8655 5 V single supply, low noise
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8605, AD8615 5 V single supply, low power

and CIN or by the

IN

V

NADC

π

2

++

)(

+

2

⎞
⎟

⎟
⎟

2

⎟

)(

NefNefV

−

−

NN

dB3

⎠

Rev. C | Page 16 of 28

SINGLE-TO-DIFFERENTIAL DRIVER

For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941-1 single-ended-to-differential
driver allows for a differential input into the part. The schematic
is shown in Figure 32.

R5

R3

100nF

100nF

±10V, ±5V, . ..

Figure 32. Single-Ended-to-Differential Driver Circuit

R6

R4

2.7nF

2.7nF

10µF

IN+

IN–

+5.2V

15Ω

15Ω

ADA4941

R1

R2

C

F

REF

AD7691

GND

+5V REF

+5.2V

VDD

R1 and R2 set the attenuation ratio between the input range and
the ADC range (V

). R1, R2, and CF are chosen depending on

REF

the desired input resistance, signal bandwidth, antialiasing, and
noise contribution. For example, for the ±10 V range with a 4 kΩ
impedance, R2 = 1 kΩ and R1 = 4 kΩ.

R3 and R4 set the common mode on the IN− input, and R5 and
R6 set the common mode on the IN+ input of the ADC. The
common mode should be set close to V
supply is desired, it can be set slightly above V

/2; however, if single

REF

/2 to provide

REF

some headroom for the ADA4941-1 output stage. For example,
for the ±10 V range with a single supply, R3 = 8.45 kΩ, R4 =

11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ.

VOLTAGE REFERENCE INPUT

The AD7691 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.

When REF is driven by a very low impedance source, for
example, a reference buffer using the AD8031 or the AD8605, a
10 µF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.

If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.

If desired, smaller reference decoupling capacitor values as low
as 2.2 µF can be used with a minimal impact on performance,
especially DNL.

Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.

06146-010

Data Sheet AD7691

POWER SUPPLY

The AD7691 uses two power supply pins: a core supply (VDD) and
a digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and VDD. To reduce the
supplies needed, the VIO and VDD pins can be tied together. The
AD7691 is independent of power supply sequencing between VIO
and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 25.

The AD7691 powers down automatically at the end of each
conversion phase, and therefore, the power scales linearly with
the sampling rate. This makes the part ideal for low sampling
rate (as low as a few hertz) and low battery-powered applications.

1000

VDD = 5V

10

VIO

0.1

OPERATING CURRENT (µA)

0.001
10 1M

100 1k 100k10k

SAMPLING RATE (SPS)

Figure 33. Operating Current vs. Sample Rate

06146-045

SUPPLYING THE ADC FROM THE REFERENCE

For simplified applications, the AD7691, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 34. The reference line can be driven by

The system power supply directly.
A reference voltage with enough current output capability, such

as the ADR43x.

A reference buffer, such as the AD8031, which can also filter the

system power supply, as shown in Figure 34.

10kΩ

5V

1µF

1

OPTIO NAL REFERENCE BUFFER AND FI LTER.

DIGITAL INTERFACE

Though the AD7691 has a reduced number of pins, it offers
flexibility in its serial interface modes.

When in
digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or
ADSP-219x. In this mode, the AD7691 can use either a 3-wire
or 4-wire interface. A 3-wire interface using the CNV, SCK, and
SDO signals minimizes wiring connections and is useful, for
instance, in isolated applications. A 4-wire interface using the
SDI, CNV, SCK, and SDO signals allows CNV, which initiates
the conversions, to be independent of the readback timing
(SDI). This is useful in low jitter sampling or simultaneous
sampling applications.

When in chain mode, the AD7691 provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.

The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is selected.

In either mode, the AD7691 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must
timeout the maximum conversion time prior to readback.

The busy indicator feature is enabled
In the

In the chain mode if SCK is high during the CNV rising edge

CS

CS

mode if CNV or SDI is low when the ADC

conversion ends (see and ). Figure 38 Figure 42

(see Figure 46).

5V

AD8031

Figure 34. Example of an Application Circuit

5V

10Ω

10µF 1µF

1

AD7691

VIOREF VDD

06146-046

mode, the AD7691 is compatible with SPI, QSPI,

CS

mode is selected if

Rev. C | Page 17 of 28

AD7691 Data Sheet

V

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 35, and the corresponding timing is given in
Figure 36.

With SDI tied to VIO, a rising edge on CNV initiates a

CS

conversion, selects the
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for instance, to bring CNV low to select other SPI devices, such
as analog multiplexers, but CNV must be returned high before
the minimum conversion time elapses and then held high for
the maximum possible conversion time to avoid the generation
of the busy signal indicator. When the conversion is complete,
the AD7691 enters the acquisition phase and powers down.
When CNV goes low, the MSB is output onto SDO. The
remaining data bits are clocked by subsequent SCK falling

mode, and forces SDO to high

SDI = 1

t

CNVH

CNV

edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge can allow a faster reading rate, provided it has

th

an acceptable hold time. After the 18

SCK falling edge, or
when CNV goes high, whichever occurs first, SDO returns to
high impedance.

CONVERT

DIGITAL HOST

DATA IN

CLK

t

CYC

IO

AD7691

Figure 35. 3-Wire

CNV

SDOSDI

SCK

CS

Mode Without Busy Indicator

Connection Diagram (SDI High)

06146-011

SCK

SDO

t

CONV

CONVERSIONACQUISITION

Figure 36. 3-Wire

t

ACQ

ACQUISITION

t

SCK

t

SCKL

123 161718

t

HSDO

t

EN

D17 D16 D15 D1 D0

CS

Mode Without Busy Indicator Serial Interface Timing (SDI High)

t

DSDO

t

SCKH

t

DIS

06146-012

Rev. C | Page 18 of 28

Data Sheet AD7691

V

CS MODE, 3-WIRE WITH BUSY INDICATOR

This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host having an interrupt input.

The connection diagram is shown in Figure 37, and the
corresponding timing is given in Figure 38.

With SDI tied to VIO, a rising edge on CNV initiates a

CS

conversion, selects the
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7691 then
enters the acquisition phase and powers down. The data bits
are clocked out, MSB first, by subsequent SCK falling edges.

mode, and forces SDO to high

SDI = 1

t

CNVH

CNV

The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge can allow a faster reading rate, provided it has an

th

acceptable hold time. After the optional 19

SCK falling edge,
or when CNV goes high, whichever occurs first, SDO returns to
high impedance.

If multiple AD7691s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.

CONVERT

t

CYC

IO

Figure 37. 3-Wire

CNV

AD7691

SCK

VIO

SDOSDI

CS

Mode with Busy Indicator

Connection Diagram (SDI High)

47kΩ

DIGITAL HOST

DATA IN

IRQ

CLK

06146-013

SCK

SDO

t

CONV

CONVERSIONACQUISITION

Figure 38. 3-Wire

t

ACQ

ACQUISITION

t

SCK

t

SCKL

123 171819

t

HSDO

t

D17 D 16 D1 D0

CS

Mode with Busy Indicator Serial Interface Timing (SDI High)

DSDO

t

SCKH

t

DIS

06146-014

Rev. C | Page 19 of 28

AD7691 Data Sheet

S

S

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when multiple AD7691s are
connected to an SPI-compatible digital host.

A connection diagram example using two AD7691s is shown in
Figure 39, and the corresponding timing is given in Figure 40.

With SDI high, a rising edge on CNV initiates a conversion,

CS

selects the
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion

mode, and forces SDO to high impedance. In this

time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7691 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading

th

rate, provided it has an acceptable hold time. After the 18

SCK
falling edge, or when SDI goes high, whichever occurs first, SDO
returns to high impedance and another AD7691 can be read.

CS2
CS1
CONVERT

CNV

SDOSDI

SCK

Figure 39. 4-Wire

CNV

AD7691AD7691

CS

Mode Without Busy Indicator Connection Diagram

SDOSDI

SCK

DIGITAL HO ST

DATA IN
CLK

06146-015

t

CYC

CNV

t

ACQ

ACQUISITI ON

19 2018

D0 D17 D16

t

DIS

06146-016

t

SSDICNV

DI (CS1)

DI (CS2)

SCK

SDO

t

HSDICNV

t

CONV

CONVERS IONACQUISIT ION

t

SCK

t

SCKL

16 17

t

SCKH

t

DSDO

D1

Mode Without Busy Indicator Serial Interface Timing

t

EN

123 343536

t

HSDO

D17 D16 D15 D1 D0

Figure 40. 4-Wire

CS

Rev. C | Page 20 of 28

Data Sheet AD7691

CS MODE, 4-WIRE WITH BUSY INDICATOR

This mode is normally used when a single AD7691 is connected
to an SPI-compatible digital host with an interrupt input, and it
is desired to keep CNV, which is used to sample the analog
input, independent of the signal used to select the data reading.
This requirement is particularly important in applications
where low jitter on CNV is desired.

The connection diagram is shown in Figure 41, and the
corresponding timing is given in Figure 42.

With SDI high, a rising edge on CNV initiates a conversion,

CS

selects the
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO

mode, and forces SDO to high impedance. In this

CNV

line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7691
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge can allow a faster reading rate, provided it has an

th

acceptable hold time. After the optional 19

SCK falling edge,
or SDI going high, whichever occurs first, SDO returns to high
impedance.

CS1
CONVERT

Figure 41. 4-Wire

t

CYC

CNV

AD7691

SDOSDI

SCK

CS

Mode with Busy Indicator Connection Diagram

VIO

47kΩ

DIGITAL HOST

DATA IN

IRQ

CLK

06146-017

SDI

SCK

SDO

t

SSDICNV

t

HSDICNV

t

CONV

CONVERSIONACQUISITI ON

t

EN

Figure 42. 4-Wire

t

ACQ

ACQUISITION

t

SCK

t

SCKL

1 2 3 171819

t

HSDO

t

DSDO

D17 D16 D1 D0

CS

Mode with Busy Indicator Serial Interface Timing

t

SCKH

t

DIS

06146-018

Rev. C | Page 21 of 28

AD7691 Data Sheet

CHAIN MODE WITHOUT BUSY INDICATOR

This mode can be used to daisy-chain multiple AD7691s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.

A connection diagram example using two AD7691s is shown in
Figure 43, and the corresponding timing is given in Figure 44.

When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data

readback. When the conversion is complete, the MSB is output
onto SDO and the AD7691 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge can allow a faster reading
rate and, consequently, more AD7691s in the chain, provided
the digital host has an acceptable hold time. The maximum
conversion rate may be reduced due to the total readback time.

CONVERT

CNV

AD7691

A

SCK

SDOSDI

CNV

AD7691

B

SCK

DIGITAL HO ST

SDOSDI

DATA IN

CLK

06146-019

Figure 43. Chain Mode Without Busy Indicator Connection Diagram

SDIA = 0

CNV

SCK

t

HSCKCNV

SDOA = SDI

SDO

t

CONV

CONVERSIONACQUISITION

t

t

SSCKCNV

123 343536

t

t

EN

B

t

HSDO

t

DSDO

B

SSDISCK

DA17 DA16 DA15

DB17 DB16 DB15 DA1DB1DB0DA17 DA16

SCKL

t

Figure 44. Chain Mode Without Busy Indicator Serial Interface Timing

16 17

HSDISCK

t

CYC

ACQUISITION

t

SCK

DA1

t

t

SCKH

DA0

ACQ

19 2018

DA0

06146-020

Rev. C | Page 22 of 28

Data Sheet AD7691

CHAIN MODE WITH BUSY INDICATOR

This mode can also be used to daisy-chain multiple AD7691s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register.

A connection diagram example using three AD7691s is shown
in Figure 45, and the corresponding timing is given in Figure 46.

When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have

completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7691 ADC labeled C in Figure 45) is
driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7691 then enters the acquisition phase and powers
down. The data bits stored in the internal shift register are
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N + 1 clocks are required to
readback the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate and, consequently, more AD7691s in the
chain, provided the digital host has an acceptable hold time.

CONVERT

CNV = SDI

ACQUISITI ON

SCK

t

HSCKCNV

SDOA = SDI

= SDI

SDO

B

SDO

A

B

C

C

CNV

AD7691

SCK

t

CONV

CONVERSIO N

t

SSCKCNV

t

EN

t

DSDOSDI

t

DSDOSDI

CNV

SDOSDI

A

AD7691

B

SCK

SDOSDI

CNV

AD7691

C

SCK

SDOSDI

Figure 45. Chain Mode with Busy Indicator Connection Diagram

t

CYC

t

ACQ

ACQUISITI ON

t

t

SCKH

123 39 53 54

t

SSDISCK

DA17 DA16 DA15

t

HSDO

t

DSDO

DB17 DB16 DB15 DA1DB1DB0DA17 DA16

DC17 DC16 DC15 DA1DA0DC1DC0D

SCK

417

t

HSDISCK

DA1

t

SCKL

19 3818

DA0

21 35 3620

37

DA0

1DB0DA17DB17 DB16

D

B

Figure 46. Chain Mode with Busy Indicator Serial Interface Timing

DIGITAL HO ST

DATA IN

IRQ

CLK

16

A

t

DSDOSDI

t

DSDOSDI

t

DSDOSDI

6146-021

55

06146-022

Rev. C | Page 23 of 28

AD7691 Data Sheet

APPLICATION HINTS

LAYOUT

The printed circuit board that houses the AD7691 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pin
configuration of the AD7691, with its analog signals on the left
side and its digital signals on the right side, eases this task.

Avoid running digital lines under the device because this couples
noise onto the die unless a ground plane under the AD7691 is
used as a shield. Fast switching signals, such as CNV or clocks,
should not run near analog signal paths. Crossover of digital
and analog signals should be avoided.

At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the latter case,
the planes should be joined underneath the AD7691.

The AD7691 voltage reference input, REF, has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.

Finally, the power supplies, VDD and VIO, of the AD7691
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7691 and connected using short, wide
traces to provide low impedance paths and to reduce the effect
of glitches on the power supply lines.

An example layout following these rules is shown in Figure 47
and Figure 48.

Figure 47. Example Layout of the AD7691 (Top Layer)

6146-023

EVALUATING THE AD7691 PERFORMANCE

Other recommended layouts for the AD7691 are outlined
in the documentation of the evaluation board for the AD7691
(EVAL-AD7691CBZ). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-CONTROL BRD3Z.

Figure 48. Example Layout of the AD7691 (Bottom Layer)

06146-048

Rev. C | Page 24 of 28

Data Sheet AD7691

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

6

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.50 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 49.10-Lead Mini Small Outline Package [MSOP]

3.10

3.00 SQ

2.90

5.15

4.90

4.65

5

15° MAX

6°
0°

0.23

0.13

0.30

0.15

1.10 MAX

(RM-10)

Dimensions shown in millimeters

2.48

2.38

2.23

0.70

0.55

0.40

0.50 BSC

091709-A

PIN 1 INDEX

AREA

0.80

0.75

0.70

SEATING

PLANE

TOP VIEW

0.30

0.25

0.20

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

6

EXPOSED

PAD

5

BOTTOM VIEW

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

10

1.74

1.64

1.49

1

1

P

N

I

R

A

O

T

N

I

D

C

I

)

5

1

.

R

0

(

121009-A

Figure 50. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Branding Ordering Quantity

AD7691BCPZRL –40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 C4E Reel, 5,000
AD7691BCPZRL7 –40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 C4E Reel, 1,500
AD7691BRMZ –40°C to +85°C 10-Lead MSOP RM-10 C4E Tube, 50
AD7691BRMZ-RL7 –40°C to +85°C 10-Lead MSOP RM-10 C4E Reel, 1,000
EVAL-AD7691SDZ Evaluation Board
EVAL-SDP-CB1Z Controller Board

1

Z = RoHS Compliant Part.

Rev. C | Page 25 of 28

AD7691 Data Sheet

NOTES

Rev. C | Page 26 of 28

Data Sheet AD7691

NOTES

Rev. C | Page 27 of 28

AD7691 Data Sheet

NOTES

©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06146-0-3/12(C)

Rev. C | Page 28 of 28