16-Bit, 500 kSPS PulSAR™
K
Preliminary Technical Data
FEATURES
16-bit resolution with no missing codes
Throughput: 500 kSPS
INL: ±0.6 LSB typ, ±2 LSB max (±0.003 % of FSR)
S/(N + D): 93.5 dB @ 20 kHz
THD: −110 dB @ 20 kHz
Pseudo-differential analog input range
0 V to V
with V
REF
No pipeline delay
Single-supply 5V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®/QSPI™/µWire/DSP compatible
Daisy chain multiple ADCs and BUSY indicator
Power dissipation
4 mW @ 5 V/100 kSPS,
4 µW @ 5 V/100 SPS
Stand-by current: 1 nA
10-lead package: MSOP (MSOP-8 size) and
QFN (LFCSP), 3 mm × 3 mm same space as SOT-23
Pin-for-pin compatible with the AD7685, AD7687, and
AD7688
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
up to VDD
REF
ADC in MSOP/QFN
AD7686
APPLICATION DIAGRAM
0.5 TO 5V 5V
0 TO VREF
IN+
IN–
REF
AD7686
GND
VDD
Figure 1.
VIO
SDI
SCK
SDO
CNV
Table 1. MSOP, QFN (LFCSP)/SOT-23 16-Bit PulSAR ADC
Type 100 kSPS 250 kSPS 500 kSPS
True Differential AD7684 AD7687 AD7688
Pseudo
AD7683
Differential/Unipolar
Unipolar AD7680
GENERAL DESCRIPTION
The AD7686 is a 16-bit, charge redistribution successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5V power supply, VDD. It contains a low power,
high speed, 16-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
it samples an analog input IN+ between 0 V to REF with respect
to a ground sense IN−. The reference voltage, REF, is applied
externally and can be set up to the supply voltage.
Its power scales linearly with throughput.
1.8 TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
AD7685
AD7694
AD7686
The SPI compatible serial interface also features the ability,
using the SDI input, to daisy chain several ADCs on a single 3wire bus and provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate
supply VIO.
The AD7686 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
Rev Pr
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD7686 Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Converter Operation.................................................................. 12
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ......................................................................................8
Typical Performance Characteristics .............................................9
Circuit Information.................................................................... 12
REVISION HISTORY
5/04—Revision J: Preliminary
Typical Connection Diagram ................................................... 13
Digital Interface.......................................................................... 17
Application Hints ........................................................................... 24
Layout .......................................................................................... 24
Evaluating the AD7686’s Performance.................................... 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 26
Rev Pr K | Page 2 of 27
Preliminary Technical Data AD7686
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V
Table 2.
B Grade C Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
RESOLUTION 16 16 Bits
ANALOG INPUT
Voltage Range IN+ − IN− 0 V
Absolute Input Voltage IN+ −0.1 VDD + 0.1 −0.1 VDD + 0.1 V
IN− −0.1 0.1 −0.1 0.1 V
Analog Input CMRR fIN = 250 kHz 65 65 dB
Leakage Current at 25°C Acquisition Phase 1 1 nA
Input Impedance See the Analog Input section.
ACCURACY
No Missing Codes 16 16 Bits
Differential Linearity Error −1 ±0.7 −1 ±0.5 +2 LSB1
Integral Linearity Error −3 ±1 +3 −2 ±0.6 +2 LSB
Transition Noise REF = VDD = 5 V 0.5 0.45 LSB
Gain Error2, T
MIN
to T
±2 ±30 ±2 ±15 LSB
MAX
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error2, T
MIN
to T
±0.1 ±1.6 ±0.1 ±1.6 mV
MAX
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity
VDD = 5V ± 5%
THROUGHPUT
Conversion Rate 0 500 0 500 kSPS
Transient Response Full-Scale Step 400 400 ns
AC ACCURACY
Signal-to-Noise fIN = 20 kHz, V
Spurious-Free Dynamic Range fIN = 20 kHz −106 −110 dB
Total Harmonic Distortion fIN = 20 kHz −106 −110 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz, V
f
= 20 kHz, V
IN
Intermodulation Distortion
Second-Order Terms TBD TBD dB
Third-Order Terms TBD TBD dB
= VDD, TA = –40°C to +85°C, unless otherwise noted.
REF
0 V
REF
V
REF
±0.05 ±0.05 LSB
= 5 V 90 92 92 93.5 dB3
REF
= 5 V 90 92 92 93.5 dB
REF
= 5 V, −60 dB Input 32 33.5 dB
REF
1
LSB means least significant bit. With the 5 V input range, one LSB is 76.3 µV.
2
See section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. Terminology
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
Rev Pr K | Page 3 of 27
AD7686 Preliminary Technical Data
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V
Table 3.
Parameter Conditions Min Typ Max Unit
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 500 kSPS, REF = 5 V 100 µA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 9 MHz
Aperture Delay VDD = 5 V 2.5 ns
DIGITAL INPUTS
Logic Levels
VIL –0.3 0.3 × VIO V
VIH 0.7 × VIO VIO + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
DIGITAL OUTPUTS
Data Format Serial 16 Bits Straight Binary
Pipeline Delay
VOL I
VOH I
= +500 µA 0.4 V
SINK
= −500 µA VIO − 0.3 V
SOURCE
POWER SUPPLIES
VDD Specified Performance 4.5 5.5 V
VIO Specified Performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V
Standby Current
1, 2
VDD and VIO = 5 V, 25°C 1 50 nA
Power Dissipation VDD = 5 V, 100 SPS Throughput 4 µW
VDD = 5 V, 100 kSPS Throughput 4 6 mW
VDD = 5 V, 500 kSPS Throughput 30 mW
TEMPERATURE RANGE3
Specified Performance T
MIN
to T
= VDD, TA = –40°C to +85°C, unless otherwise noted.
REF
Conversion Results Available Immediately
after Completed Conversion
−40 +85 °C
MAX
1
With all digital inputs forced to VIO or GND as required.
2
During acquisition phase.
3
Contact Analog Devices for extended temperature range.
Rev Pr K | Page 4 of 27
Preliminary Technical Data AD7686
TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
Table 4.
Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time between Conversions t
CNV Pulse Width ( CS Mode )
SCK Period ( CS Mode )
SCK Period ( Chain Mode ) t
VIO above 4.5 V 19 ns
VIO above 3 V 20 ns
VIO above 2.7 V 21 ns
VIO above 2.3 V 22 ns
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t
VIO above 4.5 V 14 ns
VIO above 3 V 15 ns
VIO above 2.7 V 16 ns
VIO above 2.3 V 17 ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO above 4.5 V 15 ns
VIO above 2.7 V 18 ns
VIO above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with BUSY indicator) t
VIO above 4.5 V 15 ns
VIO above 2.3 V 26 ns
0.5 1.6 µs
CONV
400 ns
ACQ
2 µs
CYC
10 ns
t
CNVH
15 ns
t
SCK
SCK
7 ns
SCKL
7 ns
SCKH
5 ns
HSDO
DSDO
tEN
t
25 ns
DIS
t
15 ns
SSDICNV
t
0 ns
HSDICNV
5 ns
SSCKCNV
5 ns
HSCKCNV
5 ns
SSDISCK
4 ns
HSDISCK
DSDOSDI
Rev Pr K | Page 5 of 27
AD7686 Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs
IN+1, IN−1, REF
GND − 0.3 V to VDD + 0.3 V
or ±130 mA
Supply Voltages
VDD, VIO to GND −0.3 V to +7 V
VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 200°C/W (MSOP-10)
θJC Thermal Impedance 44°C/W (MSOP-10)
Lead Temperature Range
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1
See the Analog Input section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500µAI
TO SDO
Figure 2. Load Circuit for Digital Interface Timing
50pF
C
L
500µAI
30% VIO
t
DELAY
2V OR VIO – 0.5V
0.8V OR 0.5V
NOTES
1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 3. Voltage Reference Levels for Timing
OL
1.4V
OH
70% VIO
1
2
02968-PrH-002
t
DELAY
2V OR VIO – 0.5V
0.8V OR 0.5V
1
2
02968-PrH-003
Rev Pr K | Page 6 of 27
Preliminary Technical Data AD7686
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
REF
2
VDD
3
IN+
AD7686
4
IN–
5
GND
Figure 4.10-Lead MSOP and QFN (LFCSP) Pin Configuration
10
VIO
9
SDI
8
SCK
7
SDO
6
CNV
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Function
1 REF AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 µF capacitor.
2 VDD P Power Supply.
3 IN+ AI
Analog Input. It is referred to in IN−. The voltage range, i.e., the difference between IN+ and IN−, is 0 V to
.
V
REF
4 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground.
5 GND P Power Supply Ground.
6 CNV DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
CS
selects the interface mode of the part, chain or
mode. In CS mode, it enables the SDO pin when low. In
chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 16 SCK cycles.
CS
mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY
indicator feature is enabled.
10 VIO P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
1
AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power
Rev Pr K | Page 7 of 27
AD7686 Preliminary Technical Data
[
(
)
−+=
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs 1/2 LSB before
the first code transition. Positive full scale is defined as a level 1
1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line
( ). Figure 21
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level 1/2 LSB above analog
ground (38.1 µV for the 0 V to 5 V range). The offset error is the
deviation of the actual transition from that point.
Gain Error
The last transition (from 111 . . . 10 to 111 . . . 11) should occur
for an analog voltage 1 1/2 LSB below the nominal full scale
(4.999886 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset has been adjusted out.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula
]
DNSENOB
dB
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Response
The time required for the ADC to accurately acquire its input
after a full-scale step function was applied.
)02.6/76.1/
Rev Pr K | Page 8 of 27
Preliminary Technical Data AD7686
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. Integral Nonlinearity vs. Code
Figure 6. Histogram of a DC Input at the Code Center
Figure 8. Differential Nonlinearity vs. Code
Figure 9. Histogram of a DC Input at the Code Center
Figure 7. FFT Plot
Rev Pr K | Page 9 of 27
Figure 10. S/[N + D] vs. Frequency
AD7686 Preliminary Technical Data
Figure 11. SNR vs. Temperature
Figure 12. THD vs. Frequency
Figure 14. SNR and THD vs. Input Level
Figure 15. Operating Currents vs. Supply
Figure 13. THD, SFDR vs. Temperature
Rev Pr K | Page 10 of 27
Figure 16. Power-Down Currents vs. Temperature
Preliminary Technical Data AD7686
Figure 17. Operating Currents vs. Temperature
Figure 18. Offset and Gain Error vs. Temperature
Figure 19. t
vs. Capacitance Load and Supply
DSDO
Rev Pr K | Page 11 of 27
AD7686 Preliminary Technical Data
IN+
REF
GND
IN–
16,384C
16,384C
4C 2C C C32,768C
4C 2C C C32,768C
Figure 20. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7686 is a fast, low power, single-supply, precise 16-bit
ADC using a successive approximation architecture.
The AD7686 is capable of converting 500,000 samples per
second (500 kSPS) and powers down between conversions.
When operating at 100 SPS, for example, it consumes typically
4µW, ideal for battery-powered applications.
The AD7686 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7686 is specified from 4.5 V to 5.5 V, and can be
interfaced to either 5 V, 3.3 V, 2.5 V, or 1.8 V digital logic. It is
housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that
combines space savings and allows flexible configurations.
It is pin-for-pin-compatible with the AD7685, AD7687, and
AD7688.
LSB
LSB
SWITCHES CONTROL
SW+MSB
COMP
SW–MSB
CONTROL
LOGIC
CNV
BUSY
OUTPUT CODE
02968-PrH-005
CONVERTER OPERATION
The AD7686 is a successive approximation ADC based on a
charge redistribution DAC. F shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between GND and REF, the comparator
input varies by binary weighted voltage steps (V
V
/65536). The control logic toggles these switches, starting
REF
with the MSB, in order to bring the comparator back into a
balanced condition. After the completion of this process, the
part returns to the acquisition phase and the control logic
generates the ADC output code and a BUSY signal indicator.
igure 20
REF
/2, V
REF
/4 . . .
Because the AD7686 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev Pr K | Page 12 of 27
Preliminary Technical Data AD7686
Transfer Functions
The ideal transfer characteristic for the AD7686 is shown in
and . Figure 21
Table 7
111...111
111...110
111...101
ADC CODE (STRAIGHT BINARY)
000...010
000...001
000...000
–FS
–FS + 1 LSB
–FS + 0.5 LSB
ANALOG INPUT
+FS – 1 LSB
+FS – 1.5 LSB
Figure 21. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Analog Input
Description
V
= 5 V Digital Output Code Hexa
REF
FSR – 1 LSB 4.999924 V FFFF1
Midscale + 1 LSB 2.500076 V 8001
Midscale 2.5 V 8000
Midscale – 1 LSB 2.499924 V 7FFF
–FSR + 1 LSB 76.3 µV 0001
–FSR 0 V 00002
1
This is also the code for an overranged analog input (V
V
).
GND
2
This is also the code for an underranged analog input (V
– VIN above V
IN+
– VIN below V
IN+
(NOTE 1)
≥7V
0 TO VREF
(NOTE 3)
REF
≥7V
≤–2V
(NOTE 2)
33Ω
2.7nF
(NOTE 4)
10µF
IN+
IN–
02968-PrH-006
–
REF
).
GND
REF
AD7686
GND
TYPICAL CONNECTION DIAGRAM
Figure 22
diagram for the AD7686 when multiple supplies are available.
VDD
VIO
SCK
SDO
CNV
shows an example of the recommended connection
5V
100nF
1.8V TO VDD
100nF
SDI
3- OR 4-WIRE INTERFACE (NOTE 5)
NOTE 1: SEE REFERENCE SECTION FOR REFERENCE SELECTION.
NOTE 2: C
NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION.
NOTE 4: OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
NOTE 5: SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
IS USUALLY
REF
A 10 µF CERAMIC CAPACITOR (X5R).
Figure 22. Typical Application Diagram with multiple supplies
Rev Pr K | Page 13 of 27
AD7686 Preliminary Technical Data
Analog Input
Figure 23
shows an equivalent circuit of the input structure of
the AD7686.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this will cause these diodes to become
forward-biased and start conducting current. However, these
diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions could eventually
occur when the input buffer’s (U1) supplies are different from
VDD. In such a case, an input buffer with a short-circuit current
limitation can be used to protect the part.
VDD
IN+
OR IN–
GND
Figure 23. Equivalent Analog Input Circuit
D1
C
PIN
D2
R
C
IN
IN
This analog input structure allows the sampling of the
differential signal between IN+ and IN−. By using this
differential input, small signals common to both inputs are
rejected, as shown in Fi , which represents the typical
gure 24
CMRR over frequency. For instance, by using IN− to sense a
remote signal ground, ground potential differences between the
sensor and the local ADC ground are eliminated.
During the acquisition phase, the impedance of the analog
input IN+ can be modeled as a parallel combination of
capacitor C1 and the network formed by the series connection
of R1 and C2. C1 is primarily the pin capacitance. R1 is typically
600 Ω and is a lumped component made up of some serial
resistors and the on resistance of the switches. C2 is typically
30 pF and is mainly the ADC sampling capacitor. During the
conversion phase, where the switches are opened, the input
impedance is limited to C1. R1 and C2 make a 1-pole, low-pass
filter that reduces undesirable aliasing effect and limits the
noise.
When the source impedance of the driving circuit is low, the
AD7686 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency, as shown in
. Figure 25
Figure 24. Analog Inp ut CMRR v s. Frequenc y
Figure 25. THD vs. Analog Input Frequency and Source Resistance
Rev Pr K | Page 14 of 27
Preliminary Technical Data AD7686
Driver Amplifier Choice
Although the AD7686 is easy to drive, the driver amplifier
needs to meet the following requirements:
• The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7686. Note that the
AD7686 has a noise much lower than most of the other 16bit ADCs and, therefore, can be driven by a noisier op amp
while preserving the same or better system performance.
The noise coming from the driver is filtered by the AD7686
analog input circuit 1-pole, low-pass filter made by R1 and
C2 or by the external filter, if one is used. Because the
typical noise of the AD7686 is 35 µV rms, the SNR
degradation due to the amplifier is
Ne
)(f
N
SNR
LOSS
=
20log
1225
35
π
+
−23dB
2
where:
f
is the input bandwidth in MHz of the AD7686
–3dB
(9 MHz) or the cutoff frequency of the input filter, if one is
used.
N is the noise factor of the amplifier (+1 in buffer
configuration).
Table 8. Recommended Driver Amplifiers.
Amplifier Typical Application
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8605, AD8615 5 V single-supply, low power
AD8519 Small, low power and low frequency
AD8031 High frequency and low power
Voltage Reference Input
The AD7686 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins as explained in the Layout section.
When REF is driven by a very low impedance source, e.g., a
reference buffer using the AD8031 or the AD8605, a 10 µF
(X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R, 1206
size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values down
to 2.2 µF can be used with a minimal impact on performance,
especially DNL.
e
is the equivalent input noise voltage of the op amp, in
N
nV/√Hz.
• For ac applications, the driver needs to have a THD
performance suitable to that of the AD7686. F
igure 12
gives the THD versus frequency that the driver should
exceed.
• For multichannel multiplexed applications, the driver
amplifier and the AD7686 analog input circuit must be able
to settle for a full-scale step of the capacitor array at a 16bit level (0.0015%). In the amplifier’s data sheet, settling at
0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
Rev Pr K | Page 15 of 27
AD7686 Preliminary Technical Data
Power Supply
The AD7686 is specified 4.5 V to 5.5 V. It has, unlike other low
voltage converters, a noise low enough to design a 16-bit
resolution system with respectable performance. It uses two
power supply pins: a core supply VDD and a digital
input/output interface supply VIO. VIO allows direct interface
with any logic between 1.8 V and VDD. To reduce the supplies
needed, the VIO and VDD can be tied together. The AD7686 is
independent of power supply sequencing between VIO and
VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in ,
Figure 26
which represents PSRR over frequency.
Supplying the ADC from the Reference
For simplified applications, the AD7686, with its low operating
current, can be supplied directly using the reference circuit, as
shown in Figure 28. The reference line can be driven by either:
• The system power supply directly
A reference voltage with enough current output
•
capability, such as the ADR43x
• A reference buffer, such as the AD8031, that can also
filter the system power supply, as shown in Figure 28.
Figure 26. PSRR v s. Frequency
The AD7686 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate as shown in see . This makes the part
Figure 27
ideal for low sampling rate (even a few Hz) and low batterypowered applications.
5V
10kΩ
5V
1µF
NOTE 1: OPTIONAL REFERENCE BUFFER AND FILTER
AD8031
(NOTE 1)
Figure 28. Example of Application Circuit
5V
10µF 1µF
10Ω
VIOREF VDD
AD7686
Figure 27. Operating Currents vs. Sampling Rate
Rev Pr K | Page 16 of 27
Preliminary Technical Data AD7686
DIGITAL INTERFACE
Though the AD7686 has a reduced number of pins, it offers
flexibility in its serial interface modes.
CS
The AD7686, when in
digital hosts, and DSPs, e.g., Blackfin® ADSP-BF53x or ADSP219x). This interface can use either 3-wire or 4-wire. A 3-wire
interface using the CNV, SCK, and SDO signals minimizes
wiring connections useful, for instance, in isolated applications.
A 4-wire interface using the SDI, CNV, SCK, and SDO signals
allows CNV, which initiates the conversions, to be independent
of the readback timing (SDI). This is useful in low jitter
sampling or simultaneous sampling applications.
The AD7686, when in chain mode, provides a daisy chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The
SDI is high and the chain mode is selected if SDI is low. The SDI
hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
mode, is compatible with SPI, QSPI,
CS
mode is selected if
In either mode, the AD7686 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a BUSY signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a BUSY indicator,
the user must time out the maximum conversion time prior to
readback.
The BUSY indicator feature is enabled as follows:
• In the
• In the chain mode, if SCK is high during the CNV rising edge
CS
mode, if CNV or SDI is low when the ADC
conversion ends ( and ). Figure 32 Figure 36
( ). Figure 40
Rev Pr K | Page 17 of 27
AD7686 Preliminary Technical Data
V
CS
MODE 3-Wire, No BUSY Indicator
This mode is usually used when a single AD7686 is connected
to an SPI compatible digital host. The connection diagram is
shown in F and the corresponding timing is given in
Figure 30
igure 29
.
With SDI tied to VIO, a rising edge on CNV initiates a
CS
conversion, selects the
mode, and forces SDO to high
impedance. Once a conversion is initiated, it will continue to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7686
enters the acquisition phase and powers down. When CNV goes
low, the MSB is output onto SDO. The remaining data bits are
SDI = 1
t
CNVH
CNV
t
then clocked by subsequent SCK falling edges. The data is valid
on both SCK edges. Although the rising edge can be used to
capture the data, a digital host also using the SCK falling edge
will allow a faster reading rate provided it has an acceptable
hold time. After the 16th SCK falling edge or when CNV goes
high, whichever is earlier, SDO returns to high impedance.
CONVERT
DIGITAL HOST
DATA IN
CLK
CYC
IO
CNV
AD7686
Figure 29.
SDOSDI
SCK
CS
Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
SCK
SDO
t
CONV
CONVERSIONACQUISITION
Figure 30.
1 2 3 14 15 16
t
HSDO
t
EN
D15 D14 D13 D1 D0
CS
Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
t
ACQ
ACQUISITION
t
DSDO
t
SCKL
t
SCKH
t
SCK
t
DIS
02968-PrH-008
Rev Pr K | Page 18 of 27
Preliminary Technical Data AD7686
V
CS
Mode 3-Wire with BUSY Indicator
This mode is usually used when a single AD7686 is connected
to an SPI compatible digital host having an interrupt input.
The connection diagram is shown in and the
corresponding timing is given in .
Figure 31
Figure 32
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the
CS
mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion is
complete, SDO goes from high impedance to low. With a pullup on the SDO line, this transition can be used as an interrupt
signal to initiate the data reading controlled by the digital host.
The AD7686 then enters the acquisition phase and powers
SDI = 1
t
CNVH
CNV
t
down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge will allow a faster
reading rate provided it has an acceptable hold time. After the
optional 17th SCK falling edge, or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CONVERT
CYC
IO
CNV
AD7686
Figure 31.
SDOSDI
SCK
CS
Mode 3-Wire with BUSY Indicator
Connection Diagram (SDI High)
VIO
47kΩ
DIGITAL HOST
DATA IN
IRQ
CLK
SCK
SDO
t
CONVERSIONACQUISITION
Figure 32.
CONV
t
ACQ
ACQUISITION
t
SCK
t
SCKL
1 2 3 15 16 17
t
HSDO
t
DSDO
D15 D14 D1 D0
CS
Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
t
SCKH
t
DIS
02968-PrH-010
Rev Pr K | Page 19 of 27
AD7686 Preliminary Technical Data
CS
Mode 4-Wire, No BUSY Indicator
This mode is usually used when multiple AD7686s are
connected to an SPI compatible digital host.
A connection diagram example using two AD7686s is shown in
and the corresponding timing is given in . Figure 33
Figure 34
With SDI high, a rising edge on CNV initiates a conversion,
selects the
CS
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
CNV
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7686 enters the acquisition phase
and powers down. Each ADC result can be read by bringing low
its SDI input which consequently outputs the MSB onto SDO.
The remaining data bits are then clocked by subsequent SCK
driving edges. The data is valid on both SCK edges. Although
the nondriving edge can be used to capture the data, a digital
host also using the SCK falling edge will allow a faster reading
rate provided it has an acceptable hold time. After the 16th SCK
falling edge, or when SDI goes high, whichever is earlier, SDO
returns to high impedance and another AD7686 can be read.
CS2
CS1
CONVERT
CNV
DIGITAL HOST
SCK
SDOSDI
DATA IN
CLK
AD7686
SCK
Figure 33.
SDOSDI
CS
Mode 4-Wire, No BUSY Indicator Connection Diagram
AD7686
t
CYC
CNV
t
ACQ
ACQUISITION
17 1816
D0 D15 D14
t
DIS
t
SDI(CS1)
SDI(CS2)
SCK
SDO
SSDICNV
t
HSDICNV
t
CONV
CONVERSIONACQUISITION
t
SCK
t
SCKL
123 303132
t
t
EN
HSDO
D15 D14 D13 D1 D0
t
DSDO
14 15
t
SCKH
D1
02968-PrH-012
Figure 34.
CS
Mode 4-Wire, No BUSY Indicator Serial Interface Timing
Rev Pr K | Page 20 of 27
Preliminary Technical Data AD7686
A
CS
Mode 4-Wire with BUSY Indicator
This mode is usually used when a single AD7686 is connected
to an SPI compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in and the
corresponding timing is given in F .
Figure 35
igure 36
low. With a pull-up on the SDO line, this transition can be used
as an interrupt signal to initiate the data readback controlled by
the digital host. The AD7686 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK driving edges. The data is valid on both
SCK edges. Although the rising edge can be used to capture the
data, a digital host also using the SCK falling edge will allow a
faster reading rate provided it has an acceptable hold time. After
the optional 17th SCK falling edge, or SDI going high,
whichever is earlier, the SDO returns to high impedance.
With SDI high, a rising edge on CNV initiates a conversion,
selects the
CS
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
CNV
t
CONV
CQUISITION
t
SSDICNV
SDI
t
HSDICNV
SCK
SDO
CONVERSION
t
EN
Figure 36.
1 2 3 15 16 17
t
HSDO
t
DSDO
CS
Mode 4-Wire with BUSY Indicator S erial Interface Timing
CNV
AD7686
t
ACQ
t
SCKL
CS
Mode 4-Wire with BUSY Indicator Connection Diagram
t
SCK
t
SCKH
Figure 35.
t
CYC
ACQUISITION
D15 D14 D1 D0
SDOSDI
SCK
VIO
47kΩ
t
DIS
CS1
CONVERT
DIGITAL HOST
DATA IN
IRQ
CLK
02968-PrH-014
Rev Pr K | Page 21 of 27
AD7686 Preliminary Technical Data
S
Chain Mode, No BUSY Indicator
This mode can be used to daisy chain multiple AD7686s on a 3wire serial interface. This feature is useful for reducing
component count and wiring connections, e.g., in isolated
multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clocking a
shift register.
A connection diagram example using two AD7686s is shown in
and the corresponding timing is given in . Figure 37
Figure 38
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the BUSY indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
CNV
AD7686
SDOSDI
A
SCK
Figure 37. Chain Mode, No BUSY Indicator Connection Diagram
onto SDO and the AD7686 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host also using the SCK falling edge will allow a faster
reading rate and, consequently more AD7686s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time. For instance, with a 5 ns digital host set-up time
and 3 V interface, up to five AD7686s running at a conversion
rate of 333 kSPS can be daisy-chained on a 3-wire port.
CONVERT
CNV
AD7686
B
SCK
SDOSDI
DIGITAL HOST
DATA IN
CLK
SDIA = 0
CNV
SCK
t
HSCKCNV
DOA = SDI
SDO
t
CONV
CONVERSIONACQUISITION
t
t
SSCKCNV
1 2 3 30 31 32
t
t
EN
B
t
HSDO
t
DSDO
B
SSDISCK
DA15 DA14 DA13
DB15 DB14 DB13 DA1DB1DB0DA15 DA14
SCKL
t
HSDISC
Figure 38. Chain Mode, No BUSY Indicator Serial Interface Timing
14 15
t
CYC
ACQUISITION
t
SCK
t
DA1
t
ACQ
SCKH
DA0
17 1816
DA0
02968-PrH-016
Rev Pr K | Page 22 of 27
Preliminary Technical Data AD7686
A
Chain Mode with BUSY Indicator
This mode can also be used to daisy chain multiple AD7686s on
a 3-wire serial interface while providing a BUSY indicator. This
feature is useful for reducing component count and wiring
connections, e.g., in isolated multiconverter applications or for
systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7686s is shown
in and the corresponding timing is given in F . Figure 39
igure 40
When SDI and CNV are low, SDO is driven low. With SCK high,
a rising edge on CNV initiates a conversion, selects the chain
mode, and enables the BUSY indicator feature. In this mode,
CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the nearend ADC ( ADC C in
CNV
AD7686
A
SCK
SDOSDI
Figure 39. Chain Mode with BUSY Indicator Connection Diagram
CNV
AD7686
B
SCK
SDOSDI
Figure 39
be used as a BUSY indicator to trigger the data readback
controlled by the digital host. The AD7686 then enters the
acquisition phase and powers down. The data bits stored in the
internal shift register are then clocked out, MSB first, by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 16 × N + 1 clocks are required to readback the N ADCs.
Although the rising edge can be used to capture the data, a
digital host also using the SCK falling edge will allow a faster
reading rate and, consequently more AD7686s in the chain,
provided the digital host has an acceptable hold time. For
instance, with a 5 ns digital host set-up time and 3 V interface,
up to five AD7686s running at a conversion rate of 333 kSPS
can be daisy-chained to a single 3-wire port.
) SDO will be driven high. This transition on SDO can
CONVERT
CNV
AD7686
C
SCK
SDOSDI
DIGITAL HOST
DATA IN
IRQ
CLK
CNV = SDI
CQUISITION
SCK
t
HSCKCNV
SDOA = SDI
SDO
= SDI
B
SDO
A
B
C
C
t
CONV
CONVERSION
t
SSCKCNV
t
EN
t
DSDOSDI
t
CYC
t
ACQ
ACQUISITION
t
t
SCKH
123 35 47 48
t
SSDISCK
DA15 DA14 DA13
t
HSDO
t
DSDO
DB15 DB14 DB13 DA1DB1DB0DA15 DA14
DC15 DC14 DC13 DA1DA0DC1DC0D
SCK
415
t
HSDISC
DA1
t
SCKL
17 3416
DA0
19 31 3218
33
DA0
D
1DB0DA15DB15 DB14
B
14
A
49
Figure 40. Chain Mode with BUSY Indicator Serial Interface Timing
02968-PrH-018
Rev Pr K | Page 23 of 27
AD7686 Preliminary Technical Data
APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7686 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7686 with all its analog signals on the left side and all its
digital signals on the right side eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7686 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided
At least one ground plane should be used. It could be common
or split between the digital and analog section. In such a case, it
should be joined underneath the AD7686s.
The AD7686 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. That is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connect these pins with wide, low
impedance traces.
Finally, the power supply VDD and VIO of the AD7686 should
be decoupled with ceramic capacitors, typically 100 nF, placed
close to the AD7686 and connected using short and large traces
to provide low impedance paths and reduce the effect of glitches
on the power supply lines.
An example of layout following these rules is shown in F
and .
41
Figure 42
igure
EVALUATING THE AD7686’S PERFORMANCE
Other recommended layouts for the AD7686 are outlined in the
evaluation board for the AD7686 (EVAL-AD7686). The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-CONTROL BRD2.
Figure 41. Example of Layout of the AD7686 ( Top Layer)
Figure 42. Example of Layout of the AD7686 (Bottom Layer)
Rev Pr K | Page 24 of 27
Preliminary Technical Data AD7686
S
OUTLINE DIMENSIONS
3.00 BSC
6
10
3.00 BSC
1
PIN 1
0.50 BSC
0.95
0.85
0.75
0.15
0.00
0.27
0.17
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 43.10-Lead Micro Small Outline Package [MSOP]
INDEX
1.50
BCS SQ
0.80
0.75
0.70
EATING
PLANE
AREA
3.00
BSC SQ
TOP VIEW
0.80 MAX
0.55 TYP
0.30
0.23
0.18
Figure 44. 10-Lead Lead Frame Chip Scale Package [ QFN (LFCSP)]
4.90 BSC
5
1.10 MAX
SEATING
PLANE
0.23
0.08
8°
0°
(RM-10)
Dimensions shown in millimeters
0.50 BSC
1
PIN 1
INDICATOR
0.20 REF
0.05 MAX
0.02 NOM
EXPOSED PAD
(BOTTOM VIEW)
10
2.48
2.38
2.23
3 mm × 3 mm Body
(CP-10)
Dimensions shown in millimeters
0.80
0.60
0.40
0.50
0.40
0.30
5
1.74
1.64
1.49
6
PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES
Rev Pr K | Page 25 of 27
AD7686 Preliminary Technical Data
ORDERING GUIDE
Models Integral Nonlinearity Temperature Range Package (Option) Transport Media, Quantity Brand
AD7686BRM ±3 LSB max –40°C to +85°C MSOP (RM-10) Tube, 50 C02
AD7686BRMRL2 ±3 LSB max –40°C to +85°C MSOP (RM-10) Reel, 250 C02
AD7686BRMRL7 ±3 LSB max –40°C to +85°C MSOP (RM-10) Reel, 1,000 C02
AD7686BCPWP ±3 LSB max –40°C to +85°C QFN [LFCSP] (CP-10) Waffle pack, 50 TBD
AD7686BCPRL7 ±3 LSB max –40°C to +85°C QFN [LFCSP] (CP-10) Reel, 1,500 TBD
AD7686CRM ±2 LSB max –40°C to +85°C MSOP (RM-10) Tube, 50 TBD
AD7686CRMRL2 ±2 LSB max –40°C to +85°C MSOP (RM-10) Reel, 250 TBD
AD7686CRMRL7 ±2 LSB max –40°C to +85°C MSOP (RM-10) Reel, 1,000 TBD
AD7686CCPWP ±2 LSB max –40°C to +85°C QFN [LFCSP] (CP-10) Waffle pack, 50 TBD
AD7686CCPRL7 ±2 LSB max –40°C to +85°C QFN [LFCSP] (CP-10) Reel, 1,500 TBD
EVAL-AD7686CB1 Evaluation Board
EVAL-CONTROL BRD22 Controller Board
EVAL-CONTROL BRD32 Controller Board
1
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.
2
These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
Rev Pr K | Page 26 of 27
Preliminary Technical Data AD7686
PR02969-0-5/04(PrK)
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
Rev Pr K | Page 27 of 27
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