Datasheet AD7685 Datasheet (Analog Devices)

Page 1

16-Bit, 250 kSPS PulSAR™

FEATURES

16-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.6 LSB typ, ±2 LSB max (±0.003 % of FSR) S/(N + D): 93.5 dB @ 20 kHz THD: −110 dB @ 20 kHz Pseudo differential analog input range

0 V to V

with V

REF

No pipeline delay Single-supply operation 2.3 V to 5.5 V with

1.8 V to 5 V logic interface Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible Daisy-chain multiple ADCs, BUSY indicator Power dissipation

1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS,

1.4 µW @ 2.5 V/100 SPS Standby current: 1 nA 10-lead package: MSOP (MSOP-8 size) and

3 mm × 3 mm QFN

Pin-for-pin compatible with AD7686, AD7687, and AD7688

APPLICATIONS

Battery-powered equipment

Medical instruments Mobile communications

Personal digital assistants Data acquisition Instrumentation Process controls

2.0

1.5

1.0

up to VDD

REF

(LFCSP) (SOT-23 size)

POSITIVE INL = +0.33LSB NEGATIVE INL =–0.50LSB

ADC in MSOP/QFN

AD7685

APPLICATION DIAGRAM

0.5V TO VDD 2.5V TO 5V

0 TO VREF

IN+ IN–

REF

AD7685

GND

VDD

VIO

SDI SCK SDO CNV

Figure 2.

Table 1. MSOP, QFN1 (LFCSP)/SOT-23 16-Bit PulSAR ADCs

Type 100 kSPS 250 kSPS 500 kSPS

True Differential AD7684 AD7687 AD7688 Pseudo AD7683 AD7685 AD7686 Differential/Unipolar AD7694 Unipolar AD7680

GENERAL DESCRIPTION

The AD7685 is a 16-bit, charge redistribution successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.3 V to 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN−. The reference voltage, REF, is applied externally and can be set up to the supply voltage.

Power dissipation scales linearly with throughput.

1.8V TO VDD

3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS)

02968-001

0.5

INL (LSB)

–0.5

–1.0

–1.5

–2.0

CODE

Rev A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Anal og Devices. Trademarks and registered trademarks are the property of their respective owners.

Figure 1. Integral Nonlinearity vs. Code.

655360 16384 32768 49152

02968-005

The SPI-compatible serial interface also features the ability, using the SDI input, to daisy chain several ADCs on a single 3-wire bus or provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate supply VIO.

The AD7685 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C.

QFN package in development. Contact sales for samples and availability.

www.analog.com

Page 2

AD7685

Specifications..................................................................................... 3

Typical Conne ction Diagram ................................................... 14

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Te r m in o l o g y ...................................................................................... 9

Typical Performance Characteristics........................................... 10

Circuit Information.................................................................... 13

Converter Operation.................................................................. 13

REVISION HISTORY

12/04—Rev. 0 to Rev. A

Changes to Specifications................................................................ 3

Changes to Figure 17 Captions..................................................... 11

Changes to Power Supply Section ................................................17

Changes to Digital Interface Section............................................ 18

Changes to Changes to

Changes to Chain Mode, No Busy Indicator Section ................ 23

Changes to Chain Mode with Busy Indicator Section............... 24

Added True 16-Bit Isolated Application Example Section........ 26

Added Figure 47.............................................................................. 26

Changes to Ordering Guide.......................................................... 28

Mode 4-Wire No Busy Indicator Section .........21

Mode 4-Wire with Busy Indicator Section....... 22

Digital Interface.......................................................................... 18

Application Hints ........................................................................... 25

Layout .......................................................................................... 25

Evaluating the AD7685’s Performance.................................... 25

True 16-Bit Isolated Application Example .............................. 26

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 28

4/04—Revision 0: Initial Revision

Rev A | Page 2 of 28

Page 3

AD7685

SPECIFICATIONS

VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 2.

A Grade B Grade C Grade Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION 16 16 16 Bits ANALOG INPUT

Voltage Range IN+ − IN− 0 V Absolute Input Voltage IN+ −0.1 VDD +

IN− −0.1 +0.1 −0.1 +0.1 −0.1 +0.1 V Analog Input CMRR fIN = 250 kHz 65 65 65 dB Leakage Current at 25°C Acquisition Phase 1 1 1 nA Input Impedance See the Analog Input section

ACCURACY

No Missing Codes 15 16 16 Bits Differential Linearity Error −1 ±0.7 −1 ±0.5 +1.5 LSB Integral Linearity Error −6 +6 −3 ±1 +3 −2 ±0.6 +2 LSB Transition Noise REF = VDD = 5 V 0.5 0.5 0.45 LSB Gain Error2, T Gain Error Temperature

MIN

to T

MAX

±2 ±30 ±2 ±30 ±2 ±15 LSB ±0.3 ±0.3 ±0.3 ppm/°C

Drift

Offset Error2, T

to T

MIN

MAX

VDD = 4.5 V to 5.5 V ±0.1 ±1.6 ±0.1 ±1.6 ±0.1 ±1.6 mV VDD = 2.3 V to 4.5 V ±0.7 ±3.5 ±0.7 ±3.5 ±0.7 ±3.5 mV Offset Temperature Drift ±0.3 ±0.3 ±0.3 ppm/°C Power Supply Sensitivity VDD = 5 V ± 5% ±0.05 ±0.05 ±0.05 LSB

THROUGHPUT

Conversion Rate VDD = 4.5 V to 5.5 V 0 250 0 250 0 250 kSPS VDD = 2.3 V to 4.5 V 0 200 0 200 0 200 kSPS Transient Response Full-Scale Step 1.8 1.8 1.8 µs

AC ACCURACY

Signal-to-Noise fIN = 20 kHz,

= 5 V

REF

Spurious-Free Dynamic

= 20 kHz,

= 2.5 V

REF

fIN = 20 kHz −100 −106 −110 dB

Range Total Harmonic Distortion fIN = 20 kHz −100 −106 −110 dB Signal-to-(Noise +

Distortion) f

fIN = 20 kHz,

= 5 V

REF

= 20 kHz,

= 5 V,

REF

−60 dB Input

= 20 kHz,

= 2.5 V

REF

Intermodulation Distortion4 −110 −115 dB

LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV.

See section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. Terminology

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

= 21.4 kHz, f

IN1

= 18.9 kHz, each tone at −7 dB below full scale.

IN2

= VDD, TA = –40°C to +85°C, unless otherwise noted.

REF

0 V

−0.1 VDD +

0.1

90 90 92 91.5 93.5 dB

86 86 88 87.5 88.5 dB

89 90 92 91.5 93.5 dB

32 33.5 dB

86 85.5 87.5 87 88.5 dB

REF

0 V

REF

−0.1 VDD +

V V

0.1

Rev A | Page 3 of 28

Page 4

AD7685

VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 3.

Parameter Conditions Min Typ Max Unit

REFERENCE

Voltage Range 0.5 VDD + 0.3 V Load Current 250 kSPS, REF = 5 V 50 µA

SAMPLING DYNAMICS

−3 dB Input Bandwidth 2 MHz Aperture Delay VDD = 5 V 2.5 ns

DIGITAL INPUTS

Logic Levels

–0.3 0.3 × VIO V

0.7 × VIO VIO + 0.3 V

−1 +1 µA

DIGITAL OUTPUTS

Data Format Serial 16 Bits Straight Binary Pipeline Delay

= +500 µA 0.4 V

SINK

= −500 µA VIO − 0.3 V

SOURCE

POWER SUPPLIES

VDD Specified Performance 2.3 5.5 V VIO Specified Performance 2.3 VDD + 0.3 V VIO Range 1.8 VDD + 0.3 V Standby Current

1, 2

VDD and VIO = 5 V, 25°C 1 50 nA Power Dissipation VDD = 2.5 V, 100 SPS Throughput 1.4 µW VDD = 2.5 V, 100 kSPS Throughput 1.35 2.4 mW VDD = 2.5 V, 200 kSPS Throughput 2.7 4.8 mW VDD = 5 V, 100 kSPS Throughput 4 6 mW VDD = 5 V, 250 kSPS Throughput 15 mW

TEMPERATURE RANGE

Specified Performance T

to T

MIN

With all digital inputs forced to VIO or GND as required.

During acquisition phase.

Contact sales for extended temperature range.

= VDD, TA = –40°C to +85°C, unless otherwise noted.

REF

Conversion Results Available Immediately

MAX

−40 +85 °C

after Completed Conversion

Rev A | Page 4 of 28

Page 5

AD7685

TIMING SPECIFICATIONS

−40°C to +85°C, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

Table 4. VDD = 4.5 V to 5.5 V

Conversion Time: CNV Rising Edge to Data Available t Acquisition Time t Time between Conversions t CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) t

VIO above 4.5 V 17 ns VIO above 3 V 18 ns VIO above 2.7 V 19 ns

VIO above 2.3 V 20 ns SCK Low Time t SCK High Time t SCK Falling Edge to Data Remains Valid t SCK Falling Edge to Data Valid Delay t

VIO above 4.5 V 14 ns

VIO above 3 V 15 ns

VIO above 2.7 V 16 ns

VIO above 2.3 V 17 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO above 4.5 V 15 ns

VIO above 2.7 V 18 ns

VIO above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t SDI High to SDO High (Chain Mode with BUSY Indicator) t

VIO above 4.5 V 15 ns

VIO above 2.3 V 26 ns

See and for load conditions. Figure 3 Figure 4

Symbol Min Typ Max Unit

CONV

ACQ

CYC

CNVH

SCK

SCKL

SCKH

HSDO

DSDO

DIS

SSDICNV

HSDICNV

SSCKCNV

HSCKCNV

SSDISCK

HSDISCK

DSDOSDI

0.5 2.2 µs

1.8 µs 4 µs 10 ns 15 ns

7 ns 7 ns 5 ns

25 ns 15 ns 0 ns 5 ns

5 ns 3 ns 4 ns

Rev A | Page 5 of 28

Page 6

AD7685

−40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

Table 5. VDD = 2.3V to 4.5 V

Conversion Time: CNV Rising Edge to Data Available t Acquisition Time t Time between Conversions t CNV Pulse Width ( CS Mode ) SCK Period ( CS Mode ) SCK Period ( Chain Mode ) t

VIO above 3 V 29 ns VIO above 2.7 V 35 ns

VIO above 2.3 V 40 ns SCK Low Time t SCK High Time t SCK Falling Edge to Data Remains Valid t SCK Falling Edge to Data Valid Delay t

VIO above 3 V 24 ns

VIO above 2.7 V 30 ns

VIO above 2.3 V 35 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO above 2.7 V 18 ns

See and for load conditions. Figure 3 Figure 4

Symbol Min Typ Max Unit

CONV

ACQ

CYC

CNVH

SCK

SCKL

SCKH

HSDO

DSDO

DIS

SSDICNV

HSDICNV

SSCKCNV

HSCKCNV

SSDISCK

HSDISCK

DSDOSDI

0.7 3.2 µs

1.8 µs 5 µs 10 ns 25 ns

12 ns 12 ns 5 ns

25 ns 30 ns 0 ns 5 ns

8 ns 5 ns 4 ns 36 ns

Rev A | Page 6 of 28

Page 7

AD7685

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Ratings

Analog Inputs

IN+1, IN−1, REF

GND − 0.3 V to VDD + 0.3 V or ±130 mA

Supply Voltages

VDD, VIO to GND −0.3 V to +7 V

VDD to VIO ±7 V Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 200°C/W (MSOP-10) θJC Thermal Impedance 44°C/W (MSOP-10) Lead Temperature Range

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

See the section. Analog Input

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

500µAI

TO SDO

Figure 3. Load Circuit for Digital Interface Timing

50pF

500µAI

30% VIO

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

NOTES:

1. 2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.

2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 4. Voltage Levels for Timing

1.4V

70% VIO

02968-002

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

02968-003

Rev A | Page 7 of 28

Page 8

AD7685

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REF

VDD

IN+

AD7685

IN–

GND

Figure 5. 10-Lead MSOP and QFN

VIO

SDI SCK

SDO

CNV

(LFCSP) Pin Configuration

02968-004

Table 7. Pin Function Descriptions

Pin No.

Mnemonic Type

1 REF AI

Function

Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be

decoupled closely to the pin with a 10 µF capacitor. 2 VDD P Power Supply. 3 IN+ AI Analog Input. It is referred to IN−. The voltage range, i.e., the difference between IN+ and IN−, is 0 V to V

REF

. 4 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. 6 CNV DI

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or

CS mode. In CS mode, it enables the SDO pin when low. In chain

mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to

daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is

output on SDO with a delay of 16 SCK cycles.

CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the

serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY indicator

feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).

QFN package in development. Contact sales for samples and availability.

AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power.

Rev A | Page 8 of 28

Page 9

AD7685

[

(

)

TERMINOLOGY

Integral Nonlinearity Error (INL)

It refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (Figure 25).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.

Offset Error

The first transition should occur at a level 1/2 LSB above analog ground (38.1 µV for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point.

Gain Error

The last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset has been adjusted out.

Spurious-Free Dynamic Range (SFDR)

The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula

]

DNSENOB

and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB.

Signal-to-(Noise + Distortion) Ratio (S/[N+D])

S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in dB.

Aperture Delay

Aperture delay is a measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion.

/6.021.76/

−

Transient Response

The time required for the ADC to accurately acquire its input after a full-scale step function was applied.

Rev A | Page 9 of 28

Page 10

AD7685

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

1.5

POSITIVE INL = +0.33LSB NEGATIVE INL =–0.50LSB

2.0

1.5

POSITIVE DNL = +0.21LSB NEGATIVE DNL =–0.30LSB

1.0

0.5

INL (LSB)

–0.5

–1.0

–1.5

–2.0

CODE

Figure 6. Integral Nonlinearity vs. Code

250000

204292

200000

150000

100000

COUNTS

50000

0012 00

29041

CODE IN HEX

27755

80EA 80EB 80EC 80ED80E5 80E6 80E7 80E8 80E9

Figure 7. Histogram of a DC Input at the Code Center

VDD = REF = 5V

1.0

0.5

DNL (LSB)

–0.5

–1.0

–1.5

655360 16384 32768 49152

02968-005

–2.0

CODE

655360 16384 32768 49152

02968-008

Figure 9. Differential Nonlinearity vs. Code

02968-006

140000

120000

100000

80000

60000

COUNTS

40000

20000

125055

60966

8667

213

CODE IN HEX

59082

VDD = REF = 2.5V

6956

179 0 0

8058804E 804F 8050 8051 8052 8053 8054 8055 8056 8057

02968-009

Figure 10. Histogram of a DC Input at the Code Center

AMPLITUDE (dB OF FULL SCALE)

–20

–40

–60

–80

–100

–120

–140

–160

–180

8192 POINT FFT VDD = REF = 5V

= 250kSPS

= 20.45kHz

SNR = 93.3dB THD = –111.6dB SFDR = –113.7dB SECOND HARMONIC = –113.7dB THIRD HARMONIC = –117.6dB

FREQUENCY (kHz)

1200 20406080100

02968-007

Figure 8. FFT Plot

AMPLITUDE (dB OF FULL SCALE)

–20

–40

–60

–80

–100

–120

–140

–160

–180

16384 POINT FFT VDD = REF = 2.5V

= 250kSPS

= 20.45kHz

SNR = 88.8dB THD = –103.5dB SFDR = –104.5dB SECOND HARMONIC = –112.4dB THIRD HARMONIC = –105.4dB

FREQUENCY (kHz)

1200 20406080100

02968-010

Figure 11. FFT Plot

Rev A | Page 10 of 28

Page 11

AD7685

100

SNR

–90

–95

–100

SNR, S/(N + D) (dB)

REFERENCE VOLTAGE (V)

Figure 12. SNR, S/(N + D), and ENOB vs. Reference Voltage

100

S/(N + D) (dB)

VREF = 2.5V,–1dB

FREQUENCY (kHz)

VREF = 5V,–10dB

VREF = 5V,–1dB

Figure 13. S/[N + D] vs. Freq uency

S/(N + D)

ENOB

–105

THD, SFDR (dB)

–110

–115

–120

–125

–130

THD

SFDR

REFERENCE VOLTAGE (V)

5.52.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

02968-014

ENOB (Bits)

5.52.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

02968-011

Figure 15. THD, SFDR vs. Reference Voltage

–60

–70

–80

–90

THD (dB)

–100

–110

2000 50 100 150

02968-012

–120

VREF = 2.5V,–1dB

FREQUENCY (kHz)

VREF = 5V,–1dB

VREF = 5V,–10dB

2000 50 100 150

02968-015

Figure 16. THD vs. Frequency

100

SNR (dB)

VREF = 5V

VREF = 2.5V

TEMPERATURE (°C)

Figure 14. SNR vs. Temperature

125–55 –35 –15 5 25 45 65 85 105

02968-013

Rev A | Page 11 of 28

–90

–100

–110

THD (dB)

–120

–130

VREF = 2.5V

VREF = 5V

TEMPERATURE (°C)

Figure 17. THD vs. Temperature

125–55 –35 –15 5 25 45 65 85 105

02968-016

Page 12

AD7685

–105

1000

= 100kSPS

SNR REFERENCE TO FULL SCALE (dB)

OPERATING CURRENT (

1000

750

500

250

SNR

THD

INPUT LEVEL (dB)

Figure 18. SNR and THD vs. Input Level

VDD

VIO

SUPPLY (V)

Figure 19. Operating Currents vs. Supply

fS = 100kSPS

0–10–8–6–4–2

–110

–115

–120

5.52.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1

THD (dB)

02968-017

02968-018

OPERATING CURRENT (

OFFSET, GAIN ERROR (LSB)

VDD = 5V

750

VDD = 2.5V

500

250

VIO

TEMPERATURE (°C)

Figure 21. Operating Currents vs. Temperature

6 5 4 3 2 1

0 –1 –2 –3 –4 –5 –6

TEMPERATURE (°C)

OFFSET ERROR

Figure 22. Offset and Gain Error vs. Temperature

GAIN ERROR

125–55 –35 –15 5 25 45 65 85 105

02968-020

125–55 –35 –15 5 25 45 65 85 105

02968-021

1000

750

500

250

POWER-DOWN CURRENT (nA)

TEMPERATURE (°C)

Figure 20. Power-Down Currents vs. Temperature

VDD + VIO

125–55 –35 –15 5 25 45 65 85 105

02968-019

Rev A | Page 12 of 28

VDD = 2.5V, 25°C

DELAY (ns)

DSDO

VDD = 3.3V, 25°C

Figure 23. t

VDD = 2.5V, 85°C

VDD = 3.3V, 85°C

SDO CAPACITIVE LOAD (pF)

vs. Capacitance Load and Supply

DSDO

VDD = 5V, 25°C

VDD = 5V, 85°C

1200 20406080100

02968-022

Page 13

AD7685

IN+

REF

GND

IN–

16,384C

4C 2C C C32,768C

Figure 24. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7685 is a fast, low power, single-supply, precise 16-bit ADC using a successive approximation architecture.

The AD7685 is capable of converting 250,000 samples per second (250 kSPS) and powers down between conversions. When operating at 100 SPS, for example, it consumes typically

1.35 µW with a 2.5 V supply, ideal for battery-powered applications.

The AD7685 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications.

The AD7685 is specified from 2.3 V to 5.5 V and can be interfaced to any 1.8 V to 5 V digital logic family. It is housed in a 10-lead MSOP or a tiny 10-lead QFN space savings and allows flexible configurations.

It is pin-for-pin-compatible with the AD7688.

______________________________________

QFN package in development. Contact sales for samples and availability.

(LFCSP) that combines

AD7686, AD7687, and

LSB

SWITCHES CONTROL

SW+MSB

COMP

SW–MSB

CONTROL

LOGIC

CNV

BUSY

OUTPUT CODE

02968-023

CONVERTER OPERATION

The AD7685 is a successive approximation ADC based on a charge redistribution DAC. Figure 24 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the comparator’s input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs IN+ and IN− captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (V V

/65536). The control logic toggles these switches, starting

REF

with the MSB, in order to bring the comparator back into a balanced condition. After the completion of this process, the part powers down and returns to the acquisition phase and the control logic generates the ADC output code and a BUSY signal indicator.

REF

/2, V

REF

/4 . . .

Because the AD7685 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process.

Rev A | Page 13 of 28

Page 14

AD7685

Transfer Functions

The ideal transfer characteristic for the AD7685 is shown in Figure 25 and Table 8.

111...111

111...110

111...101

ADC CODE (STRAIGHT BINARY)

000...010

000...001

000...000

–FS

–FS + 1 LSB

–FS + 0.5 LSB

ANALOG INPUT

Figure 25. ADC Ideal Transfer Function

Table 8. Output Codes and Ideal Input Voltages

Analog Input

Description

= 5 V Digital Output Code Hexa

REF

FSR – 1 LSB 4.999924 V FFFF Midscale + 1 LSB 2.500076 V 8001 Midscale 2.5 V 8000 Midscale – 1 LSB 2.499924 V 7FFF –FSR + 1 LSB 76.3 µV 0001 –FSR 0 V 0000

______________________________________

This is also the code for an overranged analog input (V

This is also the code for an underranged analog input (V

≥7V

+FS – 1 LSB

+FS – 1.5 LSB

– V

IN+

IN-

IN+

REF

above V

– V

IN-

10µF

– V

REF

below V

02968-024

GND

TYPICAL CONNECTION DIAGRAM

Figure 26 shows an example of the recommended connection diagram for the AD7685 when multiple supplies are available.

100nF

≥7V

REF

33Ω

TO VREF

≤–2V

NOTES:

1. SEE REFERENCE SECTION FOR REFERENCE SELECTION.

2. C

REF

3. SEE DRIVER AMPLIFIER CHOICE SECTION.

4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION.

5. SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.

2.7nF

IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).

IN+

IN–

VDD

AD7685

GND

VIO

100nF

SDI SCK SDO CNV

1.8V TO VDD

3- OR 4-WIRE INTERFACE

02968-025

Figure 26. Typical Application Diagram with Multiple Supplies

Rev A | Page 14 of 28

Page 15

AD7685

Analog Input

Figure 27 shows an equivalent circuit of the input structure of the AD7685.

The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V because this will cause these diodes to begin to forward-bias and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions could eventually occur when the input buffer’s (U1) supplies are different from VDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part.

VDD

IN+

OR IN–

GND

02968-026

Figure 27. Equivalent Analog Input Circuit

This analog input structure allows the sampling of the differential signal between IN+ and IN−. By using this differential input, small signals common to both inputs are rejected, as shown in Figure 28, which represents the typical CMRR over frequency. For instance, by using IN− to sense a remote signal ground, ground potential differences between the sensor and the local ADC ground are eliminated.

CMRR (dB)

VDD = 5V

= 2.5V

During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination of capacitor C connection of R R

is typically 3 kΩ and is a lumped component made up of

and the network formed by the series

and CIN. C

is primarily the pin capacitance.

some serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to C

. RIN and CIN make a

1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise.

When the source impedance of the driving circuit is low, the AD7685 can be driven directly. Large source impedances significantly affect the ac performance, especially total harmonic distortion (THD). The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency, as shown in Figure 29.

–60

–70

–80

–90

RS = 250

RS = 100

RS = 50 RS = 33

Ω

Ω Ω

FREQUENCY (kHz)

1000 255075

02968-028

THD (dB)

–100

–110

–120

Figure 29. THD vs. Analog Input Frequency and Source Resistance

FREQUENCY (kHz)

Figure 28. Analog Input C MRR vs. Frequency

100001 10 100 1000

02968-027

Rev A | Page 15 of 28

Page 16

AD7685

Driver Amplifier Choice

Although the AD7685 is easy to drive, the driver amplifier needs to meet the following requirements:

• The noise generated by the driver amplifier needs to be kept

as low as possible in order to preserve the SNR and transition noise performance of the AD7685. Note that the AD7685 has a noise much lower than most of the other 16-bit ADCs and, therefore, can be driven by a noisier amplifier in order to meet a given system noise specification. The noise coming from the amplifier is filtered by the AD7685 analog input circuit low-pass filter made by R filter, if one is used. Because the typical noise of the AD7685 is 35 µV rms, the SNR degradation due to the amplifier is

⎛ ⎜

SNR

LOSS

20log

⎜ ⎜

⎜ ⎝

and CIN or by an external

⎞

⎟ ⎟ ⎟

)(f

⎟

⎠

−23dB

Table 9. Recommended Driver Amplifiers.

Amplifier Typical Application

AD8021 Very low noise and high frequency AD8022 Low noise and high frequency OP184 Low power, low noise, and low frequency AD8605, AD8615 5 V single-supply, low power AD8519 Small, low power and low frequency AD8031 High frequency and low power

Voltage Reference Input

The AD7685 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins as explained in the Layout section.

When REF is driven by a very low impedance source, e.g., a reference buffer using the

AD8031 or the AD8605, a 10 µF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance.

where:

is the input bandwidth in MHz of the AD7685

–3dB

(2 MHz) or the cutoff frequency of the input filter, if one is used.

N is the noise gain of the amplifier (e.g., +1 in buffer configuration).

is the equivalent input noise voltage of the op amp, in

nV/√Hz.

• For ac applications, the driver should have a THD

performance commensurate with the AD7685. Figure 16 shows the AD7685’s THD vs. frequency.

• For multichannel, multiplexed applications, the driver

amplifier and the AD7685 analog input circuit must settle a full-scale step onto the capacitor array at a 16-bit level (0.0015%). In the amplifier’s data sheet, settling at 0.1% to

0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection.

If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 µF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift

ADR43x reference.

If desired, smaller reference decoupling capacitor values down to 2.2 µF can be used with a minimal impact on performance, especially DNL.

Rev A | Page 16 of 28

Page 17

AD7685

Power Supply

The AD7685 is specified over a wide operating range from 2.3 V to 5.5 V. It has, unlike other low voltage converters, a noise low enough to design a 16-bit resolution system with low supply and respectable performance. It uses two power supply pins: a core supply VDD and a digital input/output interface supply VIO. VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the number of supplies needed, the VIO and VDD can be tied together. The AD7685 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 30, which represents PSRR over frequency.

110

100

PSRR (dB)

VDD = 5V

VDD = 2.5V

Supplying the ADC from the Reference

For simplified applications, the AD7685, with its low operating current, can be supplied directly using the reference circuit, as shown in Figure 32. The reference line can be driven by either:

• The system power supply directly

• A reference voltage with enough current output capability,

such as the ADR43x

• A reference buffer, such as the AD8031, that can also filter the

system power supply, as shown in Figure 32.

10kΩ

1µF

AD8031

10Ω

10µF 1µF

VIOREF VDD

AD7685

FREQUENCY (kHz)

100001 10 100 1000

02968-029

Figure 30. PSRR v s. Frequency

The AD7685 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate as shown in see Figure 31. This makes the part ideal for low sampling rate (even a few Hz) and low batterypowered applications.

1000

0.1

OPERATING CURRENT (µA)

0.001

SAMPLING RATE (SPS)

Figure 31. Operating Currents vs. Sampling Rate

VIO

VDD = 5V

VDD = 2.5V

100000010 100 1000 10000 100000

02968-030

NOTE: OPTIONAL REFERENCE BUFFER AND FILTER.

02968-031

Figure 32. Example of Application Circuit

Rev A | Page 17 of 28

Page 18

AD7685

DIGITAL INTERFACE

Though the AD7685 has a reduced number of pins, it offers substantial flexibility in its serial interface modes.

The AD7685, when in digital hosts, and DSPs, e.g., Blackfin® ADSP-BF53x or ADSP-

219x. This interface can use either 3-wire or 4-wire. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections, useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications.

The AD7685, when in chain mode, provides a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register.

mode, is compatible with SPI, QSPI,

The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The

SDI is high and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected.

In either the flexibility to optionally force a start bit in front of the data bits.

This start bit can be used as a BUSY signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a BUSY indicator, the user must time out the maximum conversion time prior to readback.

The BUSY indicator feature is enabled as follows:

• In the

conversion ends (Figure 36 and Figure 40).

• In the chain mode, if SCK is high during the CNV rising edge

(Figure 44).

mode or the chain mode, the AD7685 offers the

mode, if CNV or SDI is low when the ADC

mode is selected if

Rev A | Page 18 of 28

Page 19

AD7685

Mode 3-Wire, No BUSY Indicator

This mode is usually used when a single AD7685 is connected to an SPI compatible digital host. The connection diagram is shown in Figure 33 and the corresponding timing is given in Figure 34.

With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the

mode, and forces SDO to high

CS impedance. Once a conversion is initiated, it will continue to completion irrespective of the state of CNV. For instance, it could be useful to bring CNV low to select other SPI devices, such as analog multiplexers, but CNV must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator. When the conversion is complete, the AD7685 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are

SDI = 1

CNVH

CNV

then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance.

CONVERT

DIGITAL HOST

DATA IN

CLK

CYC

CNV

AD7685

Figure 33.

SDOSDI

SCK

Mode 3-Wire, No BUSY Indicator

Connection Diagram (SDI High)

02968-032

SCK

SDO

CONV

CONVERSIONACQUISITION

Figure 34.

1 2 3 14 15 16

HSDO

D15 D14 D13 D1 D0

Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)

ACQ

ACQUISITION

DSDO

SCKL

SCKH

SCK

DIS

02968-033

Rev A | Page 19 of 28

Page 20

AD7685

Mode 3-Wire with BUSY Indicator

This mode is usually used when a single AD7685 is connected to an SPI compatible digital host having an interrupt input.

The connection diagram is shown in Figure 35 and the corresponding timing is given in Figure 36.

With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the

impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV could be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pullup on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7685 then enters the acquisition phase and powers

mode, and forces SDO to high

SDI = 1

CNVH

CNV

down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance.

CONVERT

VIO

CNV

AD7685

SCK

Figure 35.

SDOSDI

Mode 3-Wire with BUSY Indicator

Connection Diagram (SDI High)

CYC

47k

DIGITAL HOST

Ω

DATA IN

IRQ

CLK

02968-034

SCK

SDO

CONVERSIONACQUISITION

Figure 36.

CONV

ACQ

ACQUISITION

SCK

SCKL

1 2 3 15 16 17

HSDO

DSDO

D15 D14 D1 D0

Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)

SCKH

DIS

02968-035

Rev A | Page 20 of 28

Page 21

AD7685

Mode 4-Wire, No BUSY Indicator

This mode is usually used when multiple AD7685s are connected to an SPI compatible digital host.

A connection diagram example using two AD7685s is shown in Figure 37 and the corresponding timing is given in Figure 38.

With SDI high, a rising edge on CNV initiates a conversion, selects the

mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator. When the

conversion is complete, the AD7685 enters the acquisition phase and powers down. Each ADC result can be read by bringing low its SDI input which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge, or when SDI goes high, whichever is earlier, SDO returns to high impedance and another AD7685 can be read.

If multiple AD7685s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation.

CS2 CS1 CONVERT

CNV

AD7685

SCK

Figure 37.

CNV

SDOSDI

Mode 4-Wire, No BUSY Indicator Connection Diagram

AD7685

SDOSDI

SCK

DIGITAL HOST

DATA IN CLK

02968-036

CYC

CNV

ACQ

ACQUISITION

17 1816

D0 D15 D14

DIS

SSDICNV

SDI(CS1)

SDI(CS2)

SCK

SDO

HSDICNV

CONV

CONVERSIONACQUISITION

SCK

SCKL

DSDO

14 15

SCKH

123 303132

HSDO

D15 D14 D13 D1 D0

02968-037

Figure 38.

Mode 4-Wire, No BUSY Indicator Serial Interface Timing

Rev A | Page 21 of 28

Page 22

AD7685

Mode 4-Wire with BUSY Indicator

This mode is usually used when a single AD7685 is connected to an SPI compatible digital host, which has an interrupt input, and it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired.

The connection diagram is shown in Figure 39 and the corresponding timing is given in Figure 40.

low. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7685 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge, or SDI going high, whichever is earlier, the SDO returns to high impedance.

With SDI high, a rising edge on CNV initiates a conversion, selects the

mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to

CNV

CONV

CQUISITION

SSDICNV

SDI

HSDICNV

SCK

SDO

CONVERSION

Figure 40.

1 2 3 15 16 17

HSDO

DSDO

Mode 4-Wire with BUSY Indicator Serial Interface Timing

CNV

AD7685

ACQ

SCKL

Mode 4-Wire with BUSY Indicator Connection Diagram

SCK

SCKH

Figure 39.

CYC

ACQUISITION

D15 D14 D1 D0

SDOSDI

SCK

VIO

47kΩ

DIS

CS1 CONVERT

DIGITAL HOST

DATA IN

IRQ

CLK

02968-039

02968-038

Rev A | Page 22 of 28

Page 23

AD7685

Chain Mode, No BUSY Indicator

This mode can be used to daisy-chain multiple AD7685s on a 3-wire serial interface. This feature is useful for reducing component count and wiring connections, e.g., in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register.

A connection diagram example using two AD7685s is shown in Figure 41 and the corresponding timing is given in Figure 42.

When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion and selects the chain mode. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO and the

AD7685 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are then clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N clocks are required to readback the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate and, consequently more AD7685s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. For instance, with a 5 ns digital host set-up time and 3 V interface, up to eight AD7685s running at a conversion rate of 220 kSPS can be daisy-chained on a 3-wire port.

CONVERT

CNV

AD7685

SCK

SDOSDI

CNV

AD7685

SCK

DIGITAL HOST

SDOSDI

DATA IN

CLK

02968-040

Figure 41. Chain Mode Connection Diagram

SDIA = 0

CNV

SCK

HSCKCNV

DOA = SDI

SDO

CONV

CONVERSIONACQUISITION

SSCKCNV

1 2 3 30 31 32

HSDO

DSDO

SSDISCK

DA15 DA14 DA13

DB15 DB14 DB13 DA1DB1DB0DA15 DA14

SCKL

HSDISC

Figure 42. Chain Mode Serial Interface Timing

14 15

CYC

ACQUISITION

SCK

DA1

ACQ

SCKH

DA0

17 1816

DA0

02968-041

Rev A | Page 23 of 28

Page 24

AD7685

Chain Mode with BUSY Indicator

This mode can also be used to daisy chain multiple AD7685s on a 3-wire serial interface while providing a BUSY indicator. This feature is useful for reducing component count and wiring connections, e.g., in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register.

A connection diagram example using three AD7685s is shown in Figure 43 and the corresponding timing is given in Figure 44.

When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the BUSY indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the nearend ADC (ADC C in

Figure 43) SDO is driven high. This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host. The AD7685 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are then clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to readback the N ADCs. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge allows a faster reading rate and, consequently, more AD7685s in the chain, provided the digital host has an acceptable hold time. For instance, with a 5 ns digital host setup time and 3 V interface, up to eight AD7685s running at a conversion rate of 220 kSPS can be daisy-chained to a single 3-wire port.

CONVERT

CNV = SDI

CQUISITION

SCK

HSCKCNV

SDOA = SDI

SDOB = SDI

SDO

CNV

AD7685

SCK

CONV

CONVERSION

SSCKCNV

DSDOSDI

CNV

SDOSDI

AD7685

SCK

SDOSDI

CNV

AD7685

SCK

SDOSDI

DIGITAL HOST

DATA IN

IRQ

CLK

02968-042

Figure 43. Chain Mode with BUSY Indicator Connection Diagram

CYC

ACQ

ACQUISITION

SCKH

123 35 47 48

SSDISCK

DA15 DA14 DA13

HSDO

DSDO

DB15 DB14 DB13 DA1DB1DB0DA15 DA14

DC15 DC14 DC13 DA1DA0DC1DC0D

SCK

415

HSDISC

DA1

SCKL

17 3416

DA0

19 31 3218

DA0

1DB0DA15DB15 DB14

Figure 44. Chain Mode with BUSY Indicator Serial Interface Timing

02968-043

Rev A | Page 24 of 28

Page 25

AD7685

APPLICATION HINTS

LAYOUT

The printed circuit board that houses the AD7685 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7685 with all its analog signals on the left side and all its digital signals on the right side eases this task.

Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7685 is used as a shield. Fast switching signals, such as CNV or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided

At least one ground plane should be used. It could be common or split between the digital and analog section. In the latter case, the planes should be joined underneath the AD7685.

The AD7685 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and connected with wide, low impedance traces.

Figure 45. Example of Layout of the AD7685 ( Top Layer)

02968-044

Finally, the power supplies VDD and VIO should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7685 and connected using short and wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines.

An example layout following these rules is shown in Figure 45 and Figure 46.

EVALUATING THE AD7685’S PERFORMANCE

Other recommended layouts for the AD7685 are outlined in the documentation of the evaluation board for the AD7685 (

EVAL-AD7685). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3.

Figure 46. Example of Layout of the AD7685 (Bottom Layer)

02968-045

Rev A | Page 25 of 28

Page 26

AD7685

TRUE 16-BIT ISOLATED APPLICATION EXAMPLE

In applications where high accuracy and isolation are required, e.g., power monitoring, motor control, and some medical equipment, the circuit given in Figure 47, using the AD7685 and the ADuM1402C digital isolator, provides a compact and high performance solution.

Multiple AD7685s are daisy-chained to reduce the number of signals to isolate. Note that the SCKOUT, which is a readback of the AD7685’s clock, has a very short skew with the DATA signal. This skew is the channel-to-channel matching propagation delay of the

5V REF 5V

10µF 100nF

5V REF 5V

REF VDD

IN+

10µF 100nF

REF VDD

IN+

VIO

AD7685

IN– GND

VIO

AD7685

IN– GND

SDO SCK CNV

SDI

SDO SCK CNV

SDI

±10V INPUT

4kΩ

2V REF

4kΩ

2V REF

1kΩ

1/4 AD8618

1kΩ

1/4 AD8618

digital isolator (t

). This allows running the serial

PSKCD

interface at the maximum speed of the digital isolator (45 Mbits/s for the ADuM1402C), which would have been otherwise limited by the cascade of the propagation delays of the digital isolator.

The complete analog chain runs on a 5 V single supply using the ADR391 low dropout reference voltage and the rail-torail CMOS AD8618 amplifier while offering true bipolar input range.

100nF

DD1

GND

VIA

VIB

VOC

VOD

, V

ADuM1402C

DD2

, V

GND

VOA

VOB

VIC

VID

2.7V TO 5V

100nF

DATA

SCKOUT

SCKIN

CONVERT

5V REF 5V

10µF 100nF

5V REF 5V

REF VDD

IN+

10µF 100nF

REF VDD

IN+

AD7685

IN– GND

AD7685

IN–

GND

VIO

SDO SCK CNV

SDI

SDO SCK CNV

SDI

1kΩ1kΩ

5V REF

ADR391

OUT

GND

1kΩ

2V REF

4kΩ

100nF10µF

02968-046

±10V INPUT

4kΩ

2V REF

1kΩ

1/4 AD8618

1kΩ4kΩ

1/4 AD8618

Figure 47. A True 16-Bit Isolated Simultaneous Sampling Acquisition System

Rev A | Page 26 of 28

Page 27

AD7685

OUTLINE DIMENSIONS

3.00 BSC

PIN 1

0.50 BSC

0.95

0.85

0.75

0.15

0.00

0.27

0.17

COPLANARITY

0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA

Figure 48.10-Lead Micro Small Outline Package [MSOP]

INDEX

1.50

BCS SQ

0.80

0.75

0.70

SEATING

PLANE

AREA

3.00

BSC SQ

TOP VIEW

0.80 MAX

0.55 TYP

SIDE VIEW

0.30

0.23

0.18

Figure 49. 10-Terminal Quad Flat No Lead Package[QFN

4.90 BSC

1.10 MAX

SEATING PLANE

0.23

0.08

8° 0°

(RM-10)

Dimensions shown in millimeters

PIN 1 INDICATOR

0.50

BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

EXPOSED

(BOTTOM VIEW)

1.74

1.64

1.49

PAD

3 mm × 3 mm Body

(CP-10-9)

Dimensions shown in millimeters

0.80

0.60

0.40

2.48

2.38

2.23

PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES

(LFCSP)]

QFN package in development. Contact sales for samples and availability.

Rev A | Page 27 of 28

Page 28

AD7685

ORDERING GUIDE

Transport

Model

Integral Nonlinearity

No Missing Code

Temperature Range

Package Description

Package Option

Media, Quantity

AD7685ARM ±6 LSB max 15 Bits –40°C to +85°C MSOP RM-10 Tube, 50 C37 AD7685ARMRL7 ±6 LSB max 15 Bits –40°C to +85°C MSOP RM-10 Reel, 1,000 C37 AD7685BRM ±3 LSB max 16 Bits –40°C to +85°C MSOP RM-10 Tube, 50 C01 AD7685BRMRL7 ±3 LSB max 16 Bits –40°C to +85°C MSOP RM-10 Reel, 1,000 C01 AD7685CRM ±2 LSB max 16 Bits –40°C to +85°C MSOP RM-10 Tube, 50 C00 AD7685CRMRL7 ±2 LSB max 16 Bits –40°C to +85°C MSOP RM-10 Reel, 1,000 C00 EVAL-AD7685CB1 Evaluation Board EVAL-CONTROL BRD2

Controller Board

EVAL-CONTROL BRD32 Controller Board

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.

These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

Branding

D02968–0–12/04(A)

Rev A | Page 28 of 28

Datasheet AD7685 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

APPLICATION DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

CIRCUIT INFORMATION

CONVERTER OPERATION

Transfer Functions

TYPICAL CONNECTION DIAGRAM

Analog Input

Driver Amplifier Choice

Voltage Reference Input

Power Supply

Supplying the ADC from the Reference

DIGITAL INTERFACE

Mode 3-Wire, No BUSY Indicator

Mode 3-Wire with BUSY Indicator

Mode 4-Wire, No BUSY Indicator

Mode 4-Wire with BUSY Indicator

Chain Mode, No BUSY Indicator

Chain Mode with BUSY Indicator

APPLICATION HINTS

LAYOUT

EVALUATING THE AD7685’S PERFORMANCE

TRUE 16-BIT ISOLATED APPLICATION EXAMPLE

OUTLINE DIMENSIONS

ORDERING GUIDE