Datasheet AD7682 Datasheet (ANALOG DEVICES)

16-Bit, 4-Channel,

www.BDTIC.com/ADI

250 kSPS PulSAR® ADC

Preliminary Technical Data

FEATURES

16-bit resolution with no missing codes
4-channel multiplexer with:

Unipolar single ended or

Differential (GND sense)/pseudo-bipolar inputs
Throughput: 250 kSPS
INL/DNL: ±0.6 LSB typical
Dynamic range: 93.5 dB
SINAD: 92.5 dB @ 20 kHz
THD: −100 dB @ 20 kHz
Analog input range:

0 V to V

with V

REF

up to VDD

REF

Reference:

Internal selectable 2.5 V/4.096 V or

External buffered (up to 4.096 V)

External (up to VDD)
Internal temperature sensor
Channel sequencer, selectable 1-pole filter, BUSY indicator
No pipeline delay, SAR architecture
Single-supply 2.7V – 5.5 V operation with

1.8 V to 5 V logic interface
Serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible
Power dissipation:

6 mW @ 5 V/100 kSPS
Standby current: 1 nA
20-lead 4 mm × 4 mm LFCSP package

APPLICATIONS

Battery-powered equipment

Medical instruments
Mobile communications

Personal digital assitants
Data acquisition
Seismic data acquisition systems
Instrumentation
Process Control

IN0
IN1
IN2
IN3

COM

Table 1. Multichannel14-/16-Bit PulSAR ADC

Type Channels

14-Bit 8 AD7949 ADA4841-x
16-Bit 4 AD7682 ADA4841-x
16-Bit 8 AD7689 AD7699 ADA4841-x

GENERAL DESCRIPTION

The AD7682 is a 4-channel 16-bit, charge redistribution successive
approximation register (SAR), analog-to-digital converter (ADC)
that operates from a single power supply, VDD.

The AD7682 contains all of the components for use in a multi­channel, low power, data acquisition system including: a true 16-bit
SAR ADC with no missing codes; a 4-channel, low crosstalk
multiplexer useful for configuring the inputs as single ended (with
or without ground sense), differential or bipolar; an internal low
drift reference (selectable 2.5V or 4.096V) and buffer; a
temperature sensor; a selectable 1-pole filter; and a sequencer
useful when channels are continuously scanned in order.

The AD7682 uses a simple SPI interface for writing to the
configuration register and receiving conversion results. The SPI
interface uses a separate supply, VIO, which is set to the host logic
level.

Power dissipation scales with throughput.

The AD7682 is housed in a tiny 20-lead LFCSP with operation
specified from −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

0.5V to 4.096V

Band Gap

REF

Temp

Sensor

0.1μF

REFIN

MUX

0.5V to VDD

10μF

1-Pole

LPF

REF

16-Bit SAR

Sequencer

Figure 1.

250
kSPS

ADC

AD7682

2.7V to 5V

VDD

AD7682

SPI Serial

Interface

GND

500
kSPS

VIO

ADC
Driver

1.8V to
VDD

CNV
SCK

SDO
DIN

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

AD7682 Preliminary Technical Data

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 7

ESD Caution...................................................................................7

Pin Configurations and Function Descriptions............................8

Typical Performance Characteristics..............................................9

Terminology.................................................................................... 10

Outline Dimensions....................................................................... 11

Ordering Guide .......................................................................... 11

Rev. PrA | Page 2 of 11

Preliminary Technical Data AD7682

www.BDTIC.com/ADI

SPECIFICATIONS

VDD = 2.5 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 2.

Parameter Conditions/Comments Min Typ Max Unit

RESOLUTION 16 Bits
ANALOG INPUT

Voltage Range Unipolar mode 0 +V
Bipolar mode −V
Absolute Input Voltage

Analog Input CMRR fIN = 250 kHz TBD dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance

THROUGHPUT

Conversion Rate VDD = 4.096V to 5.5 0 250 kSPS
VDD = 2.5V to 4.096V 1 200
Transient Response Full-scale step 1.8

ACCURACY

No Missing Codes 16 Bits
Integral Linearity Error -2 ±0.6 +2 LSB1
Differential Linearity Error −1 ±0.25 +1.5 LSB
Transition Noise REF = VDD = 5 V 0.5 LSB
Gain Error2 −30 ±0.5 +30 LSB
Gain Error Match TBD LSB
Gain Error Temperature Drift ±0.3 ppm/°C
Offset Error2 −5 ±0.5 +5 LSB
Offset Error Match TBD LSB
Offset Error Temperature Drift ±0.3 ppm/°C
Power Supply Sensitivity

AC ACCURACY3

Dynamic Range 93.5 dB4
Signal-to-Noise fIN = 20 kHz, VREF = 5V 92.5 dB
f
Signal-to-(Noise + Distortion) fIN = 20 kHz, VREF = 5V 92.5 dB
f
Total Harmonic Distortion fIN = 20 kHz −100 dB
Spurious-Free Dynamic Range fIN = 20 kHz 110 dB
Channel-to-Channel Crosstalk

Intermodulation Distortion5 115 dB

SAMPLING DYNAMICS

−3 dB Input Bandwidth Selectable 0.425 1.7 MHz
Aperture Delay VDD = 5V 2.5 ns

1

LSB means least significant bit. With the 5 V input range, one LSB is 76.3 µV.

2

See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.

3

With V

= 5 V, unless otherwise noted.

REF

4

All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

5

f

= 21.4 kHz and f

IN1

= 18.9 kHz, with each tone at −7 dB below full scale.

IN2

= VDD, all specifications T

REF

Positive input, unipolar and

MIN

to T

, unless other wise noted.

MAX

/2 +V

REF

−0.1 V

V

REF

/2

REF

+ 0.1 V

REF

bipolar mode
Negative or COM input, unipolar

−0.1 +0.1

mode
Negative or COM input, bipolar

/2 – 0.1 V

REF

/2 V

REF

/2 + 0.1

REF

V

mode

VDD = 5 V ± 5%

= 20 kHz, VREF = 2.5V 88.5

IN

= 20 kHz, VREF = 2.5V 88.5 dB

IN

= 100 kHz on adjacent

f

IN

±1 ppm

-117 dB

channel(s)

μs

Rev. PrA | Page 3 of 11

AD7682 Preliminary Technical Data

www.BDTIC.com/ADI

VDD = 2.5 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 3.

Parameter Conditions/Comments Min Typ Max Unit

INTERNAL REFERENCE

Output Voltage For 4.096 V output, @ 25°C 4.086 4.096 4.106
For 2.5 V output, @ 25°C 2.490 2.500 2.510
Temperature Drift –40°C to +85°C ±TBD
Line Regulation VDD = 5 V ± 5% ±TBD
Long-Term Drift 1000 hours 50
Turn-On Settling Time C

EXTERNAL REFERENCE

Voltage Range REF Input 0.5 VDD + 0.3 V
REFIN Input (Buffered) 0.5 VDD – 0.2 V
Current Drain 250 kSPS, REF = 5V 50 µA

TEMPERATURE SENSOR

Output Voltage1 @ 25°C 283 mV
Temperature Sensitivity 1 mV/°C

DIGITAL INPUTS

Logic Levels

VIL −0.3 +0.3 × VIO V
VIH 0.7 × VIO VIO + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA

DIGITAL OUTPUTS

Data Format2
Pipeline Delay3
VOL I
VOH I

POWER SUPPLIES

VDD Specified performance 2.3 5.5 V
VIO Specified performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V

Standby Current

4, 5

VDD and VIO = 5 V, 25°C 1 50 nA
Power Dissipation VDD = 5V , 100 kSPS throughput 6 mW
VDD = 5V , 250 kSPS throughput 15 mW

Energy per Conversion 50 nJ

TEMPERATURE RANGE6

Specified Performance T

1

The output voltage is internal and present on a dedicated multiplexer input.

2

Unipolar mode: serial 16-bit straight binary

Bipolar mode: serial 16-bit 2’s complement.

3

Conversion results available immediately after completed conversion.

4

With all digital inputs forced to VIO or GND as required.

5

During acquisition phase.

6

Contact an Analog Devices sales representative for the extended temperature range.

= VDD, all specifications T

REF

= 22 µF TBD

REF

= +500 µA 0.4 V

SINK

= −500 µA VIO − 0.3 V

SOURCE

VDD = 5V , 250 kSPS throughput

MIN

to T

, unless other wise noted.

MAX

18.5 mW
internal reference and buffer
enabled

to T

MIN

−40 +85 °C

MAX

V
V
ppm/°C
ppm/V
ppm
ms

Rev. PrA | Page 4 of 11

Preliminary Technical Data AD7682

www.BDTIC.com/ADI

TIMING SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, all specifications T

Table 4.

1

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width t
Data Write/Read During Conversion t
SCK Period t
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t

VIO Above 4.5 V 14 ns
VIO Above 3 V 15 ns
VIO Above 2.7 V 16 ns
VIO Above 2.3 V 17 ns

CNV Low to SDO D15 MSB Valid tEN

VIO Above 4.5 V 15 ns
VIO Above 2.7 V 18 ns

VIO Above 2.3 V 22 ns
CNV High or Last SCK Falling Edge to SDO High Impedance t
CNV Low to SCK High t
DIN Valid Setup Time t
DIN Valid Hold Time t

1

See Figure 2 and Figure 3 for load conditions.

MIN

to T

, unless otherwise noted.

MAX

2.2 µs

CONV

1.8 µs

ACQ

4 µs

CYC

10 ns

CNVH

1.5 µs

DATA

15 ns

SCK

7 ns

SCKL

7 ns

SCKH

4 ns

HSDO

DSDO

25 ns

DIS

10 ns

CLSCK

4 ns

SDIN

4 ns

HDIN

Rev. PrA | Page 5 of 11

AD7682 Preliminary Technical Data

T

2

www.BDTIC.com/ADI

VDD = 2.5 V to 4.5 V, VIO = 2.3 V to VDD, all specifications T

1

Table 5.

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width t
Data Write/Read During Conversion t
SCK Period t
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t

VIO Above 3 V 24 ns
VIO Above 2.7 V 30 ns
VIO Above 2.3 V 35 ns

CNV Low to SDO D15 MSB Valid tEN

VIO Above 2.7 V 18 ns

VIO Above 2.3 V 22 ns
CNV High or Last SCK Falling Edge to SDO High Impedance t
CNV Low to SCK High t
SDI Valid Setup Time t
SDI Valid Hold Time t

1

See Figure 2 and Figure 3 for load conditions.

MIN

to T

, unless otherwise noted.

MAX

3.2 µs

CONV

1.8 µs

ACQ

5 µs

CYC

10 ns

CNVH

0.7 µs

DATA

25 ns

SCK

12 ns

SCKL

12 ns

SCKH

5 ns

HSDO

DSDO

25 ns

DIS

10 ns

CSCK

5 ns

SDIN

4 ns

HDIN

O SDO

50pF

C

L

500µA I

500µA I

OL

OH

1.4V

00

Figure 2. Load Circuit for Digital Interface Timing

30% VIO

t

DELAY

2V OR VIO – 0.5V

0.8V OR 0. 5V

1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF V IO BELOW 2.5V.

2. 0.8V IF VIO ABOVE 2.5 V , 0.5V I F VIO BELOW 2.5V.

Figure 3. Voltage Levels for Timing

70% VIO

t

DELAY

1

2

2V OR VIO – 0.5V

0.8V OR 0.5 V

1

2

003

Rev. PrA | Page 6 of 11

Preliminary Technical Data AD7682

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Analog Inputs

INn, COM

REF, REFIN GND − 0.3 V to VDD + 0.3 V
Supply Voltages

VDD, VIO to GND −0.3 V to +7 V

VDD to VIO ±7 V
DIN, CNV, SCK to GND −0.3 V to VIO + 0.3 V
SDO to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance (MSOP-10) 200°C/W
θJC Thermal Impedance (MSOP-10) 44°C/W

GND − 0.3 V to VDD + 0.3 V
or ±130 mA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. PrA | Page 7 of 11

AD7682 Preliminary Technical Data

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

IN0

IN1

NC

VDD

NC

6

17

1

18

19

20

PIN 1

1VDD
2REF
3REFIN
4GND
5GND

INDICATOR

TOP VIEW

15 VIO
14 SDO
13 SCK
12 DIN
11 CNV

9

8

6

7

10

NC

NC

IN3

IN2

NC = NO CONNECT

Figure 4. 20-Lead LFCSP Pin Configuration

COM

00000-004

Table 7. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1, 20 VDD P

Power Supply. Nominally 2.5 V to 5.5 V when using an external reference, and decoupled with
10 F and 100 nF capacitors.
When using the internal reference for 2.5V output, the minimum should be 2.7V.
When using the internal reference for 4.096V output, the minimum should be 4.5V.

2 REF AI/O

Reference Input/Output.
When the internal reference is enabled, this pin produces a selectable system reference = 2.5V or

4.096V.
When the internal reference is disabled and the buffer is enabled, REF produces a buffered
version of the voltage present on the REFIN pin (4.096V max.) useful when using low cost, low
power references.
For improved drift performance, connect a precision reference to REF (0.5V to VDD).
For any reference method, this pin needs decoupling with an external a 10 F capacitor
connected as close to REF as possible. See

3 REFIN AI/O Internal Reference Output/Reference Buffer Input.

When using the internal reference, the internal unbuffered reference voltage is present and
needs decoupling with a 0.1F capacitor.
When using the internal reference buffer, apply a source between 0.5V to 4.096V which is

buffered to the REF pin as described above.
4, 5 GND P Power Supply Ground.
7, 9, 16,

18

IN2, IN3, IN0,
IN1

10 COM AI

11 CNV DI

AI Analog Inputs.

Common Channel Input. All channels [7:0] can be referenced to a common mode point of 0 V or

/2 V.

V

REF

Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is

held high, the BUSY indictor is enabled.
12 DIN DI

Data Input. This input is used for writing to the 14-bit configuration register. The configuration

register can be written to during and after conversion.
13 SCK DI

Serial Data Clock Input. This input is used to clock out the data on ADO and clock in data on DIN

in an MSB first fashion.
14 SDO DO

Serial Data Output. The conversion result is output on this pin synchronized to SCK. In unipolar

modes, conversion results are straight binary; in bipolar modes conversion results are twos

complement.
15 VIO P

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,

2.5 V, 3 V, or 5 V).

1

AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.

Rev. PrA | Page 8 of 11

Preliminary Technical Data AD7682

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

2

1.5

1

0.5

0

INL (LSB)

-0.5

-1

-1.5

-2
0 16384 32768 49152 65536

CODE

Figure 5. Integral Nonlinearity vs. Code, VREF = 5V

200000

180000

160000

140000

120000

100000

COUNTS

80000

60000

40000

20000

00

0

7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004

196433

27695

44 76

36872

CODE IN HEX

σ = 0.44
V

REF

= 5V

00

1

0.75

0.5

0.25

0

DNL (LSB)

-0.25

-0.5

-0.75

-1
0 16384 32768 49152 65536

CODE

Figure 8. Differential Nonlinearity vs. Code, VREF = 5V

200000

180000

160000

140000

120000

100000

COUNTS

80000

60000

40000

20000

00

0

7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002

784

171449

50640

37789

CODE IN HEX

457

σ =

V

REF

0.83
= 2.5V

10

Figure 6. Histogram of a DC Input at Code Center, VREF = 5V

0

-20

-40

-60

-80

-100

-120

AMPLITUDE (dB of Full Scale)

-140

-160

-180

0

5

2

0

5

FREQUENCY (kHz)

5

7

fs = 250 kSPS

= 10.1 kHz

f

IN

SNR = 91.1 dB
THD = -102 dB
SFDR = 103 dB
SINAD = 91 dB

0

0

1

Figure 7. 10kHz FFT, VREF = 5V

5

2

1

Figure 9. Histogram of a DC Input at Code Center, VREF = 2.5V

0

-20

-40

-60

-80

-100

-120

AMPLITUDE (dB of Full Scale)

-140

-160

-180

0

5

2

Figure 10. 10kHz FFT, VREF = 2.5V

Rev. PrA | Page 9 of 11

0

5

FREQUENCY (kHz)

5

7

fs = 250 kSPS

= 10.1 kHz

f

IN

SNR = 87.1 dB
THD = -104 dB
SFDR = 104 dB
SINAD = 87 dB

0

0

1

5

2

1

AD7682 Preliminary Technical Data

www.BDTIC.com/ADI

TERMINOLOGY

Least Significant Bit (LSB)

The LSB is the smallest increment that can be represented by a
converter. For an analog-to-digital converter with N bits of
resolution, the LSB expressed in volts is

V

LSB2(V) =

REF

N

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.

Offset Error

The first transition should occur at a level ½ LSB above analog
ground (38.14μV). The unipolar offset error is the deviation of
the actual transition from that point.

Gain Error

The last transition (from 111…10 to 111…11) should occur for
an analog voltage 1½ LSB below the nominal full-scale. The gain
error is the deviation in LSB (or % of full-scale range) of the
actual level of the last transition from the ideal level after the
offset error is adjusted out. Closely related is the full-scale error
(also in LSB or % of full-scale range), which includes the effects
of the offset error.

Aperture Delay

Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.

Transient Response

Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:

ENOB = (SINAD

− 1.76)/6.02

dB

and is expressed in bits.

Channel-to-Channel Crosstalk

Channel-to-channel crosstalk is a measure of the level of
crosstalk between any two adjacent channels. It is measured by
applying a DC to the channel under test and applying a full-scale,
100 kHz sine wave signal to the adjacent channel(s). The
crosstalk is the amount of signal that leaks into the test channel
and is expressed in dB.

Reference Voltage Temperature Coefficient

Reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (V
ured at T

, T(25°C), and T

MIN

TCV

REF

. It is expressed in ppm/°C as

MAX

MinVMaxV

)(–)(

)Cppm/( ×

=°

REF

REFREF

MAX

TTV

MIN

×°

) meas-

REF

6

10

)–()C25(

where:

V

(Max) = maximum V

REF

V

(Min) = minimum V

REF

(25°C) = V

V

REF

T

MAX

T

MIN

= +85°C.

= –40°C.

REF

at 25°C.

REF

REF

at T

at T

MIN

, T(25°C), or T

MIN

, T(25°C), or T

MAX

MAX

.

.

Rev. PrA | Page 10 of 11

Preliminary Technical Data AD7682

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.08

0.50

BSC

0.50

0.40

0.30

0.60 MAX

15

11

16

EXPOSED

PAD

(BOTT OM VIEW)

10

P

N

1

I

R

A

O

T

N

D

C

I

20

6

I

1

2.65

2.50 SQ

2.35

5

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING

PLANE

12° MAX

4.00

BSC SQ

TOP VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

3.75

BCS SQ

0.20 REF

0.60 MAX

0.05 MAX

0.02 NOM
COPLANARITY

ORDERING GUIDE

COMPLIANT

TO

JEDEC STANDARDS MO-220-VGGD-1

Figure 11. 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

4 mm × 4 mm Body, Very Thin Quad

(CP-20-4)

Dimensions shown in millimeters

081407-B

©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07353-0-2/08(PrA)

Rev. PrA | Page 11 of 11