3 mW, 100 kSPS,
FEATURES
Fast throughput rate: 100 kSPS
Specified for V
Low power
3 mW typ at 100 kSPS with 2.5 V supply
3.9 mW typ at 100 kSPS with 3 V supply
16.7 mW typ at 100 kSPS with 5 V supply
Wide input bandwidth
86 dB SNR at 10 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®/QSPI™/µWire/DSP compatible
Standby mode: 0.5 µA max
6-Lead SOT-23 and 8-Lead MSOP packages
APPLICATIONS
Battery-powered systems:
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Remote data acquisition systems
High speed modems
Optical sensors
GENERAL DESCRIPTION
The AD7680 is a 16-bit, fast, low power, successive approximation
ADC. The part operates from a single 2.5 V to 5.5 V power
supply and features throughput rates up to 100 kSPS. The part
contains a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 7 MHz.
The conversion process and data acquisition are controlled
CS
using
and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
point. There are no pipeline delays associated with the part.
of 2.5 V to 5.5 V
DD
CS
and the conversion is also initiated at this
16-Bit ADC in 6-Lead SOT-23
AD7680
FUNCTIONAL BLOCK DIAGRAM
V
DD
GND
16-BIT SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
Figure 1.
SCLK
SDATA
CS
03643-0-001
IN
T/H
AD7680
V
Table 1. MSOP/SOT-23 16-Bit PulSAR ADC
Type/kSPS 100 kSPS 250 kSPS 500 kSPS
True Differential AD7684 AD7687 AD7688
Pseudo Differential AD7683 AD7685 AD7686
Unipolar AD7680
PRODUCT HIGHLIGHTS
1. First 16-bit ADC in a SOT-23 package.
2. High throughput with low power consumption.
3. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced when a power-down mode is used while not
converting. The part also features a shutdown mode to
maximize power efficiency at lower throughput rates.
Power consumption is 0.5 µA max when in shutdown.
The AD7680 uses advanced design techniques to achieve very
low power dissipation at fast throughput rates. The reference for
the part is taken internally from V
, which allows the widest
DD
dynamic input range to the ADC. Thus, the analog input range
for this part is 0 V to V
. The conversion rate is determined by
DD
the SCLK frequency.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
4. Reference derived from the power supply.
5. No pipeline delays.
This part features a standard successive approximation ADC
with accurate control of the sampling instant via a
once-off conversion control.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
CS
input and
AD7680
TABLE OF CONTENTS
Specifications..................................................................................... 3
Digital Inputs.......................................................................... 13
Timing Specifications....................................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Circuit Information........................................................................ 12
Converter Operation.................................................................. 12
Analog Input............................................................................... 12
ADC Transfer Function................................................................. 13
Typical Connection Diagram ................................................... 13
REVISION HISTORY
Revision 0: Initial Version
Modes of Operation ....................................................................... 14
Normal Mode.............................................................................. 14
Power-Down Mode.................................................................... 15
Power vs. Throughput Rate ........................................................... 16
Serial Interface ................................................................................ 17
AD7680 to ADSP-218x.............................................................. 18
Application Hints ........................................................................... 19
Grounding and Layout .............................................................. 19
Evaluating the AD7680 Performance ...................................... 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Rev. 0 | Page 2 of 20
AD7680
SPECIFICATIONS1
Table 2. VDD = 4.5 V to 5.5 V, f
Parameter A, B Versions1 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 10 kHz sine wave
Signal-to-Noise + Distortion (SINAD)2 83 dB min
85 dB typ
Signal-to-Noise Ratio (SNR)2 84 dB min
86 dB typ
Total Harmonic Distortion (THD)2 −97 dB typ
Peak Harmonic or Spurious Noise (SFDR)2 −95 dB typ
Intermodulation Distortion (IMD)2
Second-Order Terms −94 dB typ
Third-Order Terms −100 dB typ
Aperture Delay 20 ns max
Aperture Jitter 30 ps typ
Full Power Bandwidth 8 MHz typ @ −3 dB
2.2 MHz typ @ −0.1 dB
DC ACCURACY
No Missing Codes 15 Bits typ
Integral Nonlinearity2 ±4 LSB typ
Offset Error2 ±1.68 mV max
Gain Error2 ±0.038 % FS max
ANALOG INPUT
Input Voltage Ranges 0 to VDD V
DC Leakage Current ±0.3 µA max
Input Capacitance 30 pF typ
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
2.8 V min
INH
0.4 V max
INL
Input Current, IIN ±0.3 µA max Typically 10 nA, VIN = 0 V or VDD
Input Capacitance, C
2, 3
10 pF max
IN
LOGIC OUTPUTS
Output High Voltage, VOH VDD − 0.2 V min I
Output Low Voltage, VOL 0.4 V max I
Floating-State Leakage Current ±0.3 µA max
Floating-State Output Capacitance
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 8 µs max 20 SCLK cycles with SCLK at 2.5 MHz
9.6 µs max 24 SCLK cycles with SCLK at 2.5 MHz
Track-and-Hold Acquisition Time 1.5 µs max
400 ns max Sine wave input ≤ 10 kHz
Throughput Rate 100 kSPS See the Serial Interface section
POWER REQUIREMENTS
VDD 4.5/5.5 V min/V max
IDD Digital I/PS = 0 V or VDD
Normal Mode (Static) 5.2 mA max SCLK on or off. VDD = 5.5 V
Normal Mode (Operational) 4.8 mA max f
Full Power-Down Mode 0.5 µA max SCLK on or off. VDD = 5.5 V
Power Dissipation4 V
Normal Mode (Operational) 26.4 mW max f
Full Power-Down 2.75 µW max
1
Temperature range as follows: B Version: −40°C to +85°C.
2
See the Terminology section.
3
Sample tested during initial release to ensure compliance.
4
See the Power vs. Throughput Rate section.
= 2.5 MHz, f
SCLK
2, 3
10 pF max
= 100 kSPS, unless otherwise noted; TA = T
SAMPLE
to T
MIN
= 200 µA
SOURCE
= 200 µA
SINK
= 100 kSPS. VDD = 5.5 V; 3.3 mA typ
SAMPLE
= 5.5 V
DD
= 100 kSPS
SAMPLE
, unless otherwise noted
MAX
Rev. 0 | Page 3 of 20
AD7680
SPECIFICATIONS1
Table 3. VDD = 2.5 V to 4.096 V, f
Parameter A Version1 B Version1 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 10 kHz sine wave
Signal-to-Noise + Distortion (SINAD)2 83 83 dB min VDD = 4.096 V
82 82 dB min VDD = 2.5 V to 3.6 V
86 86 dB typ
Signal-to-Noise Ratio (SNR)2 84 84 dB min VDD = 4.096 V
83 83 dB min VDD = 2.5 V to 3.6 V
86 86 dB typ
Total Harmonic Distortion (THD) 2 −98 −98 dB typ
Peak Harmonic or Spurious Noise (SFDR)2 −95 −99 dB typ
Intermodulation Distortion (IMD)2
Second-Order Terms −94 −94 dB typ
Third-Order Terms −100 −100 dB typ
Aperture Delay 20 10 ns max
Aperture Jitter 30 30 ps typ
Full Power Bandwidth 7 7 MHz typ @ −3 dB; VDD = 4.096 V
5 5 MHz typ @ −3 dB; VDD = 2.5 V to 3.6 V
2 2 MHz typ @ −0.1 dB; VDD = 4.096 V
1.6 1.6 MHz typ @ −0.1 dB; VDD = 2.5 V to 3.6 V
DC ACCURACY
No Missing Codes 14 15 Bits min
Integral Nonlinearity2 ±3.5 ±3.5 LSB max VDD = 4.096 V
±3 ±3 LSB max VDD = 2.5 V to 3.6 V
Offset Error2 ±1.25 ±1.25 mV max VDD = 4.096 V
±1.098 ±1.098 mV max VDD = 2.5 V to 3.6 V
Gain Error2 ±0.038 ±0.038 % FS max
ANALOG INPUT
Input Voltage Ranges 0 to V
DC Leakage Current ±0.3 ±0.3 µA max
Input Capacitance 30 30 pF typ
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
IN
Input Capacitance, C
2.4 2.4 V min
INH
0.4 0.4 V max
INL
±0.3 ±0.3 µA max Typically 10 nA, VIN = 0 V or VDD
2, 3
10 10 pF max
IN
LOGIC OUTPUTS
Output High Voltage, V
V
OH
Output Low Voltage, VOL 0.4 0.4 V max I
Floating-State Leakage Current ±0.3 ±0.3 µA max
Floating-State Output Capacitance
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 8 8 µs max 20 SCLK cycles with SCLK at 2.5 MHz
9.6 9.6 µs max 24 SCLK cycles with SCLK at 2.5 MHz
Track-and-Hold Acquisition Time 1.5 1.5 µs max Full-scale step input
400 400 ns max Sine wave input ≤ 10 kHz
Throughput Rate 100 100 kSPS See the Serial Interface section
= 2.5 MHz, f
SCLK
2, 3
10 10 pF max
= 100 kSPS, unless otherwise noted; TA = T
SAMPLE
0 to V
DD
− 0.2 VDD − 0.2 V min I
DD
V
DD
MIN
= 200 µA
SOURCE
= 200 µA
SINK
to T
, unless otherwise noted.
MAX
Rev. 0 | Page 4 of 20
AD7680
Parameter A Version1 B Version1 Unit Test Conditions/Comments
POWER REQUIREMENTS
VDD 2.5/4.096 2.5/4.096 V min/max
IDD Digital I/Ps = 0 V or VDD
Normal Mode (Static) 2.8 2.8 mA max SCLK on or off; VDD = 4.096 V
2 2 mA max SCLK on or off; VDD = 3.6 V
Normal Mode (Operational) 2.6 2.6 mA max f
1.9 1.9 mA max f
Full Power-Down Mode 0.3 0.3 µA max SCLK on or off
Power Dissipation4
Normal Mode (Operational) 10.65 10.65 mW max f
6.84 6.84 mW max f
3 3 mW typ VDD = 2.5 V
Full Power-Down 1.23 1.23 µW max VDD = 4.096V
1.08 1.08 µW max VDD = 3.6 V
1
Temperature range as follows: A, B Versions: −40°C to +85°C.
2
See the Terminology section.
3
Sample tested during initial release to ensure compliance.
4
See the Power vs. Throughput Rate section.
= 100 kSPS; VDD = 4.096 V; 1.75 mA typ
SAMPLE
= 100 kSPS; VDD = 3.6 V; 1.29 mA typ
SAMPLE
= 100 kSPS; VDD = 4.096 V
SAMPLE
= 100 kSPS; VDD = 3.6 V
SAMPLE
Rev. 0 | Page 5 of 20
AD7680
TIMING SPECIFICATIONS1
Table 4. VDD = 2.5 V to 5.5 V; TA = T
Limit at T
MIN
, T
MAX
Parameter 3 V 5 V Unit Description
2
f
250 250 kHz min
SCLK
2.5 2.5 MHz max
t
20 × t
CONVERT
t
100 100 ns min Minimum quiet time required between bus relinquish and start of next conversion
QUIET
20 × t
SCLK
t1 10 10 ns min
t2 10 10 ns min
3
t
48 35 ns max
3
3
t
120 80 ns max Data access time after SCLK falling edge
4
t5 0.4 t
t6 0.4 t
0.4 t
SCLK
0.4 t
SCLK
SCLK
SCLK
t7 10 10 ns min SCLK to data valid hold time
4
t
45 35 ns max SCLK falling edge to SDATA high impedance
8
5
t
1 1 µs typ Power up time from full power-down
POWER-UP
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
5
See Power vs. Throughput Rate section.
MIN
to T
, unless otherwise noted.
MAX
min
SCLK
Minimum
CS
Delay from
CS
pulse width
to SCLK setup time
CS
until SDATA three-state disabled
ns min SCLK low pulse width
ns min SCLK high pulse width
, quoted in the timing characteristics is the true bus relinquish
8
200µAI
TO OUTPUT
PIN
C
L
50pF
200µAI
Figure 2. Load Circuit for Digital Output Timing Specification
OL
1.6V
OH
03643-0-002
Rev. 0 | Page 6 of 20
AD7680
ABSOLUTE MAXIMUM RATINGS
Table 5. TA = 25°C, unless otherwise noted.
Parameter Rating
VDD to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range
Commercial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
SOT-23 Package, Power Dissipation 450 mW
θJA Thermal Impedance 229.6°C/W
θJC Thermal Impedance 91.99°C/W
MSOP Package, Power Dissipation 450 mW
θJA Thermal Impedance 205.9°C/W
θJC Thermal Impedance 43.74°C/W
Lead Temperature, Soldering
Vapor Phase (60 secs) 215°C
Infared (15 secs) 220°C
ESD 2 kV
1
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 20
AD7680
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SOT-23
V
GND
V
DD
IN
1
AD7680
2
TOP VIEW
3
(Not to Scale)
6
5
4
CS
SDATA
SCLK
Figure 3. SOT-23 Pin Configuration
03643-0-003
V
GND
GND
V
DD
MSOP
1
AD7680
2
TOP VIEW
3
(Not to Scale)
4
IN
NC = NO CONNECT
Figure 4. MSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
SOT-23
1 1 VDD Power Supply Input. The V
2 2, 3 GND
Pin No.
MSOP Mnemonic Function
Analog Ground. Ground reference point for all circuitry on the AD7680. All analog input signals should
range for the AD7680 is from 2.5 V to 5.5 V.
DD
be referred to this GND voltage.
3 4 VIN Analog Input. Single-ended analog input channel. The input range is 0 V to V
4 5 SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from this part. This clock
input is also used as the clock source for the AD7680's conversion process.
5 7 SDATA
Data Out. Logic output. The conversion result from the AD7680 is provided on this output as a serial
data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the
AD7680 consists of four leading zeros followed by 16 bits of conversion data that are provided MSB
CS
first. This will be followed by four trailing zeroes if
is held low for a total of 24 SCLK cycles. See the
Serial Interface section.
6 8
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7680 and framing the serial data transfer.
N/A 6 NC No Connect. This pin should be left unconnected.
8
7
6
5
CS
SDATA
NC
SCLK
.
DD
03643-0-022
Rev. 0 | Page 8 of 20
AD7680
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point
1/2 LSB below the first code transition, and full scale, a point
1/2 LSB above the last code transition.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7680, it is defined as
2
2
2
2
dBTHD
= log20)(
2
4
3
V
1
++++
5
2
VVVVV
6
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Gain Error
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., V
− 1 LSB) after the offset
REF
error has been adjusted out.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1 LSB, after the end of the conversion.
See the Serial Interface section for more details.
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (f
/2, excluding dc). The ratio
S
depends on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-(noise + distortion) ratio for an ideal N-bit
converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 16-bit converter, this is 98 dB.
where V1 is the rms amplitude of the fundamental and V2, V3,
, V5, and V6 are the rms amplitudes of the second through the
V
4
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
/2, excluding dc) to the rms value of the
S
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities creates distortion products
at the sum and difference frequencies of mfa ± nfb where m, n =
0, 1, 2, 3. Intermodulation distortion terms are those for which
neither m nor n are equal to zero. For example, the second-order
terms include (fa + fb) and (fa − fb), while the third-order terms
include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa −2fb).
The AD7680 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.
Rev. 0 | Page 9 of 20
AD7680
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5 shows a typical FFT plot for the AD7680 at 100 kSPS
sample rate and 10 kHz input frequency. Figure 6 shows the
signal-to-(noise + distortion) ratio performance versus the
input frequency for various supply voltages while sampling at
100 kSPS with an SCLK of 2.5 MHz.
0
–20
–40
–60
–80
dB
–100
–120
–140
–160
0 10k 20k 30k 40k
FREQUENCY (kHz)
Figure 5. AD7680 Dynamic Performance at 100 kSPS
95
F
= 100kSPS
SAMPLE
T
= 25°C
A
VDD = 5V
F
= 100kSPS
SAMPLE
= 10kHz
F
IN
SNR = 88.28dB
SINAD = 87.82dB
THD = –97.76dB
SFDR = –98.25dB
03643-0-021
50k
Figure 7 shows a graph of the total harmonic distortion versus
the analog input frequency for various supply voltages, while
Figure 8 shows a graph of the total harmonic distortion versus
the analog input frequency for various source impedances (see
the Analog Input section). Figure 9 and Figure 10 show the
typical INL and DNL plots for the AD7680.
110
105
100
THD (dB)
95
90
10
INPUT FREQUENCY (kHz)
Figure 7. AD7680 THD vs. Analog Input Frequency
for Various Supply Voltages at 100 kSPS
110
105
F
SAMPLE
T
= 25°C
A
RIN = 10Ω
= 100kSPS
V
= 4.3V
DD
VDD = 4.75V
= 3.6V
V
DD
V
= 5.25V
DD
= 3.0V
V
DD
= 2.7V
V
DD
V
= 2.5V
DD
100
03643-0-017
90
SINAD (dB)
85
80
10
V
= 5.25V
DD
VDD = 2.5V
INPUT FREQUENCY (kHz)
Figure 6. AD7680 SINAD vs. Analog Input Frequency
for Various Supply Voltages at 100 kSPS
V
V
V
V
V
= 4.75V
DD
= 4.3V
DD
= 3.6V
DD
= 3.0V
DD
= 2.7V
DD
100
03643-0-016
100
95
90
THD (dB)
85
F
= 100kSPS
SAMPLE
80
= 25°C
T
A
= 4.75V
V
DD
75
10
INPUT FREQUENCY (kHz)
Figure 8. AD7680 THD vs. Analog Input Frequency
for Various Source Impedances
R
R
IN
R
IN
= 50Ω
IN
= 100Ω
= 1000Ω
03643-0-018
100
Rev. 0 | Page 10 of 20
AD7680
2.5
2.0
VDD = 3.0V
TEMP = 25
°
C
1.5
1.0
VDD = 3.0V
TEMP = 25
°
C
1.5
1.0
0.5
INL ERROR (LSB)
0
–0.5
–1.0
0 10000 20000 30000 40000 50000 60000
CODE
Figure 9. AD7680 Typical INL
03643-0-019
70000
0.5
0
–0.5
DNL ERROR (LSB)
–1.0
–1.5
0 10000 20000 30000 40000 50000 60000
CODE
Figure 10. AD7680 Typical DNL
03643-0-020
70000
Rev. 0 | Page 11 of 20
AD7680
V
CIRCUIT INFORMATION
The AD7680 is a fast, low power, 16-bit, single-supply ADC. The
part can be operated from a 2.5 V to 5.5 V supply and is capable of
throughput rates of 100 kSPS when provided with a 2.5 MHz clock.
The AD7680 provides the user with an on-chip track-and-hold
ADC and a serial interface housed in a tiny 6-lead SOT-23
package or in an 8-lead MSOP package, which offer the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part and also
provides the clock source for the successive approximation
ADC. The analog input range for the AD7680 is 0 V to V
external reference is not required for the ADC nor is there a
reference on-chip. The reference for the AD7680 is derived from
the power supply and thus gives the widest dynamic input range.
The AD7680 also features a power-down option to save power
between conversions. The power-down feature is implemented
across the standard serial interface as described in the Modes of
Operation section.
CONVERTER OPERATION
The AD7680 is a 16-bit, successive approximation ADC based
around a capacitive DAC. The AD7680 can convert analog
input signals in the 0 V to V
show simplified schematics of the ADC. The ADC comprises
control logic, SAR, and a capacitive DAC. Figure 11 shows the
ADC during its acquisition phase. SW2 is closed and SW1 is in
Position A. The comparator is held in a balanced condition and
the sampling capacitor acquires the signal on the selected V
channel.
SAMPLING
A
V
IN
SW1
CAPACITOR
B
ACQUISITION
PHASE
V
DD
/2
Figure 11. ADC Acquisition Phase
When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B, causing the comparator to become unbalanced
(Figure 12). The control logic and the capacitive DAC are used
to add and subtract fixed amounts of charge from the sampling
capacitor to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code
(see the ADC Transfer Function section).
range. Figure 11 and Figure 12
DD
CAPACITIVE
CONTROL
SW2
COMPARATOR
DAC
LOGIC
DD
. An
IN
03643-0-004
CAPACITIVE
DAC
SAMPLING
A
V
IN
SW1
CAPACITOR
B
CONVERSION
PHASE
V
DD
CONTROL
SW2
/2
COMPARATOR
LOGIC
03643-0-005
Figure 12. ADC Conversion Phase
ANALOG INPUT
Figure 13 shows an equivalent circuit of the analog input
structure of the AD7680. The two diodes, D1 and D2, provide
ESD protection for the analog inputs. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 300 mV. This causes these diodes to become
forward-biased and to start conducting current into the
substrate. The maximum current these diodes can conduct
without causing irreversible damage to the part is 10 mA.
Capacitor C1 in Figure 13 is typically about 5 pF and can be
attributed primarily to pin capacitance. Resistor R1 is a lumped
component made up of the on resistance of a track-and-hold
switch. This resistor is typically about 25 Ω. Capacitor C2 is the
ADC sampling capacitor and has a capacitance of 25 pF
typically. For ac applications, removing high frequency
components from the analog input signal is recommended by
use of an RC low-pass filter on the relevant analog input pin. In
applications where harmonic distortion and signal-to-noise
ratio are critical, the analog input should be driven from a low
impedance source. Large source impedances significantly affect
the ac performance of the ADC. This may necessitate the use of
an input buffer amplifier. The choice of the op amp is a function
of the particular application. When no amplifier is used to drive
the analog input, the source impedance should be limited to low
values. The maximum source impedance depends on the
amount of total harmonic distortion (THD) that can be
tolerated. The THD increases as the source impedance
increases, and performance degrades (see Figure 8).
V
DD
D1
IN
C1
5pF
D2
CONVERSION PHASE - SWITCH OPEN
TRACK PHASE - SWITCH CLOSED
Figure 13. Equivalent Analog Input Circuit
C2
25pF
R1
03643-0-006
Rev. 0 | Page 12 of 20
AD7680
ADC TRANSFER FUNCTION
The output coding of the AD7680 is straight binary. The
designed code transitions occur at successive integer LSB values,
i.e., 1 LSB, 2 LSBs. The LSB size is V
/65536. The ideal transfer
DD
characteristic for the AD7680 is shown in Figure 14.
111...111
111...110
111...000
011...111
000...010
000...001
000...000
1 LSB +V
0V
ANALOG INPUT
1 LSB = V
DD
/65536
DD
–1 LSB
03643-0-007
Figure 14. AD7680 Transfer Characteristic
TYPICAL CONNECTION DIAGRAM
Figure 15 shows a typical connection diagram for the AD7680.
V
is taken internally from VDD and as such should be well
REF
decoupled. This provides an analog input range of 0 V to V
The conversion result is output in a 24-bit word, or alternatively,
all 16 bits of the conversion result may be accessed using a
minimum of 20 SCLKs. This 20-/24-bit data stream consists of
a four leading zeros, followed by the 16 bits of conversion data,
followed by four trailing zeros in the case of the 24 SCLK
transfer. For applications where power consumption is of
concern, the power-down mode should be used between
conversions or bursts of several conversions to improve power
performance (see the Modes of Operation section).
DD
.
In fact, because the supply current required by the AD7680 is so
low, a precision reference can be used as the supply source to
the AD7680. For example, a REF19x voltage reference (REF195
for 5 V or REF193 for 3 V) or an AD780 can be used to supply
the required voltage to the ADC (see Figure 15). This
configuration is especially useful if the power supply available is
quite noisy, or if the system supply voltages are at some value
other than the required operating voltage of the AD7680, e.g.,
15 V. The REF19x or AD780 outputs a steady voltage to the
AD7680. Recommended decoupling capacitors are a 100 nF low
ESR ceramic (Farnell 335-1816) and a 10 µF low ESR tantalum
(Farnell 197-130).
0V TO V
INPUT
3V
10µF
0.1µF
TANT
V
DD
DD
V
IN
AD7680
GND
REF193
SCLK
SDATA
CS
SERIAL
INTERFACE
10µF
0.1µF
µC/µP
Figure 15. Typical Connection Diagram
5V
SUPPLY
Digital Inputs
The digital inputs applied to the AD7680 are not limited by the
maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V and are not restricted by the
V
+ 0.3 V limit as on the analog inputs. For example, if the
DD
AD7680 were operated with a V
of 3 V, 5 V logic levels could
DD
be used on the digital inputs. However, it is important to note
that the data output on SDATA still has 3 V logic levels when
V
= 3 V.
DD
03643-0-008
CS
Another advantage of SCLK and
+ 0.3 V limit is that power supply sequencing issues are
V
DD
avoided. If one of these digital inputs is applied before V
not being restricted by the
, then
DD
there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V were applied prior to V
DD
.
Rev. 0 | Page 13 of 20
AD7680
S
A
MODES OF OPERATION
The mode of operation of the AD7680 is selected by controlling
CS
the (logic) state of the
two possible modes of operation, normal and power-down. The
point at which
CS
initiated determines whether or not the AD7680 enters powerdown mode. Similarly, if the AD7680 is already in power-down,
CS
can control whether the device returns to normal operation
or remains in power-down. These modes of operation are
designed to provide flexible power management options. These
options can optimize the power dissipation/throughput rate
ratio for differing application requirements.
NORMAL MODE
This mode provides the fastest throughput rate performance,
because the user does not have to worry about the power-up
times with the AD7680 remaining fully powered all the time.
Figure 16 shows the general diagram of the operation of the
AD7680 in this mode.
signal during a conversion. There are
is pulled high after the conversion has been
CS
The conversion is initiated on the falling edge of
as described
in the Serial Interface section. To ensure that the part remains
CS
fully powered up at all times,
10 SCLK falling edges have elapsed after the falling edge of
CS
is brought high any time after the 10th SCLK falling edge,
If
must remain low until at least
CS
but before the 20th SCLK falling edge, the part remains
powered up, but the conversion is terminated and SDATA goes
back into three-state. At least 20 serial clock cycles are required
to complete the conversion and access the complete conversion
result. In addition, a total of 24 SCLK cycles accesses four
trailing zeros.
may idle low until
conversion, effectively idling
CS
may idle high until the next conversion or
CS
returns high sometime prior to the next
CS
low.
Once a data transfer is complete (SDATA has returned to threestate), another conversion can be initiated after the quiet time,
t
, has elapsed by bringing CS low again.
QUIET
.
CS
SCLK
DAT
11020
4 LEADING ZEROS + CONVERSION RESULT
Figure 16. Normal Mode Operation
03643-0-009
Rev. 0 | Page 14 of 20
AD7680
S
A
S
A
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered
down between each conversion, or a series of conversions may
be performed at a high throughput rate, and then the ADC is
powered down for a relatively long duration between these
bursts of several conversions. When the AD7680 is in
power-down, all analog circuitry is powered down.
To enter power-down, the conversion process must be
interrupted by bringing
CS
high anywhere after the second
falling edge of SCLK and before the 10th falling edge of SCLK
CS
as shown in Figure 17. Once
has been brought high in this
window of SCLKs, the part enters power-down, the conversion
CS
that was initiated by the falling edge of
SDATA goes back into three-state. If
is terminated, and
CS
is brought high before
the second SCLK falling edge, the part remains in normal mode
and will not power down. This avoids accidental power-down
due to glitches on the
CS
line.
In order to exit this mode of operation and power up the
AD7680 again, a dummy conversion is performed. On the
falling edge of
to power up as long as
CS
, the device begins to power up and continues
CS
is held low until after the falling edge
of the 10th SCLK. The device is fully powered up once at least
16 SCLKs (or approximately 6 µs) have elapsed and valid data
results from the next conversion as shown in Figure 18. If
CS
is
brought high before the 10th falling edge of SCLK, regardless of
the SCLK frequency, the AD7680 goes back into power-down
again. This avoids accidental power-up due to glitches on the
line or an inadvertent burst of 8 SCLK cycles while
CS
CS
is low. So
although the device may begin to power-up on the falling edge
CS
of
, it powers down again on the rising edge of CS as long as
it occurs before the 10th SCLK falling edge.
SCLK
DAT
CS
CS
1 2 10 20
SCLK
DAT
Figure 17. Entering Power-Down Mode
THE PART BEGINS
TO POWER UP
110201 20
INVALID DATA VALID DATA
t
POWER UP
Figure 18. Exiting Power-Down Mode
THREE-STATE
THE PART IS FULLY POWERED
UP WITH V
FULLY ACQUIRED
IN
03643-0-010
03643-0-011
Rev. 0 | Page 15 of 20
AD7680
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7680 when not
converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 19 shows how as the
throughput rate is reduced, the part remains in its shut-down
state longer, and the average power consumption over time
drops accordingly.
Figure 19 shows the power dissipation versus the throughput
rate when using the power-down mode with 3.6 V supplies, a
2.5 MHz SCLK, and a 20 SCLK serial transfer.
10
VDD = 3.6V
F
= 2.5MHz
SCLK
For example, if the AD7680 is operated in a continuous
sampling mode, with a throughput rate of 10 kSPS and an SCLK
of 2.5 MHz (V
= 3.6 V), and the device is placed in power-
DD
down mode between conversions, the power consumption is
calculated as follows. The maximum power dissipation during
normal operation is 6.84 mW (V
= 3.6 V). If the power-up
DD
time from power-down is 1 µs, and the remaining conversion
time is 8 µs, (using a 20 SCLK transfer), then the AD7680 can be
said to dissipate 6.84 mW for 9 µs during each conversion cycle.
With a throughput rate of 10 kSPS, the cycle time is 100 µs.
For the remainder of the conversion cycle, 91 µs, the part
remains in power-down mode. The AD7680 can be said to
dissipate 1.08 µW for the remaining 91 µs of the conversion
cycle. Therefore, with a throughput rate of 10 kSPS, the average
power dissipated during each cycle is
(9/100) × (6.84 mW) + (91/100) × (1.08 µW) = 0.62 mW
1
POWER (mW)
0.1
0.01
0 5 10 15 20 25
THROUGHPUT (kSPS)
Figure 19. Power vs. Throughput Using
Power-Down Mode with 20 SCLK Transfer at 3.6 V
30 35 40 45 50
03643-0-012
Rev. 0 | Page 16 of 20
AD7680
SERIAL INTERFACE
Figure 20 shows the detailed timing diagram for serial
interfacing to the AD7680. The serial clock provides the
conversion clock and also controls the transfer of information
from the AD7680 during conversion.
CS
The
signal initiates the data transfer and conversion process.
CS
The falling edge of
puts the track-and-hold into hold mode,
takes the bus out of three-state, and samples the analog input.
The conversion is also initiated at this point and requires at least
20 SCLK cycles to complete. Once 17 SCLK falling edges have
elapsed, the track-and-hold goes back into track mode on the
next SCLK rising edge. Figure 20 shows a 24 SCLK transfer that
allows a 100 kSPS throughput rate. On the 24th SCLK falling
edge, the SDATA line goes back into three-state. If the rising
CS
edge of
occurs before 24 SCLKs have elapsed, the conversion
terminates and the SDATA line goes back into three-state;
otherwise SDATA returns to three-state on the 24th SCLK
falling edge as shown in Figure 20.
A minimum of 20 serial clock cycles are required to perform
the conversion process and to access data from the AD7680.
CS
going low provides the first leading zero to be read in by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges beginning with the second
leading zero; thus the first falling clock edge on the serial clock
has the first leading zero provided and also clocks out the
second leading zero. If a 24 SCLK transfer is used as in Figure 20,
the data transfer consists of four leading zeros followed by the
16 bits of data, followed by four trailing zeros. The final bit
(fourth trailing zero) in the data transfer is valid on the 24th
falling edge, having been clocked out on the previous (23rd)
falling edge. If a 20 SCLK transfer is used as shown in Figure 21,
the data output stream consists of only four leading zeros
followed by 16 bits of data with the final bit valid on the 20th
SCLK falling edge. A 20 SCLK transfer allows for a shorter cycle
time and therefore a faster throughput rate is achieved.
t
1
CS
t
t
2
SCLK
SDATA
3-STATE 3-STATE
1234518192021222324
t
3
0 ZERO ZERO ZERO DB15 DB1 DB0 ZERO ZERO ZERO ZERO
4 LEADING ZEROS
CONVERT
t
6
t
5
t
4
t
7
4 TRAILING ZEROS
t
8
t
QUIET
03643-0-013
Figure 20. AD7680 Serial Interface Timing Diagram—24 SCLK Transfer
t
1
CS
t
CONVERT
SCLK
SDATA
t
2
12345181920
t
3
0 0ZERO ZERO ZERO DB15 DB1 DB0
4 LEADING ZEROS
Figure 21. AD7680 Serial Interface Timing Diagram—20 SCLK Transfer
t
6
t
5
t
4
t
7
t
8
t
QUIET
3-STATE3-STATE
03643-0-014
Rev. 0 | Page 17 of 20
AD7680
It is also possible to take valid data on each SCLK rising edge
rather than falling edge, since the SCLK cycle time is long
enough to ensure the data is ready on the rising edge of SCLK.
However, the first leading zero is still driven by the
edge, and so it can be taken on only the first SCLK falling edge.
It may be ignored and the first rising edge of SCLK after the
falling edge would have the second leading zero provided and
the 23rd rising SCLK edge would have the final trailing zero
provided. This method may not work with most
microcontrollers/DSPs but could possibly be used with FPGAs
and ASICs.
AD7680 TO ADSP-218x
The ADSP-218x family of DSPs can be interfaced directly to the
AD7680 without any glue logic required. The SPORT control
register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 0111, 8-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 0, Frame First Word
IRFS = 0
ITFS = 1
To implement the power-down mode, SLEN should be set to
0111 to issue an 8-bit SCLK burst. The connection diagram is
shown in Figure 22. The ADSP-218x has the TFS and RFS of the
SPORT tied together, with TFS set as an output and RFS set as
CS
falling
CS
an input. The DSP operates in alternate framing mode and the
SPORT control register is set up as described. Transmit and
receive autobuffering is used in order to get a 24 SCLK transfer.
Each buffer contains three 8-bit words. The frame synchronization signal generated on the TFS is tied to
signal processing applications, equidistant sampling is necessary.
CS
, and as with all
In this example, the timer interrupt is used to control the
sampling rate of the ADC.
AD7680*
SCLK
SDATA
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. Interfacing to the ADSP-218x
ADSP-218x*
SCLK
DR
RFS
TFS
03643-0-015
The timer register is loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, the values in the transmit autobuffer start to be
transmitted and TFS is generated. The TFS is used to control
the RFS and therefore the reading of data. The data is stored in
the receive autobuffer for processing or to be shifted later. The
frequency of the serial clock is set in the SCLKDIV register.
When the instruction to transmit with TFS is given, i.e.,
TX0 = AX0, the state of the SCLK is checked. The DSP waits
until the SCLK has gone high, low, and high again before
transmission starts. If the timer and SCLK values are chosen
such that the instruction to transmit occurs on or near the
rising edge of SCLK, the data may be transmitted or it may wait
until the next clock edge.
Rev. 0 | Page 18 of 20
AD7680
APPLICATION HINTS
GROUNDING AND LAYOUT
The printed circuit board that houses the AD7680 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be separated easily. A minimum
etch technique is generally best for ground planes, because it
gives the best shielding. Digital and analog ground planes
should be joined at only one place. If the AD7680 is in a system
where multiple devices require an AGND to DGND
connection, the connection should still be made at one point
only, a star ground point that should be established as close as
possible to the AD7680.
Avoid running digital lines under the device because these
couple noise onto the die. The analog ground plane should be
allowed to run under the AD7680 to avoid noise coupling. The
power supply lines to the AD7680 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals, such
as clocks, should be shielded with digital ground to avoid
radiating noise to other sections of the board, and clock signals
should never be run near the analog inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other, which reduces the
effects of feedthrough on the board. A microstrip technique is
by far the best but is not always possible with a double-sided
board. In this technique, the component side of the board is
dedicated to ground planes while the signals are placed on the
solder side.
Good decoupling is also very important. All analog supplies
should be decoupled with 10 µF tantalum in parallel with
0.1 µF capacitors to AGND, as discussed in the Typical
Connection Diagram section. To achieve the best performance
from these decoupling components, the user should attempt to
keep the distance between the decoupling capacitors and the
V
and GND pins to a minimum, with short track lengths
DD
connecting the respective pins.
EVALUATING THE AD7680 PERFORMANCE
The recommended layout for the AD7680 is outlined in the
evaluation board for the AD7680. The evaluation board package
includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from the
PC via the evaluation board controller. The evaluation board
controller can be used in conjunction with the AD7680 evaluation board, as well as many other Analog Devices evaluation
boards ending in the CB designator, to demonstrate/evaluate
the ac and dc performance of the AD7680.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7680.
The software and documentation are on a CD shipped with the
evaluation board.
Rev. 0 | Page 19 of 20
AD7680
0
OUTLINE DIMENSIONS
2.90 BSC
1.90
BSC
0.50
0.30
4 5
2.80 BSC
2
0.95 BSC
1.45 MAX
SEATING
PLANE
0.22
0.08
10°
0.60
4°
0.45
0°
0.30
1.60 BSC
1.30
1.15
0.90
.15 MAX
6
13
PIN 1
COMPLIANT TO JEDEC STANDARDS MO-178AB
Figure 23. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters
3.00
BSC
85
3.00
BSC
PIN 1
0.65 BSC
0.15
0.00
0.38
0.22
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA
4
SEATING
PLANE
4.90
BSC
1.10 MAX
0.23
0.08
8°
0°
0.80
0.60
0.40
Figure 24. 8-Lead Micro Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7680ARJ-REEL −40°C to +85°C 14 Bits Min Small Outline Transistor Package (SOT-23) RJ-6 CQA
AD7680ARJ-REEL7 −40°C to +85°C 14 Bits Min Small Outline Transistor Package (SOT-23) RJ-6 CQA
AD7680ARM −40°C to +85°C 14 Bits Min Micro Small Outline Package (MSOP) RM-8 CQA
AD7680ARM-REEL −40°C to +85°C 14 Bits Min Micro Small Outline Package (MSOP) RM-8 CQA
AD7680ARM-REEL7 −40°C to +85°C 14 Bits Min Micro Small Outline Package (MSOP) RM-8 CQA
AD7680BRJ-R2 −40°C to +85°C 15 Bits Min Small Outline Transistor Package (SOT-23) RJ-6 CQB
AD7680BRJ-REEL −40°C to +85°C 15 Bits Min Small Outline Transistor Package (SOT-23) RJ-6 CQB
AD7680BRJ-REEL7 −40°C to +85°C 15 Bits Min Small Outline Transistor Package (SOT-23) RJ-6 CQB
AD7680BRM −40°C to +85°C 15 Bits Min Micro Small Outline Package (MSOP) RM-8 CQB
AD7680BRM-REEL −40°C to +85°C 15 Bits Min Micro Small Outline Package (MSOP) RM-8 CQB
AD7680BRM-REEL7 −40°C to +85°C 15 Bits Min Micro Small Outline Package (MSOP) RM-8 CQB
1
Linearity error here refers to no missing codes.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03643-0-1/04(0)
Temperature
Range
Linearity
Error (LSB)
Package
1
Description
Rev. 0 | Page 20 of 20
Package
Option
Branding
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