Datasheet AD7679 Datasheet (Analog Devices)

18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC

FEATURES

18-bit resolution with no missing codes
No pipeline delay (SAR architecture)

(V

Differential input range: ±V
Throughput: 570 kSPS
INL: ±2.5 LSB max (±9.5 ppm of full scale)
Dynamic range : 103 dB typ (V
S/(N+D): 100 dB typ @ 2 kHz (V
Parallel (18-,16-, or 8-bit bus) and serial 5 V/3 V interface

®/QSPI™/MICROWIRE™/DSP compatible

SPI
On-board reference buffer
Single 5 V supply operation
Power dissipation: 76 mW @ 500 kSPS

150 µW @ 1 kSPS
48-lead LQFP or 48-lead LFCSP package
Pin-to-pin compatible upgrade of AD7674/AD7676/AD7678

APPLICATIONS

CT scanners
High dynamic data acquisition
Geophone and hydrophone sensors

replacement (low power, multichannel)

Σ-∆
Instrumentation
Spectrum analysis
Medical instruments

GENERAL DESCRIPTION

The AD7679 is an 18-bit, 570 kSPS, charge redistribution SAR,
fully differential analog-to-digital converter that operates on a
single 5 V power supply. The part contains a high speed 18-bit
sampling ADC, an internal conversion clock, an internal
reference buffer, error correction circuits, and both serial and
parallel system interface ports.

REF

REF

REF

REF

= 5 V)

= 5 V)

up to 5 V)

AD7679

FUNCTIONAL BLOCK DIAGRAM

PDBUF

AGND
AVDD

REFBUFIN

IN+

IN–

PD

RESET

CALIBRATION CIRCUITRY

Table 1. PulSAR Selection

Type/kSPS 100–250 500–570

Pseudo­Differential

True Bipolar AD7663 AD7665 AD7671
True

Differential
18-Bit AD7678 AD7679 AD7674
Multichannel/

Simultaneous

PRODUCT HIGHLIGHTS

1. High Resolution, Fast Throughput.
The AD7679 is a 570 kSPS, charge redistribution, 18-bit
SAR ADC (no latency).

REF

REFGND

AD7679

SWITCHED

CAP DAC

PARALLEL

CLOCK

CONTROL LOGIC AND

CNVST

Figure 1. Functional Block Diagram

INTERFACE

SERIAL

PORT

DGNDDVDD

OVDD

OGND

18

D[17:0]

BUSY

RD

CS

MODE0

MODE1

03085–0–001

800–
1000

AD7651
AD7660/AD7661

AD7650/AD7652
AD7664/AD7666

AD7653
AD7667

AD7675 AD7676 AD7677

AD7654
AD7655

The part is available in a 48-lead LQFP or 48-lead LFCSP with
operation specified from –40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

2. Excellent Accuracy.
The AD7679 has a maximum integral nonlinearity of

2.5 LSB with no missing 18-bit codes.

3. Serial or Parallel Interface.
Versatile parallel (18-, 16-, or 8-bit bus) or 3-wire serial
interface arrangement compatible with both 3 V and
5 V logic.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD7679

TABLE OF CONTENTS

Specifications..................................................................................... 3

Digital Interface.......................................................................... 20

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 7

Pin Configuration and Functional Descriptions.......................... 8

Definition of Specifications........................................................... 11

Typical Performance Characteristics ........................................... 12

Circuit Information........................................................................ 15

Converter Operation.................................................................. 15

Typical Connection Diagram ................................................... 17

Power Dissipation versus Throughput.................................... 19

Conversion Control ................................................................... 19

REVISION HISTORY

Revision 0: Initial Version

Parallel Interface......................................................................... 20

Serial Interface............................................................................ 20

Master Serial Interface............................................................... 21

Slave Serial Interface.................................................................. 22

Microprocessor Interfacing ...................................................... 24

Application Hints ........................................................................... 25

Layout .......................................................................................... 25

Evaluating the AD7679’s Performance.................................... 25

Outline Dimensions....................................................................... 26

Ordering Guide............................................................................... 26

Rev. 0 | Page 2 of 28

AD7679

SPECIFICATIONS

Table 2. –40°C to +85°C, V

Parameter Conditions Min Typ Max Unit

RESOLUTION 18 Bits
ANALOG INPUT

Voltage Range V
Operating Input Voltage V
Analog Input CMRR fIN = 100 kHz 68 dB
Input Current 570 kSPS Throughput 25 µA
Input Impedance1

THROUGHPUT SPEED

Complete Cycle 1.75 µs
Throughput Rate 0 570 kSPS

DC ACCURACY

Integral Linearity Error –2.5 +2.5 LSB2
Differential Linearity Error –1 +1.75 LSB
No Missing Codes 18 Bits
Transition Noise V
Zero Error, T

MIN

to T

MAX

Zero Error Temperature Drift ±0.5 ppm/°C
Gain Error, T

MIN

to T

MAX

Gain Error Temperature Drift ±1.6 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±4 LSB

AC ACCURACY

Signal-to-Noise

Dynamic Range V
Spurious-Free Dynamic Range

Total Harmonic Distortion

–3 dB Input Bandwidth 26 MHz

SAMPLING DYNAMICS

Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 250 ns
Overvoltage Recovery 250 ns

REFERENCE

External Reference Voltage Range REF 3 4.096 AVDD + 0.1 V
REF Voltage with Reference Buffer REFBUFIN = 2.5 V 4.05 4.096 4.15 V
Reference Buffer Input Voltage Range REFBUFIN 1.8 2.5 2.6 V
REFBUFIN Input Current –1 +1 µA
REF Current Drain 570 kSPS Throughput 235 µA

= 4.096 V, AVDD = DVDD= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.

REF

– V

–V

IN+

IN–

, V

to AGND –0.1 AVDD+0.1 V

IN+

IN–

= 5 V 0.7 LSB

3

–40 +40 LSB

3

–0.048 See Note 3 +0.048 % of FSR

REF

fIN = 2 kHz, V
V

= 4.096 V 97.5 99 dB

REF

fIN = 10 kHz, V

= 100 kHz, V

f

IN

= V

IN+

= 5 V 101 dB4

REF

= 4.096 V 98 dB

REF

= 4.096 V 97 dB

REF

= V

IN–

/2 = 2.5 V 103 dB

REF

+V

REF

V

REF

fIN = 2 kHz 120 dB
fIN = 10 kHz 118 dB
f

= 100 kHz 105 dB

IN

fIN = 2 kHz –115 dB
fIN = 10 kHz –113 dB
f

= 100 kHz –98 dB

IN

fIN = 2 kHz, V

= 2 kHz, –60 dB Input 40 dB

f

IN

REF

= 4.096 V 98 dB Signal-to-(Noise + Distortion)

Rev. 0 | Page 3 of 28

AD7679

Parameter Conditions Min Typ Max Unit

DIGITAL INPUTS

Logic Levels

VIL –0.3 +0.8 V
VIH 2.0 DVDD + 0.3 V
IIL –1 +1 µA
IIH –1 +1 µA

DIGITAL OUTPUTS

Data Format5
Pipeline Delay6

VOL I
VOH I

POWER SUPPLIES

Specified Performance

AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 DVDD + 0.37 V

Operating Current 500 kSPS Throughput

AVDD PDBUF High 10.8 mA
DVDD8 4.5 mA
OVDD8 50 µA

POWER DISSIPATION8

TEMPERATURE RANGE9

Specified Performance T

= 1.6 mA 0.4 V

SINK

= –500 µA OVDD – 0.6 V

SOURCE

PDBUF High @ 500 kSPS 76 90 mW
PDBUF High @ 1 kSPS 150 µW
PDBUF Low @ 500 kSPS 89 103 mW

to T

MIN

–40 +85 °C

MAX

1

See section. Analog Inputs

2

LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 µV.

3

See section. The nominal gain error is not centered at zero and is +0.273% of FSR. This specification is the deviation from this nominal

Definition of Specifications

value. These specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used.

4

All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified.

5

Parallel or Serial 18-Bit.

6

Conversion results are available immediately after completed conversion.

7

The max should be the minimum of 5.25 V and DVDD + 0.3 V.

8

Tested in Parallel Reading mode.

9

Contact factory for extended temperature range.

Rev. 0 | Page 4 of 28

AD7679

TIMING SPECIFICATIONS

Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.

Parameter Symbol Min Typ Max Unit

Refer to Figure 32 and Figure 33

Convert Pulsewidth t1 10 ns
Time between Conversions t2 1.75 µs

t

CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except Master Serial Read after Convert t4 1.5 µs
Aperture Delay t5 2 ns
End of Conversion to BUSY LOW Delay t6 10 ns
Conversion Time t7 1.5 µs
Acquisition Time t8 250 ns
RESET Pulsewidth t9 10 ns

Refer to Figure 34, Figure 35, and Figure 36 (Parallel Interface Modes)

CNVST LOW to Data Valid Delay
Data Valid to BUSY LOW Delay t11 20 ns
Bus Access Request to Data Valid t12 45 ns
Bus Relinquish Time t13 5 15 ns

Refer to Figure 38 and Figure 39 (Master Serial Interface Modes) 1

CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay2 t
Internal SCLK Period2 t
Internal SCLK HIGH2 t
Internal SCLK LOW2 t
SDOUT Valid Setup Time2 t
SDOUT Valid Hold Time2 t
SCLK Last Edge to SYNC Delay2 t
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert2 t
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay t30 25 ns

Refer to Figure 40 and Figure 41 (Slave Serial Interface Modes)

External SCLK Setup Time t31 5 ns
External SCLK Active Edge to SDOUT Delay t32 3 18 ns
SDIN Setup Time t33 5 ns
SDIN Hold Time t34 5 ns
External SCLK Period t35 25 ns
External SCLK HIGH t36 10 ns
External SCLK LOW t37 10 ns

1

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

2

In Serial Master Read during Convert mode. See for Serial Master Read after Convert mode. Table 4

35 ns

3

t

1.5 µs

10

t

10 ns

14

t

10 ns

15

t

10 ns

16

t

525 ns

17

3 ns

18

25 40 ns

19

12 ns

20

7 ns

21

4 ns

22

2 ns

23

3 ns

24

t

10 ns

25

t

10 ns

26

t

10 ns

27

See Table 4

28

1.5 µs

t

29

Rev. 0 | Page 5 of 28

AD7679

Table 4. Serial Clock Timings in Master Read after Convert

DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns
Internal SCLK Period Minimum t19 25 60 120 240 ns
Internal SCLK Period Maximum t19 40 80 160 320 ns
Internal SCLK HIGH Minimum t20 12 22 50 100 ns
Internal SCLK LOW Minimum t21 7 21 49 99 ns
SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns
SDOUT Valid Hold Time Minimum t23 2 4 30 89 ns
SCLK Last Edge to SYNC Delay Minimum t24 3 60 140 300 ns
Busy High Width Maximum t28 2.25 3 4.5 7.5 µs

Rev. 0 | Page 6 of 28

AD7679

ABSOLUTE MAXIMUM RATINGS

Table 5. AD7679 Absolute Maximum Ratings1

Parameter Rating

Analog Inputs

IN+2, IN–2, REF, REFBUFIN, REFGND
to AGND

AVDD + 0.3 V to
AGND – 0.3 V

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD –0.3 V to +7 V

Digital Inputs –0.3 V to DVDD + 0.3 V
Internal Power Dissipation3 700 mW
Internal Power Dissipation4 2.5 W
Junction Temperature 150°C
Storage Temperature Range –65°C to +150°C
Lead Temperature Range

(Soldering 10 sec)

300°C

1

Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

2

See An section. alog Inputs

3

Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W,

θJC = 30°C/W.

4

Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W.

I

1.6mA

TO OUTPUT

PIN

C

L
1

60pF

500µA

1

IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.

Figure 2. Load Circuit for Digital Interface Timing

SDOUT, SYNC, SCLK Outputs, C

0.8V

t

DELAY

2V

0.8V

Figure 3. Voltage Reference Levels for Timing

OL

1.4V

I

OH

= 10 pF

L

03085–0–002

2V

t

DELAY

2V

0.8V

03085–0–003

Rev. 0 | Page 7 of 28

AD7679

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

PDBUF

AVDD

REFBUFINNCAGND

IN+NCNCNCIN–

AD7679

TOP VIEW

(Not to Scale)

OVDD

OGND

D8/INVSCLK

D9/RDC/SDIN

DVDD

AGND

AVD D

MODE0

MODE1

D0/OB/2C

NC

NC

D1/A0

D2/A1

D3

D4/DIVSCLK[0]

D5/DIVSCLK[1]

NC = NO CONNECT

48 47 46 45 4 4 39 38 3 743 42 41 40

1

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

D6/EXT/INT

D7/INVSYNC

Figure 4. 48-Lead LQFP(ST-48) and 48-Lead LFCSP (CP-48)

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1, 44 AGND P Analog Power Ground Pin.
2, 47 AVDD P Input Analog Power Pins. Nominally 5 V.
3 MODE0 DI Data Output Interface Mode Selection.
4 MODE1 DI Data Output Interface Mode Selection:

Interface MODE MODE1 MODE0 Description

0 0 0 18-Bit Interface
1 0 1 16-Bit Interface
2 1 0 Byte Interface
3 1 1 Serial Interface

5

D0/OB/2C

DI/O

When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the
data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos
complement. When OB/2C

is HIGH, the digital output is straight binary; when LOW, the MSB is

inverted, resulting in a twos complement output from its internal shift register.

6, 7, 40–

NC No Connect.

42, 45
8 D1/A0 DI/O

When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all
other modes, this input pin controls the form in which data is output, as shown in Table 7.

9 D2/A1 DI/O

When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output
bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7.

10 D3 DO

In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin
is always an output, regardless of the interface mode.

11, 12 D[4:5]or

DIVSCLK[0:1]

DI/O In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus.

When MODE = 3 (serial mode), EXT/INT
convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock

that clocks the data output. In other serial modes, these pins are not used.

13 D6

or EXT/INT

DI/O In all modes except MODE = 3, this output is used as Bit 6 of the parallel port data output bus.

When MODE = 3 (serial mode), this input, part of the serial port, is used as a digital select input for
choosing the internal data clock or an external data clock. With EXT/INT
selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an
external clock signal connected to the SCLK input.

REFGND

DGND

D11/SCLK

D12/SYNC

D10/SDOUT

is LOW, and RDC/SDIN is LOW (serial master read after

REF

D13/RDERROR

36

AGND

35

CNVST

34

PD

33

RESET

32

CS

31

RD

30

DGND

29

BUSY

28

D17

27

D16

26

D15

25

D14

03085–0–004

tied LOW, the internal clock is

Rev. 0 | Page 8 of 28

AD7679

Pin No. Mnemonic Type1 Description

14 D7

or INVSYNC

15 D8

or INVSCLK

16 D9

or RDC/SDIN

17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P

19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.
21 D10

or SDOUT

22 D11

or SCLK

23 D12

or SYNC

24 D13

or RDERROR

25–28 D[14:17] DO

29 BUSY DO

30 DGND P Must Be Tied to Digital Ground.
31

32

33 RESET DI

34 PD DI

RD
CS

DI/O In all modes except MODE = 3, this output is used as Bit 7 of the parallel port data output bus.

When MODE = 3 (serial mode), this input, part of the serial port, is used to select the active state of the
SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.

DI/O In all modes except MODE = 3, this output is used as Bit 8 of the parallel port data output bus.

When MODE = 3 (serial mode), this input, part of the serial port, is used to invert the SCLK signal. It is
active in both master and slave mode.

DI/O In all modes except MODE = 3, this output is used as Bit 9 of the parallel port data output bus.

When MODE = 3 (serial mode), this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/INT. When EXT/ INT is HIGH,
RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs
onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK
periods after the initiation of the read sequence. When EXT/INT
read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When
RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete.

Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should
not exceed DVDD by more than 0.3 V.

DO In all modes except MODE = 3, this output is used as Bit 10 of the parallel port data output bus.

When MODE = 3 (serial mode), this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7679 provides the
conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial

mode when EXT/INT is HIGH and INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and is
valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and is
valid on the next rising edge.

DI/O In all modes except MODE = 3, this output is used as Bit 11 of the parallel port data output bus.

When MODE = 3 (serial mode), this pin, part of the serial port, is used as a serial data clock input or
output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is
updated depends upon the logic state of the INVSCLK pin.

DO In all modes except MODE = 3, this output is used as Bit 12 of the parallel port data output bus.

When MODE = 3 (serial mode), this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is
valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW
while SDOUT output is valid.

DO In all modes except MODE = 3, this output is used as Bit 13 of the parallel port data output bus.

In MODE = 3 (serial mode) and when EXT/ INT is HIGH, this output, part of the serial port, is used as an
incomplete read error flag. In slave mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed high.

Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the
interface mode.

Busy Output. Transitions HIGH when a conversion is started. Remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.

DI
DI

Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is

also used to gate the external clock.
Reset Input. When set to a logic HIGH, reset the AD7679. Current conversion, if any, is aborted. If not

used, this pin could be tied to DGND.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are

inhibited after the current one is completed.

is LOW, RDC/SDIN is used to select the

= Logic LOW). When a read sequence is

Rev. 0 | Page 9 of 28

AD7679

Pin No. Mnemonic Type1 Description

35

36 AGND P Must Be Tied to Analog Ground.
37 REF AI

38 REFGND AI Reference Input Analog Ground.
39 IN– AI Differential Negative Analog Input.
43 IN+ AI Differential Positive Analog Input.
46 REFBUFIN AI

48 PDBUF DI

CNVST

1

AI = Analog Input; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.

Table 7. Data Bus Interface Definitions

MODE MODE1 MODE0 D0/OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description

0 0 0 R[0] R[1] R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 18-Bit Parallel
1 0 1

1 0 1

2 1 0

2 1 0

2 1 0

2 1 0

3 1 1

R[0:17] is the 18-bit ADC value stored in its output register.

DI

Start Conversion. If CNVST is held HIGH when the acquisition phase (t8) is complete, the next falling
edge on CNVST
is held LOW when the acquisition phase is complete, the internal sample/hold is put into the hold

state and a conversion is started immediately.

Reference Input Voltage and Internal Reference Buffer Output. Apply an external reference on this pin
if the internal reference buffer is not used. Should be decoupled effectively with or without the
internal buffer.

Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It outputs 4.096 V
typically when 2.5 V is applied on this pin.

Allows Choice of Buffering Reference. When LOW, buffer is selected. When HIGH, buffer is
switched off.

A0:0 R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 16-Bit High Word

OB/2C

A0:1 R[0] R[1] All Zeros 16-Bit Low Word

OB/2C

A0:0 A1:0 All Hi-Z R[10:11] R[12:15] R[16:17] 8-Bit HIGH Byte

OB/2C

A0:0 A1:1 All Hi-Z R[2:3] R[4:7] R[8:9] 8-Bit MID Byte

OB/2C

A0:1 A1:0 All Hi-Z R[0:1] All Zeros 8-Bit LOW Byte

OB/2C

A0:1 A1:1 All Hi-Z All Zeros R[0:1] 8-Bit LOW Byte

OB/2C

OB/2C

puts the internal sample/hold into the hold state and initiates a conversion. If CNVST

All Hi-Z Serial Interface Serial Interface

Rev. 0 | Page 10 of 28

AD7679

DEFINITION OF SPECIFICATIONS

Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.

Gain Error

The first transition (from 000…00 to 000…01) should occur for
an analog voltage ½ LSB above the nominal –full scale
(–4.095991 V for the ±4.096 V range). The last transition (from
111…10 to 111…11) should occur for an analog voltage
1½ LSB below the nominal full scale (4.095977 V for the
±4.096 V range). The gain error is the deviation of the
difference between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels.

Zero Error

The zero error is the difference between the ideal midscale
input voltage (0 V) from the actual voltage producing the
midscale output code.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured with the inputs shorted together. The
value for dynamic range is expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (S/[N+D])

S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.

Aperture Delay

Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the

the input signal is held for a conversion.

CNVST

input to when

Transient Response

Transient response is the time required for the AD7679 to
achieve its rated accuracy after a full-scale step function is
applied to its input.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input, and is expressed in bits. It is related to S/(N+D) by the
following formula:

ENOB = (S/[N+D]dB – 1.76)/6.02

Rev. 0 | Page 11 of 28

AD7679

4

TYPICAL PERFORMANCE CHARACTERISTICS

2.5

2.0

1.5

1.0

0.5

0

–0.5

INL-LSB (18-Bit)

–1.0

–1.5

–2.0

–2.5

0 65536 131072 196608 262144

Figure 5. Integral Nonlinearity vs. Code

70000

60000

50000

40000

30000

COUNTS

20000

10000

0

73

1FEBE1FEBD 1FEC0 1FEC1 1FEC2 1FEC3 1FEC4 1FEC5 1FEC6

Figure 6. Histogram of 131,072 Conversions of a

DC Input at the Code Transition

100

7584

CODE IN HEX

CODE

58510

59001

4616

264

03085-0-005

V

REF

= 5V

0000

03085-0-006

2.0

1.5

1.0

0.5

DNL-LSB (18-Bit)

0

–0.5

–1.0

0 65536 131072 196608 26214

CODE

Figure 8. Differential Nonlinearity vs. Code

90000

80000

70000

60000

50000

40000

COUNTS

30000

20000

10000

0

1FEBF1FEBE 1FEC0 1FEC1 1FEC2 1FEC3 1FEC4 1FEC5 1FEC6

23080

CODE IN HEX

22496

3838

Figure 9. Histogram of 131,072 Conversions of a

DC Input at the Code Center

120

03085-0-008

V

REF

= 5V

05979920

03085-0-009

80

60

40

NUMBER OF UNITS

20

0

0

0.5 1.0 1.5 2.0

POSITIVE INL (LSB)

Figure 7. Typical Positive INL Distribution (424 Units)

03085-0-007

2.5

100

80

60

40

NUMBER OF UNITS

20

0

–2.5

–2.0 –1.5 –1.0 –0.5

NEGATIVE INL (LSB)

Figure 10. Typical Negative INL Distribution (424 Units)

03085-0-010

0

Rev. 0 | Page 12 of 28

AD7679

120

105

17.0

100

80

60

40

NUMBER OF UNITS

20

0

0

0.5 1.0 1.5

POSITIVE DNL (LSB)

Figure 11. Typical Positive DNL Distribution (424 Units)

180

160

140

120

100

80

60

NUMBER OF UNITS

40

20

0
–1.00

–0.75 –0.50 –0.25

NEGATIVE DNL (LSB)

Figure 12. Typical Negative DNL Distribution (424 Units)

0

–20

–40

–60

–80

–100

–120

–140

AMPLITUDE (dB of Full Scale)

–160

–180

0 30 60 240 270

90 120 150 180 210

FREQUENCY (kHz)

fS = 570kSPS
f

= 10kHz

IN

V

REF

SNR = 98.5dB
THD = 115.8dB
SFDR = 117.4dB
S/(N+D) = 98.4dB

Figure 13. FFT (10 kHz Tone)

03085-0-011

03085-0-014

= 4.096V

03085-0-012

2.0

100

95

90

85

SNR AND S/[N+D] (dB)

80

75

1

10 100 1000

FREQUENCY (kHz)

SNR

S/(N+D)

ENOB

03085-0-015

16.5

16.0

15.5

15.0

14.5

14.0

ENOB (Bits)

Figure 14. SNR, S /(N+D), and ENOB v s. Frequency

03085-0-016

140

120

100

80

60

40

20

0

SFDR (dB)

–60

–70

–80

–90

–100

–110

THD, HARMONICS (dB)

–120

0

–130

1

10 100 1000

SFDR

THD

FREQUENCY (kHz)

THIRD

HARMONIC

SECOND

HARMONIC

Figure 15. THD, SFDR, and Harmonics vs. Frequency

102

V

= 4.096V

REF

100

S/(N+D)

98

SNR REFERRED TO FULL SCALE (dB)

96

–60

–50 0–10–20–30–40

INPUT LEVEL (dB)

SNR

03085-0-017

Figure 16. SNR and S/(N+D) vs. Input Level

Rev. 0 | Page 13 of 28

AD7679

100

SNR

99

S/(N+D)

98

SNR, S/[N+D] (dB)

97

96

–55

Figure 17. SNR, S/(N+D), and ENOB vs. Temperature

–100

–110

–120

THD, HARMONICS (dB)

–130

–140

–55

100000

ENOB

–35 12585655–15

25 45 105

TEMPERATURE (

°

C)

THD

THIRD
HARMONIC

SECOND
HARMONIC

–35 12585655–15

25 45 105

TEMPERATURE (°C)

Figure 18. THD and Harmonics vs. Temperature

03085-0-018

03085-0-019

16.5

16.0

15.5

15.0

14.5

1000

900

800

700

500

500

400

300

200

100

POWER-DOWN OPERATING CURRENTS (nA)

0
–55

–35–155 25456585105

TEMPERATURE (°C)

OVDD

DVDD

AVDD

03085-0-021

125

Figure 20. Power-Down Operating Currents vs. Temperature

25

20

15

10

5

0

–5

–10

ZERO ERROR,POSITIVE AND

NEGATIVE FULL SCALE (LSB)

–15

–20

–25

–55

NEGATIVE

FULL SCALE

POSITIVE
FULL SCALE

–35 12585655–15

25 45 105

TEMPERATURE (°C)

ZERO ERROR

03085-0-022

Figure 21. Zero Error Positive and Negative Full Scale vs. Temperature

50

10000

1000

100

10

1

0.1

OPERATING CURRENTS (µA)

0.01

0.001

AV D D

10

SAMPLING RATE (SPS)

Figure 19. Operating Current vs. Sampling Rate

DVDD

OVD D

PDBUF H IGH

100k10k1k1001

03085-0-020

1M

40

30

DELAY (ns)

20

12

t

10

0

0

Figure 22. Typical Delay vs. Load Capacitance C

OVDD = 2.7V @ 85°C

OVDD = 5V @ 85°C

OVDD = 5V @ 25°C

100

CL (pF)

OVDD = 2.7V @ 25°C

03085-0-024

L

20015050

Rev. 0 | Page 14 of 28

AD7679

CIRCUIT INFORMATION

IN+

SWITCHES

REF

REFGND

262,144C 131,072C

262,144C 131,072C

MSB

MSB

4C 2C C C

4C 2C C C

LSB

LSB

SW+

SW–

COMP

CONTROL

CONTROL

LOGIC

CNVST

BUSY

OUTPUT

CODE

IN–

Figure 23. ADC Simplified Schematic

The AD7679 is a very fast, low power, single-supply, precise
18-bit analog-to-digital converter (ADC) using successive
approximation architecture.

The AD7679’s linearity and dynamic range are similar or better
than many Σ-Δ ADCs. With the advantages of its successive
architecture, which ease multiplexing and reduce power with
throughput, it can be advantageous in applications that
normally use Σ-Δ ADCs.

The AD7679 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.

The AD7679 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP, or a tiny 48-lead LFCSP that offers space savings
and allows for flexible configurations as either a serial or
parallel interface. The AD7679 is pin-to-pin compatible with
the AD7674, AD7676, and AD7678.

03085–0–025

CONVERTER OPERATION

The AD7679 is a successive approximation ADC based on a
charge redistribution DAC. Figure 23 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary weighted capacitors that are
connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW–.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN– inputs. When the
acquisition phase is complete and the

conversion phase is initiated. When the conversion phase
begins, SW+ and SW– are opened first. The two capacitor arrays
are then disconnected from the inputs and connected to the
REFGND input. Therefore, the differential voltage between the
IN+ and IN– inputs captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between REFGND and REF, the comparator input varies
by binary weighted voltage steps (V

REF

The control logic toggles these switches, starting with the MSB
first, to bring the comparator back into a balanced condition.
After completing this process, the control logic generates the
ADC output code and brings the BUSY output low.

CNVST

/2, V

REF

/4...V

input goes low, a

/262144).

REF

Rev. 0 | Page 15 of 28

AD7679

Transfer Functions

Except in 18-bit interface mode, the AD7679 offers straight
binary and twos complement output coding when using OB/

See Figure 24 and Table 8 for the ideal transfer characteristic.

111...111

111...110

111...101

ADC CODE (Straight Binary)

000...010

000...001

000...000

–FS + 1 LSB–FS

–FS + 0.5 LSB

ANALOG INPUT

+FS – 1.5 LSB

Figure 24. ADC Ideal Transfer Function

ANALOG

SUPPLY

(5V)

+

10µF

+FS – 1 LSB

03085-0-026

20Ω

NOTE 5

100nF

.

2C

+

10µ F 100nF

Table 8. Output Codes and Ideal Input Voltages

Description

Analog Input
V

= 4.096 V

REF

Straight
Binary
(Hex)

Twos
Complement
(Hex)

FSR –1 LSB 4.095962 V 3FFFF1 1FFFF1
FSR – 2 LSB 4.095924 V 3FFFE 1FFFE
Midscale +

31.25 µV 20001 00001

1 LSB
Midscale 0 V 20000 00000
Midscale –

–31.25 µV 1FFFF 3FFFF

1 LSB
–FSR + 1 LSB -4.095962 V 00001 20001
–FSR -4.096 V 000002 200002

1

This is also the code for overrange analog input (V

above V

2

This is also the code for underrange analog input (V

below –V

DVDD

– V

+ V

REFGND

REFGND

).

).

100nF+10µ F

DIGITAL SUPPLY
(3.3V OR 5V)

REF

REF

– V

IN+

IN–

– V

IN+

IN–

ADR421

2.5V REF

NOTE 1

ANALOG INPUT+

ANALOG INPUT–

AVD D AGND DGND

2.7nF

2.7nF

NOTE 4

REFBUFIN

REF

REFGND

IN+

IN–

AD7679

1MΩ

50kΩ

100nF

NOTE 2

–

NOTE 3

U1

+

AD8021

–

NOTE 3

+

AD8021

NOTES

1. SEE VOLTAGE REFERENCE INPUT SECTION.

2. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.

3.THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.

4. SEE ANALOG INPUTS SECTION.

5. OPTION, SEE POWER SUPPLY SECTION.

6. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.

100nF

C

REF

47µF

NOTE 1

30Ω

C

C

NOTE 4

30Ω

U2

C

C

DVDD

Figure 25. Typical Connection Diagram (Internal Reference Buffer, Serial Interface)

OVD D OGND

SCLK

SDOUT

BUSY

CNVST

MODE1
MODE0

OB/2C

PDBUF

RESET

RD

CS

PD

50Ω

NOTE 6

DVDD

SERIAL PORT

D

CLOCK

µC/µP/DSP

03085-0-027

Rev. 0 | Page 16 of 28

AD7679

TYPICAL CONNECTION DIAGRAM

Figure 25 shows a typical connection diagram for the AD7679.
Different circuitry shown on this diagram is optional and is
discussed later in this data sheet.

Analog Inputs

Figure 26 shows a simplified analog input section of the
AD7679. The diodes shown in Figure 26 provide ESD
protection for the inputs. Care must be taken to ensure that the
analog input signal never exceeds the absolute ratings on these
inputs. This will cause these diodes to become forward biased
and start conducting current. These diodes can handle a
forward-biased current of 120 mA max. This condition could
eventually occur when the input buffer’s U1 or U2 supplies are
different from AVDD. In such a case, an input buffer with a
short-circuit current limitation can be used to protect the part.

AV D D

consists of the ADC sampling capacitor. This 1-pole filter with a
–3 dB cutoff frequency of 26 MHz typ reduces any undesirable
aliasing effect and limits the noise coming from the inputs.

Because the input impedance of the AD7679 is very high, the
part can be driven directly by a low impedance source without
gain error. This allows the user to put an external 1-pole RC
filter between the amplifier output and the ADC analog inputs,
as shown in Figure 25, to even further improve the noise
filtering done by the AD7679 analog input circuit. However, the
source impedance has to be kept low because it affects the ac
performance, especially the total harmonic distortion (THD).
The maximum source impedance depends on the amount of
THD that can be tolerated. The THD degrades as a function of
source impedance and the maximum input frequency, as shown
in Figure 28.

–95

–100

20kHz

IN+

IN–

AGND

Figure 26. Simplified Analog Input

R+ = 102Ω

R– = 102Ω

C

S

C

S

03085-0-028

This analog input structure is a true differential structure. By
using these differential inputs, signals common to both inputs
are rejected as shown in Figure 27, which represents typical
CMRR over frequency.

80

75

70

65

CMRR (dB)

60

55

–105

THD (dB)

–110

–115

–120

Figure 28. THD vs. Analog Input Frequency and Source Resistance

45 75 10515

INPUT RESISTANCE (Ω)

10kHz

2kHz

03085-0-030

Driver Amplifier Choice

Although the AD7679 is easy to drive, the driver amplifier
needs to meet the following requirements:

• • The driver amplifier and the AD7679 analog input circuit

have to be able to settle for a full-scale step of the capacitor
array at an 18-bit level (0.0004%). In the amplifier’s data
sheet, settling at 0.1% or 0.01% is more commonly
specified. This could differ significantly from the settling
time at an 18-bit level and, therefore, should be verified
prior to driver selection. The tiny op amp AD8021, which
combines ultralow noise and high gain-bandwidth, meets
this settling time requirement.

50

Figure 27. Analog In put CMRR vs. Frequency

100 1000 10000110

FREQUECY (kHz)

03085-0-029

During the acquisition phase for ac signals, the AD7679 behaves
like a 1-pole RC filter consisting of the equivalent resistance,
R+, R–, and C

. Resistors R+ and R– are typically 102 Ω and are

S

lumped components made up of a serial resistor and the on
resistance of the switches. C

is typically 60 pF and mainly

S

Rev. 0 | Page 17 of 28

The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7679. The noise
coming from the driver is filtered by the AD7679 analog
input circuit 1-pole low-pass filter made by R+, R–, and C

.

S

AD7679

The SNR degradation due to the amplifier is






=

LOSS

SNR

log20







where:

is the –3 dB input bandwidth in MHz of the AD7679

f

–3dB

(26 MHz) or the cutoff frequency of the input filter, if used.
N is the noise factor of the amplifiers (1 if in buffer
configuration).

e

is the equivalent input noise voltage of each op amp in

N

nV/√Hz.

For instance, for a driver with an equivalent input noise of
2 nV/√Hz (e.g., AD8021) configured as a buffer, thus with a
noise gain of +1, the SNR degrades by only 0.34 dB with
the filter in Figure 25, and by 1.8 dB without it.

25

Ne

2

)(625

N

f

π+

3dB–











ANALOG INPUT

(UNIPOLAR

0V TO 4.096V)

U1

AD8021

10pF

590

Ω

30

Ω

590Ω

2.7nF

30

Ω

1.82k

8.25kΩ

Figure 29. Single-Ended-to-Differential Driver Circuit

U2

100nF

(Internal Reference Buffer Used)

Ω

AD8021

10pF

2.7nF

IN+

IN–

AD7679

REF

10µF

REFBUFIN

03085-0-031

2.5V

Voltage Reference

The AD7679 allows the use of an external voltage reference
either with or without the internal reference buffer.

• The driver needs to have a THD performance suitable to

that of the AD7679.

The AD8021 meets these requirements and is usually
appropriate for almost all applications. The AD8021 needs a
10 pF external compensation capacitor, which should have good
linearity as an NPO ceramic or mica type.

The AD8022 could be used if a dual version is needed and gain
of 1 is present. The AD829 is an alternative in applications
where high frequency (above 100 kHz) performance is not
required. In gain of 1 applications, it requires an 82 pF
compensation capacitor. The AD8610 is another option when
low bias current is needed in low frequency applications.

Single-to-Differential Driver

For applications using unipolar analog signals, a single-ended­to-differential driver will allow for a differential input into the
part. The schematic is shown in Figure 29. When provided an
input signal of 0 to V
differential ±V

REF

, this configuration will produce a

REF

with midscale at V

REF

/2.

If the application can tolerate more noise, the AD8138,
differential driver can be used.

Using the internal reference buffer is recommended when
sharing a common reference voltage between multiple ADCs is
desired.

However, the advantages of using the external reference voltage
directly are

• • The SNR and dynamic range improvement (about 1.7 dB)

resulting from the use of a reference voltage very close to
the supply (5 V) instead of a typical 4.096 V reference when
the internal buffer is used.

The power saving when the internal reference buffer is
powered down (PDBUF high).

To use the internal reference buffer, PDBUF should be LOW. A

2.5 V reference voltage applied on the REFBUFIN input will
result in a 4.096 V reference on the REF pin.

In both cases, the voltage reference input REF has a dynamic
input impedance and therefore requires an efficient decoupling
between REF and REFGND inputs. The decoupling consists of a
low ESR 47 µF tantalum capacitor connected to the REF and
REFGND inputs with minimum parasitic inductance.

Care should also be taken with the reference temperature
coefficient of the voltage reference, which directly affects the
full-scale accuracy if this parameter matters. For instance, a
±4 ppm/°C temperature coefficient of the reference changes the
full scale by ±1 LSB/°C.

Rev. 0 | Page 18 of 28

AD7679

Power Supply

The AD7679 uses three sets of power supply pins: an analog 5 V
supply (AVDD), a digital 5 V core supply (DVDD), and a digital
output interface supply (OVDD). The OVDD supply defines the
output logic level and allows direct interface with any logic
working between 2.7 V and DVDD + 0.3 V. To reduce the
number of supplies needed, the digital core (DVDD) can be
supplied through a simple RC filter from the analog supply, as
shown in Figure 25. The AD7679 is independent of power
supply sequencing once OVDD does not exceed DVDD by
more than 0.3 V, and is therefore free from supply voltage
induced latch-up. Additionally, it is very insensitive to power
supply variations over a wide frequency range (see Figure 30).

65

60

55

PSRR (dB)

50

1000000

100000

10000

1000

100

10

POWER DISSAPATION (µW)

1

PDBUF H IGH

0.1
10

SAMPLING RATE (SPS)

Figure 31. Power Dissipation vs. Sample Rate

100k10k1k1001

03085-0-033

1M

CONVERSION CONTROL

Figure 32 shows the detailed timing diagrams of the conversion
process. The AD7679 is controlled by the

initiates conversion. Once initiated, it cannot be restarted or
aborted, even by PD, until the conversion is complete. The
CNVST

signal operates independently of CS and RD.

CNVST

signal, which

45

40

Figure 30. PSRR v s. Frequency

100 1000 10000110

FREQUECY (kHz)

03085-0-032

POWER DISSIPATION VERSUS THROUGHPUT

The AD7679 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows for a
significant power savings when the conversion rate is reduced,
as shown in Figure 31. This feature makes the AD7679 ideal for
very low power battery applications.

It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be
driven close to the power rails (DVDD and DGND), and
OVDD should not exceed DVDD by more than 0.3 V.

t

t

CNVST

BUSY

t

t

MODE ACQUIRE CONVERT ACQUIRE CONVERT

Although

CNVST

1

t

3

5

4

t

7

Figure 32. Basic Conversion Timing

is a digital signal, it should be designed with

2

t

6

t

8

03085-0-034

special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.

For applications where SNR is critical, the

CNVST

signal should

have very low jitter. This may be achieved by using a dedicated
oscillator for

CNVST

generation, or to clock it with a high

frequency low jitter clock, as shown in Figure 25.

For other applications, conversions can be automatically
initiated. If

is held low when BUSY is low, the AD7679

CNVST
controls the acquisition phase and automatically initiates a new
conversion. By keeping

CNVST

low, the AD7679 keeps the

conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up,

CNVST

should be brought low once to initiate the

conversion process. In this mode, the AD7679 could sometimes
run slightly faster than the guaranteed limits of 570 kSPS.

Rev. 0 | Page 19 of 28

AD7679

DIGITAL INTERFACE

The AD7679 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7679 digital interface also accommodates both 3 V and 5 V
logic by simply connecting the AD7679’s OVDD supply pin to
the host system interface digital supply. Finally, by using the
OB/

input pin in any mode but 18-bit interface mode, both

2C

twos complement and straight binary coding can be used.

The two signals, CS and RD, control the interface. When at least
one of these signals is high, the interface outputs are in high

impedance. Usually,

multicircuit applications, and is held low in a single AD7679
design.

is generally used to enable the conversion result on

RD

the data bus.

RESET

BUSY

allows the selection of each AD7679 in

CS

t

9

that it is read only during the first half of the conversion phase.
This avoids any potential feedthrough between voltage
transients on the digital interface and the most critical analog
conversion circuitry. Refer to Table 7 for a detailed description
of the different options available.

CS

RD

BUSY

DATA

BUS

t

12

Figure 35. Slave Parallel Data Timing for Reading (Read after Convert)

CS = 0

CNVST,

RD

CURRENT

CONVERSION

t

t

1

13

03085-0-037

DATA

BUS

t

8

CNVST

03085-0-035

Figure 33. RESET Timing

CS = RD = 0

CNVST

BUSY

DATA

BUS

t

1

t

10

t

4

t

3

PREVIOUS CONVERSION DATA NEW DATA

t

11

03085-0-036

Figure 34. Master Parallel Data Timing for Reading (Continuous Read)

PARALLEL INTERFACE

The AD7679 is configured to use the parallel interface with an
18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The
data can be read either after each conversion, which is during
the next acquisition phase, or during the following conversion,
as shown in Figure 35 and Figure 36, respectively. When the
data is read during the conversion, however, it is recommended

BUSY

DATA

BUS

t

3

t

12

PREVIOUS

CONVERSION

t

t

4

13

03085-0-038

Figure 36. Slave Parallel Data Timing for Reading (Read during Convert)

CS

RD

A0, A1

PINS D[15:8]

PINS D[7:0]

HI-Z

t

HI-Z

HIGH BYTE LOW BYTE

12

LOW BYTE HIGH BYTE

t

12

HI-Z

t

13

HI-Z

03085-0-039

Figure 37. 8-Bit and 16-Bit Parallel Interface

SERIAL INTERFACE

The AD7679 is configured to use the serial interface when
MODE0 and MODE1 are held high. The AD7679 outputs 18
bits of data, MSB first, on the SDOUT pin. This data is
synchronized with the 18 clock pulses provided on the SCLK
pin. The output data is valid on both the rising and falling edge
of the data clock.

Rev. 0 | Page 20 of 28

AD7679

MASTER SERIAL INTERFACE

Internal Clock

The AD7679 is configured to generate and provide the serial
data clock SCLK when the EXT/

AD7679 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. Figure 38 and Figure 39 show
the detailed timing diagrams of these two modes.

pin is held low. The

INT

In Read during Conversion mode, the serial clock and data
toggle at appropriate instants, minimizing potential feedthrough
between digital activity and critical conversion decisions.

In Read after Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.

To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.

Usually, because the AD7679 is used with a fast throughput, the
mode master read during conversion is the most recommended
serial mode.

CS, RD

CNVST

BUSY

SYNC

SCLK

SDOUT

t

3

t

t

15

t

16

EXT/INT = 0

t

29

t

14

t

22

18

t

19

t

20

123 161718

D17 D16 D2 D1 D0X

Figure 38. Master Serial Data Timing for Reading (Read after Convert)

RDC/SDIN = 0 INVSCLK = INVSYNC = 0

t

28

t

21

t

23

t

30

t

25

t

24

03085-0-040

t

26

t

27

Rev. 0 | Page 21 of 28

AD7679

S

CS, RD

CNVST

BUSY

SYNC

SCLK

DOUT

t

16

EXT/INT = 0

t

1

t

3

t

17

t

14

t

15

t

18

t

22

Figure 39. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)

t

19

t20t

21

123 161718

D17 D16 D2 D1 D0X

SLAVE SERIAL INTERFACE

External Clock

The AD7679 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/

held high. In this mode, several methods can be used to read the
data. The external serial clock is gated by

. When CS and RD

CS
are both low, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 40 and Figure 41 show the detailed timing

diagrams of these methods.

While the AD7679 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7679 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that toggles only when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.

INT

pin is

RDC/SDIN = 1 INVSCLK = INVSYNC = 0

t

23

t

25

t

24

t

t

03085-0-041

26

27

External Discontinuous Clock Data Read after
Conversion

This mode is the most recommended of the serial slave modes.
Figure 40 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both

are low. Data is shifted out MSB first with 18 clock pulses,

RD
and is valid on the rising and falling edge of the clock.

Among the advantages of this method, the conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Also, data can be read at speeds up to 40 MHz, accommodating
both slow digital host interface and the fastest serial reading.

Finally, in this mode only, the AD7679 provides a daisy-chain
feature using the RDC/SDIN input pin to cascade multiple
converters together. This feature is useful for reducing
component count and wiring connections when desired (for
instance, in isolated multiconverter applications).

An example of the concatenation of two devices is shown in
Figure 42. Simultaneous sampling is possible by using a
common

CNVST

signal. It should be noted that the RDC/SDIN

input is latched on the edge of SCLK opposite the one used to
shift out data on SDOUT. Thus, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SCLK cycle.

CS

and

Rev. 0 | Page 22 of 28

AD7679

CS

BUSY

EXT/INT = 1 RD = 0

t

35

t

t

36

37

INVSCLK = 0

SCLK

SDOUT

SDIN

CS

CNVST

BUSY

SCLK

SDOUT

123 17181920

t

31

D17 D16 D1 D0D15

t

16

X17 X16 X15 X1 X0 Y17 Y16

t

33

t

32

t

34

Figure 40. Slave Serial Data Timing for Reading (Read after Convert)

EXT/INT = 1 RD = 0

t

3

t

16

t

35

t36t

37

12 3 1718

t

31

t

32

INVSCLK = 0

D1 D0X D17 D16 D15

Figure 41. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)

X17 X16X

03085-0-042

03085-0-043

Rev. 0 | Page 23 of 28

AD7679

BUSY
OUT

BUSY BUSY

RDC/SDIN SDOUT

SCLK IN

CS IN

CNVST IN

AD7679

#2 (UPSTREAM)

CNVST

CS

SCLK

AD7679

#1 (DOWNSTREAM)

RDC/SDIN SDOUT

CNVST

SCLK

DATA
OUT

CS

03085-0-044

Figure 42. Two AD7679s in a Daisy-Chain Configuration

External Clock Data Read during Conversion

Figure 41 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are low, the result

of the previous conversion can be read. The data is shifted out
MSB first with 18 clock pulses, and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete. If that is not done,
RDERROR is pulsed high and can be used to interrupt the host
interface to prevent incomplete data reading. There is no daisy­chain feature in this mode, and the RDC/SDIN input should
always be tied either high or low.

To reduce performance degradation due to digital activity, a fast
discontinuous clock is recommended to ensure that all bits are
read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue
to read the last bits even after a new conversion has been
initiated.

MICROPROCESSOR INTERFACING

The AD7679 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7679 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7679 to prevent digital noise from coupling
into the ADC. The following section illustrates the use of the
AD7679 with an SPI equipped DSP, the ADSP-219x.

SPI Interface (ADSP-219x)

Figure 43 shows an interface diagram between the AD7679 and
the SPI equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7679 acts as a slave device, and data
must be read after conversion. This mode also allows the daisy­chain feature. The convert command could be initiated in
response to an internal timer interrupt. The 18-bit output data
are read with 3-byte SPI access. The reading process could be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial
interface (SPI) on the ADSP-219x is configured for master
mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase
Bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by
writing to the SPI Control register (SPICLTx). It should be
noted that to meet all timing requirements, the SPI clock should
be limited to 17 Mbits/s, which allow it to read an ADC result in
about 1.1 µs. When a higher sampling rate is desired, use of one
of the parallel interface modes is recommended.

DVD D

AD7679*

SER/PAR

EXT/INT

RD

INVSCLK

BUSY

CS

SDOUT

SCLK

CNVST

ADSP-219x*

PFx

SPIxSEL (PFx)

MISOx

SCKx

PFx or TFSx

Rev. 0 | Page 24 of 28

* ADDITIONAL PINS OMITTED FOR CLARITY

Figure 43. Interfacing the AD7679 to an SPI Interface

03085-0-045

AD7679

APPLICATION HINTS

LAYOUT

The AD7679 has very good immunity to noise on the power
supplies. However, care should still be taken with regard to
grounding layout.

The printed circuit board that houses the AD7679 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. Digital and
analog ground planes should be joined in only one place,
preferably underneath the AD7679, or at least as close to the
AD7679 as possible. If the AD7679 is in a system where
multiple devices require analog-to-digital ground connections,
the connection should still be made at one point only, a star
ground point that should be established as close to the AD7679
as possible.

The user should avoid running digital lines under the device, as
these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7679 to avoid noise
coupling. Fast switching signals like

shielded with digital ground to avoid radiating noise to other
sections of the board, and should never run near analog signal
paths. Crossover of digital and analog signals should be avoided.
Traces on different but close layers of the board should run at
right angles to each other. This will reduce the effect of
feedthrough through the board. The power supply lines to the
AD7679 should use as large a trace as possible to provide low
impedance paths and reduce the effect of glitches on the power
supply lines. Good decoupling is also important to lower the
supply’s impedance presented to the AD7679 and to reduce the
magnitude of the supply spikes. Decoupling ceramic capacitors,
typically 100 nF, should be placed close to and ideally right up
against each power supply pin (AVDD, DVDD, and OVDD)
and their corresponding ground pins. Additionally, low ESR 10
µF capacitors should be located near the ADC to further reduce
low frequency ripple.

or clocks should be

CNVST

The DVDD supply of the AD7679 can be a separate supply or
can come from the analog supply, AVDD, or the digital interface
supply, OVDD. When the system digital supply is noisy or when
fast switching digital signals are present, and if no separate
supply is available, the user should connect the DVDD digital
supply to the analog supply AVDD through an RC filter, (see
Figure 25), and connect the system supply to the interface
digital supply OVDD and the remaining digital circuitry. When
DVDD is powered from the system supply, it is useful to insert a
bead to further reduce high frequency spikes.

The AD7679 has four different ground pins: REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage and
should be a low impedance return to the reference because it
carries pulsed currents. AGND is the ground to which most
internal ADC analog signals are referenced. This ground must
be connected with the least resistance to the analog ground
plane. DGND must be tied to the analog or digital ground plane
depending on the configuration. OGND is connected to the
digital system ground.

The layout of the decoupling of the reference voltage is
important. The decoupling capacitor should be close to the
ADC and should be connected with short and large traces to
minimize parasitic inductances.

EVALUATING THE AD7679’S PERFORMANCE

A recommended layout for the AD7679 is outlined in the
documentation of the
the AD7679. The evaluation board package includes a fully
assembled and tested evaluation board, documentation, and
software for controlling the board from a PC via the

CONTROL BRD2

EVAL-AD7679CB evaluation board for

EVAL-

.

Rev. 0 | Page 25 of 28

AD7679

Q

OUTLINE DIMENSIONS

1.45

1.40

1.35

0.15

0.05

PIN 1
INDICATOR

10°

6°
2°

SEATING
PLANE

ROTATED 90°CCW

VIEW A

0.10 MAX
COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026BBC

0.20

0.09

7°

3.5°
0°

0.75

0.60

0.45

SEATING

PLANE

1.60
MAX

VIEW A

Figure 44. 48-Lead Low Profile Quad Flatpack [LQFP] (ST-48)

(Dimensions shown in millimeters)

7.00

BSC SQ

0.60 MAX

37

36

0.60 MAX

1

12

0.50
BSC

48

13

9.00 BSC
SQ

PIN 1

TOP VIEW

(PINS DOWN )

0.30

0.23

0.18

37

36

7.00

BSC S

25

24

0.27

0.22

0.17

PIN 1

48

INDICATOR

1

5.25
SQ

5.10

4.95

12

PADDLE CONNECTED TO AGND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCE

1.00

0.90

0.80

0.20
REF

12° MAX

SEATING
PLANE

TOP

VIEW

0.80 MAX

0.65 NOM

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

6.75

BSC SQ

0.50

0.40

0.30

0.05 MAX

0.02 NOM

COPLANARITY

0.08

BOTTOM

VIEW

25

24

5.50
REF

13

Figure 45. 48-Lead Leadframe Chip Scale Package [LFCSP] (CP-48)

(Dimensions shown in millimeters)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary
ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7679AST –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7679ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7679ACP –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48
AD7679ACPRL –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48
EVAL-AD7679CB
EVAL-CONTROL BRD2

1

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

2

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

1

2

Evaluation Board
Controller Board

Rev. 0 | Page 26 of 28

AD7679

NOTES

Rev. 0 | Page 27 of 28

AD7679

NOTES

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.

C03085–0–7/03(0)

Rev. 0 | Page 28 of 28