Datasheet AD7667CB, AD7667ASTRL, AD7667AST, AD7667ACPRL, AD7667ACP Datasheet (Analog Devices)

REV. PrA

Preliminary Technical Data

PRELIMINARY TECHNICAL DATA

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

a

AD7667

*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

16-Bit 1 MSPS SAR Unipolar ADC with Ref

FUNCTIONAL BLOCK DIAGRAM

SWITCHED

CAP DAC

16

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

CLOCK

AD7667

DATA[15:0]
BUSY
RD
CS
SER/PAR
OB/2C

OGND

OVDD

DGNDDVDD

AVDD

AGND

REF REFGND

IN

INGND

PD

RESET

SERIAL

PORT

PARALLEL

INTERFACE

CNVSTWARP IMPULSE

2.5 V REF

PDREF

PDBUF

REFBUFIN

BYTESWAP

FEATURES
Throughput:

1 MSPS (Warp Mode)

800 kSPS (Normal Mode)
INL: ±2.5 LSB Max (±0.0038% of Full Scale)
16 Bits Resolution with No Missing Codes
Analog Input Voltage Range: 0 V to 2.5 V
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
SPI

TM

/QSPITM/MICROWIRETM/DSP Compatible
Single 5 V Supply Operation
Power Dissipation

112 mW Typ without REF, 122 mW Typ with REF

15 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flat Pack (LQFP);
48-Lead Chip Scale Package (LFCSP);
Pin-to-Pin Compatible with PulSAR ADCs

APPLICATIONS
Data Acquisition
Instrumentation
Digital Signal Processing
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control

GENERAL DESCRIPTION

The AD7667 is a 16-bit, 1 MSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high-speed 16-bit sampling
ADC, an internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system inter­face ports.

It features a very high sampling rate mode (Warp) and, for
asynchronous conversion rate applications, a fast mode
(Normal) and, for low power applications, a reduced power
mode (Impulse) where the power is scaled with the through­put.

It is fabricated using Analog Devices’ high-performance, 0.6 micron
CMOS process, with correspondingly low cost and is available in a
48-lead LQFP and a tiny 48-lead LFCSP with operation speci­fied from –40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Fast Throughput
The AD7667 is a 1 MSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.

2. Internal Reference
The AD7667 has an internal reference and allows for an
external reference to be used.

3. Superior INL
The AD7667 has a maximum integral nonlinearity of 2.5
LSB with no missing 16-bit code.

4. Single-Supply Operation
The AD7667 operates from a single 5 V supply and dissipates
a typical of 112 mW. In impulse mode, its power dissi­pation decreases with the throughput. It consumes 7 µW
maximum when in power-down.

5. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement
compatible with both 3 V or 5 V logic.

*Patent pending.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE ia a trademark of National Semiconductor Corporation

Pseudo AD7651 AD7650/52 AD7653

Differential AD7660/61 AD7664/66 AD7667

True Bipolar AD7663 AD7665 AD7671
True AD7675 AD7676 AD7677

Differential

Type / kSPS

100 - 250

500 - 570

1000

PulSAR Selection

PRELIMINARY TECHNICAL DATA

REV. PrA

–2–

AD7667

Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits

ANALOG INPUT

Voltage Range V

IN

– V

INGND

0V

REF

V

Operating Input Voltage V

IN

–0.1 +3 V

V

INGND

–0.1 +0.5 V
Analog Input CMRR fIN = 10 kHz TB D dB
Input Current 1 MSPS Throughput 11 µA
Input Impedance See Analog Input Section

THROUGHPUT SPEED

Complete Cycle In Warp Mode 1 µs
Throughput Rate In Warp Mode 1 1000 kSPS
Time Between Conversions In Warp Mode 1 ms
Complete Cycle In Normal Mode 1.25 µs
Throughput Rate In Normal Mode 0 800 kSPS
Complete Cycle In Impulse Mode 1.5 µs
Throughput Rate In Impulse Mode 0 666 kSPS

DC ACCURACY

Integral Linearity Error –2.5 +2.5 LSB

1

No Missing Codes 16 Bits
Transition Noise 0.7 LSB
Full-Scale Error

2

REF = 2.5 V ±TBD % of FSR

Unipolar Zero Error

2

±TBD ±TBD LSB

Power Supply Sensitivity AVDD = 5 V ± 5% ±TBD LSB

AC ACCURACY

Signal-to-Noise f

IN

= 100 kHz 90 d B
Spurious Free Dynamic Range fIN = 100 kHz 100 dB
Total Harmonic Distortion fIN = 45 kHz -100 dB

fIN = 100 kHz -100 dB

Signal-to-(Noise+Distortion) fIN = 100 kHz 90 d B

–60 dB Input, fIN = 100 kHz 30 d B

–3 dB Input Bandwidth TB D MH z

SAMPLING DYNAMICS

Aperture Delay 2ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 250 ns

REFERENCE

Internal Reference Voltage @

25C

TBD 2.5 TBD V
Internal Reference Source Current TBD µA
Internal Reference Temp Drift

–40C to +85C TBD ppm/C

Internal Reference Temp Drift

0C to +70C TBD ppm/C

Turn-on Settling Time TBD
External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 1 MSPS Throughput TBD µA

Temperature Pin
Voltage Output @

25C 313 mV

Temperature Sensitivity 1 mV/C

Output Resistance 4.3 k 

DIGITAL INPUTS

Logic Levels

V

IL

–0.3 +0.8 V

V

IH

2.0 OVDD + 0.3 V

I

IL

–1 +1 µA

I

IH

–1 +1 µA

DIGITAL OUTPUTS

Data Format Parallel or Serial 16-Bits
Pipeline Delay Conversion Results Available

Immediately after
Completed Conversion

V

OL

I

SINK

= 1.6 mA 0.4 V

V

OH

I

SOURCE

= –500 µA OVDD – 0.6 V

POWER SUPPLIES

Specified Performance

AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25

9

V

–SPECIFICATIONS

(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)

REV. PrA

PRELIMINARY TECHNICAL DATA

–3–

AD7667

Parameter Conditions Min Typ Max Unit

TIMING SPECIFICATIONS

Symbol Min Typ Max Unit

REFER TO FIGURES 11 AND 12

Convert Pulsewidth t

1

5ns

Time Between Conversions t

2

1/1.25/1.5 Note 1 µs

(Warp Mode/Normal Mode/Impulse Mode)

CNVST LOW to BUSY HIGH Delay t

3

30 ns

BUSY HIGH All Modes Except in t

4

0.75/1/1.25 µs
Master Serial Read After Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)

Aperture Delay t

5

2ns

End of Conversion to BUSY LOW Delay t

6

10 ns

Conversion Time t

7

0.75/1/1.25 µs
(Warp Mode/Normal Mode/Impulse Mode)

Acquisition Time t

8

250 ns

RESET Pulsewidth t

9

10 ns

REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)

CNVST LOW to DATA Valid Delay t

10

0.75/1/1.25 µs
(Warp Mode/Normal Mode/Impulse Mode)

DATA Valid to BUSY LOW Delay t

11

45 ns

Bus Access Request to DATA Valid t

12

40 ns

Bus Relinquish Time t

13

515ns

REFER TO FIGURES 16 AND 17 (Master Serial Interface Modes)

2

CS LOW to SYNC Valid Delay t

14

10 ns

CS LOW to Internal SCLK Valid Delay

2

t

15

10 ns

CS LOW to SDOUT Delay t

16

10 ns

CNVST LOW to SYNC Delay t

17

25/275/525 ns

(Warp Mode/Normal Mode/Impulse Mode)

SYNC Asserted to SCLK First Edge Delay t

18

3ns

Internal SCLK Period

3

t

19

25 40 ns

Internal SCLK HIGH

3

t

20

12 ns

Internal SCLK LOW

3

t

21

7ns

SDOUT Valid Setup Time

3

t

22

4ns

SDOUT Valid Hold Time

3

t

23

2ns

SCLK Last Edge to SYNC Delay

3

t

24

3

CS HIGH to SYNC HI-Z t

25

10 ns

CS HIGH to Internal SCLK HI-Z t

26

10 ns

CS HIGH to SDOUT HI-Z t

27

10 ns

BUSY HIGH in Master Serial Read after Convert

3

t

28

See Table I µs

(Warp Mode/Normal Mode/Impulse Mode)

CNVST LOW to SYNC Asserted Delay t

29

0.75/1/1.25 µs

(Warp Mode/Normal Mode/Impulse Mode)

SYNC Deasserted to BUSY LOW Delay t

30

25 ns

(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)

Operating Current

4

1 MSPS Throughput

AVDD

5

TBD mA

DVDD

5

TBD mA

OVDD

5

TBD µA

Power Dissipation

5

without REF 1 MSPS Throughput 112 mW

100 SPS Throughput

6

15 µW

In Power-Down Mode

7

TBD µW

Power Dissipation

5

with REF 1 MSPS Throughput 122 mW

100 SPS Throughput

6

10.015 mW

In Power-Down Mode

7

TBD µW

TEMPERATURE RANGE

8

Specified Performance T

MIN

to T

MAX

–40 +85

°C

NOTES

1

LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV.

2

See Definition of Specifications section. These specifications do not include the error contribution from the external reference.

3

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.

4

In warp mode.

5

Tested in parallel reading mode using external reference.

6

In impulse mode with external REF.

7

With all digital inputs forced to DVDD or DGND respect

ively.

8

Contact factory for extended temperature range.

9

The max should be the minimum of 5.25V and DVDD+0.3 V.

Specifications subject to change without notice.

REV. PrA

PRELIMINARY TECHNICAL DATA

–4–

AD7667

Table I. Serial clock timings in Master Read after Convert

DIVSCLK[1] 0011unit
DIVSCLK[0] 0101

SYNC to SCLK First Edge Delay Minimum t

18

3 171717ns

Internal SCLK Period minimum t

19

25 50 100 200 ns

Internal SCLK Period typical t

19

40 70 140 280 ns

Internal SCLK HIGH Minimum t

20

12 22 50 100 ns

Internal SCLK LOW Minimum t

21

7 214999ns

SDOUT Valid Setup Time Minimum t

22

4 181818ns

SDOUT Valid Hold Time Minimum t

23

2 4 3089ns

SCLK Last Edge to SYNC Delay Minimum t

24

3 60 140 300 ns

Busy High Width Maximum (Warp) t

24

1.5 2 3 5.25 µs

Busy High Width Maximum (Normal) t

24

1.75 2.25 3.25 5.55 µs

Busy High Width Maximum (Impulse) t

24

2 2.5 3.5 5.75 µs

REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)

2

External SCLK Setup Time t

31

5ns

External SCLK Active Edge to SDOUT Delay t

32

318ns

SDIN Setup Time t

33

5ns

SDIN Hold Time t

34

5ns

External SCLK Period t

35

25 ns

External SCLK HIGH t

36

10 ns

External SCLK LOW t

37

10 ns

NOTES

1

In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.

2

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

3

In serial master read during convert mode. See Table I for serial master read after convert mode.

Specifications subject to change without notice.

Symbol Min Typ Max Unit

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–5–

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7667 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Temperature

Model Range Package Description Package Option
AD7667AST –40°C to +85°C Quad Flatpack (LQFP) ST-48

AD7667ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7667ACP –40°C to +85°C Chip Scale (LFCSP) CP-48
AD7667ACPRL –40°C to +85°C Chip Scale (LFCSP) CP-48
EVAL-AD7667CB

1

Evaluation Board

EVAL-CONTROL BRD2

2

Controller Board

NOTES

1

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

2

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

ABSOLUTE MAXIMUM RATINGS*

IN2, TEMP2,REF, REFBUFIN, INGND, REFGND to AGND

. . . . . . . . . . . . . . . . . . . . . . .AVDD + 0.3 V to AGND – 0.3 V

Ground Voltage Differences

AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD . . . . . . . . . . . . . . . -0.3V to +7 V

AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . ±7 V

DVDD to OVDD . . . . . . . . . . . . . . . . . . . . -0.3V to +7 V

Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 3.0 V

Internal Power Dissipation

3

. . . . . . . . . . . . . . . . . . . 700 mW

Internal Power Dissipation

4

. . . . . . . . . . . . . . . . . . . . . 2.5 W

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range

(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

See Analog Input section.

3

Specification is for the device in free air:

48-Lead LQFP; θ

JA

= 91°C/W, θ

JC

= 30°C/W

4

Specification is for the device in free air:

48-Lead LFCSP; θ

JA

= 26°C/W

I

OH

500A

1.6mA I

OL

TO OUTPUT

PIN

1.4V

C

L

60pF*

*

IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C

L

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, C

L

= 10 pF

0.8V

2V

2V

0.8V

0.8V

2V

t

DELAY

t

DELAY

Figure 2. Voltage Reference Levels for Timing

WARNING!

ESD SENSITIVE DEVICE

REV. PrA

PRELIMINARY TECHNICAL DATA

–6–

AD7667

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Type Description
1 AGND P Analog Power Ground Pin

2 AVDD P Input Analog Power Pins. Nominally 5 V.
3, 40–42, NC No Connect
44
4 BYTESWAP DI Parallel Mode Selection (8/16 bit). When LOW, the LSB is output on D[7:0] and the

MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB
is output on D[7:0].

5 OB/2C D I Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is

straight binary; when LOW, the MSB is inverted resulting in a two’s complement output
from its internal shift register.

6 WARP DI Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode,

the maximum throughput is achievable, and a minimum conversion rate must be applied
in order to guarantee full specified accuracy. When LOW, full accuracy is maintained
independent of the minimum conversion rate.

7 IMPULSE DI Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.

In this mode, the power dissipation is approximately proportional to the sampling rate.

8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the

serial interface mode is selected and some bits of the DATA bus are used as a serial port.

9,10 DATA[0:1] DI Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these

outputs are in high impedance.

11,12 DATA[2:3]or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port

DIVSCLK[0:1] Data Output Bus. When SER/PAR is HIGH , EXT/INT is LOW, and RDC/SDIN is

LOW, which is serial master read after convert, these inputs, part of the serial port, are
used to slow down if desired the internal serial clock which clocks the data output. In
other serial moes, these pins are not used

13 DATA[4] DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output

Bus.

or EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input

for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal
clock

is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is syn

chronized

to an external clock signal connected to the SCLK input.

14 DATA[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output

Bus.

or INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active

PIN CONFIGURATION

48-Lead LQFP

(ST-48)

36
35
34
33
32
31
30
29
28
27
26
25

13 14 15 16 17 18 19 20 21 22 23 24

1
2
3
4
5
6
7
8

9
10
11
12

48 47 46 45 44 39 38 3743 42 41 40

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

AGND
CNVST
PD
RESET
CS
RD
DGND

AGND
AVDD

NC

BYTESWAP

OB/2C
WARP

IMPULSE

NC = NO CONNECT

SER/PAR

D0
D1

D2/SCLK0

BUSY
D15
D14
D13

AD7667

D3/SCLK1

D12

D4/EXT/INT

D5/INVSYNC

D6/INVSCLK

D7/RDC/SDIN

OGND

OVDD

DVDD

DGND

D8/SDOUT

D9/SCLK

D10/SYNC

D11/RDERROR

PDBUF

PDREF

REFBUFIN

TEMPNCINNCNCNCINGND

REFGND

REF

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–7–

state of the SYNC signal. It is active in both master and slave mode. When LOW, SYNC
is active HIGH. When HIGH, SYNC is active LOW.

15 DATA[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output

Bus.

or INVSCLK

When SER/

PAR

is HIGH, this input, part of the serial port, is used to invert the SCLK signal.

It is active in both master and slave mode.

16 DATA[7] DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output

Bus.

or RDC/SDIN When SER/PAR is HIGH, this input, part of the serial port, is used as either an external

data input or a read mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy chain the conver ­sion results from two or more ADCs onto a single SDOUT line. The digital data level on
SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read
sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN
is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW,

the data can be output on SDOUT only when the conversion is complete.
17 OGND P Input/Output Interface Digital Power Ground
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply than the supply of

the host interface (5 V or 3 V).
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground
21 DATA[8] DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.

or SDOUT When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data out

put synchronized to SCLK. Conversion results are stored in an on-chip register. The

AD7667 provides the conversion result, MSB first, from its internal shift register. The

DATA format is determined by the logic level of OB/2C. In serial mode, when EXT/INT

is LOW, SDOUT is valid on both edges of SCLK.

In serial mode, when EXT/INT is HIGH:

If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next

falling edge.

If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising

edge.
22 DATA[9] DI/O When SER/PAR is LOW, this output is used as the Bit 9 of the Parallel Port Data

or SCLK Output Bus.

When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock

input or output, dependent upon the logic state of the EXT/INT pin. The active edge

where the data SDOUT is updated depends upon the logic state of the INVSCLK pin.
23 DATA[10] DO When SER/PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output

Bus.

or SYNC When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output

frame synchronization for use with the internal data clock (EXT/INT = Logic LOW).

When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and

remains HIGH while SDOUT output is valid. When a read sequence is initiated and

INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is

valid.
24 DATA[11] DO When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output

Bus.

or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port,

is used as a incomplete read error flag. In slave mode, when a data read is started and

not complete when the following conversion is complete, the current data is lost and

RDERROR is pulsed high.
25–28 DATA[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regard

less of the state of SER/PAR.
29 BUS Y D O Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until

the conversion is complete and the data is latched into the on-chip shift register. The fall

ing edge of BUSY could be used as a data ready clock signal.
30 DGND P Must Be Tied to Digital Ground
31 RD DI

Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is

enabled.

32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is

enabled. CS is also used to gate the external clock.

Pin No. Mnemonic Type Description

REV. PrA

PRELIMINARY TECHNICAL DATA

–8–

AD7667

33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7667. Current conversion if any is

aborted. If not used, this pin could be tied to DGND.

34 P D DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver

sions are inhibited after the current one is completed.

35 CNVST D I Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state

and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW), if
CNVST is held low when the acquisition phase (t

8

) is complete, the internal sample/hold

is put into the hold state and a conversion is immediately started.
36 AGND P Must Be Tied to Analog Ground
37 REF AI Reference Input Voltage
38 REFGND AI Reference Input Analog Ground
39 INGND AI Analog Input Ground
43 IN AI Primart Analog Input with a Range of 0 to 2.5 V.
45 TEMP AO Temperature sensor voltage output.
46 REFBUFIN AI/O Reference Input Voltage. The reference output and the reference buffer input.
47 PDREF DI Allows choice of Internal or External voltage reference. When HIGH, the internal refer-

ence is switched off and an external reference must be used. When low,the on-chip refer

ence is turned on.
48 PDBUF DI Allows choice of buffering internal reference. When LOW, the buffer is selected. When

HIGH, the buffer is switched off.
NOTES
AI = Analog Input
AI/O = Bidirectional Analog
AO = Analog Output
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power

Pin No. Mnemonic Type Description

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–9–

DEFINITION OF SPECIFICATIONS

INTEGRAL NONLINEARITY ERROR (INL)

Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive full
scale.” The point used as “negative full scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.

DIFFERENTIAL NONLINEARITY ERROR (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differen­tial nonlinearity is the maximum deviation from this ideal
value. It is often specified in terms of resolution for which no
missing codes are guaranteed.

FULL-SCALE ERROR

The last transition (from 011 . . . 10 to 011 . . . 11 in two’s
complement coding) should occur for an analog voltage 1 1/2 LSB
below the nominal full scale (2.49994278 V for the 0 V–2.5 V
range). The full-scale error is the deviation of the actual level of
the last transition from the ideal level.

UNIPOLAR ZERO ERROR

The first transition should occur at a level 1/2 LSB above analog
ground (19.073 µV for the 0 V–2.5 V range). Unipolar zero error is
the deviation of the actual transition from that point.

SPURIOUS FREE DYNAMIC RANGE (SFDR)

The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.

EFFECTIVE NUMBER OF BITS (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula:

ENOB = (S/[N+D]

dB

– 1.76)/6.02

and is expressed in bits.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

SIGNAL TO (NOISE + DISTORTION) RATIO
(S/[N+D])

S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.

APERTURE DELAY

Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.

TRANSIENT RESPONSE

The time required for the AD7667 to achieve its rated accu­racy after a full-scale step function is applied to its input.

OVERVOLTAGE RECOVERY

The time required for the ADC to recover to full accuracy
after an analog input signal 150% of full-scale is reduced to
50% of the full-scale value.

REV. PrA

PRELIMINARY TECHNICAL DATA

–10–

AD7667

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

TPC 1. Integral Nonlinearity vs. Code

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

TPC 2. Histogram of 16,384 Conversions of a DC Input at
the Code Transition

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

TPC 3. FFT Plot

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

TPC 4. Differential Nonlinearity vs. Code

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

TPC 5. Histogram of 16,384 Conversions of a DC Input at
the Code Center

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

TPC 6. SNR, THD vs. Temperature

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–11–

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

TPC 7. SNR, S/(N+D), and ENOB vs. Frequency

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

TPC 8. SNR and S/(N+D) vs. Input Level
(Referred to Full Scale)

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

TPC 9. Operating Currents vs. Sample Rate

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

TPC 10. THD, Harmonics, and SFDR vs. Frequency

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

TPC 11. Typical Delay vs. Load Capacitance C

L

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

TPC 12. Power-Down Operating Currents vs. Temperature

REV. PrA

PRELIMINARY TECHNICAL DATA

–12–

AD7667

CIRCUIT INFORMATION

The AD7667 is a very fast, low power, single supply, pre­cise 16-bit analog-to-digital converter (ADC). The
AD7667 features different modes to optimize performances
according to the applications.

In warp mode, the AD7667 is capable of converting
1,000,000 samples per second (1MSPS).

The AD7667 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe­line or latency, making it ideal for multiple multiplexed channel
applications.

The AD7667 can be operated from a single 5 V supply and
be interfaced to either 5 V or 3 V digital logic. It is housed
in either a 48-lead LQFP package or a 48-lead LFCSP that
saves space and allows flexible configurations as either serial or
parallel interface. The AD7667 is a pin-to-pin compatible
upgrade of the AD7661/64/66.

CONVERTER OPERATION

The AD7667 is a successive-approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of an array of 16 binary weighted capacitors and an additional
“LSB” capacitor. The comparator’s negative input is connected to a
“dummy” capacitor of the same value as the capacitive DAC
array.

During the acquisition phase, the common terminal of the array
tied to the comparator's positive input is connected to AGND
via SW

A

. All independent switches are connected to the analog
input IN. Thus, the capacitor array is used as a sampling capaci­tor and acquires the analog signal on IN input. Similarly, the
“dummy” capacitor acquires the analog signal on INGND input.

When the CNVST input goes low, a conversion phase is initi­ated. When the conversion phase begins, SW

A

and SWB are
opened first. The capacitor array and the “dummy” capacitor are
then disconnected from the inputs and connected to the REF­GND input. Therefore, the differential voltage between IN and
INGND captured at the end of the acquisition phase is applied
to the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between REFGND or REF, the comparator input varies by
binary-weighted voltage steps (V

REF

/2, V

REF

/4,...V

REF

/65536).
The control logic toggles these switches, starting with the MSB
first, to bring the comparator back into a balanced condition.

After the completion of this process, the control logic generates
the ADC output code and brings BUSY output low.

Modes of Operation

The AD7667 features three modes of operations, Warp, Normal,
and Impulse. Each of these modes is more suitable for specific
applications.

The Warp mode allows the fastest conversion rate up to 1
MSPS. However, in this mode, and this mode only, the full
specified accuracy is guaranteed only when the time between
conversion does not exceed 1 ms. If the time between two con­secutive conversions is longer than 1 ms, for instance, after
power-up, the first conversion result should be ignored. This
mode makes the AD7667 ideal for applications where both high
accuracy and fast sample rate are required.

The normal mode is the fastest mode (800 kSPS) without any
limitation about the time between conversions. This mode
makes the AD7667 ideal for asynchronous applications such as
data acquisition systems, where both high accuracy and fast
sample rate are required.

The impulse mode, the lowest power dissipation mode, allows
power saving between conversions. When operating at 100 SPS,
for example, it typically consumes only 15 µW. This feature
makes the AD7667 ideal for battery-powered applications.

Transfer Functions

Using the OB/2C digital input, the AD7667 offers two output
codings: straight binary and two’s complement. The LSB size is
V

REF

/65536, which is about 38.15 µV. The ideal transfer charac-

teristic for the AD7667 is shown in Figure 4 and Table I.

000...000

000...001

000...010

111...101

111...110

111...111

ADC CODE › Straight Binary

ANALOG INPUT

V

REF

› 1.5 LSB

V

REF

› 1 LSB

1 LSB0V

0.5 LSB

1 LSB = V

REF

/65536

Figure 4. ADC Ideal Transfer Function

SW

A

COMP

SW

B

IN

REF

REFGND

LSB

MSB

32,768C

INGND

16,384C 4C 2C C C

65,536C

CONTROL

LOGIC

SWITCHES

CONTROL

BUSY

OUTPUT

CODE

CNVST

Figure 3. ADC Simplified Schematic

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–13–

Table I. Output Codes and Ideal Input Voltages

Digital Output Code

Hexa

Analog Straight Two’s

D

escription Input Binary Comple-

ment

FSR –1 LSB 2.499962 V FFFF

1

7FFF

1

FSR – 2 LSB 2.499923 V FFFE 7FFE
Midscale + 1 LSB 1.250038 V 8001 0001
Midscale 1.25 V 8000 0000
Midscale – 1 LSB 1.249962 V 7FFF FFFF
–FSR + 1 LSB 38 µV 0001 8001
–FSR 0 V 0000

2

8000

2

NOTES

1

This is also the code for overrange analog input (VIN – V

INGND

above

V

REF

– V

REFGND

).

2

This is also the code for underrange analog input (VIN below V

INGND

).

TYPICAL CONNECTION DIAGRAM

Figure 5 shows a typical connection diagram for the AD7667.

Analog Input

Figure 6 shows an equivalent circuit of the input structure of
the AD7667.

C2

R1

D1

D2

C1

IN

OR INGND

AGND

AVDD

Figure 6. Equivalent Analog Input Circuit

The two diodes D1 and D2 provide ESD protection for
the analog inputs IN and INGND. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 0.3 V. This will cause these diodes to
become forward-biased and start conducting current.
These diodes can handle a forward-biased current of 100
mA maximum. For instance, these conditions could eventu­ally occur when the input buffer’s (U1) supplies are

100nF10F 100nF 10F

AVDD

10F 100nF

AGND DGND DVDD OVDD OGND

WARP

IMPULSE

SER/PAR

CNVST

BUSY

SDOUT

SCLK

RDCSRESET

PD

IN

INGND

REFGND

REF

100

D

3

CLOCK

AD7667

ANALOG INPUT

(0V TO 2.5V)

C/P/DSP

SERIAL

PORT

DIGITAL SUPPLY
(3.3V OR 5V)

ANALOG

SUPPLY

(5V)

NOTES:

1

THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER

2

THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.

3

OPTIONAL LOW JITTER CNVST.

DVDD

C

C

OB/2C

2.7nF

U1

2

15

PDBUFPDREF

REFBUFIN

1

47F

100 nF

BYTESWAP

Figure 5. Typical Connection Diagram

REV. PrA

PRELIMINARY TECHNICAL DATA

–14–

AD7667

different from AVDD. In such case, an input buffer with a
short circuit current limitation can be used to protect the
part.

This analog input structure allows the sampling of the
differential signal between IN and INGND. Unlike other
converters, the INGND input is sampled at the same time as
the IN input. By using this differential input, small signals
common to both inputs are rejected, as shown in Figure 7,
which represents the typical CMRR over frequency. For in­stance, by using INGND to sense a remote signal ground,
difference of ground potentials between the sensor and the
local ADC ground are eliminated.

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

Figure 7. Analog Input CMR vs. Frequency

During the acquisition phase, the impedance of the analog
input IN can be modeled as a parallel combination of ca­pacitor C1 and the network formed by the series connection
of R1 and C2. Capacitor C1 is primarily the pin capacitance.
The resistor R1 is typically 183  and is a lumped compo-
nent made up of some serial resistors and the on resistance of
the switches. The capacitor C2 is typically 60 pF and is mainly
the ADC sampling capacitor. During the conversion phase, where
the switches are opened, the input impedance is limited to C1. Th e
R1, C2 makes a one-pole low-pass filter that reduces undesir­able aliasing effect and limits the noise.

When the source impedance of the driving circuit is low,
the AD7667 can be driven directly. Large source imped­ances will significantly affect the ac performances,
especially the total harmonic distortion. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD degrades
in function of the source impedance and the maximum input
frequency as shown in Figure TBD.

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

Figure 8. THD vs. Analog Input Frequency and

Source Resistance

Driver Amplifier Choice

Although the AD7667 is easy to drive, the driver amplifier
needs to meet at least the following requirements:

−

The driver amplifier and the AD7667 analog input circuit
must be able together to settle for a full-scale step the capaci­tor array at a 16-bit level (0.0015%). In the amplifier’s data
sheet, the settling at 0.1% to 0.01% is more commonly speci­fied. It could significantly differ from the settling time at 16
bit level and it should therefore be verified prior to the
driver selection. The tiny op amp AD8021, which com­bines ultralow noise and a high-gain bandwidth, meets
this settling time requirement even when used with high
gain up to 13.

−

The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7667. The noise
coming from the driver is filtered by the AD7667 analog
input circuit one-pole low-pass filter made by R1 and C2
or the external filter if any is used. The SNR degredation
due to the amplifier is:

 f

-3dB

( N eN

)

2

2

784 +

(

)

28

SNR

LOSS

= 20 LOG

where
f

–3dB

is the –3 dB input bandwidth of the AD7667 in MHz
(14.5) or the cutoff frequency of the input filter if
any used.

N is the noise gain of the amplifier (1 if in buffer

configuration).

e

N

is the equivalent input noise voltage of the op amp
in nV/
(Hz)

1/2

.

For instance, a driver like the AD8021, with an equivalent
input noise of 2 nV/ Hz and configured as a buffer, thus with
a noise gain of 1, the SNR degrades by only 0.13 dB with the
filter used in figure 5.

−

The driver needs to have a THD performance suitable to that
of the AD7667.

The AD8021 meets these requirements and is usually appro­priate for almost all applications. The AD8021 needs an
external compensation capacitor of 10 pF. This capacitor
should have good linearity as an NPO ceramic or mica type.

The AD8022 could also be used where dual version is needed
and gain of 1 is used.

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–15–

The AD829 is another alternative where high-frequency
(above 100 kHz) performance is not required. In gain of
1, it requires an 82 pF compensation capacitor.

The AD8610 is another option where low bias current is
needed in low-frequency applications.

Voltage Reference Input

The AD7667 allows the choice of either an internal 2.5 V
voltage reference or an external 2.5 V reference.

To use the internal reference along with the internal buffer,
PDREF and PDBUF should both be LOW. This will pro­duce a voltage on REFBUFIN of 1.25 V and the buffer’s
gain will be 2, resulting in a 2.5 V reference on REF pin.

To use an external reference along with the internal
buffer, PDREF should be HIGH and PDBUF should be
LOW. This powers down the internal reference and allows
for the 2.5 V reference to be applied to REFBUFIN. In
this mode the buffer’s gain is 1.

To use both external reference, PDREF and PDBUF
should both be HIGH. The reference input should be
applied to REF.

It is useful to decouple the REFBUFIN pin with a 100

nF

ceramic capacitor.

The output impedance of the REFBUFIN

pin is 4 k

. Thus, the 100

nF capacitor provides an RC filter

for noise reduction.
It should be noted that the internal reference and internal

buffer are independent of the power down (PD) pin of the
part. Powering down the part does not power down the inter­nal reference or the internal buffer. Furthermore, powering
down the internal reference and internal buffer, as well as
powering them up, requires time. This is due to the fact that
we have charging and discharging capacitors on the REF
which require some settling time. Therefore, for applications
requiring low power, there will always be a typical of 10 mW
of power dissipated when using the internal reference and
internal buffer even during times with no conversions.

The internal reference is temperature compensated to

2.5V ± TBD mV.

The reference is trimmed to provide
a typical drift of TBD ppm/C. This typical drift char­acteristic is shown in Figure TBD. For improved drift
performance, an external reference such as the AD780
can be used

.

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

Figure TBD

For the external reference, the voltage reference input REF
of the AD7667 has a dynamic input impedance; it should
therefore be driven by a low-impedance source with an
efficient decoupling between REF and REFGND inputs.
This decoupling depends on the choice

of the voltage refer-

ence but usually consists of a 1 µF

ceramic capacitor and a
low ESR tantalum capacitor connected to the REF and
REFGND inputs with minimum parasitic inductance. 47
µF is an appropriate value for the tantalum capacitor when
using either the internal reference of one of the recom­mended reference voltages:

− The low noise, low temperature drift ADR421 and

AD780 voltage references

− The low power ADR291 voltage reference

− The low cost AD1582 voltage reference

For applications using multiple AD7667s, it is more effective
to buffer the reference voltage using the internal buffer. To
do so, PDREF should be HIGH, and PDBUF should be low.

Care should also be taken with the reference temperature
coefficient of the voltage reference which directly affects the
full-scale accuracy if this parameter matters. For instance, a
±15 ppm/°C tempco of the reference changes the full scale by
±1 LSB/°C.

V

REF

, as mentioned in the specification table, could be increased
to AVDD – 1.85 V. The benefit here is the increased SNR
obtained as a result of this increase. Since the input range is
defined in terms of V

REF

, this would essentially increase the

range to make it a 0 to 3 V input range with an AVDD above

4.85 V. One of the benefits here is the additional SNR ob­tained as a result of this increase. The theoretical
improvement as a result of this increase in reference is 1.58
dB (20 log [3/2.5]). Due to the theoretical quantization
noise, however, the observed improvement is approximately
1 dB. The AD780 can be selected with a 3 V reference
voltage.

The TEMP pin, which measures the temperature of the
AD7667, can be used as follows. Refer to figure TBD to
see the connectivity. The output of the TEMP pin is ap­plied to one of the inputs of the analog switch (ADG779).
The other input, as shown is the analog signal. The output
of the switch is connected to the AD8021 which is config­ured as a follower. The output of the op-amp is applied to
the IN pin. Refer to the Specification Table for the appro­priate values related to the TEMP pin. This configuration
could be very useful to improve the calibration accuracy
over the temperature range.

C

C

AD8021

IN

AD7667

ANALOG INPUT

(UNIPOLAR)

IN

temperature
sensor

ADG779

TEMP

REV. PrA

PRELIMINARY TECHNICAL DATA

–16–

AD7667

Figure TBD

Power Supply

The AD7667 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.7 V and
DVDD + 0.3 V. To reduce the number of supplies needed,
the digital core (DVDD) can be supplied through a simple
RC filter from the analog supply as shown in Figure 5. The
AD7667 is independent of power supply sequencing, once
OVDD does not exceed DVDD by more than 0.3V, and thus
free from supply voltage induced latchup.

POWER DISSIPATION Vs. THROUGHPUT

Operating currents are very low during the acquisition phase,
which

allows a significant power saving when the conversion rate

is reduced

as shown in Figure 10. This power saving depends on
the mode used. In impulse mode, the AD7667 automatically
reduces its power consumption at the end of each conversion
phase. This feature makes the AD7667 ideal for very low power
battery applications. It should be noted that the digital interface
remains active even during the acquisition phase. To reduce the
operating digital supply currents even further, the digital inputs
need to be driven

close to the power supply rails (i.e., DVDD or

DGND

) and OVDD should not exceed DVDD by more than

0.3V.

-160

-140

-120

-100

-80

-60

-40

-20

0

1

TO BE

SUPPLIED

Figure 10. Power Dissipation vs. Sample Rate

CONVERSION CONTROL

Figure 11 shows the detailed timing diagrams of the conver­sion process. The AD7667 is controlled by the signal CNVST
which initiates conversion. Once initiated, it cannot be
restarted or aborted, even by the power-down input PD, until
the conversion is complete. The CNVST signal operates
independently of CS and RD signals.

CNVST

BUSY

MODE

t

2

t

1

t

3

t

4

t

5

t

6

t

7

t

8

ACQUIRE CONVERT ACQUIRE CONVERT

Figure 11. Basic Conversion Timing

In impulse mode, conversions can be automatically initi­ated. If CNVST is held low when BUSY is low, the
AD7667 controls the acquisition phase and then automati­cally initiates a new conversion. By keeping CNVST low,
the AD7667 keeps the conversion process running by itself.
It should be noted that the analog input has to be settled
when BUSY goes low. Also, at power-up, CNVST
should be brought low once to initiate the conversion pro­cess. In this mode, the AD7667 could sometimes run
slightly faster then the guaranteed limits in the impulse mode
of 666 kSPS. This feature does not exist in warp or normal
modes.

t

9

t

8

RESET

DATA

BUSY

CNVST

Figure 12. RESET Timing

Although CNVST is a digital signal, it should be de­signed with special care with fast, clean edges, and levels
with minimum overshoot and undershoot or ringing.

It is a good thing to shield the CNVST trace with ground and
also to add a low value serial resistor (i.e., 50 ) termination
close to the output of the component that drives this line.

For applications where the SNR is critical, CNVST signal
should have a very low jitter. Some solutions to achieve that is
to use a dedicated oscillator for CNVST generation or, at least,
to clock it with a high-frequency low-jitter clock as shown in
Figure 5.

DIGITAL INTERFACE

The AD7667 has a versatile digital interface; it can be
interfaced with the host system by using either a serial or

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–17–

parallel interface. The serial interface is multiplexed on
the parallel data bus. The AD7667 digital interface also
accommodates both 3 V or 5 V logic by simply connecting
the OVDD supply pin of the AD7667 to the host system
interface digital supply. Finally, by using the OB/2C in­put pin, both two’s complement or straight binary coding
can be used.

The two signals CS and RD control the interface. CS and RD
have a similar effect because they are OR’d together inter­nally. When at least one of these signals is high, the interface
outputs are in high impedance. Usually, CS allows the selec­tion of each AD7667 in multicircuits applications and is held

low in a single AD7667 design. RD is generally used to
enable the conversion result on the data bus.

t

3

BUSY

CS, RD

CNVST

SYNC

SCLK

SDOUT

t

28

t

29

t

14

t

18

t

19

t

20

t

21

t

24

t

26

t

27

t

23

t

22

t

16

t

15

1 2 3 14 15 16

D15 D14 D2 D1 D0

X

EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0

t

25

t

30

Figure 16. Master Serial Data Timing for Reading (Read After Convert)

EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0

t

3

t

1

t

17

t

14

t

19

t

20

t

21

t

24

t

26

t

25

t

27

t

23

t

22

t

16

t

15

D15 D14 D2 D1 D0X

123 141516

t

18

BUSY

CS, RD

CNVST

SYNC

SCLK

SDOUT

Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)

REV. PrA

PRELIMINARY TECHNICAL DATA

–18–

AD7667

t

1

t

3

t

4

t

11

CNVST

BUSY

DATA

BUS

CS = RD = 0

t

10

PREVIOUS CONVERSION DATA NEW DATA

Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)

PARALLEL INTERFACE

The AD7667 is configured to use the parallel interface when
the SER/PAR is held low. The data can be read either after
each conversion, which is during the next acquisition phase,
or during the following conversion as shown, respectively, in
Figure 14 and Figure 15. When the data is read during the
conversion, however, it is recommended that it is read only
during the first half of the conversion phase. That avoids
any potential feedthrough between voltage transients on the
digital interface and the most critical analog conversion cir­cuitry.

CURRENT

CONVERSION

BUSY

DATA

BUS

CS

RD

t

12

t

13

Figure 14. Slave Parallel Data Timing for Reading
(Read After Convert)

The BYTESWAP pin allows a glueless interface to a 8 bits
bus. As shown in Figure TBD, the LSB byte is output on
D[7:0] and the MSB is output on D[15:8] when
BYTESWAP is low. When BYTESWAP is high, the LSB and
MSB bytes are swapped and the LSB is output on D[15:8]
and the MSB is output on D[7:0]. By connecting
BYTESWAP to an address line, the 16 bits data can be read
in 2 bytes on either D[15:8] or D[7:0].

SCLK

SDOUT

D15 D14 D1 D0D13

X15 X14 X13 X1 X0 Y15 Y14

CS

BUSY

SDIN

EXT/INT = 1 INVSCLK = 0

t

35

t

36

t

37

t

31

t

32

t

16

t

33

t

34

X15 X14

X

1 2 3 1415161718

RD = 0

Figure 18. Slave Serial Data Timing for Reading (Read After Convert)

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–19–

CS

BYTE

Pins D[15:8]

HI-Z

HIGH BYTE LOW BYTE

HI-Z

HI-Z

HIGH BYTELOW BYTE

HI-Z

t

12

t

12

t

13

Pins D[7:0]

RD

Figure TBD, 8-bit Parallel Interface

t

1

t

3

t

4

CS = 0

CNVST

,

RD

BUSY

PREVIOUS

CONVERSION

t

12

t

13

DATA

BUS

Figure 15. Slave Parallel Data Timing for Reading
(Read During Convert)

SERIAL INTERFACE

The AD7667 is configured to use the serial interface when
the SER/PAR is held high. The AD7667 outputs 16 bits of
data, MSB first, on the SDOUT pin. This data is synchro­nized with the 16 clock pulses provided on SCLK pin. The
output data is valid on both the rising and falling edge of the
data clock.

MASTER SERIAL INTERFACE
Internal Clock

The AD7667 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7667 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on RDC/
SDIN input, the data can be read after each conversion or
during the following conversion. Figure 16 and Figure 17
show the detailed timing diagrams of these two modes.

Usually, because the AD7667 is used with a fast throughput,
the mode master, read during conversion is the most recom­mended serial mode when it can be used.

In read-during-conversion mode, the serial clock and data
toggle at appropriate instants which minimize potential
feedthrough between digital activity and the critical conver­sion decisions.

In read-after-conversion mode, it should be noted that, unlike in
other modes, the signal BUSY returns low after the 16 data bits
are pulsed out and not at the end of the conversion phase which
results in a longer BUSY width.

SLAVE SERIAL INTERFACE

External Clock

The AD7667 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS. When CS and
RD are both low, the data can be read after each conversion
or during the following conversion. The external clock can be
either a continuous or discontinuous clock. A discontinuous
clock can be either normally high or normally low when inac­tive. Figure 18 and Figure 20 show the detailed timing diagrams
of these methods.

While the AD7667 is performing a bit decision, it is impor­tant that voltage transients not occur on digital input/output
pins or degradation of the conversion result could occur.
This is particularly important during the second half of the
conversion phase because the AD7667 provides error cor­rection circuitry that can correct for an improper bit

SDOUT

CS

SCLK

D1 D0X D15 D14 D13

1 2 3 141516

t

3

t

35

t

36

t

37

t

31

t

32

t

16

CNVST

BUSY

EXT/INT = 1 INVSCLK = 0

RD = 0

Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)

REV. PrA

PRELIMINARY TECHNICAL DATA

–20–

AD7667

decision made during the first half of the conversion
phase. For this reason, it is recommended that when an
external clock is being provided, it is a discontinuous
clock that is toggling only when BUSY is low or, more
importantly, that it does not transition during the latter
half of BUSY high.

External Discontinuous Clock Data Read After Conver­sion

Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave
modes. Figure 18 shows the detailed timing diagrams of this
method. After a conversion is complete, indicated by BUSY
returning low, the result of this conversion can be read while
both CS and RD are low. The data is shifted out, MSB first,
with 16 clock pulses and is valid on both rising and falling
edge of the clock.

Among the advantages of this method, the conversion perfor­mance is not degraded because there are no voltage transients
on the digital interface during the conversion process.

Another advantage is to be able to read the data at any speed
up to 40 MHz which accommodates both slow digital host
interface and the fastest serial reading.

Finally, in this mode only, the AD7667 provides a “daisy­chain” feature using the RDC/SDIN input pin for cascading
multiple converters together. This feature is useful for reducing
component count and wiring connections when desired as, for
instance, in isolated multiconverter applications.

An example of the concatenation of two devices is shown in
Figure 19. Simultaneous sampling is possible by using a com­mon CNVST signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite to the one used to
shift out the data on SDOUT. Hence, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter
on the next SCLK cycle.

CNVST

CS

SCLK

SDOUTRDC/SDIN

BUSYBUSY

DATA
OUT

AD7667

#1

(DOWNSTREAM)

BUSY
OUT

CNVST

CS

SCLK

AD7667

#2

(UPSTREAM)

RDC/SDIN SDOUT

SCLK IN

CS IN

CNVST IN

Figure 19. Two AD7667s in a “Daisy-Chain” Configuration

External Clock Data Read During Conversion

Figure 20 shows the detailed timing diagrams of this
method. During a conversion, while both CS and RD are
both low, the result of the previous conversion can be read.
The data is shifted out, MSB first, with 16 clock pulses and is

valid on both rising and falling edge of the clock. The 16
bits have to be read before the current conversion is com­plete. If that is not done, RDERROR is pulsed high and
can be used to interrupt the host interface to prevent
incomplete data reading. There is no “daisy chain”
feature in this mode and RDC/SDIN input should al­ways be tied either high or low.

To reduce performance degradation due to digital activity, a
fast discontinuous clock of, at least 25 MHz, when impulse mode is
used, 32 MHz when normal mode is used or 40 MHz when
warp mode is used, is recommended to ensure th at a l l the bits
are read during the first half of the conversion phase. It is
also possible to begin to read the data after conversion and
continue to read the last bits even after a new conversion has
been initiated. That allows the use of a slower clock speed like
18 MHz in impulse mode, 21 MHz in normal mode and 26
MHz in warp mode.

MICROPROCESSOR INTERFACING

The AD7667 is ideally suited for traditional dc measure­me nt applications supporting a microprocessor, and ac signal
processing applications interfacing to a digital signal processor.
The AD7667 is designed to interface either with a parallel 16­bit-wide interface or with a general-purpose serial port or I/O
ports on a microcontroller. A variety of external buffers can be
used with the AD7667 to prevent digital noise from coupling
into the ADC. The following sections illustrate the use of the
AD7667 with an SPI-equipped microcontroller, the ADSP­21065L and ADSP-218x signal processors.

SPI Interface (MC68HC11)

Figure 21 shows an interface diagram between the AD7667
and an SPI-equipped microcontroller like the MC68HC11. To
accommodate the slower speed of the microcontroller, the
AD7667 acts as a slave device and data must be read after
conversion. This mode allows also the “daisy chain” feature.

The convert command could be initiated in response to
an internal timer interrupt. The reading of output data,
one byte at a time, if necessary, could be initiated in
response to the end-of-conversion signal (BUSY going
low) using to an interrupt line of the microcontroller. The
Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), Clock Polar­ity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and
SPI Interrupt Enable (SPIE = 1) by writing to the SPI Con­trol Register (SPCR). The IRQ is configured for
edge-sensitive-only operation (IRQE = 1 in OPTION
register).

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–21–

IRQ

MC68HC11*

CNVST

AD7667*

CS

BUSY

MISO/SDI
SCK
I/O PORT

SDOUT

SCLKRD

INVSCLK

EXT/INT

SER/PAR

DVDD

*ADDITIONAL PINS OMITTED FOR CLARITY

DVDD

Figure 21. Interfacing the AD7667 to SPI Interface

ADSP-21065L in Master Serial Interface

As shown in Figure 22, the AD7667 can be interfaced to
the ADSP-21065L using the serial interface in master mode
without any glue logic required. This mode combines the
advantages of reducing the number of wire connections and
being able to read the data during or after conversion at user
convenience.

The AD7667 is configured for the internal clock mode (EXT/
INT low) and acts, therefore, as the master device. The con­vert command can be generated by either an external low
jitter oscillator or, as shown, by a FLAG output of the ADSP­21065L or by a frame output TFS of one serial port of the
ADSP-21065L which can be used as a timer. The serial port
on the ADSP-21065L is configured for external clock (IRFS
= 0), rising edge active (CKRE = 1), external late framed
sync signals (IRFS = 0, LAFS = 1, RFSR = 1) and active
high (LRFS = 0). The serial port of the ADSP-21065L is
configured by writing to its receive control register
(SRCTL)—see ADSP-2106x SHARC User’s Manual. Be­cause the serial port within the ADSP-21065L will be seeing a
discontinuous clock, an initial word reading has to be done after
the ADSP-21065L has been reset to ensure that the serial
port is properly synchronized to this clock during each follow­ing data read operation.

RFS

ADSP-21065L*

SHARC

CNVST

AD7667*

CS

SYNC

RD

DR
RCLK
FLAG OR TFS

SDOUT

SCLKINVSYNC

INVSCLK

EXT/INT

RDC/SDIN

SER/PAR

DVDD

*

ADDITIONAL PINS OMITTED FOR CLARITY

DVDD

Figure 22. Interfacing to the ADSP-21065L Using the
Serial Master Mode

APPLICATION HINTS
Bipolar and Wider Input Ranges

In some applications, it is desired to use a bipolar or wider
ana log input range like, for instance, ±10 V, ±5 V or 0 V to 5 V.
Although the AD7667 has only one unipolar range, by simple
modifications of the input driver circuitry, bipolar and wider
input ranges can be used without any performance degradation.

Figure 23 shows a connection diagram which allows
that. Components values required and resulting full­scale ranges are shown in Table II.

For applications where accurate gain and offset are de­sired, they can be calibrated by acquiring a ground and a
voltage reference using an analog multiplexer, U2, as
shown for bipolar input ranges in Figure 23.

U1

ANALOG

INPUT

R2

R3

R4

100nF

R1

C

F

U2

C

REF

IN

INGND
REF

REFGND

100nF

AD7667

Figure 23. Using the AD7667 in 16-Bit Bipolar and/or
Wider Input Ranges

Table II. Component Values and Input Ranges

Input Range R1 R2 R3 R4

±10 V 250  2 k 10 k 8 k
±5 V 500  2 k 10 k 6.67 k

0 V to –5 V 1 k 2 k None 0 

Layout

The AD7667 has very good immunity to noise on the
power supplies as can be seen in Figure 9. However, care
should still be taken with regard to grounding layout.

The printed circuit board that houses the AD7667 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use
of ground planes that can be easily separated. Digital and
analog ground planes should be joined in only one place,
preferably underneath the AD7667, or, at least, as close as
possible to the AD7667. If the AD7667 is in a system where
multiple devices require analog-to-digital ground connections,
the connection should still be made at one point only, a star
ground point, which should be established as close as possible
to the AD7667.

It is recommended to avoid running digital lines under
the device as these will couple noise onto the die. The ana­log ground plane should be allowed to run under the
AD7667 to avoid noise coupling. Fast switching signals
like CNVST or clocks should be shielded with digital
ground to avoid radiating noise to other sections of the
board, and should never run near analog signal paths.
Crossover of digital and analog signals should be avoided.
Traces on different but close layers of the board should run

REV. PrA

PRELIMINARY TECHNICAL DATA

–22–

AD7667

at right angles to each other. This will reduce the effect of
feedthrough through the board.

The power supplies lines to the AD7667 should use as
large trace as possible to provide low impedance paths and
reduce the effect of glitches on the power supplies lines.
Good decoupling is also important to lower the supplies
impedance presented to the AD7667 and reduce the magni­tude of the supply spikes. Decoupling ceramic capacitors,
typically 100 nF, should be placed on each power supplies
pins AVDD, DVDD, and OVDD close to, and ideally right
up against, these pins and their corresponding ground pins.
Additionally, low ESR 10 µF capacitors should be located in
the vicinity of the ADC to further reduce low frequency
ripple.

The DVDD supply of the AD7667 can be either a separate
supply or come from the analog supply AVDD or the digi­tal interface supply OVDD. When the system digital supply
is noisy, or fast switching digital signals are present, it is
recommended that if no separate supply available, connect
the DVDD digital supply to the analog supply, AVDD,
through an RC filter as shown in Figure 5, and connect
the system supply to the interface digital supply, OVDD,
and the remaining digital circuitry. When DVDD is powered
from the system supply, it is useful to insert a bead to fur­ther reduce high-frequency spikes.

The AD7667 has five different ground pins: INGND, REF­GND, AGND, DGND, and OGND. INGND is used to
sense the analo g input signal. REFGND senses the refer­ence voltage and should be a low impedance return to the
reference because it carries pulsed currents. AGND is the
ground to which most internal ADC analog signals are
referenced. This ground must be connected with the least
resistance to the analog ground plane. DGND must be
tied to the analog or digital ground plane depending on the
configuration. OGND is connected to the digital system
ground.

Evaluating the AD7667 Performance

A recommended layout for the AD7667 is outlined in the
evaluation board for the AD7667. The evaluation board
package includes a fully assembled and tested evaluation
board, documentation, and software for controlling the board
from a PC via the Eval-Control Board.

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–23–

48-Lead Quad Flatpack (LQFP)

(ST-48)

TOP VIEW

(PINS DOWN)

1

12

13

25

24

36

37

48

0.019 (0.5)
BSC

0.276
(7.00)

BSC

SQ

0.011 (0.27)

0.006 (0.17)

0.354 (9.00) BSC SQ

0.063 (1.60)
MAX

0.030 (0.75)

0.018 (0.45)

0.008 (0.2)

0.004 (0.09)

0
MIN

COPLANARITY

0.003 (0.08)

SEATING
PLANE

0.006 (0.15)

0.002

(

0.05

)

7
0

0.057 (1.45)

0.053 (1.35)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

PIN 1
INDICATOR

TOP

VIEW

0.266 (6.75)
BSC SQ

0.276 (7.0)
BSC SQ

1

48

12

13

37

36

24

25

BOTTOM

VIEW

0.215 (5.45)

0.209 (5.30) SQ

0.203 (5.15)

0.024 (0.60)

0.017 (0.42)

0.009 (0.24)

0.024 (0.60)

0.017 (0.42)

0.009 (0.24)

0.020 (0.50)

0.016 (0.40)

0.012 (0.30)

0.012 (0.30)

0.009 (0.23)

0.007 (0.18)

0.020 (0.50)
BSC

0.031 (0.80) MAX

0.026 (0.65) NOM

12 MAX

0.039 (1.00) MAX

0.033 (0.85) NOM

0.008 (0.20)
REF

0.002 (0.05)

0.0004 (0.01)

0.0 (0.0)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS

Pad Connected to AGND

48-Lead Frame Chip Scale Package (LQFP)

(CP-48)