Datasheet AD7666 Datasheet (Analog Devices)

16-Bit 500 kSPS PulSAR

®

FEATURES

2.5 V internal reference: typical drift 3 ppm/°C
Guaranteed max drift 15 ppm/°C

Throughput: 500 kSPS
INL: ±2.0 LSB max (±0.0038% of full scale)
16-bit resolution with no missing codes
S/(N+D): 88 dB min @ 20 kHz
THD: –96 dB max @ 20 kHz
Analog input voltage range: 0 V to 2.5 V
Both AC and DC specifications
No pipeline delay
Parallel and serial 5 V/3 V interface

TM

®/QSPI

SPI
Single 5 V supply operation
Power dissipation

66 mW typ, 132 µW @ 1 kSPS without REF
81 mW typ with REF

48-lead LQFP and 48-lead LFCSP packages
Pin-to-pin compatible with PulSAR ADCs

APPLICATIONS

Data acquisition
Medical instruments
Digital signal processing
Spectrum analysis
Instrumentation
Battery-powered systems
Process control

GENERAL DESCRIPTION

The AD7666* is a 16-bit, 500 kSPS, charge redistribution SAR
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high speed, 16-bit sampling
ADC, an internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system inter­face ports. The AD7666 is hardware factory-calibrated and
comprehensively tested to ensure ac parameters such as signal­to-noise ratio (SNR) and total harmonic distortion (THD), in
addition to the more traditional dc parameters of gain, offset,
and linearity.

The AD7666 is available in a 48-lead LQFP and a tiny 48-lead
LFCSP, with operation specified from –40°C to +85°C.

*

Patent Pending.

/MICROWIRETM/DSP compatible

Unipolar ADC with Reference

AD7666

FUNCTIONAL BLOCK DIAGRAM

AGND
AVDD

INGND

PDREF
PDBUF

RESET

REFBUFIN

REF

IN

PD

REF REFGND

AD7666

SWITCHED

CAP DAC

CLOCK

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

CNVST

Figure 1. Functional Block Diagram

Table 1. PulSAR Selection

Type/kSPS 100–250 500–570

Pseudo­Differential

AD7651

AD7660/AD7661

True Bipolar AD7663 AD7665 AD7671
True

AD7675 AD7676 AD7677

Differential
18-Bit AD7678 AD7679 AD7674
Multichannel/

Simultaneous

PRODUCT HIGHLIGHTS

1. Fast Throughput.

The AD7666 is a 500 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.

2. Superior INL.

The AD7666 has a maximum integral nonlinearity of

2.0 LSB with no missing 16-bit codes.

3. Internal Reference.

The AD7666 has an internal reference with a typical
temperature drift of 3 ppm/°C.

4. Single-Supply Operation.

The AD7666 operates from a single 5 V supply. Its power
dissipation decreases with throughput.

5. Serial or Parallel Interface.

Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V and 5 V logic.

DGNDDVDD

SERIAL

PORT

16

PARALLEL

INTERFACE

AD7650/AD7652
AD7664/AD7666

AD7654
AD7655

OVDD
OGND

DATA[15:0]
BUSY
RD
CS
SER/PAR
OB/2C
BYTESWAP

800–
1000

AD7653
AD7667

03034-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD7666

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Definitions of Specifications......................................................... 11

Typical Performance Characteristics........................................... 12

Circuit Information........................................................................ 16

Converter Operation.................................................................. 16

Typical C onnection Diagram ................................................... 18

Power Dissipation versus Throughput.................................... 20

Conversion Control....................................................................21

REVISION HISTORY

Revision 0: Initial Version

Digital Interface.......................................................................... 22

Parallel Interface ......................................................................... 22

Serial Interface............................................................................ 22

Master Serial Interface............................................................... 23

Slave Serial Interface .................................................................. 24

Microprocessor Interfacing....................................................... 26

Application Hints ........................................................................... 27

Bipolar and Wider Input Ranges.............................................. 27

Layout .......................................................................................... 27

Evaluating the AD7666’s Performance.................................... 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

AD7666

SPECIFICATIONS

Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted

Parameter Conditions Min Typ Max Unit

RESOLUTION 16 Bits
ANALOG INPUT

Voltage Range VIN – V
Operating Input Voltage VIN –0.1 +3 V

V

INGND

Analog Input CMRR fIN = 10 kHz 65 dB
Input Current 500 kSPS Throughput 7.7 µA
Input Impedance1

THROUGHPUT SPEED

Complete Cycle 2 µs
Throughput Rate 0 500 kSPS

DC ACCURACY

Integral Linearity Error –2.0 +2.0 LSB2
No Missing Codes 16 Bits
Differential Linearity Error –1.0 +1.5 LSB
Transition Noise 0.7 LSB
Unipolar Zero Error, T

MIN

3

to T

±5 LSB

MAX

Unipolar Zero Error Temperature Drift ±0.5 ppm/°C
Full-Scale Error, T

MIN

to T

3

REF = 2.5 V ±0.08 % of FSR

MAX

Full-Scale Error Temperature Drift ±1.4 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±2 LSB

AC ACCURACY

Signal-to-Noise fIN = 20 kHz 88 89.2 dB4
Spurious Free Dynamic Range fIN = 20 kHz 96 107 dB
Total Harmonic Distortion fIN = 20 kHz –106 –96 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz 88 89.1 dB

–60 dB Input, fIN = 20 kHz 30 dB

–3 dB Input Bandwidth 12 MHz

SAMPLING DYNAMICS

Aperture Delay 2 ns
Aperture Jitter 5 ps rms

Transient Response Full-Scale Step 750 ns

REFERENCE

Internal Reference Voltage V

REF

Internal Reference Temperature Drift –40°C to +85°C ±3 ±15 ppm/°C
Output Voltage Hysteresis –40°C to +85°C 50 ppm
Long Term Drift 100 ppm/1000 Hours
Line Regulation AVDD = 5 V ± 5% ±15 ppm/V
Turn-On Settling Time C

REF

Temperature Pin

Voltage Output @ 25°C 300 mV

Temperature Sensitivity 1 mV/°C
Output Resistance 4 kΩ
External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 500 kSPS Throughput 120 µA

0 V

INGND

V

REF

–0.1 +0.5 V

@ 25°C 2.493 2.5 2.507 V

= 10 µF 5 ms

Rev. 0 | Page 3 of 28

AD7666

Parameter Conditions Min Typ Max Unit

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format
Pipeline Delay

V

OL

V

OH

5

6

POWER SUPPLIES

Specified Performance

AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25

Operating Current 500 kSPS Throughput

8

AVDD

9

AVDD

10

DVDD
OVDD10 102 µA

Power Dissipation without REF8, 10 500 kSPS Throughput 66 75 mW

1 kSPS Throughput 132 µW

Power Dissipation with REF8, 10 500 kSPS Throughput 81 90 mW

TEMPERATURE RANGE

11

Specified Performance T

1

See An section. alog Input

2

LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV.

3

See the De section. These specifications do not include the error contribution from the external reference. finitions of Specifications

4

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

5

Parallel or Serial 16-Bit.

6

Conversion results are available immediately after completed conversion.

7

The max should be the minimum of 5.25 V and DVDD + 0.3 V.

8

With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH.

9

With PDREF, PDBUF LOW and PD HIGH.

10

Tested in parallel reading mode.

11

Consult factory for extended temperature range.

–0.3 +0.8 V

2.0 DVDD + 0.3 V
–1 +1 µA
–1 +1 µA

I

= 1.6 mA 0.4 V

SINK

I

= –500 µA OVDD – 0.6 V

SOURCE

7

V

With Reference and Buffer 12.2 mA
Reference and Buffer Alone 3 mA

4.1 mA

MIN

to T

MAX

–40 +85 °C

Rev. 0 | Page 4 of 28

AD7666

TIMING SPECIFICATIONS

Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted

Parameter Symbol Min Typ Max Unit

Refer to Figure 33 and Figure 34

Convert Pulse Width t
Time between Conversions t
CNVST LOW to BUSY HIGH Delay

BUSY HIGH All Modes Except Master Serial Read after Convert t
Aperture Delay t
End of Conversion to BUSY LOW Delay t
Conversion Time t
Acquisition Time t
RESET Pulse Width t

1

2

t

3

4

5

6

7

8

9

Refer to Figure 35, Figure 36, and Figure 37 (Parallel Interface Modes)

CNVST LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay t
Bus Access Request to DATA Valid t
Bus Relinquish Time t

Refer to Figure 39 and Figure 40 (Master Serial Interface Modes)

1

CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay1
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay t
Internal SCLK Period

2

Internal SCLK HIGH2 t
Internal SCLK LOW2 t
SDOUT Valid Setup Time2 t
SDOUT Valid Hold Time2 t
SCLK Last Edge to SYNC Delay2 t
CS HIGH to SYNC HI-Z

CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert2 t
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay t

t

10

11

12

13

t

14

t

15

t

16

t

17

18

t

19

20

21

22

23

24

t

25

t

26

t

27

28

t

29

30

Refer to Figure 41 and Figure 42 (Slave Serial Interface Modes)1

External SCLK Setup Time t
External SCLK Active Edge to SDOUT Delay t
SDIN Setup Time t
SDIN Hold Time t
External SCLK Period t
External SCLK HIGH t
External SCLK LOW t

1

In serial interface mode, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

2

In serial master read during convert mode. See Table 4 for serial master read after convert mode.

31

32

33

34

35

36

37

10 ns
2 µs

35 ns

1.25 µs
2 ns
10 ns

1.25 µs
750 ns
10 ns

1.25 µs
12 ns
45 ns
5 15 ns

10 ns
10 ns
10 ns
525 ns

3 ns
25 40 ns
12 ns
7 ns
4 ns
2 ns
3 ns

10 ns
10 ns
10 ns

See Table 4

1.25 µs
25 ns

5 ns
3 18 ns
5 ns
5 ns
25 ns
10 ns
10 ns

Rev. 0 | Page 5 of 28

AD7666

Table 4. Serial Clock Timings in Master Read after Convert

DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SCLK First Edge Delay Minimum t
Internal SCLK Period Minimum t
Internal SCLK Period Maximum t
Internal SCLK HIGH Minimum t
Internal SCLK LOW Minimum t
SDOUT Valid Setup Time Minimum t
SDOUT Valid Hold Time Minimum t
SCLK Last Edge to SYNC Delay Minimum t
BUSY HIGH Width Maximum t

18

19

19

20

21

22

23

24

24

3 17 17 17 ns
25 50 100 200 ns
40 70 140 280 ns
12 22 50 100 ns
7 21 49 99 ns
4 18 18 18 ns
2 4 30 80 ns
3 55 130 290 ns
2 2.5 3.5 5.75 µs

Rev. 0 | Page 6 of 28

AD7666

ABSOLUTE MAXIMUM RATINGS

Table 5. AD7666 Stress Ratings1

Parameter Rating

IN2, TEMP2, REF, REFBUFIN, INGND,

REFGND to AGND

AVDD + 0.3 V to

AGND – 0.3 V

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V

DVDD to OVDD –0.3 V to +7 V
Digital Inputs –0.3 V to DVDD + 0.3 V
PDREF, PDBUF

3

±20 mA
Internal Power Dissipation4 700 mW
Internal Power Dissipation5 2.5 W
Junction Temperature 150°C
Storage Temperature Range –65°C to +150°C
Lead Temperature Range

300°C

(Soldering 10 sec)

1

Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.

2

See Analog Input section.

3

See the Voltage Reference Input section.

4

Specification is for the device in free air:

48-Lead LQFP; θ

5

Specification is for the device in free air:

48-Lead LFCSP; θ

= 91°C/W, θJC = 30°C/W

JA

= 26°C/W.

JA

1.6mA

TO OUTPUT

PIN

C

L

60pF

*

500µA

*IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD
C

OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.

L

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, SCLK Outputs C

0.8V

t

DELAY

2V

0.8V

Figure 3. Voltage Reference Levels for Timing

I

OL

1.4V

I

OH

03033-0-002

= 10 pF

L

2V

t

DELAY

2V

0.8V

03033-0-003

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this product features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 7 of 28

AD7666

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PDBUF

PDREF

REFBUFIN

TEMP

AVDDINAGND

OVDD

OGND

AGNDNCINGND

DVDD

DGND

D8/SDOUT

48

47 46 45 44 39 38 3743 42 41 40

1

AGND
AVDD

NC

BYTESWAP

OB/2C

NC
NC

SER/PAR

D0

D1
D2/DIVSCLK0
D3/DIVSCLK1

NC = NO CONNECT

10
11
12

2
3
4
5
6
7
8
9

PIN 1
IDENTIFIER

AD7666

TOP VIEW

(Not to Scale)

13 14

15 16 17 18 19 20 21 22 23 24

D4/EXT/INT

D6/INVSCLK

D5/INVSYNC

D7/RDC/SDIN

Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1Description

1, 36,

AGND P Analog Power Ground Pin.

41, 42
2, 44 AVDD P Input Analog Power Pin. Nominally 5 V.
3, 6,

NC No Connect.

7, 40
4 BYTESWAP DI

Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].

5

OB/

2C

DI

Straight Binary/Binary Twos Complement. When OB/
when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift
register.

8

SER/

PAR

DI

Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial
interface mode is selected and some bits of the DATA bus are used as a serial port.

9, 10 D[0:1] DO

Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/
impedance.

11, 12

D[2:3]or
DIVSCLK[0:1]

DI/O

When SER/
When SER/

PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert),

these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that
clocks the data output. In other serial modes, these pins are not used.

13

D4 or
EXT/

INT

DI/O

When SER/
When SER/

PAR is LOW, this output is used as Bit 4 of the parallel port data output bus.

PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing
the internal data clock or an external data clock. With EXT/
on the SCLK output. With EXT/

INT set to a logic HIGH, output data is synchronized to an external

clock signal connected to the SCLK input.

14

D5 or
INVSYNC

DI/O

When SER/
When SER/

PAR is LOW, this output is used as Bit 5 of the parallel port data output bus.

PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC
signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH,
SYNC is active LOW.

15

D6 or
INVSCLK

DI/O

When SER/
When SER/

PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.

PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active
in both master and slave modes.

REFGND

REF

36

AGND

35

CNVST

34

PD

33

RESET

32

CS

31

RD

30

DGND

29

BUSY

28

D15

27

D14

26

D13

25

D12

D9/SCLK

D10/SYNC

D11/RDERROR

03034-0-004

2C is HIGH, the digital output is straight binary;

PAR is HIGH, these outputs are in high

INT tied LOW, the internal clock is selected

Rev. 0 | Page 8 of 28

AD7666

Pin No. Mnemonic Type1Description

16

17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V).
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.
21

22

23

24

25–28 D[12:15] DO

29 BUSY DO

30 DGND P Must Be Tied to Digital Ground.
31

32

33 RESET DI

34 PD DI

35

37 REF AI/O Reference Input Voltage. On-chip reference output voltage.
38 REFGND AI Reference Input Analog Ground.
39 INGND AI Analog Input Ground.

D7 or
RDC/SDIN

D8 or
SDOUT

D9 or
SCLK

D10 or
SYNC

D11 or
RDERROR

RD
CS

CNVST

DI/O

DO

DI/O

DO

DO

DI
DI

DI

When SER/
When SER/
read mode selection input depending on the state of EXT/

When EXT/
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA
with a delay of 16 SCLK periods after the initiation of the read sequence.

When EXT/
is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT
only when the conversion is complete.

When SER/
When SER/
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7666 provides the

conversion result, MSB first, from its internal shift register. The DATA format is determined by the
logic level of OB/
serial mode when EXT/
valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and
valid on the next rising edge.

When SER/
When SER/

depending upon the logic state of the EXT/
updated depends upon the logic state of the INVSCLK pin.

When SER/
When SER/

synchronization for use with the internal data clock (EXT/
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is

valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW
while the SDOUT output is valid.

When SER/
SER/
flag. In slave mode, when a data read is started and not complete when the following conversion is

complete, the current data is lost and RDERROR is pulsed HIGH.
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the

state of SER/
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is

complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.

Read Data. When
Chip Select. When

is also used to gate the external clock.
Reset Input. When set to a logic HIGH, this pin resets the AD7666 and the current conversion, if any,

is aborted. If not used, this pin could be tied to DGND.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are

inhibited after the current one is completed.
Start Conversion. If
on
most appropriate if low sampling jitter is desired. If

complete, the internal sample/hold is put into the hold state and a conversion is immediately
started.

PAR is LOW, this output is used as Bit 7 of the parallel port data output bus.
PAR is HIGH, this input, part of the serial port, is used as either an external data input or a

INT.

INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results

INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data

PAR is LOW, this output is used as Bit 8 of the parallel port data output bus.
PAR is HIGH, this output, part of the serial port, is used as a serial data output

2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In

INT is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and

PAR is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus.
PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,

INT pin. The active edge where the data SDOUT is

PAR is LOW, this output is used as Bit 10 of the parallel port data output bus.
PAR is HIGH, this output, part of the serial port, is used as a digital output frame

INT = logic LOW). When a read sequence is

PAR is LOW, this output is used as Bit 11 of the parallel port data output bus. When

PAR and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read error

PAR.

CS and RD are both LOW, the interface parallel or serial output bus is enabled.

CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS

CNVST is HIGH when the acquisition phase (t8) is complete, the next falling edge

CNVST puts the internal sample/hold into the hold state and initiates a conversion. The mode is

CNVST is LOW when the acquisition phase (t8) is

Rev. 0 | Page 9 of 28

AD7666

Pin No. Mnemonic Type1Description

43 IN AI Primary Analog Input with a Range of 0 V to 2.5 V.
45 TEMP AO Temperature Sensor Voltage Output.
46 REFBUFIN AI/O Reference Input Voltage. The reference output and the reference buffer input.
47 PDREF DI

48 PDBUF DI

1

AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.

This pin allows the choice of internal or external voltage references. When LOW, the on-chip
reference is turned on. When HIGH, the internal reference is switched off and an external reference
must be used.

This pin allows the choice of buffering an internal or external reference with the internal buffer.
When LOW, the buffer is selected. When HIGH, the buffer is switched off.

Rev. 0 | Page 10 of 28

AD7666

DEFINITIONS OF SPECIFICATIONS

Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.

Full-Scale Error

The last transition (from 011…10 to 011…11 in twos
complement coding) should occur for an analog voltage 1½ LSB
below the nominal full scale (2.49994278 V for the 0 V to 2.5 V
range). The full-scale error is the deviation of the actual level of
the last transition from the ideal level.

Unipolar Zero Error

The first transition should occur at a level ½ LSB above analog
ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero
error is the deviation of the actual transition from that point.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.

Effective Number Of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) and is expressed in bits by the
following formula:

ENOB = (S/[N+D]dB – 1.76)/6.02

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (S/[N+D])

S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.

Aperture Delay

Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the

CNVST

input to when

the input signal is held for a conversion.

Transient Response

Transient response is the time required for the AD7666 to
achieve its rated accuracy after a full-scale step function is
applied to its input.

Reference Voltage Temperature Coefficient

Reference voltage temperature coefficient is derived from the
maximum and minimum reference output voltage (V
measured at T

, T(25°C), and T

MIN

. It is expressed in ppm/°C

MAX

REF

)

using the following equation:

(V(V

MinMax

)–)

REF

CppmTCV

)/( ×

=°

REF

REFREF

MAX

TTV

MIN

C

×°

6

10

)–()25(

where:

V

(Max) = Maximum V

REF

(Min) = Minimum V

V

REF

V

(25°C) = V

REF

T

MAX

T

MIN

= +85°C

= –40°C

REF

at +25°C

REF

REF

at T

at T

MIN

, T(25°C), or T

MIN

, T(25°C), or T

MAX

MAX

Thermal Hysteresis

Thermal hysteresis is defined as the absolute maximum change
of reference output voltage after the device is cycled through
temperature from either

T_HYS+ = +25°C to T

T_HYS– = +25°C to T

to +25°C

MAX

to +25°C

MIN

It is expressed in ppm using the following equation:

)_()25(

HYS

=

)( ×

ppmV

−°

REF

HYSTVCV

REFREF

)25(

CV

°

10

6

where:

V

(25°C) = V

REF

(T_HYS) = Maximum change of V

V

REF

at 25°C

REF

at T_HYS+ or

REF

T_HYS–.

Rev. 0 | Page 11 of 28

AD7666

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

1.5

1.0

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

0 16384 32768 49152 65536

CODE

Figure 5. Integral Nonlinearity vs. Code

20

15

10

NUMBER OF UNITS

5

03034-0-005

0.5

DNL (LSB)

0

–0.5

–1.0

0 16384 32768 49152 65536

CODE

Figure 8. Differential Nonlinearity vs. Code

20

15

10

NUMBER OF UNITS

5

03034-0-008

0

0 0.5 1.0 1.5 2.0

POSITIVE INL (LSB)

Figure 6. Typical Positive INL Distribution (99 Units)

30

20

10

NUMBER OF UNITS

0

0 0.25 0.50 0.75 1.00 1.25 1.50

POSITIVE DNL (LSB)

Figure 7. Typical Positive DNL Distribution (99 Units)

03034-0-006

03034-0-007

0

–2.0 –1.5 –1.0 –0.5 0

NEGATIVE INL (LSB)

Figure 9. Typical Negative INL Distribution (99 Units)

40

30

20

NUMBER OF UNITS

10

0
–1.00 –0.75 –0.50 –0.25 0

NEGATIVE DNL (LSB)

Figure 10. Typical Negative DNL Distribution (99 Units)

03034-0-009

03034-0-010

Rev. 0 | Page 12 of 28

AD7666

120000

100000

80000

60000

COUNTS

40000

20000

15968

0

0

7FFC

211

1

7FFE 7FFF 8000 8001 8002 80037FFD 8004

112335

111791

CODE IN HEX

20187

623

Figure 11. Histogram of 261,120 Conversions of a

DC Input at the Code Transition

0

f

–20

–40

–60

–80

–100

–120

–140

AMPLITUDE (dB of Full Scale)

–160

–180

0 50 100 150 200 250

FREQUENCY (kHz)

= 500kSPS

S

f

= 101.361kHz

IN

SNR = 88.6dB
THD = –98.1dB
SFDR = 99.2dB
S/[N+D] = 88.1dB

Figure 12. FFT Plot

91

90

89

88

87

86

85

SNR, S/[N+D] (dB)

84

83

82

81

1 10 100 1000

FREQUENCY (kHz)

ENOB

Figure 13. SNR, S /(N+D), and ENOB vs. Fre quency

4

SNR

S/[N+D]

0

03034-0-011

03034-0-012

15.5

15.0

14.5

14.0

ENOB (Bits)

13.5

13.0

03034-0-013

180000

160000

140000

120000

100000

80000

COUNTS

60000

40000

20000

0

0

7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002

2789

11

148481

52691

CODE IN HEX

53814

3300

34

Figure 14. Histogram of 261,120 Conversions of a

DC Input at the Code Center

–70

–75

–80

–85

–90

–95

–100

–105

THD, HARMONICS (dB)

–110

–115

–120

1 10 100 1000

FREQUENCY (kHz)

THD

THIRD
HARMONIC

SFDR

SECOND
HARMONIC

Figure 15. THD, H armonics, and SFDR vs. Frequency

91

90

SNR

S/[N+D]

89

SNR, S/[N+D] REFERRED TO FULL-SCALE (dB)

88

–50 –40 –30 –20 –10 0

–60

INPUT LEVEL (dB)

Figure 16. SNR and S/(N+D) vs. Input Level (Referred to Full Scale)

0

120

110

100

90

80

70

SFDR (dB)

60

50

40

30

20

03034-0-014

03034-0-015

03034-0-016

Rev. 0 | Page 13 of 28

AD7666

92

91

90

89

SNR, S/[N+D] (dB)

88

87

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

Figure 17. SNR, S/(N+D), and ENOB vs. Temperature

–100

–105

THD

–110

THD, HARMONICS (dB)

SECOND
HARMONIC

–115

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

Figure 18. THD and Harmonics vs. Temperature

100000

ENOB

THIRD
HARMONIC

SNR

S/[N+D]

15.5

15.0

14.5

14.0

13.5

13.0

ENOB (Bits)

03034-0-017

03034-0-018

6
5
4
3
2
1

0
–1
–2
–3
–4
–5

ZERO ERROR, FULL-SCALE ERROR (LSB)

–6

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

FULL-SCALE
ERROR

ZERO ERROR

Figure 20. Zero Error, Full-Scale Error without Reference vs. Temperature

2.5016

2.5014

2.5012

2.5010

2.5008

2.5006

2.5004

VREF (V)

2.5002

2.5000

2.4998

2.4996

2.4994
–40 –20 0 20 40 60 80 100 120

)

C

°

(

E

R

T

U

A

E

R

P

M

E

T

Figure 21.Typical Reference Voltage Output vs. Temperature (2 Units)

25

03034-0-020

03034-0-021

10000

1000

100

10

1

0.1

OPERATING CURRENTS (µA)

0.01

0.001
10 100 1k 10k 100k 1M

AVDD

DVDD

SAMPLING RATE (SPS)

OVDD

PDREF = PDBUF = HIGH

Figure 19. Operating Current vs. Sample Rate

03034-0-019

Figure 22. Reference Voltage Temperature Coefficient Distribution (93 Units)

Rev. 0 | Page 14 of 28

20

15

10

NUMBER OF UNITS

5

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

REFERENCE DRIFT (ppm/°C)

7

8.0

5

.

03034-0-039

AD7666

50

45

40

35

30

25

DELAY (ns)

20

12

t

15

10

5

0

0 50 100 150 200

OVDD = 2.7V @ 25°C

OVDD = 5V @ 25°C

C

L

OVDD = 2.7V @ 85°C

(pF)

Figure 23. Typical Delay vs. Load Capacitance, C

OVDD = 5V @ 85°C

L

03035-0-023

Rev. 0 | Page 15 of 28

AD7666

CIRCUIT INFORMATION

IN

REF

REFGND

32,768C

INGND

MSB

16,384C 4C 2C C C

65,536C

Figure 24. ADC Simplified Schematic

LSB

SW

SW

A

COMP

B

SWITCHES

CONTROL

CONTROL

LOGIC

CNVST

BUSY

OUTPUT

CODE

03033-0-020

The AD7666 is a very fast, low power, single supply, precise
16-bit analog-to-digital converter (ADC). The AD7666 is
capable of converting 100,000 samples per second (500 kSPS)
and allows power savings between conversions.

The AD7666 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.

The AD7666 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in
either a 48-lead LQFP or a 48-lead LFCSP that saves space and
allows flexible configurations as either a serial or parallel inter­face. The AD7666 is pin-to-pin compatible with PulSAR ADCs
and is an upgrade of the

AD7661 and AD7664.

CONVERTER OPERATION

The AD7666 is a successive-approximation ADC based on a
charge redistribution DAC. Figure 24 shows a simplified sche­matic of the ADC. The capacitive DAC consists of an array of
16 binary weighted capacitors and an additional LSB capacitor.
The comparator’s negative input is connected to a dummy
capacitor of the same value as the capacitive DAC array.

During the acquisition phase, the common terminal of the array
tied to the comparator's positive input is connected to AGND
via SW

. All independent switches are connected to the analog

A

input IN. Thus, the capacitor array is used as a sampling
capacitor and acquires the analog signal on IN. Similarly, the
dummy capacitor acquires the analog signal on INGND.

When
the conversion phase begins, SW

goes LOW, a conversion phase is initiated. When

CNVST

and SWB are opened. The

A

capacitor array and dummy capacitor are then disconnected
from the inputs and connected to REFGND. Therefore, the
differential voltage between IN and INGND captured at the end
of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between REFGND and REF,
the comparator input varies by binary weighted voltage steps

/2, V

(V

REF

/4, …V

REF

/65536). The control logic toggles these

REF

switches, starting with the MSB, to bring the comparator back
into a balanced condition.

After this process is completed, the control logic generates the
ADC output code and brings the BUSY output LOW.

Rev. 0 | Page 16 of 28

AD7666

Ω

A

T

Transfer Functions

Using the OB/2C digital input, the AD7666 offers two output
codings: straight binary and twos complement. The LSB size is

/65536, which is about 38.15 µV. The AD7666’s ideal

V

REF

transfer characteristic is shown in Figure 25 and Table 7.

/65536

REF

ANALOG INPUT

V

REF

V

REF

– 1.5 LSB

– 1 LSB

03033-0-021

111...111

111...110

111...101

ADC CODE (Straight Binary)

000...010

000...001

000...000

1 LSB =V

1LSB0V

0.5 LSB

Figure 25. ADC Ideal Transfer Function

Table 7. Output Codes and Ideal Input Voltages

Analog

Description

Input

FSR –1 LSB 2.499962 V FFFF

Digital Output Code (Hex)

Straight
Binary

1

Twos
Complement

7FFF1
FSR – 2 LSB 2.499923 V FFFE 7FFE
Midscale + 1 LSB 1.250038 V 8001 0001
Midscale 1.25 V 8000 0000
Midscale – 1 LSB 1.249962 V 7FFF FFFF
–FSR + 1 LSB 38 µV 0001 8001
–FSR 0 V 0000

1

This is also the code for overrange analog input (VIN – V

V

– V

REFGND

).

REF

2

This is also the code for underrange analog input (VIN below V

2

80002

INGND

above

INGND

).

ANALOG

SUPPLY

NALOG INPU

(0VTO 2.5V)

(5V)

+

4

C

R

2

U1

C

C

NOTES

1

THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER.

2

THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.

3

OPTIONAL LOW JITTER.

4

A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M).

SEE VOLTAGE REFERENCE INPUT SECTION.

10

µ

F

100nF

15

Ω

2.7nF

100nF

PDREF

20

+

AVDD DGND DVDD OVDD OGND

REF
REFBUFIN

REFGND

IN

INGND

AGND

1

PDBUF

PD RESET

10

µ

F

AD7666

100nF

BYTESWAP

RDCS

SCLK

SDOUT

BUSY

CNVST

OB/2C

SER/PAR

Figure 26. Typical Connection Diagram

100nF

DIGITAL SUPPLY

10

µ

F

SERIAL

PORT

(3.3V OR 5V)

+

µC/µP/DSP

3

D

DVDD

CLOCK

03034-0-022

Rev. 0 | Page 17 of 28

AD7666

TYPICAL CONNECTION DIAGRAM

Figure 26 shows a typical connection diagram for the AD7666.

Analog Input

Figure 27 shows an equivalent circuit of the input structure of
the AD7666.

The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN and INGND. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 0.3 V. This will cause these diodes to become
forward-biased and start conducting current. These diodes can
handle a forward-biased current of 100 mA maximum. For
instance, these conditions could eventually occur when the
input buffer’s (U1) supplies are different from AVDD. In such a
case, an input buffer with a short-circuit current limitation can
be used to protect the part.

AVDD

OR INGND

AGND

IN

Figure 27. Equivalent Analog Input Circuit

D1

C1

D2

R1

This analog input structure allows the sampling of the differen­tial signal between IN and INGND. Unlike other converters,
INGND is sampled at the same time as IN. By using this
differential input, small signals common to both inputs are
rejected, as shown in Figure 28, which represents the typical
CMRR over frequency with on-chip and external references.
For instance, by using INGND to sense a remote signal ground,
ground potential differences between the sensor and the local
ADC ground are eliminated.

90

80

REF

70

60

CMRR (dB)

50

40

30

1 10 100 1000 10000

Figure 28. Analog In put CMRR vs. Fre quency

EXT REF

FREQUENCY (kHz)

C2

03033-0-023

03034-0-028

During the acquisition phase, the impedance of the analog
input IN can be modeled as a parallel combination of capacitor
C1 and the network formed by the series connection of R1 and
C2. C1 is primarily the pin capacitance. R1 is typically 168 Ω
and is a lumped component made up of some serial resistors
and the on resistance of the switches. C2 is typically 60 pF and
is mainly the ADC sampling capacitor. During the conversion
phase, where the switches are opened, the input impedance is
limited to C1. R1 and C2 make a 1-pole low-pass filter that
reduces undesirable aliasing effect and limits the noise.

When the source impedance of the driving circuit is low, the
AD7666 can be driven directly. Large source impedances will
significantly affect the ac performance, especially total
harmonic distortion (THD). The maximum source impedance
depends on the amount of THD that can be tolerated. The THD
degrades as a function of the source impedance and the
maximum input frequency, as shown in Figure 29.

–50

–60

–70

–80

THD (dB)

–90

–100

–110

1 10 100 1000

INPUT FREQUENCY (kHz)

Figure 29. THD vs. Analog Input Frequency and Source Resistance

RS = 500

RS = 100

RS = 50
RS = 20

Ω

Ω

Ω

Ω

03034-0-029

Driver Amplifier Choice

Although the AD7666 is easy to drive, the driver amplifier
needs to meet the following requirements:

• The driver amplifier and the AD7666 analog input circuit

must be able to settle for a full-scale step of the capacitor
array at a 16-bit level (0.0015%). In the amplifier’s data
sheet, settling at 0.1% to 0.01% is more commonly speci­fied. This could differ significantly from the settling time at
a 16-bit level and should be verified prior to driver
selection. The tiny op amp

AD8021, which combines ultra

low noise and high gain-bandwidth, meets this settling
time requirement even when used with gains up to 13.

Rev. 0 | Page 18 of 28

AD7666

• The noise generated by the driver amplifier needs to be

kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7666. The noise
coming from the driver is filtered by the AD7666 analog
input circuit, 1-pole, low-pass filter made by R1 and C2 or
by the external filter, if one is used. The SNR degradation
due to the amplifier is

Voltage Reference Input

The AD7666 allows the choice of either a very low temperature
drift internal voltage reference or an external 2.5 V reference.

Unlike many ADCs with internal references, the internal
reference of the AD7666 provides excellent performance and
can be used in almost all applications.

⎛
⎜

SNR

LOSS

=

⎜

log20

⎜

784

⎜
⎝

28

π

+

−23

dB

2

⎞
⎟

⎟
⎟

)(

Nef

⎟

N

⎠

where:

f

is the input bandwidth of the AD7666 (13 MHz) or

–3dB

the cutoff frequency of the input filter (3.9 MHz), if
one is used.

N is the noise factor of the amplifier (+1 in buffer

configuration).

eN is the equivalent input noise voltage of the op amp, in

nV/√Hz.

For instance, a driver with an equivalent input noise of
2 nV/√Hz, like the AD8021 with a noise gain of +1 when
configured as a buffer, degrades the SNR by only 0.13 dB
when using the filter shown in Figure 26, and by 0.43 dB
without the filter shown in Figure 26.

•

The driver needs to have a THD performance suitable to

that of the AD7666. Figure 15 gives the THD versus
frequency that the driver should exceed.

The AD8021 meets these requirements and is appropriate for
almost all applications. The AD8021 needs a 10 pF external
compensation capacitor that should have good linearity as an
NPO ceramic or mica type. Moreover, the use of a noninverting
+1 gain arrangement is recommended and helps to obtain the
best signal-to-noise ratio.

The AD8022 could also be used if a dual version is needed and
gain of 1 is present. The AD829 is an alternative in applications
where high frequency (above 100 kHz) performance is not
required. In gain of 1 applications, it requires an 82 pF
compensation capacitor. The AD8610 is an option when low
bias current is needed in low frequency applications.

To use the internal reference along with the internal buffer,
PDREF and PDBUF should both be LOW. This will produce

1.2 V on REFBUFIN which, amplified by the buffer, will result
in a 2.5 V reference on the REF pin.

The output impedance of REFBUFIN is 11 k

the internal reference is enabled. It is necessary to

Ω (minimum) when

decouple
REFBUFIN with a ceramic capacitor greater than 10 nF. Thus
the capacitor provides an RC filter for noise reduction.

To use an external reference along with the internal buffer,
PDREF should be HIGH and PDBUF should be LOW. This
powers down the internal reference and allows the 2.5 V
reference to be applied to REFBUFIN.

To use an external reference directly on REF pin, PDREF and
PDBUF should both be HIGH.

PDREF and PDBUF power down the internal reference and the
internal reference buffer, respectively. Note that the PDREF and
PDBUF input current should never exceed 20 mA. This could
eventually occur when input voltage is above AVDD (for
instance at power up). In this case, a 100 Ω series resistor is
recommended.

The internal reference is temperature compensated to 2.5 V
± 7 mV. The reference is trimmed to provide a typical drift of
3 ppm/°C . This typical drift characteristic is shown in
Figure 22. For improved drift performance, an external
reference, such as the AD780, can be used.

The AD7666 voltage reference input REF has a dynamic input
impedance; it should therefore be driven by a low impedance
source with efficient decoupling between the REF and
REFGND inputs. This decoupling depends on the choice of the
voltage reference, but usually consists of a low ESR tantalum
capacitor connected to REF and REFGND, with minimum
parasitic inductance. A 10 µF (X5R, 1206 size) ceramic chip
capacitor (or 47 µF tantalum capacitor) is appropriate when
using either the internal reference or one of these
recommended reference voltages:

•

The low noise, low temperature drift ADR421 and AD780

•

The low power ADR291

•

The low cost AD1582

Rev. 0 | Page 19 of 28

AD7666

For applications that use multiple AD7666s, it is more effective
to use the internal buffer to buffer the reference voltage.

Care should be taken with the voltage reference’s temperature
coefficient, which directly affects the full-scale accuracy if this
parameter matters. For instance, a ±15 ppm/°C temperature
coefficient of the reference changes full scale by ±1 LSB/°C.

Note that V
input range is defined in terms of V
increase the range to 0 V to 3 V with an AVDD above 4.85 V.

AD780 can be selected with a 3 V reference voltage.

The

The TEMP pin, which measures the temperature of the
AD7666, can be used as shown in Figure 30. The output of
TEMP pin is applied to one of the inputs of the analog switch

ADG779), and the ADC itself is used to measure its own

(e.g.,
temperature. This configuration is very useful for improving the
calibration accuracy over the temperature range.

ANALOG INPUT

(UNIPOLAR)

Power Supply

The AD7666 uses three power supply pins: an analog 5 V supply
AVDD, a digital 5 V core supply DVDD, and a digital input/
output interface supply OVDD. OVDD allows direct interface
with any logic between 2.7 V and DVDD + 0.3 V. To reduce the
supplies needed, the digital core (DVDD) can be supplied
through a simple RC filter from the analog supply, as shown in
Figure 26. The AD7666 is independent of power supply
sequencing once OVDD does not exceed DVDD by more than

0.3 V, and is thus free of supply voltage induced latch-up.
Additionally, it is very insensitive to power supply variations
over a wide frequency range, as shown in Figure 31, which
represents PSRR over frequency with on-chip and external
references.

can be increased to AVDD – 1.85 V. Since the

REF

, this would essentially

REF

ADG779

AD8021

IN

C

C

TEMP

TEMPERATURE
SENSOR

AD7666

Figure 30. Temperature Sensor Connection Diagram

03034-0-024

90

80

70

60

PSRR (dB)

50

40

30

INT REF

1 10 100 1000 10000

EXT REF

FREQUENCY (kHz)

Figure 31. PSRR v s. Frequency

POWER DISSIPATION VERSUS THROUGHPUT

Operating currents are very low during the acquisition phase,
allowing significant power savings when the conversion rate is
reduced (see Figure 32). The AD7666 automatically reduces its
power consumption at the end of each conversion phase. This
makes the part ideal for very low power battery applications.
The digital interface and the reference remain active even
during the acquisition phase. To reduce operating digital supply
currents even further, digital inputs need to be driven close to
the power supply rails (i.e., DVDD or DGND), and OVDD
should not exceed DVDD by more than 0.3 V.

1M

100k

10k

1k

POWER DISSIPATION (µW)

100

10

10 100 1k 10k 100k 1M

SAMPLING RATE (SPS)

Figure 32. Power Dissipation vs. Sampling Rate

PDREF = PDBUF = HIGH

03034-0-031

03034-0-032

Rev. 0 | Page 20 of 28

AD7666

t

CONVERSION CONTROL

Figure 33 shows the detailed timing diagrams of the conversion

CNVST

CNVST

signal, which

signal should

with a

process. The AD7666 is controlled by the

CNVST

initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete.

CNVST

operates independently of CS and RD.

Conversions can be automatically initiated with the AD7666. If

is held LOW when BUSY is LOW, the AD7666 controls

CNVST
the acquisition phase and automatically initiates a new

conversion. By keeping

CNVST

LOW, the AD7666 keeps the

conversion process running by itself. It should be noted that the
analog input must be settled when BUSY goes LOW. Also, at
power-up,

CNVST

should be brought LOW once to initiate the

conversion process. In this mode, the AD7666 can run slightly
faster than the guaranteed 500 kSPS.

Although

is a digital signal, it should be designed with

CNVST

special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.

The

trace should be shielded with ground and a low

CNVST
value serial resistor (i.e., 50 Ω) termination should be added
close to the output of the component that drives this line.

For applications where SNR is critical, the
have very low jitter. This may be achieved by using a dedicated

oscillator for

CNVST

generation, or to clock

high frequency, low jitter clock, as shown in Figure 26.

t

1

CNVST

BUSY

t

3

t

5

MODE

ACQUIRE CONVERT ACQUIRE CONVERT

t

4

t

7

Figure 33. Basic Conversion Timing

t

9

RESET

BUSY

DATA

CNVST

Figure 34. RESET Timing

CS = RD = 0

t

CNVST

BUSY

DATA

BUS

t

3

1

PREVIOUS CONVERSION DATA NEW DATA

Figure 35. Master Parallel Data Timing for Reading (Continuous Read)

2

t

6

t

8

t

8

t

10

t

4

t

11

03033-0-026

03033-0-027

03033-0-028

Rev. 0 | Page 21 of 28

AD7666

DIGITAL INTERFACE

The AD7666 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or a parallel
interface. The serial interface is multiplexed on the parallel data
bus. The AD7666 digital interface also accommodates both 3 V
and 5 V logic by simply connecting the OVDD supply pin of the
AD7666 to the host system interface digital supply. Finally, by
using the OB/

binary coding can be used.

The two signals,
have a similar effect because they are OR’d together internally.

When at least one of these signals is HIGH, the interface
outputs are in high impedance. Usually

of each AD7666 in multicircuit applications and is held low in a
single AD7666 design.

conversion result on the data bus.

PARALLEL INTERFACE

The AD7666 is configured to use the parallel interface when
SER/

PA R

conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 36 and
Figure 37, respectively. When the data is read during the
conversion, however, it is recommended that it is read only
during the first half of the conversion phase. This avoids any
potential feedthrough between voltage transients on the digital
interface and the most critical analog conversion circuitry.

input pin, both twos complement or straight

2C

and RD, control the interface. CS and RD

CS

allows the selection

CS

is generally used to enable the

RD

is held LOW. The data can be read either after each

CS

RD

BUSY

DAT A

BUS

t

12

CURRENT

CONVERSION

t

13

Figure 36. Slave Parallel Data Timing for Reading (Read after Convert)

CS = 0

CNVST,

RD

BUSY

DATA

BUS

t

t

12

3

t

1

PREVIOUS

CONVERSION

t

4

t

13

Figure 37. Slave Parallel Data Timing for Reading (Read during Convert)

03033-0-029

03033-0-030

The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 38, the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].

SERIAL INTERFACE

The AD7666 is configured to use the serial interface when
SER/

MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edges of the data clock.

is held HIGH. The AD7666 outputs 16 bits of data,

PA R

CS

RD

BYTESWAP

PINS D[15:8]

PINS D[7:0]

HI-Z

HI-Z

HIGH BYTE LOW BYTE

t

12

LOW BYTE HIGH BYTE

Figure 38. 8-Bit Parallel Interface

HI-Z

t

12

t

HI-Z

13

03033-0-031

Rev. 0 | Page 22 of 28

AD7666

MASTER SERIAL INTERFACE

Internal Clock

The AD7666 is configured to generate and provide the serial
data clock SCLK when the EXT/

AD7666 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. Figure 39 and Figure 40 show
detailed timing diagrams of these two modes.

pin is held LOW. The

INT

Usually, because the AD7666 is used with a fast throughput, the
Master Read During Conversion mode is the most recommen­ded serial mode. In this mode, the serial clock and data toggle at
appropriate instants, minimizing potential feedthrough between
digital activity and critical conversion decisions.

In Read After Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.

CS, RD

CNVST

BUSY

SYNC

SCLK

SDOUT

EXT/INT = 0

t

3

t

29

t

14

t

20

t

15

X

t

16

t

22

RDC/SDIN = 0 INVSCLK = INVSYNC = 0

t

28

t

30

t

18

t

19

t

21

123 141516

D15 D14 D2 D1 D0

t

23

t

24

t

25

t

26

t

27

03033-0-032

Figure 39. Master Serial Data Timing for Reading (Read after Convert)

EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0

CS, RD

t

1

CNVST

t

3

BUSY

SYNC

SCLK

SDOUT

t

17

t

14

t

15

t

18

t

16

t

22

t

19

t20t

21

12 3 141516

D15 D14 D2 D1 D0X

t

23

Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)

Rev. 0 | Page 23 of 28

t

25

t

24

t

26

t

27

03033-0-033

AD7666

S

SLAVE SERIAL INTERFACE

External Clock

The AD7666 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/

held HIGH. In this mode, several methods can be used to read
the data. The external serial clock is gated by

are both LOW, the data can be read after each conversion or

RD

CS

during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally HIGH or normally LOW when
inactive. Figure 41 and Figure 42 show the detailed timing
diagrams of these methods. Usually, because the AD7666 has a
longer acquisition phase than conversion phase, the data are
read immediately after conversion.

RD

BUSY

t

35

t36t

SCLK

SDOUT

t

31

t

16

1 2 3 14151617 18

X

D15 D14 D1

pin is

INT

. When CS and

EXT/INT = 1

37

t

32

t

34

D13

While the AD7666 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7666 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that is toggling only when BUSY is
LOW, or, more importantly, that it does not transition during
the latter half of BUSY HIGH.

INVSCLK = 0

RD = 0

D0

X15 X14

SDIN

CS

CNVST

BUSY

SCLK

DOUT

X15 X14 X13 X1 X0 Y15 Y14

t

33

Figure 41. Slave Serial Data Timing for Reading (Read after Convert)

D1

RD = 0

D0

EXT/INT = 1 INVSCLK = 0

t

3

t

16

t

35

t36t

37

123 141516

t

31

X

D15 D14 D13

t

32

Figure 42. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)

03033-0-034

03033-0-035

Rev. 0 | Page 24 of 28

AD7666

External Discontinuous Clock Data Read After Conversion

Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave
modes. Figure 41 shows the detailed timing diagrams of this
method. After a conversion is complete, indicated by BUSY
returning LOW, the conversion’s result can be read while both

and RD are LOW. Data is shifted out MSB first with 16 clock

CS
pulses and is valid on the rising and falling edges of the clock.

Among the advantages of this method is the fact that
conversion performance is not degraded because there are no
voltage transients on the digital interface during the conversion
process. Another advantage is the ability to read the data at any
speed up to 40 MHz, which accommodates both the slow digital
host interface and the fastest serial reading.

Finally, in this mode only, the AD7666 provides a daisy-chain
feature using the RDC/SDIN pin for cascading multiple con­verters together. This feature is useful for reducing component
count and wiring connections when desired, as, for instance, in
isolated multiconverter applications.

External Clock Data Read During Conversion

Figure 42 shows the detailed timing diagrams of this method.
During a conversion, while both

and RD are LOW, the result

CS

of the previous conversion can be read. The data is shifted out
MSB first with 16 clock pulses, and is valid on both the rising
and falling edges of the clock. The 16 bits must be read before
the current conversion is complete; otherwise, RDERROR is
pulsed HIGH and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain feature
in this mode and the RDC/SDIN input should always be tied
either HIGH or LOW.

To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 18 MHz is recommended to
ensure that all the bits are read during the first half of the
conversion phase. It is also possible to begin to read data after
conversion and continue to read the last bits after a new
conversion has been initiated. This allows the use of a slower
clock speed like 14 MHz.

An example of the concatenation of two devices is shown in
Figure 43. Simultaneous sampling is possible by using a
common

signal. It should be noted that the RDC/SDIN

CNVST
input is latched on the opposite edge of SCLK of the one used to
shift out the data on SDOUT. Therefore, the MSB of the
“upstream” converter just follows the LSB of the “downstream”

converter on the next SCLK cycle.

BUSY
OUT

BUSYBUSY

AD7666

(UPSTREAM)

RDC/SDIN SDOUT

SCLK IN

CS IN

CNVST IN

Figure 43. Two AD7666s in a Daisy-Chain Configuration

#2

CNVST

CS

SCLK

AD7666

#1

(DOWNSTREAM)

SDOUTRDC/SDIN

CNVST

SCLK

CS

DATA
OUT

03034-0-036

Rev. 0 | Page 25 of 28

AD7666

MICROPROCESSOR INTERFACING

The AD7666 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7666 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7666 to prevent digital noise from coupling
into the ADC. The following section discusses the use of an
AD7666 with an ADSP-219x SPI equipped DSP.

SPI Interface (ADSP-219x)

Figure 44 shows an interface diagram between the AD7666 and
the SPI equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7666 acts as a slave device and data
must be read after conversion. This mode also allows the daisy­chain feature. The convert command can be initiated in
response to an internal timer interrupt. The reading process can
be initiated in response to the end-of-conversion signal (BUSY

going LOW) using an interrupt line of the DSP. The serial inter­face (SPI) on the ADSP-219x is configured for master mode—
(MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit
(CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00—by
writing to the SPI control register (SPICLTx). To meet all timing
requirements, the SPI clock should be limited to 17 Mbps,
which allows it to read an ADC result in less than 1 µs. When a
higher sampling rate is desired, use of one of the parallel
interface modes is recommended.

DVDD

AD7666*

SER/PAR
EXT/INT

BUSY

RD
INVSCLK

Figure 44. Interfacing the AD7666 to an SPI Interface

CS

SDOUT

SCLK

CNVST

*ADDITIONAL PINS OMITTED FOR CLARITY

ADSP-219x*

PFx
SPIxSEL (PFx)
MISOx
SCKx
PFx or TFSx

03034-0-037

Rev. 0 | Page 26 of 28

AD7666

APPLICATION HINTS

BIPOLAR AND WIDER INPUT RANGES

In some applications, it is desirable to use a bipolar or wider
analog input range such as ±10 V, ±5 V, or 0 V to 5 V. Although
the AD7666 has only one unipolar range, simple modifications
of input driver circuitry allow bipolar and wider input ranges to
be used without any performance degradation. Figure 45 shows
a connection diagram that allows this. Component values
required and resulting full-scale ranges are shown in Table 8.

When desired, accurate gain and offset can be calibrated by
acquiring a ground and voltage reference using an analog
multiplexer (U2), as shown in Figure 45.

C

F

R1

U2

R2

R3 R4

C

REF

15Ω

U1

2.7nF

100nF

IN

AD7666

INGND
REF

REFGND

03034-0-038

ANALOG

INPUT

Figure 45. Using the AD7666 in 16-Bit Bipolar and/or Wider Input Ranges

Table 8. Component Values and Input Ranges

Input Range R1 (Ω) R2 (kΩ) R3 (kΩ) R4 (kΩ)

±10 V 500 4 2.5 2
±5 V 500 2 2.5 1.67
0 V to –5 V 500 1 None 0

LAYOUT

The AD7666 has very good immunity to noise on the power
supplies. However, care should still be taken with regard to
grounding layout.

The printed circuit board that houses the AD7666 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
ground planes that can be separated easily. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7666, or as close as possible to the AD7666.
If the AD7666 is in a system where multiple devices require
analog-to-digital ground connections, the connection should
still be made at one point only, a star ground point that should
be established as close as possible to the AD7666.

Running digital lines under the device should be avoided since
these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7666 to avoid noise
coupling. Fast switching signals like

or clocks should be

CNVST

shielded with digital ground to avoid radiating noise to other
sections of the board, and should never run near analog signal
paths. Crossover of digital and analog signals should be avoided.
Traces on different but close layers of the board should run at
right angles to each other. This will reduce the effect of crosstalk
through the board.

The power supply lines to the AD7666 should use as large a
trace as possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decoupling is
also important to lower the supply’s impedance presented to the
AD7666 and to reduce the magnitude of the supply spikes.
Decoupling ceramic capacitors, typically 100 nF, should be
placed on each power supply pin—AVDD, DVDD, and
OVDD—close to, and ideally right up against these pins and
their corresponding ground pins. Additionally, low ESR 10 µF
capacitors should be located near the ADC to further reduce
low frequency ripple.

The DVDD supply of the AD7666 can be a separate supply, or
can come from the analog supply AVDD or the digital interface
supply OVDD. When the system digital supply is noisy or when
fast switching digital signals are present, if no separate supply is
available, the user should connect DVDD to AVDD through an
RC filter (see Figure 26) and the system supply to OVDD and
the remaining digital circuitry. When DVDD is powered from
the system supply, it is useful to insert a bead to further reduce
high frequency spikes.

The AD7666 has five different ground pins: INGND, REFGND,
AGND, DGND, and OGND. INGND is used to sense the analog
input signal. REFGND senses the reference voltage and, because
it carries pulsed currents, should be a low impedance return to
the reference. AGND is the ground to which most internal ADC
analog signals are referenced; it must be connected with the
least resistance to the analog ground plane. DGND must be tied
to the analog or digital ground plane depending on the config­uration. OGND is connected to the digital system ground.

EVALUATING THE AD7666’S PERFORMANCE

A recommended layout for the AD7666 is outlined in the

EVAL-AD7666 evaluation board for the AD7666. The

evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the

EVAL-CONTROL BRD2.

Rev. 0 | Page 27 of 28

AD7666

Q

OUTLINE DIMENSIONS

1.45

1.40

1.35

0.15

0.05

PIN 1
INDICATOR

10°

6°
2°

SEATING
PLANE

VIEW A

ROTATED 90°CCW

7.00

BSC SQ

0.75

0.60

0.45

SEATING

PLANE

0.20

0.09
7°

3.5°
0°

0.10 MAX
COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026BBC

1.60
MAX

VIEW A

1

12

0.50

BSC

48

13

TOP VIEW

(PINS DOWN )

Figure 46. 48-Lead Quad Flatpack (LQFP) [ST-48]

Dimensions shown in millimeters

37

36

0.60 MAX

0.60 MAX

9.00 BSC
SQ

PIN 1

0.30

0.23

0.18

37

36

7.00

BSC S

25

24

0.27

0.22

0.17

PIN 1

48

INDICATOR

1

5.25

5.10 SQ

4.95

12

13

PADDLE CONNECTED TO AGND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES

0.25 MIN

1.00

0.85

0.80



12° MAX

SEATING
PLANE

TOP

VIEW

6.75

BSC SQ

0.50

0.40

0.30

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

0.20 REF

0.05 MAX

0.02 NOM

25

24

COPLANARITY

0.08

BOTTOM

VIEW

5.50
REF

Figure 47. 48-Lead Frame Chip Scale Package (LFCSP) [CP-48]

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7666AST –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7666ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7666ACP –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48
AD7666ACPRL –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48
EVAL-AD7666CB
EVAL-CONTROL BRD2

1

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

2

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

1

2

Evaluation Board
Controller Board

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D03034–0–1/04(0)

Rev. 0 | Page 28 of 28