Datasheet AD7663 Datasheet (Analog Devices)

a

16-Bit, 250 kSPS CMOS ADC

FEATURES
Throughput: 250 kSPS
INL: 3 LSB Max (0.0046% of Full Scale)
16-Bit Resolution with No Missing Codes
S/(N+D): 90 dB Typ @ 100 kHz
THD: –100 dB Typ @ 100 kHz
Analog Input Voltage Ranges

Bipolar: 10 V, 5 V, 2.5 V

Unipolar: 0 V to 10 V, 0 V to 5 V, 0 V to 2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel (8/16 Bits) and Serial 5 V/3 V Interface

®

/QSPI™/MICROWIRE™/DSP Compatible

SPI
Single 5 V Supply Operation
Power Dissipation

35 mW Typical

15 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flatpack (LQFP)
Package: 48-Lead Chip Scale (LFCSP)
Pin-to-Pin Compatible with the AD7660/AD7664/AD7665

APPLICATIONS
Data Acquisition
Motor Control
Communication
Instrumentation
Spectrum Analysis
Medical Instruments
Process Control

GENERAL DESCRIPTION

The AD7663 is a 16-bit, 250 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. It contains a high speed 16-bit sampling ADC, a resistor
input scaler that allows various input ranges, an internal conver­sion clock, error correction circuits, and both serial and parallel
system interface ports.

The AD7663 is hardware factory-calibrated and is comprehen­sively tested to ensure such ac parameters as signal-to-noise ratio
(SNR) and total harmonic distortion (THD), in addition to the
more traditional dc parameters of gain, offset, and linearity.

It is fabricated using Analog Devices’ high performance, 0.6 micron
CMOS process and is available in a 48-lead LQFP and a tiny
48-lead LFCSP with operation specified from –40°C to +85°C.

*Patent pending

AD7663

*

FUNCTIONAL BLOCK DIAGRAM

DGNDDVDDAVDD AGND REF REFGND

PD

4R

4R

2R

R

SWITCHED

CAP DAC

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

CNVST

AD7663

CLOCK

SERIAL

PORT

PARALLEL

INTERFACE

16

OVDD

OGND

SER/PAR

BUSY

D[15:0]

CS

RD

OB/2C

BYTESWAP

IND(4R)

INC(4R)

INB(2R)

INA(R)

INGND

RESET

PulSAR Selection

Type/kSPS 100–250 500–570 800–1000

Pseudo AD7660 AD7650
Differential AD7664

True Bipolar AD7663 AD7665 AD7671

True Differential AD7675 AD7676 AD7677

18-Bit AD7678 AD7679 AD7674

Simultaneous/ AD7654 AD7655
Multichannel

PRODUCT HIGHLIGHTS

1. Fast Throughput
The AD7663 is a 250 kSPS charge redistribution, 16-bit
SAR ADC with various bipolar and unipolar input ranges.

2. Single-Supply Operation
The AD7663 operates from a single 5 V supply and dissipates
only 35 mW typical. Its power dissipation decreases with
the throughput to, for instance, only 15 µW at a 100 SPS
throughput.
It consumes 7 µW maximum when in power-down.

3. Superior INL
The AD7663 has a maximum integral nonlinearity of 3 LSB
with no missing 16-bit code.

4. Serial or Parallel Interface
Versatile parallel (8 bits or 16 bits) or 2-wire serial interface
arrangement compatible with both 3 V or 5 V logic.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)

AD7663–SPECIFICATIONS

(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)

Parameter Conditions Min Typ Max Unit

RESOLUTION 16 Bits

ANALOG INPUT

Voltage Range V
Common-Mode Input Voltage V

– V

IND

INGND

INGND

±4 REF, 0 V to 4 REF, ±2 REF (See Table I)

–0.1 +0.5 V
Analog Input CMRR fIN = 45 kHz 62 dB
Input Impedance See Table I

THROUGHPUT SPEED

Complete Cycle 4µs
Throughput Rate 0 250 kSPS

DC ACCURACY

Integral Linearity Error –3+3LSB

1

No Missing Codes 16 Bits
Transition Noise 0.7 LSB
Bipolar Zero Error

Bipolar Full-Scale Error
Unipolar Zero Error2, T
Unipolar Full-Scale Error

2

, T

MIN

2

, T

MIN

to T

MIN

to T

2

, T

MAX

MIN

to T

MAX

to T

MAX

MAX

±5 V Range –25 +25 LSB
Other Range –0.06 +0.06 % of FSR

–0.25 +0.25 % of FSR

–0.18 +0.18 % of FSR

–0.38 +0.38 % of FSR

Power Supply Sensitivity AVDD = 5 V ±5% ±0.1 LSB

AC ACCURACY

Signal-to-Noise fIN = 10 kHz 89 90 dB

3

fIN = 100 kHz 90 dB

Spurious-Free Dynamic Range f

= 100 kHz 100 dB

IN

Total Harmonic Distortion fIN = 100 kHz –100 dB
Signal-to-(Noise+Distortion) f

= 10 kHz 88.5 90 dB

IN

= 100 kHz, –60 dB Input 30 dB

f

IN

–3 dB Input Bandwidth 800 kHz

SAMPLING DYNAMICS

Aperture Delay 2ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 2.75 µs

REFERENCE

External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 250 kSPS Throughput 50 µA

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

–0.3 +0.8 V

+2.0 DVDD + 0.3 V

–1+1µA

–1+1µA

DIGITAL OUTPUTS

Data Format Parallel or Serial 16-Bit
Pipeline Delay Conversion Results Available Immediately

after Completed Conversion

I

V

OL

V

OH

= 1.6 mA 0.4 V

SINK

I

= –500 µA OVDD – 0.6 V

SOURCE

POWER SUPPLIES

Specified Performance

AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25

4

V

Operating Current 250 kSPS Throughput

AVDD 5mA

5

DVDD

5

OVDD

Power Dissipation

6

250 kSPS Throughput
100 SPS Throughput
In Power-Down Mode

5

5

7

1.8 mA
10 µA
35 41 mW
15 µW

7µW

–2–

REV. B

AD7663

Parameter Conditions Min Typ Max Unit

TEMPERATURE RANGE

Specified Performance T

NOTES

1

LSB means least significant bit. With the ±5 V input range, one LSB is 152.588 µV.

2

See Definition of Specifications section. These specifications do not include the error contribution from the external reference.

3

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

4

The max should be the minimum of 5.25 V and DVDD + 0.3 V.

5

Tested in Parallel Reading Mode.

6

Tested with the 0 V to 5 V range and VIN – V

7

With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively.

8

Contact factory for extended temperature range.

Specifications subject to change without notice.

8

to T

MIN

= 0 V. See Power Dissipation section.

INGND

MAX

–40 +85 °C

Table I. Analog Input Configuration

Input Voltage Input
Range IND(4R) INC(4R) INB(2R) INA(R) Impedance

±4 REF
±2 REF V
±REF V
0 V to 4 REF V
0 V to 2 REF V
0 V to REF V

NOTES

1

2

3

TIMING SPECIFICATIONS

Parameter

2

Typical analog input impedance.
With REF = 3 V, in this range, the input should be limited to –11 V to +12 V.
For this range the input is high impedance.

V

IN

IN

IN

IN

IN

IN

INGND INGND REF 5.85 kW
V

IN

V

IN

V

IN

V

IN

V

IN

(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)

INGND REF 3.41 kW
V

IN

REF 2.56 kW

INGND INGND 3.41 kW
V

IN

V

IN

INGND 2.56 kW
V

IN

Note 3

Symbol Min Typ Max Unit

Refer to Figures 11 and 12

Convert Pulsewidth t
Time between Conversions t
CNVST LOW to BUSY HIGH Delay t
BUSY HIGH All Modes Except in t

1

2

3

4

5ns
4µs

30 ns

1.25 µs

Master Serial Read after Convert Mode
Aperture Delay t
End of Conversion to BUSY LOW Delay t
Conversion Time t
Acquisition Time t
RESET Pulsewidth t

5

6

7

8

9

10 ns

2.75 µs
10 ns

2ns

1.25 µs

Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes)

CNVST LOW to DATA Valid Delay t
DATA Valid to BUSY LOW Delay t
Bus Access Request to DATA Valid t
Bus Relinquish Time t

Refer to Figures 17 and 18 (Master Serial Interface Modes)

1

CS LOW to SYNC Valid Delay t
CS LOW to Internal SCLK Valid Delay t
CS LOW to SDOUT Delay t
CNVST LOW to SYNC Delay (Read during Convert) t

SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK HIGH
Internal SCLK LOW
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay

2

2

2

2

2

2

2

10

11

12

13

14

15

16

17

t

18

t

19

t

20

t

21

t

22

t

23

t

24

20 ns

515ns

0.5 µs
4ns
25 40 ns
15 ns

9.5 ns

4.5 ns
2ns
3ns

1.25 µs

40 ns

10 ns
10 ns
10 ns

1

REV. B

–3–

AD7663

TIMING SPECIFICATIONS

Parameter

Refer to Figures 17 and 18 (Master Serial Interface Modes)

CS HIGH to SYNC HI-Z t
CS HIGH to Internal SCLK HI-Z t
CS HIGH to SDOUT HI-Z t

BUSY HIGH in Master Serial Read after Convert t
CNVST LOW to SYNC Asserted Delay t

(continued)

Symbol Min Typ Max

1

25

26

27

28

29

(Master Serial Read after Convert)

SYNC Deasserted to BUSY LOW Delay t

30

Refer to Figures 19 and 21 (Slave Serial Interface Modes)

External SCLK Setup Time t
External SCLK Active Edge to SDOUT Delay t
SDIN Setup Time t
SDIN Hold Time t
External SCLK Period t
External SCLK HIGH t
External SCLK LOW t

NOTES

1

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C

2

In Serial Master Read during Convert Mode. See Table II for Master Read after Convert Mode.

Specifications subject to change without notice.

31

32

33

34

35

36

37

5ns
316ns
5ns
5ns
25 ns
10 ns
10 ns

of 10 pF; otherwise, the load is 60 pF maximum.

L

Table II. Serial Clock Timings in Master Read after Convert

Unit

10 ns
10 ns
10 ns

See Table II µs

1.25 µs

25 ns

DIVSCLK[1] 0011
DIVSCLK[0] 0101 Unit

SYNC to SCLK First Edge Delay Minimum t
Internal SCLK Period Minimum t
Internal SCLK Period Maximum t
Internal SCLK HIGH Minimum t
Internal SCLK LOW Minimum t
SDOUT Valid Setup Time Minimum t
SDOUT Valid Hold Time Minimum t
SCLK Last Edge to SYNC Delay Minimum t
BUSY HIGH Width Maximum t

I

1.6mA

TO OUTPUT

PIN

*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

C

L

C

L

60pF*

500A

OL

1.4V

I

OH

Figure 1. Load Circuit for Digital Interface Timing

18

19

19

20

21

22

23

24

28

4202020 ns
25 50 100 200 ns
40 70 140 280 ns
15 25 50 100 ns

9.5 24 49 99 ns

4.5 22 22 22 ns
243090 ns
360140 300 ns
2 2.5 3.5 5.75 µs

0.8V

t

DELAY

0.8V 0.8V

2V

t

DELAY

2V2V

Figure 2. Voltage Reference Levels for Timing

–4–

REV. B

AD7663

36

35

34

33

32

31

30

29

28

27

26

25

13 14

15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48

47 46 45 44 39 38 3743 42 41 40

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

AGND

CNVST

PD

RESET

CS
RD

DGND

AGND
AVDD

NC

BYTESWAP

OB/2C

NC

NC

NC = NO CONNECT

SER/PAR

D0

D1

D2/DIVSCLK[0]

BUSY

D15

D14

D13

AD7663

D3/DIVSCLK[1]

D12

D4/EXT/INT

D5/INVSYNC

D6/INVSCLK

D7/RDC/SDIN

OGND

OVDD

DVDD

DGND

D8/SDOUT

D9/SCLK

D10/SYNC

D11/RDERROR

NCNCNCNCNC

IND(4R)

INC(4R)

INB(2R)

INA(R)

INGND

REFGND

REF

ABSOLUTE MAXIMUM RATINGS

Analog Inputs

2

IND

, INC2, INB2 . . . . . . . . . . . . . . . . . . . . –11 V to +30 V

1

INA, REF, INGND, REFGND

. . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to AVDD + 0.3 V

Ground Voltage Differences

AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V

AVDD to DVDD,

AVDD to OVDD . . . . . . . . . . . . . . ±7 V

DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

Internal Power Dissipation

3

. . . . . . . . . . . . . . . . . . . 700 mW

Internal Power Dissipation4 . . . . . . . . . . . . . . . . . . . . . 2.5 W

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range

(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

See Analog Inputs section.

3

Specification is for device in free air: 48-Lead LQFP: qJA = 91°C/W, qJC = 30°C/W.

4

Specification is for device in free air: 48-Lead LFCSP: qJC = 26⬚C/W.

PIN CONFIGURATION

ST-48 and CP-48

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7663AST –40°C to +85°CQuad Flatpack (LQFP) ST-48
AD7663ASTRL –40°C to +85°CQuad Flatpack (LQFP) ST-48
AD7663ACP –40⬚C to +85⬚CChip Scale (LFCSP) CP-48
AD7663ACPRL –40⬚C to +85⬚CChip Scale (LFCSP) CP-48
EVAL-AD7663CB
EVAL-CONTROL BRD2

NOTES

1

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

2

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

1

2

Evaluation Board
Controller Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7663 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. B

–5–

AD7663

PIN FUNCTION DESCRIPTION

Pin
No. Mnemonic Type Description

1 AGND P Analog Power Ground Pin.
2 AVDD P Input Analog Power Pin. Nominally 5 V.
3, 6, 7, NC No Connect.

44–48
4 BYTESWAP DI Parallel Mode Selection (8/16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output

on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].

5OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight

binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal
shift register.

8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the

Serial Interface Mode is selected and some bits of the Data bus are used as a Serial Port.

9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs

are in high impedance.

11, 12 D[2:3] or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data

Output Bus.

DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial

Master Read after Convert Mode. These inputs, part of the Serial Port, are used to slow down,
if desired, the internal serial clock that clocks the data output. In the other serial modes, these
pins are high impedance outputs.

13 D[4] DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.

or EXT/INT When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for

choosing the internal or an external data clock, called respectively, Master and Slave Modes.
With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT
set to a logic HIGH, output data is synchronized to an external clock signal connected to the
SCLK input, and external clock is gated by CS.

14 D[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.

or INVSYNC When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of

the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.

15 D[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.

or INVSCLK When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal.

It is active in both master and slave mode.

16 D[7] DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.

or RDC/SDIN When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data

input or a read mode selection input, depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion
results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence.

When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is
HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW,

the data can be output on SDOUT only when the conversion is complete.
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host

interface (5 V or 3 V).
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.

–6–

REV. B

AD7663

PIN FUNCTION DESCRIPTION (continued)

Pin
No. Mnemonic Type Description

21 D[8] DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.

or SDOUT When SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output

synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7663 provides
the conversion result, MSB first, from its internal shift register. The Data format is determined
by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both
edges of SCLK.

In serial mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge.

22 D[9] DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.

or SCLK When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input or

output, dependent upon the logic state of the EXT/INT pin. The active edge where the data
SDOUT is updated depends upon the logic state of the INVSCLK pin.

23 D[10] DO When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.

or SYNC When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output frame

synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while
SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is
driven LOW and remains LOW while SDOUT output is valid.

24 D[11] DO When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.

or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as

an incomplete read error flag. In Slave Mode, when a data read is started and not complete when
the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.

25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs

are in high impedance.

29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the

conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data-ready clock signal.

30 DGND P Must Be Tied to Digital Ground.
31 RD DI Read Data. When CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled.
32 CS DI Chip Select. When CS and RD are both LOW, the Interface Parallel or Serial Output Bus is

enabled. CS is also used to gate the external clock.

33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7663. Current conversion, if any, is aborted.

If not used, this pin could be tied to DGND.

34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions

are inhibited after the current one is completed.

35 CNVST DI Start Conversion. If CNVST is HIGH when the acquisition phase (t

edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion.
This mode is the most appropriate if low sampling jitter is desired. If CNVST is LOW when the
acquisition phase (t

) is complete, the internal sample-and-hold is put into the hold state and a

8

conversion is immediately started.
36 AGND P Must Be Tied to Analog Ground.
37 REF AI Reference Input Voltage .
38 REFGND AI Reference Input Analog Ground.
39 INGND AI Analog Input Ground.
40, 41, INA, INB, AI Analog Inputs. Refer to Table I for input range configuration.

42, 43 INC, IND

NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power

) is complete, the next falling

8

REV. B

–7–

AD7663

DEFINITION OF SPECIFICATIONS
Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It is
often specified in terms of resolution for which no missing codes
are guaranteed.

Full-Scale Error

The last transition (from 011 . . . 10 to 011 ...11 in twos
complement coding) should occur for an analog voltage 1 1/2 LSB
below the nominal full scale (2.499886 V for the ±2.5 V range).
The full-scale error is the deviation of the actual level of the last
transition from the ideal level.

Bipolar Zero Error

The difference between the ideal midscale input voltage (0 V) and
the actual voltage producing the midscale output code.

Unipolar Zero Error

In Unipolar Mode, the first transition should occur at a level
1/2 LSB above analog ground. The unipolar zero error is the
deviation of the actual transition from that point.

Spurious-Free Dynamic Range (SFDR)

The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

A measurement of the resolution with a sine wave input. It is
related to S/(N+D) by the following formula:

ENOB S N D

and is expressed in bits.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the first five harmonic components to
the rms value of a full-scale input signal, expressed in decibels.

Signal-to-Noise Ratio (SNR)

The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist fre­quency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (S/[N+D])

The ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
S/(N+D) is expressed in decibels.

Aperture Delay

A measure of the acquisition performance measured from the
falling edge of the CNVST input to when the input signal is
held for a conversion.

Transient Response

The time required for the AD7663 to achieve its rated accuracy
after a full-scale step function is applied to its input.

=+

[]

()

-

176 602..

dB

)

–8–

REV. B

3.0

0033

1800

6802

6745

1000

400

8000

7000

6000

5000

4000

3000

2000

1000

0

7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8004 8005

COUNTS

CODE IN HEXA

2.5

2.0

1.5

1.0

0.5

0

–0.5

INL – LSB

–1.0

–1.5

–2.0

–2.5

–3.0

0 16384 32768 49152 65536

CODE

TPC 1. Integral Nonlinearity vs. Code

Typical Performance Characteristics–

TPC 4. Histogram of 16,384 Conversions of a DC Input
at the Code Transition

AD7663

50

45

40

35

30

25

20

NUMBER OF UNITS

15

10

5

0

0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.1 2.7

TPC 2. Typical Positive INL Distribution (446 Units)

80

70

60

50

40

30

NUMBER OF UNITS

20

REV. B

10

0

–3 –2.7 –2.4 –2.1 –1.8 –1.5 –1.2 –0.9 –0.6 –0.3

TPC 3. Typical Negative INL Distribution (446 Units)

POSITIVE INL – LSB

NEGATIVE INL – LSB

9000

8000

7000

6000

5000

4000

COUNTS

3000

2000

1000

002

0

7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006

233

8032

3944

CODE IN HEXA

3902

271

000

TPC 5. Histogram of 16,384 Conversions of a DC Input
at the Code Center

–0

–20

–40

–60

–80

–100

–120

–140

AMPLITUDE – dB OF FULL SCALE

–160

–180

0 25 50 75 100 125

FREQUENCY – kHz

4096 POINT FFT
FS = 250kHz
f

= 45kHz, –0.5dB

IN

SNR = 90.1dB
SINAD = 89.8dB
THD = –100.5dB
SFDR = 102.7dB

TPC 6. FFT Plot

–9–

AD7663

–60

–65

–70

–75

–80

–85

–90

–95

–100

–105

–110

–115

110

105

100

95

90

85

80

75

70

65

60

1 10 100 1000

THD, HARMONICS – dB

SFDR – dB

FREQUENCY – kHz

SFDR

THD

THIRD HARMONIC

SECOND HARMONIC

100

95

SNR

90

SINAD

85

80

SNR AND S/[N+D] – dB

75

70

1 10 100 1000

FREQUENCY – kHz

ENOB

TPC 7. SNR, S/(N+D), and ENOB vs. Frequency

92

90

88

SNR – (REFERRED TO FULL SCALE) – dB

86

–80 –70 –60 –50 –40 –30 –20 –10 0

INPUT LEVEL – dB

TPC 8. SNR vs. Input Level

16.0

15.5

15.0

14.5

14.0

13.5

13.0

ENOB – Bits

TPC 10. THD, Harmonics, and SFDR vs. Frequency

–60

–70

–80

–90

–100

–110

–120

–130

THD, HARMONICS – dB

–140

–150

–160

–60 –50 –40 –30 –20 –10 0

THD

SECOND HARMONIC

INPUT LEVEL – dB

THIRD HARMONIC

TPC 11. THD, Harmonics vs. Input Level

96

THD

93

90

SNR – dB

87

84

–55 –35 –15 5 25 45 65 85 105 125

TPC 9. SNR and THD vs. Temperature

SNR

TEMPERATURE – C

–98

–100

–102

–104

THD – dB

–10–

50

40

30

DELAY – ns

20

12

t

10

0

050100 150 200

CL – pF

TPC 12. Typical Delay vs. Load Capacitance, C

L

REV. B

AD7663

100000

10000

1000

100

10

1

0.1

OPERATING CURRENTS – A

0.01

0.001
1 10 100 1000 10000 100000 1000000

SAMPLING RATE – SPS

AV DD

DVD D

OVD D

TPC 13. Operating Currents vs. Sample Rate

500

450

400

350

300

250

200

150

100

50

POWER-DOWN OPERATING CURRENTS – nA

0
–55 –35 –15 5 25 45 65 85 105

TEMPERATURE – C

OVD D

DVD D

AV DD

TPC 14. Power-Down Operating Currents vs. Temperature

10

8

6

LSB

–2

–8

–10

4

2

0

–4

–6

+FS

–55 125–35

–FS

OFFSET

–15 5 25 456585105

TEMPERATURE – C

TPC 15. +FS, Offset, and –FS vs. Temperature

CIRCUIT INFORMATION

The AD7663 is a fast, low power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7663 is capable of
converting 250,000 samples per second (250 kSPS) and allows
power saving between conversions. When operating at 100 SPS,
for example, it consumes typically only 15 µW. This feature
makes the AD7663 ideal for battery-powered applications.

The AD7663 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any pipeline
or latency, making it ideal for multiple multiplexed channel
applications.

It is specified to operate with both bipolar and unipolar input
ranges by changing the connection of its input resistive scaler.

The AD7663 can be operated from a single 5 V supply and can be
interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead
LQFP package or a 48-lead LFCSP package that combines space
savings and flexible configurations as either serial or parallel inter­face. The AD7663 is pin-to-pin compatible with the AD7660.

CONVERTER OPERATION

The AD7663 is a successive approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The input analog signal is
first scaled down and level shifted by the internal input resistive
scaler, which allows both unipolar ranges (0 V to 2.5 V, 0 V to 5 V,
and 0 V to 10 V) and bipolar ranges (±2.5 V, ±5 V, and ±10 V).
The output voltage range of the resistive scaler is always 0 V to

2.5 V. The capacitive DAC consists of an array of 16 binary
weighted capacitors and an additional “LSB” capacitor. The
comparator’s negative input is connected to a “dummy” capacitor
of the same value as the capacitive DAC array.

During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND
via SW

. All independent switches are connected to the output

A

of the resistive scaler. Thus, the capacitor array is used as a
sampling capacitor and acquires the analog signal. Similarly, the
dummy capacitor acquires the analog signal on INGND input.

When the acquisition phase is complete and the CNVST input
goes or is LOW, a conversion phase is initiated. When the conver­sion phase begins, SW

and SWB are opened first. The capacitor

A

array and the dummy capacitor are then disconnected from the
inputs and connected to the REFGND input. Therefore, the differ­ential voltage between the output of the resistive scaler and INGND
captured at the end of the acquisition phase is applied to the
comparator inputs, causing the comparator to become unbalanced.

By switching each element of the capacitor array between
REFGND or REF, the comparator input varies by binary
weighted voltage steps (V

REF

/2, V

REF

/4 . . .V

/65,536). The

REF

control logic toggles these switches, starting with the MSB first,
in order to bring the comparator back into a balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings the BUSY output LOW.

REV. B

–11–

AD7663

111...111

111...110

111...101

ADC CODE – Straight Binary

000...010

000...001

000...000

4R

IND

4R

INC

2R

INB

INA

–FS + 0.5 LSB

REF

REFGND

MSB

16,384C

R

INGND

32,768C

4C

2C

CC

65,536C

LSB

SW

SW

B

A

COMP

SWITCHES

CONTROL

CONTROL

LOGIC

CNVST

BUSY

OUTPUT

CODE

Figure 3. ADC Simplified Schematic

Transfer Functions

Using the OB/2C digital input, the AD7663 offers two output
codings: straight binary and twos complement. The ideal transfer
characteristic for the AD7663 is shown in Figure 4 and Table III.

TYPICAL CONNECTION DIAGRAM

Figure 5 shows a typical connection diagram for the AD7663.
Different circuitry shown on this diagram is optional and is
discussed in the figure’s notes.

Analog Inputs

The AD7663 is specified to operate with six full-scale analog
input ranges. Connections required for each of the four analog

–FS + 1 LSB–FS

ANALOG INPUT

+FS – 1 LSB

+FS – 1.5 LSB

inputs, IND, INC, INB, and INA, and the resulting full-scale
ranges are shown in Table I. The typical input impedance for
each analog input range is also shown.

Figure 4. ADC Ideal Transfer Function

Table III. Output Codes and Ideal Input Voltages

Digital Output
Code (Hexa)
Straight Twos

Description Analog Input Binary Complement

1

Full-Scale Range
Least Significant Bit 305.2 µV 152.6 µV 76.3 µV 152.6 µV 76.3 µV 38.15 µV
FSR – 1 LSB 9.999695 V 4.999847 V 2.499924 V 9.999847 V 4.999924 V 2.499962 V FFFF

±10 V ±5 V ±2.5 V 0 V to 10 V 0 V to 5 V 0 V to 2.5 V

2

7FFF

2

Midscale + 1 LSB 305.2 µV 152.6 µV 76.3 µV 5.000153 V 2.570076 V 1.257038 V 8001 0001
Midscale 0 V 0 V 0 V 5 V 2.5 V 1.25 V 8000 0000
Midscale – 1 LSB –305.2 µV –152.6 µV –76.3 µV 4.999847 V 2.499924 V 1.249962 V 7FFF FFFF

–FSR + 1 LSB –9.999695 V –4.999847 V –2.499924 V 152.6 µV 76.3 µV 38.15 µV 0001 8001
–FSR –10 V –5 V –2.5 V 0 V 0 V 0 V 000038000

NOTES

1

Values with REF = 2.5 V, with REF = 3 V, all values will scale linearly.

2

This is also the code for an overrange analog input.

3

This is also the code for an underrange analog input.

3

–12–

REV. B

AD7663

ADR421

2.5V REF
NOTE 1

ANALOG

INPUT

(10V)

ANALOG

SUPPLY

(5V)

100nF

NOTE 3

1M

++

10F 100nF

+

50k

C

REF

NOTE 2

100

NOTE 7

AVDD

AGND DGND DVDD OVDD OGND

REF

REFGND

100nF10F

AD7663

U2

+

10F

+

100nF

AD8031

NOTE 4

50

U1

NOTE 5

+

AD8021

NOTES

1. SEE VOLTAGE REFERENCE INPUT SECTION.

2. WITH THE RECOMMENDED VOLTAGE REFERENCES, C

3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.

4. FOR BIPOLAR RANGE ONLY. SEE SCALER REFERENCE INPUT SECTION.

5. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.

6. WITH 0V TO 2.5V RANGE ONLY. SEE ANALOG INPUTS SECTION.

7. OPTION. SEE POWER SUPPLY SECTION.

8. OPTIONAL LOW JITTER CNVST. SEE CONVERSION CONTROL SECTION.

15

2.7nF

NOTE

6

C

C

INA

IND

INGND

INB

INC

IS 47F. SEE VOLTAGE REFERENCE INPUT SECTION.

REF

DVDD

SCLK

SDOUT

BUSY

CNVST

OB/2C

SER/PAR

CS
RD

BYTESWAP

RESET

PD

+

100nF 10F

50

NOTE 8

DVDD

DIGITAL SUPPLY
(3.3V OR 5V)

SERIAL

PORT

D

C/P/DSP

CLOCK

Figure 5. Typical Connection Diagram (±10 V Range Shown)

Figure 6 shows a simplified analog input section of the AD7663.

AVDD

IND

INC

INB

INA

AGND

4R

4R

2R

R

R = 1.28k

R1

C

S

Figure 6. Simplified Analog Input

The four resistors connected to the four analog inputs form a resis­tive scaler that scales down and shifts the analog input range to a
common input range of 0 V to 2.5 V at the input of the switched
capacitive ADC.

By connecting the four inputs INA, INB, INC, and IND to the
input signal itself, the ground, or a 2.5 V reference, other analog
input ranges can be obtained.

The diodes shown in Figure 6 provide ESD protection for the four
analog inputs. The inputs INB, INC, and IND have a high voltage
protection (–11 V to +30 V) to allow wide input voltage range.
Care must be taken to ensure that the analog input signal never
exceeds the absolute ratings on these inputs, including INA
(0 V to 5 V). This will cause these diodes to become forward­biased and start conducting current. These diodes can handle a
forward-biased current of 120 mA maximum. For instance, when
using the 0 V to 2.5 V input range, these conditions could even­tually occur on the input INA when the input buffer’s (U1) supplies
are different from AVDD. In such cases, an input buffer with a
short-circuit current limitation can be used to protect the part.

This analog input structure allows the sampling of the differential
signal between the output of the resistive scaler and INGND. Unlike
other converters, the INGND input is sampled at the same time as
the inputs. By using this differential input, small signals common
to both inputs are rejected as shown in Figure 7, which represents
the typical CMRR over frequency. For instance, by using INGND
to sense a remote signal ground, the difference of ground potentials
between the sensor and the local ADC ground is eliminated.

REV. B

–13–

AD7663

75

70

65

60

55

CMRR – dB

50

45

40

35

0 10 100 1000

FREQUENCY – kHz

Figure 7. Analog Input CMRR vs. Frequency

During the acquisition phase for ac signals, the AD7663 behaves
like a one-pole RC filter consisting of the equivalent resistance of
the resistive scaler R/2 in series with R1 and C

. The resistor R1

S

is typically 2700 W and is a lumped component made up of some
serial resistors and the on-resistance of the switches. The capacitor

is typically 60 pF and is mainly the ADC sampling capacitor.

C

S

This one-pole filter with a typical –3 dB cutoff frequency of
800 kHz reduces undesirable aliasing effects and limits the noise
coming from the inputs.

Except when using the 0 V to 2.5 V analog input voltage range,
the AD7663 has to be driven by a very low impedance source to
avoid gain errors. That can be done by using a driver amplifier
whose choice is eased by the primarily resistive analog input
circuitry of the AD7663.

When using the 0 V to 2.5 V analog input voltage range, the input
impedance of the AD7663 is very high so the AD7663 can be
driven directly by a low impedance source without gain error.
That allows, as shown in Figure 5, putting an external one-pole
RC filter between the output of the amplifier output and the ADC
analog inputs to even further improve the noise filtering by the
AD7663 analog input circuit. However, the source impedance
has to be kept low because it affects the ac performances, especially
the total harmonic distortion (THD). The maximum source
impedance depends on the amount of THD that can be tolerated.
The THD degradation is a function of the source impedance
and the maximum input frequency as shown in Figure 8.

–70

–80

R = 100



–90

THD

–100

–110

10

R = 50

FREQUENCY – kHz

R = 11

100 1000

Figure 8. THD vs. Analog Input Frequency and Input
Resistance (0 V to 2.5 V Only)

–14–

Driver Amplifier Choice

Although the AD7663 is easy to drive, the driver amplifier needs
to meet at least the following requirements:

•

The driver amplifier and the AD7663 analog input circuit
have to be able, together, to settle for a full-scale step of the
capacitor array at a 16-bit level (0.0015%). In the amplifier’s
data sheet, the settling at 0.1% to 0.01% is more commonly
specified. It could significantly differ from the settling time at
16-bit level and, therefore, it should be verified prior to the
driver selection. The tiny op amp AD8021, which combines
ultralow noise and a high gain bandwidth, meets this settling
time requirement even when used with a high gain up to 13.

•

The noise generated by the driver amplifier needs to be kept
as low as possible in order to preserve the SNR and transition
noise performance of the AD7663. The noise coming from
the driver is first scaled down by the resistive scaler according
to the analog input voltage range used, and is then filtered by
the AD7663 analog input circuit one-pole, low-pass filter
made by (R/2 + R1) and C

. The SNR degradation due to

S

the amplifier is

SNR

LOSS

Ê
Á

Á

20

=

log

Á
Á

784

Á
Ë

28

25

Ne

.

Ê

p

f

+

Á

dB

3

–

2

FSR

Ë

ˆ
˜

˜
˜

2

ˆ

˜

N

˜

˜

¯

¯

where:

is the –3 dB input bandwidth in MHz of the AD7663

f

–3 dB

(0.8 MHz) or the cut-off frequency of the input filter
if any used (0 V to 2.5 V range).

N is the noise factor of the amplifier (1 if in buffer

configuration).

e

is the equivalent input noise voltage of the op amp

N

in nV/Hz

1/2

.

FSR is the full-scale span (i.e., 5 V for ±2.5 V range).

For instance, when using the 0 V to 2.5 V range, a driver
like the AD8610 with an equivalent input noise of 6 nV/÷Hz
and configured as a buffer, thus with a noise gain of 1, the
SNR degrades by only 0.24 dB.

•

The driver needs to have a THD performance suitable to
that of the AD7663. TPC 10 gives the THD versus frequency
that the driver should preferably exceed.

The AD8021 meets these requirements and is usually appropri­ate for almost all applications. The AD8021 needs an external
compensation capacitor of 10 pF. This capacitor should have good
linearity as an NPO ceramic or mica type.

The AD8022 could also be used where a dual version is needed
and gain of 1 is used.

The AD829 is another alternative where high frequency (above
100 kHz) performance is not required. In a gain of 1, it requires
an 82 pF compensation capacitor.

The AD8610 is also another option where low bias current is
needed in low frequency applications.

REV. B

AD7663

110

105

100

95

90

85

80

75

70

65

60

55

50

1 10 100 1000

PSRR – dB

FREQUENCY – kHz

Voltage Reference Input

The AD7663 uses an external 2.5 V voltage reference.

The voltage reference input REF of the AD7663 has a dynamic
input impedance; it should therefore be driven by a low impedance
source with an efficient decoupling between REF and REFGND
inputs. This decoupling depends on the choice of the voltage
reference but usually consists of a 1 µF ceramic capacitor and a
low ESR tantalum capacitor connected to the REF and REFGND
inputs with minimum parasitic inductance. 47 µF is an appropriate
value for the tantalum capacitor when used with one of the
recommended reference voltages:

•

The low noise, low temperature drift ADR421 and AD780
voltage reference

•

The low power ADR291 voltage reference

•

The low cost AD1582 voltage reference

For applications using multiple AD7663s, it is more effective to
buffer the reference voltage with a low noise, very stable op amp
like the AD8031.

Care should also be taken with the reference temperature coefficient
of the voltage reference that directly affects the full-scale accu­racy if this parameter matters. For instance, a ±15 ppm/°C
tempco of the reference changes the full scale by ±1 LSB/°C.

Note that V

, as mentioned in the Specification tables, could be

REF

increased to AVDD – 1.85 V. The benefit here is the increased
SNR obtained as a result of this increase. Since the input range is
defined in terms of V

, this would essentially increase the ±REF

REF

range from ±2.5 V to ±3 V and so on with an AVDD above

4.85 V. The theoretical improvement as a result of this increase
in reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical
quantization noise, however, the observed improvement is approxi­mately 1 dB. The AD780 can be selected with a 3 V reference
voltage.

Scaler Reference Input (Bipolar Input Ranges)

When using the AD7663 with bipolar input ranges, the connection
diagram in Figure 5 shows a reference buffer amplifier. This
buffer amplifier is required to isolate the REF pin from the signal
dependent current in the INx pin. A high speed op amp, such as
the AD8031, can be used with a single 5 V power supply with­out degrading the performance of the AD7663. The buffer must
have good settling characteristics and provide low total noise
within the input bandwidth of the AD7663.

Power Supply

The AD7663 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply allows
direct interface with any logic working between 2.7 V and DVDD
+ 0.3 V. To reduce the number of supplies needed, the digital
core (DVDD) can be supplied through a simple RC filter from the
analog supply as shown in Figure 5. The AD7663 is independent
of power supply sequencing, once OVDD does not exceed DVDD
by more than 0.3 V, and thus free from supply voltage induced
latch-up. Additionally, it is very insensitive to power supply
variations over a wide frequency range as shown in Figure 9.

Figure 9. PSRR vs. Frequency

POWER DISSIPATION

The AD7663 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows a significant
power savings when the conversion rate is reduced as shown in
Figure 10. This feature makes the AD7663 ideal for very low
power battery applications.

This does not take into account the power, if any, dissipated by
the input resistive scaler that depends on the input voltage range
used and the analog input voltage even in power-down mode.
There is no power dissipated when the 0 V to 2.5 V is used or
when both the analog input voltage is 0V and a unipolar range,
0V to 5 V or 0 V to 10 V, is used.

It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.

REV. B

–15–

AD7663

100k

10k

1k

100

10

POWER DISSIPATION – ␮W

1

0.1
1

10 100 1k 10k 100k 1M

SAMPLING RATE – SPS

Figure 10. Power Dissipation vs. Sample Rate

CONVERSION CONTROL

Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7663 is controlled by the signal CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion is
complete. The CNVST signal operates independently of CS and
RD signals.

t

2

t

1

CNVST

BUSY

t

3

t

5

MODE

ACQUIRE CONVERT ACQUIRE CONVERT

t

4

t

6

t

7

t

8

Figure 11. Basic Conversion Timing

For a true sampling application, the recommended operation of
the CNVST signal is the following.

CNVST must be held HIGH from the previous falling edge of
BUSY and during a minimum delay corresponding to the acquisi­tion time t

. Then, when CNVST is brought LOW, a conversion is

8

initiated and the BUSY signal goes HIGH until the completion
of the conversion. Although CNVST is a digital signal, it should
be designed with special care with fast, clean edges, and levels
with minimum overshoot and undershoot or ringing. It is a good
thing to shield the CNVST trace with ground and also to add a
low value serial resistor (i.e., 50 W) termination close to the output
of the component that drives this line. For applications where
the SNR is critical, the CNVST signal should have a very low
jitter. To achieve this, some use a dedicated oscillator for
CNVST generation, or at least to clock it with a high frequency,
low jitter clock as shown in Figure 5.

For other applications, conversions can be automatically initiated.
If CNVST is held low when BUSY is low, the AD7663 controls
the acquisition phase and then automatically initiates a new
conversion. By keeping CNVST low, the AD7663 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up, CNVST should be brought low once to initiate the
conversion process. In this mode, the AD7663 could sometimes
run slightly faster than the guaranteed limit of 250 kSPS.

t

9

RESET

BUSY

DATA BUS

t

8

CNVST

Figure 12. RESET Timing

DIGITAL INTERFACE

The AD7663 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7663 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7663
to the host system interface digital supply. Finally, by using the
OB/2C input pin, twos complement and straight binary coding
can be used.

The two signals CS and RD control the interface. When at least
one of these signals is HIGH, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7663 in
multicircuit applications and is held LOW in a single AD7663
design. RD is generally used to enable the conversion result on
the data bus.

CS = RD = 0

t

1

CNVST

t

10

BUSY

DATA BUS

t

3

PREVIOUS CONVERSION DATA NEW DATA

t

4

t

11

Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)

–16–

REV. B

PARALLEL INTERFACE

CS

BYTE

PINS D[15:8]

HI-Z

HIGH BYTE LOW BYTE

HI-Z

HI-Z

HIGH BYTE

LOW BYTE

HI-Z

t

12

t

12

t

13

RD

PINS D[7:0]

The AD7663 is configured to use the parallel interface when
the SER/PAR is held LOW. The data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion as shown, respectively, in
Figures 14 and 15. When the data is read during the conversion,
however, it is recommended that it be read-only during the
first half of the conversion phase. That avoids any potential
feedthrough between voltage transients on the digital interface and
the most critical analog conversion circuitry.

CS

AD7663

Figure 16. 8-Bit Parallel Interface

RD

BUSY

DATA BUS

t

12

CURRENT

CONVERSION

t

13

Figure 14. Slave Parallel Data Timing for Reading (Read
after Convert)

CS = 0

t

CNVST,

RD

BUSY

DATA BUS

t

3

t

12

1

PREVIOUS

CONVERSION

t

t

4

13

Figure 15. Slave Parallel Data Timing for Reading (Read
during Convert)

The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 16, the LSB byte is output on D[7:0] and
the MSB is output on D[15:8] when BYTESWAP is LOW.
When BYTESWAP is HIGH, the LSB and MSB are swapped
and the LSB is output on D[15:8] and the MSB is output on
D[7:0]. By connecting BYTESWAP to an address line, the 16
data bits can be read in two bytes on either D[15:8] or D[7:0].

SERIAL INTERFACE

The AD7663 is configured to use the serial interface when the
SER/PAR is held HIGH. The AD7663 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edge of the data clock.

MASTER SERIAL INTERFACE
Internal Clock

The AD7663 is configured to generate and provide the serial data
clock SCLK when the EXT/INT pin is held LOW. It also generates
a SYNC signal to indicate to the host when the serial data is valid.
The serial clock SCLK and the SYNC signal can be inverted if
desired. Depending on RDC/SDIN input, the data can be read
after each conversion or during the following conversion. Figures 17
and 18 show the detailed timing diagrams of these two modes.

Usually, because the AD7663 has a longer acquisition phase
than the conversion phase, the data is read immediately after
conversion. That makes the mode master, read after conversion,
the most recommended Serial Mode when it can be used.

In Read-during-Conversion Mode, the serial clock and data
toggle at appropriate instants that minimize potential feedthrough
between digital activity and the critical conversion decisions.

In Read-after-Conversion Mode, it should be noted that unlike
in other modes, the signal BUSY returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width. In this mode, if neces­sary, the internal clock can be slowed down by a ratio selected
by the DIVSCLK inputs according to Table II.

REV. B

–17–

AD7663

CS, RD

CNVST

EXT/

= 0

INT

t

3

RDC/SDIN = 0 INVSCLK = INVSYNC = 0

BUSY

SYNC

SCLK

SDOUT

CS, RD

CNVST

BUSY

t

28

t

29

t

14

t

18

t

19

t

20

t

21

t

30

t

24

123 141516

t

15

D2 D1 D0

22

D15 D14

t

23

X

t

16

t

Figure 17. Master Serial Data Timing for Reading (Read after Convert)

EXT/

t

1

= 0

INT

t

3

RDC/SDIN = 1 INVSCLK = INVSYNC = 0

t

25

t

26

t

27

t

SYNC

SCLK

SDOUT

17

t

14

t

15

t

18

t

19

t20t

21

12 3 141516

t

24

D15 D14 D2 D1 D0X

t

16

t

22

t

23

t

25

t

26

t

27

Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)

–18–

REV. B

AD7663

CNVST

CS

SCLK

SDOUTRDC/SDIN

BUSYBUSY

DATA
OUT

AD7663

#1

(DOWNSTREAM)

BUSY
OUT

CNVST

CS

SCLK

AD7663

#2

(UPSTREAM)

RDC/SDIN SDOUT

SCLK IN

CS IN

CNVST IN

SLAVE SERIAL INTERFACE
External Clock

The AD7663 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held HIGH. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS and the data
are output when both CS and RD are LOW. Thus, depending
on CS, the data can be read after each conversion or during the
following conversion. The external clock can be either a continu­ous or discontinuous clock. A discontinuous clock can be either
normally high or normally low when inactive. Figures 19 and 21
show the detailed timing diagrams of these methods.

While the AD7663 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is par­ticularly important during the second half of the conversion
phase because the AD7663 provides error correction circuitry
that can correct for an improper bit decision made during the first
half of the conversion phase. For this reason, it is recommended
that when an external clock is being provided, it is a discontinuous
clock that is toggling only when BUSY is LOW or, more
importantly, that does not transition during the latter half of
BUSY HIGH.

External Discontinuous Clock Data Read after Conversion

This mode is the most recommended of the serial slave modes.
Figure 19 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
LOW, the result of this conversion can be read while both CS and
RD are LOW. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both the rising and falling edge of the clock.

Among the advantages of this method, the conversion performance
is not degraded because there are no voltage transients on the
digital interface during the conversion process.

CS

BUSY

SCLK

SDOUT

SDIN

Figure 19. Slave Serial Data Timing for Reading (Read after Convert)

EXT/INT = 1

t

35

t36 t

37

123 1415161718

t

31

X

D15 D14 D1

t

16

X15 X14 X13 X1 X0 Y15 Y14

t

33

t

32

D13

t

34

INVSCLK = 0

RD = 0

D0

X15 X14

Another advantage is to be able to read the data at any speed up
to 40 MHz, which accommodates both slow digital host interface
and the fastest serial reading.

Finally, in this mode only, the AD7663 provides a “daisy-chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when desired as, for instance, in
isolated multiconverter applications.

An example of the concatenation of two devices is shown in
Figure 20. Simultaneous sampling is possible by using a com­mon CNVST signal. It should be noted that the RDC/SDIN
input is latched on the opposite edge of SCLK of the one used
to shift out the data on SDOUT. Therefore, the MSB of the
“upstream” converter just follows the LSB of the “downstream”
converter on the next SCLK cycle.

Figure 20. Two AD7663s in a Daisy-Chain Configuration

REV. B

–19–

AD7663

INVSCLK = 0

CS

CNVST

BUSY

SCLK

SDOUT

EXT/INT = 1

t

3

t

16

t

35

t

t

36

37

12 3 141516

t

31

t

32

Figure 21. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)

External Clock Data Read during Conversion

Figure 21 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are LOW, the result
of the previous conversion can be read. The data is shifted out
MSB first with 16 clock pulses, and is valid on both the rising and
the falling edge of the clock. The 16 bits have to be read before
the current conversion is complete. If that is not done, RDERROR
is pulsed HIGH and can be used to interrupt the host interface
to prevent an incomplete data reading. There is no daisy-chain
feature in this mode, and RDC/SDIN input should always be
tied either HIGH or LOW.

To reduce performance degradation due to digital activity, a
fast discontinuous clock of at least 25 MHz is recommended to
ensure that all the bits are read during the first half of the conver­sion phase.

MICROPROCESSOR INTERFACING

The AD7663 is ideally suited for traditional dc measurement
applications supporting a microprocessor and ac signal processing
applications interfacing to a digital signal processor. The
AD7663 is designed to interface with either a parallel 8-bit or
16-bit wide interface or with a general-purpose Serial Port or I/O
Ports on a microcontroller. A variety of external buffers can be
used with the AD7663 to prevent digital noise from coupling into
the ADC. The following sections illustrate the use of the AD7663
with an SPI equipped microcontroller, the ADSP-21065L and
ADSP-218x signal processors.

SPI Interface (MC68HC11)

Figure 22 shows an interface diagram between the AD7663 and an
SPI-equipped microcontroller, such as the MC68HC11. To
accommodate the slower speed of the microcontroller, the AD7663
acts as a slave device and data must be read after conversion. This
mode also allows the daisy-chain feature. The convert command
could be initiated in response to an internal timer interrupt. The
reading of output data, one byte at a time if necessary, could be
initiated in response to the end-of-conversion signal (BUSY going
LOW) using an interrupt line of the microcontroller. The serial

RD = 0

D1 D0X D15 D14 D13

peripheral interface (SPI) on the MC68HC11 is configured for
Master Mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock
Phase Bit (CPHA) = 1, and SPI interrupt enable (SPIE) = 1
by writing to the SPI Control Register (SPCR). The IRQ is
configured for edge-sensitive-only operation (IRQE = 1 in
OPTION register).

DVDD

AD7663*

SER/PAR
EXT/INT

CS
RD

INVSCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

BUSY

SDOUT

SCLK

CNVST

MC68HC11*

IRQ

MISO/SDI

SCK

I/O PORT

Figure 22. Interfacing the AD7663 to SPI Interface

ADSP-21065L in Master Serial Interface

As shown in Figure 23, the AD7663 can be interfaced to the
ADSP-21065L using the serial interface in Master Mode without
any glue logic required. This mode combines the advantages of
reducing the wire connections and being able to read the data during
or after conversion at maximum speed transfer (DIVSCLK[0:1]
both low.

The AD7663 is configured for the Internal Clock Mode (EXT/INT
low) and acts therefore as the master device. The convert com­mand can be generated by an external low jitter oscillator or, as
shown, by a FLAG output of the ADSP-21065L, or by a frame
output TFS of one Serial Port of the ADSP-21065L that can be used
like a timer. The Serial Port on the ADSP-21065L is configured
for external clock (IRFS = 0), rising edge active (CKRE = 1),
external late framed sync signals (IRFS = 0, LAFS = 1,
RFSR = 1), and active HIGH (LRFS = 0). The Serial Port of
the ADSP-21065L is configured by writing to its receive control
register (SRCTL)—see ADSP-2106x SHARC User’s Manual.

–20–

REV. B

AD7663

Because the Serial Port within the ADSP-21065L will be seeing a
discontinuous clock, an initial word reading has to be done after
the ADSP-21065L has been reset to ensure that the Serial Port
is properly synchronized to this clock during each following data
read operation.

DVDD

AD7663*

SER/PAR

RDC/SDIN

RD
EXT/INT
CS

INVSYNC

INVSCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

SYNC

SDOUT

SCLK

CNVST

ADSP-21065L*

SHARC

RFS

DR

RCLK

FLAG OR TFS

Figure 23. Interfacing to the ADSP-21065L Using the
Serial Master Mode

APPLICATION HINTS
Layout

The AD7663 has very good immunity to noise on the power
supplies as can be seen in Figure 9. However, care should still be
taken with regard to grounding layout.

The printed circuit board that houses the AD7663 should be
designed so the analog and digital sections are separated and con­fined to certain areas of the board. This facilitates the use of
ground planes that can be easily separated. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7663 or at least as close as possible to the
AD7663. If the AD7663 is in a system where multiple devices
require analog-to-digital ground connections, the connection
should still be made at one point only, a star ground point that
should be established as close as possible to the AD7663.

It is recommended to avoid running digital lines under the device
as these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7663 to avoid noise cou­pling. Fast switching signals like CNVST or clocks should be
shielded with digital ground to avoid radiating noise to other
sections of the board and should never run near analog signal paths.
Crossover of digital and analog signals should be avoided. Traces

on different but close layers of the board should run at right
angles to each other. This will reduce the effect of feedthrough
through the board.

The power supply lines to the AD7663 should use as large a trace
as possible to provide low impedance paths and reduce the effect of
glitches on the power supply lines. Good decoupling is also impor­tant to lower the supplies’ impedance presented to the AD7663
and to reduce the magnitude of the supply spikes. Decoupling
ceramic capacitors, typically 100 nF, should be placed on all of
the power supply pins AVDD, DVDD, and OVDD close to, and
ideally right up against these pins and their corresponding ground
pins. Additionally, low ESR 10 µF capacitors should be located
in the vicinity of the ADC to further reduce low frequency ripple.

The DVDD supply of the AD7663 can be either a separate
supply or come from the analog supply, AVDD, or from the
digital interface supply, OVDD. When the system digital supply
is noisy or fast switching digital signals are present, it is recom­mended, if no separate supply is available, to connect the DVDD
digital supply to the analog supply, AVDD, through an RC filter
as shown in Figure 5, and to connect the system supply to the
interface digital supply OVDD and the remaining digital circuitry.
When DVDD is powered from the system supply, it is useful to
insert a bead to further reduce high frequency spikes.

The AD7663 has five different ground pins: INGND, REFGND,
AGND, DGND, and OGND. INGND is used to sense the
analog input signal. REFGND senses the reference voltage and
should be a low impedance return to the reference because it
carries pulsed currents. AGND is the ground to which most internal
ADC analog signals are referenced. This ground must be con­nected with the least resistance to the analog ground plane. DGND
must be tied to the analog or digital ground plane depending on
the configuration. OGND is connected to the digital system ground.

The layout of the decoupling of the reference voltage is important.
The decoupling capacitor should be close to the ADC and con­nected with short and large traces to minimize parasitic inductances.

Evaluating the AD7663 Performance

A recommended layout for the AD7663 is outlined in the evalu­ation board for the AD7663. The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the Eval­Control Board.

REV. B

–21–

AD7663

OUTLINE DIMENSIONS

48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)

Dimensions shown in millimeters

1.45

1.40

1.35

0.15

0.05

PIN 1
INDICATOR

10

6
2

SEATING
PLANE

ROTATED 90 CCW

VIEW A

0.10 MAX
COPLANARITY

0.75

0.60

0.45

SEATING

PLANE

0.20

0.09

7

3.5
0

COMPLIANT TO JEDEC STANDARDS MS-026BBC

1.60
MAX

VIEW A

1

12

0.50
BSC

48

(PINS DOWN)

13

48-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-48)

Dimensions shown in millimeters

7.00

BSC SQ

0.60 MAX

37

36

0.60 MAX

9.00 BSC
SQ

PIN 1

TOP VIEW

0.30

0.23

0.18

37

36

7.00

BSC SQ

25

24

0.27

0.22

0.17

PIN 1

48

INDICATOR

1

1.00

0.90

0.80

0.20
REF

12 MAX

SEATING
PLANE

TOP

VIEW

0.80 MAX

0.65 NOM

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

6.75

BSC SQ

COPLANARITY

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.08

BOTTOM

VIEW

25

24

5.50
REF

13

5.25
SQ

5.10

4.95

12

PADDLE CONNECTED TO AGND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES

–22–

REV. B

AD7663

Revision History

Location Page

4/03—Data Sheet changed from REV. A to REV. B.

Changes to PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5/02—Data Sheet changed from REV. 0 to REV. A.

Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Chart added to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Edits to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Addition of TPC 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Edits to CIRCUIT INFORMATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Edits to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Edits to Voltage Reference Input and Power Supply sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Edits to ADSP-21065L in Master Serial Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

New Package Outline Added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

REV. B

–23–

C01845–0–5/03(B)

–24–