Datasheet AD7656-1, AD7657-1, AD7658-1 Datasheet (ANALOG DEVICES)

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250 kSPS, 6-Channel, Simultaneous

Sampling, Bipolar, 16-/14-/12-Bit ADC

FEATURES

Pin and software compatible with AD7656/AD7657/AD7658

featuring reduced decoupling requirements 6 independent ADCs True bipolar analog inputs Pin-/software-selectable ranges: ±10 V, ±5 V Fast throughput rate: 250 kSPS iCMOS process technology Low power

140 mW at 250 kSPS with 5 V supplies High noise performance with wide bandwidth

88 dB SNR at 10 kHz input frequency On-chip reference and reference buffers High speed parallel, serial, and daisy-chain interface modes High speed serial interface

SPI/QSPI™/MICROWIRE™/DSP compatible Standby mode: 25 μW max 64-lead LQFP

APPLICATIONS

Power line monitoring and measuring systems Instrumentation and control systems Multiaxis positioning systems

AD7656-1/AD7657-1/AD7658-1

FUNCTIONAL BLOCK DIAGRAM

BUF

CONVST

CLK OSC

REF

T/H

CONVST B CONVST C

CONTROL

LOGIC

16-/14-/

12-BIT SAR

16-/14-/

12-BIT SAR

16-/14-/

12-BIT SAR

16-/14-/

12-BIT SAR

16-/14-/

12-BIT SAR

16-/14-/

12-BIT SAR

AD7656-1/AD7657-1/AD7658-1

AGND

OUTPUT

DRIVERS

OUTPUT

DRIVERS

OUTPUT

DRIVERS

OUTPUT

DRIVERS

DGND

Figure 1.

VCCDV

CS SER/PAR SEL V

DRIVE

STBY

DB8/DOUT A

DB6/SCLK

DB9/DOUT B

DB10/DOUT C

DATA/ CONTROL LINES

WR/REF

07017-001

EN/DIS

GENERAL DESCRIPTION

The AD7656-1/AD7657-1/AD7658-11 are reduced decoupling pinand software-compatible versions of AD7656/AD7657/AD7658. The AD7656-1/AD7657-1/AD7658-1 devices contain six 16-/ 14-/12-bit, fast, low power successive approximation ADCs in a package designed on the iCMOS® process (industrial CMOS). iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, which dramatically reduces power consumption and package size.

The AD7656-1/AD7657-1/AD7658-1 feature throughput rates of up to 250 kSPS. The parts contain low noise, wide bandwidth track-and-hold amplifiers that can handle input frequencies up to 4.5 MHz.

Protected by U.S. Patent No. 6,731,232.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The conversion process and data acquisition are controlled using the CONVST signals and an internal oscillator. Three CONVST pins (CONVST A, CONVST B, and CONVST C) allow independent, simultaneous sampling of the three ADC pairs. The AD7656-1/AD7657-1/AD7658-1 have a high speed parallel and serial interface, allowing the devices to interface with microprocessors or DSPs. When the serial interface is selected, each part has a daisy-chain feature that allows multiple ADCs to connect to a single serial interface. The AD7656-1/AD7657-1/ AD7658-1 can accommodate true bipolar input signals in the ±4 × V

and ±2 × V

REF

ranges. Each AD7656-1/AD7657-1/

REF

AD7658-1 also contains an on-chip 2.5 V reference.

PRODUCT HIGHLIGHTS

1. Six 16-/14-/12-bit, 250 kSPS ADCs on board.

2. Six true bipolar, high impedance analog inputs.

3. High speed parallel and serial interfaces.

4. Reduced decoupling requirements and reduced bill of

materials cost compared with the AD7656/AD7657/ AD7658 devices.

AD7656-1/AD7657-1/AD7658-1

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AD7656-1 ...................................................................................... 3

AD7657-1 ...................................................................................... 5

AD7658-1 ...................................................................................... 7

Timing Specifications .................................................................. 9

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 14

Terminology .................................................................................... 18

Theory of Operation ...................................................................... 20

Converter Details ....................................................................... 20

ADC Transfer Function ............................................................. 21

Internal/External Reference ...................................................... 21

Typical Connection Diagram ................................................... 21

Driving the Analog Inputs ........................................................ 22

Interface Options ........................................................................ 22

Application Hints ........................................................................... 29

Layout .......................................................................................... 29

Outline Dimensions ....................................................................... 30

Ordering Guide .......................................................................... 30

REVISION HISTORY

7/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD7656-1/AD7657-1/AD7658-1

SPECIFICATIONS

AD7656-1

= 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, V

REF

10 V to 16.5 V, V T

, unless otherwise noted.

MAX

= −10 V to −16.5 V; for the ±2 × V

range, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; f

REF

Table 1.

Parameter B Version1Y Version1Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 10 kHz sine wave

Signal-to-(Noise + Distortion) (SINAD)2 88 88 dB typ

Signal-to-Noise Ratio (SNR)2 88 88 dB typ

Total Harmonic Distortion (THD)

−90 −90 dB max

−105 −105 dB typ VDD/VSS = ±5 V to ±16.5 V

Peak Harmonic or Spurious Noise (SFDR)2 −100 −100 dB typ

Intermodulation Distortion (IMD)2 fa = 10.5 kHz, fb = 9.5 kHz

Second-Order Terms −112 −112 dB typ

Third-Order Terms −107 −107 dB typ Aperture Delay 10 10 ns max Aperture Delay Matching 4 4 ns max Aperture Jitter 35 35 ps typ Channel-to-Channel Isolation

−100 −100 dB typ f

Full-Power Bandwidth 4.5 4.5 MHz typ @ −3 dB

2.2 2.2 MHz typ @ −0.1 dB

DC ACCURACY

Resolution 16 16 Bits No Missing Codes 15 14 Bits min Integral Nonlinearity

±3 ±3 LSB max

±1 ±1 LSB typ Positive Full-Scale Error Positive Full-Scale Error Matching

±0.8 ±0.8 % FS max ±0.381% FSR typical

±0.35 ±0.35 % FS max

Bipolar Zero-Scale Error2 ±0.048 ±0.023 % FS max ±0.0137% FSR typical Bipolar Zero-Scale Error Matching Negative Full-Scale Error

±0.8 ±0.8 % FS max ±0.381% FSR typical

Negative Full-Scale Error Matching

±0.038 ±0.038 % FS max

±0.35 ±0.35 % FS max

ANALOG INPUT

Input Voltage Ranges ±4 × V ±2 × V

±4 × V

REF

±2 × V

REF

V RNGx bits or RANGE pin = 0

REF

V RNGx bits or RANGE pin = 1

REF

DC Leakage Current ±1 ±1 μA max Input Capacitance

10 10 pF typ ±4 × V

14 14 pF typ ±2 × V

REFERENCE INPUT/OUTPUT

Reference Input Voltage Range 2.5 2.5 V min/max DC Leakage Current ±1 ±1 μA max Input Capacitance

18.5 18.5 pF typ

Reference Output Voltage 2.49/2.51 2.49/2.51 V min/max Long-Term Stability 150 150 ppm typ 1000 hours Reference Temperature Coefficient 25 25 ppm/°C max 6 6 ppm/°C typ

= 2.7 V to 5.25 V; for the ±4 × V

DRIVE

SAMPLE

on unselected channels up to 100 kHz

See Tab le 8 for minimum V each range

range when in track

REF

range when in track

REF

= 1

REF

DIS

EN/

range, VDD =

REF

= 250 kSPS, TA = T

for

DD/VSS

MIN

Rev. 0 | Page 3 of 32

AD7656-1/AD7657-1/AD7658-1

Parameter B Version1Y Version

Unit Test Conditions/Comments

LOGIC INPUTS

Input High Voltage (V Input Low Voltage (V

) 0.7 × V

INH

) 0.3 × V

INL

0.7 × V

DRIVE

0.3 × V

DRIVE

V min

DRIVE

V max

DRIVE

Input Current (IIN) ±10 ±10 μA max Typically 10 nA, VIN = 0 V or V Input Capacitance (CIN)3 10 10 pF max

LOGIC OUTPUTS

Output High Voltage (VOH) V Output Low Voltage (VOL) 0.2 0.2 V max I

− 0.2 V

DRIVE

− 0.2 V min I

DRIVE

= 200 μA

SOURCE

= 200 μA

SINK

Floating-State Leakage Current ±10 ±10 μA max Floating-State Output Capacitance

10 10 pF max

Output Coding Twos complement

CONVERSION RATE

Conversion Time 3.1 3.1 μs max Track-and-Hold Acquisition Time

2, 3

550 550 ns max

Throughput Rate 250 250 kSPS Parallel interface mode only

POWER REQUIREMENTS

VDD 5/15 5/15 V nom min/max For the 4 × V VSS −5/−15 −5/−15 V nom min/max For the 4 × V

range, VDD = 10 V to 16.5 V

REF

range, VDD = −10 V to −16.5 V

REF

AVCC 5 5 V nom DVCC 5 5 V nom V

3/5 3/5 V nom min/max

DRIVE

TOTAL

Normal Mode—Static 18 18 mA max

Normal Mode—Operational 26 26 mA max

ISS (Operational) 0.25 0.25 mA max VSS = −16.5 V, f I

(Operational) 0.25 0.25 mA max VDD = 16.5 V, f

Partial Power-Down Mode 7 7 mA max

Full Power-Down Mode (STBY Pin)

Power Dissipation

Digital inputs = 0 V or V

400 400 μA max

= DVCC = V

= −16.5 V

= 250 kSPS, AVCC = DVCC = V

SAMPLE

= 16.5 V, VSS = −16.5 V

= DVCC = V

= −16.5 V

SCLK on or off, AVCC = DVCC = V V

= 16.5 V, VSS = −16.5 V

= DV

= −16.5 V

= 5.25 V, VDD = 16.5 V,

DRIVE

= 250 kSPS

SAMPLE

= 250 kSPS

SAMPLE

= 5.25 V, VDD = 16.5 V,

DRIVE

= V

= 5.25 V, VDD = 16.5 V,

DRIVE

Normal Mode—Static 94 94 mW max Normal Mode—Operational 140 140 mW max f

= 250 kSPS

SAMPLE

Partial Power-Down Mode 40 40 mW max Full Power-Down Mode (STBY Pin)

The temperature range for the B version is −40°C to +85°C and for the Y version is −40°C to +125°C.

See the Terminology section.

Sample tested during initial release to ensure compliance.

Includes I

AVCC

, I

, and I

VDD

VSS

VDRIVE

DVCC

25 25 μW max

DRIVE

= 5.25 V,

DRIVE

= 5.25 V,

Rev. 0 | Page 4 of 32

AD7656-1/AD7657-1/AD7658-1

AD7657-1

= 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, V

REF

10 V to 16.5 V, V T

, unless otherwise noted.

MAX

= −10 V to −16.5 V; for the ±2 × V

range, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; f

REF

Table 2.

Parameter B Version1Y Version1Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 10 kHz sine wave

Signal-to-(Noise + Distortion) (SINAD)2 82.5 82.5 dB typ Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD)

83.5 83.5 dB typ

−90 −90 dB max

−105 −105 dB typ Peak Harmonic or Spurious Noise (SFDR)

−100 −100 dB typ

Intermodulation Distortion (IMD)2 fa = 10.5 kHz, fb = 9.5 kHz

Second-Order Terms −109 −109 dB typ

Third-Order Terms −104 −104 dB typ Aperture Delay 10 10 ns max Aperture Delay Matching 4 4 ns max Aperture Jitter 35 35 ps typ Channel-to-Channel Isolation

−100 −100 dB typ f

Full-Power Bandwidth 4.5 4.5 MHz typ @ −3 dB

2.2 2.2 MHz typ @ −0.1 dB

DC ACCURACY

Resolution 14 14 Bits No Missing Codes 14 14 Bits min Integral Nonlinearity

±1 ±1 LSB max

±1 ±1 LSB typ Positive Full-Scale Error Positive Full-Scale Error Matching

±0.95 ±0.95 % FS max ±0.27% FSR typical

±0.366 ±0.366 % FS max

Bipolar Zero-Scale Error2 ±0.04 ±0.04 % FS max ±0.016% FSR typical Bipolar Zero-Scale Error Matching Negative Full-Scale Error

±0.95 ±0.95 % FS max ±0.27% FSR typical

Negative Full-Scale Error Matching

±0.0427 ±0.0427 % FS max

±0.366 ±0.366 % FS max

ANALOG INPUT

Input Voltage Ranges ±4 × V ±2 × V

±4 × V

REF

±2 × V

REF

V RNGx bits or RANGE pin = 0

REF

V RNGx bits or RANGE pin = 1

REF

DC Leakage Current ±1 ±1 μA max Input Capacitance

10 10 pF typ ±4 × V

14 14 pF typ ±2 × V

REFERENCE INPUT/OUTPUT

Reference Input Voltage Range 2.5 2.5 V min/max DC Leakage Current ±1 ±1 μA max Input Capacitance

18.5 18.5 pF typ

Reference Output Voltage 2.49/2.51 2.49/2.51 V min/max Long-Term Stability 150 150 ppm typ 1000 hours Reference Temperature Coefficient 25 25 ppm/°C max 6 6 ppm/°C typ

LOGIC INPUTS

Input High Voltage (V Input Low Voltage (V

) 0.7 × V

INH

) 0.3 × V

INL

0.7 × V

DRIVE

0.3 × V

DRIVE

V min

DRIVE

V max

DRIVE

Input Current (IIN) ±10 ±10 μA max Typically 10 nA, VIN = 0 V or V Input Capacitance (CIN)3 10 10 pF max

= 2.7 V to 5.25 V; for the ±4 × V

DRIVE

SAMPLE

on unselected channels up to 100 kHz

See Tab le 8 for minimum V each range

range when in track

REF

range when in track

REF

= 1

DIS

EN/

range, VDD =

REF

= 250 kSPS, TA = T

for

DD/VSS

DRIVE

MIN

Rev. 0 | Page 5 of 32

AD7656-1/AD7657-1/AD7658-1

Parameter B Version1Y Version

Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage (VOH) V Output Low Voltage (VOL) 0.2 0.2 V max I

− 0.2 V

DRIVE

− 0.2 V min I

DRIVE

= 200 μA

SOURCE

= 200 μA

SINK

Floating-State Leakage Current ±10 ±10 μA max Floating-State Output Capacitance

10 10 pF max

Output Coding Twos complement

CONVERSION RATE

Conversion Time 3.1 3.1 μs max Track-and-Hold Acquisition Time

2, 3

550 550 ns max

Throughput Rate 250 250 kSPS Parallel interface mode only

POWER REQUIREMENTS

VDD 5/15 5/15 V nom min/max For the 4 × V VSS −5/−15 −5/−15 V nom min/max For the 4 × V

range, VDD = 10 V to 16.5 V

REF

range, VDD = −10 V to −16.5 V

REF

AVCC 5 5 V nom DVCC 5 5 V nom V

3/5 3/5 V nom min/max

DRIVE

TOTAL

Normal Mode—Static 18 18 mA max

Normal Mode—Operational 26 26 mA max

ISS (Operational) 0.25 0.25 mA max VSS = −16.5 V, f I

(Operational) 0.25 0.25 mA max VDD = 16.5 V, f

Partial Power-Down Mode 7 7 mA max

Full Power-Down Mode (STBY Pin)

Power Dissipation

Digital inputs = 0 V or V

400 400 μA max

= DVCC = V

= −16.5 V

= 250 kSPS, AVCC = DVCC = V

SAMPLE

= 16.5 V, VSS = −16.5 V

= DVCC = V

= −16.5 V

SCLK on or off, AVCC = DVCC = V

= 16.5 V, VSS = −16.5 V

= DV

= −16.5 V

= 5.25 V, VDD = 16.5 V,

DRIVE

= 250 kSPS

SAMPLE

= 250 kSPS

SAMPLE

= 5.25 V, VDD = 16.5 V,

DRIVE

= V

= 5.25 V, VDD = 16.5 V,

DRIVE

Normal Mode—Static 94 94 mW max Normal Mode—Operational 140 140 mW max f

= 250 kSPS

SAMPLE

Partial Power-Down Mode 40 40 mW max Full Power-Down Mode (STBY Pin)

The temperature range for the B version is −40°C to +85°C and for the Y version is −40°C to +125°C.

See the Terminology section.

Sample tested during initial release to ensure compliance.

Includes I

AVCC

, I

, and I

VDD

VSS

VDRIVE

DVCC

25 25 μW max

DRIVE

= 5.25 V,

DRIVE

= 5.25 V,

Rev. 0 | Page 6 of 32

AD7656-1/AD7657-1/AD7658-1

AD7658-1

= 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, V

REF

to 16.5 V, V

= −10 V to −16.5 V; for ±2 × V

range, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; f

REF

unless otherwise noted.

Table 3.

Parameter B Version1Y Version1Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 10 kHz sine wave

Signal-to-(Noise + Distortion) (SINAD)2 73.5 73.5 dB typ

73.5 73.5 dB typ Total Harmonic Distortion (THD)

−88 −88 dB max

−100 −100 dB typ Peak Harmonic or Spurious Noise (SFDR)

−97 −97 dB typ

Intermodulation Distortion (IMD)2 fa = 10.5 kHz, fb = 9.5 kHz

Second-Order Terms −106 −106 dB typ

Third-Order Terms −101 −101 dB typ Aperture Delay 10 10 ns max Aperture Delay Matching 4 4 ns max Aperture Jitter 35 35 ps typ Channel-to-Channel Isolation

−100 −100 dB typ f

Full-Power Bandwidth 4.5 4.5 MHz typ @ −3 dB

2.2 2.2 MHz typ @ −0.1 dB

DC ACCURACY

Resolution 12 12 Bits No Missing Codes 12 12 Bits min Differential Nonlinearity ±0.7 ±0.7 LSB max Integral Nonlinearity Positive Full-Scale Error Positive Full-Scale Error Matching

±0.5 ±0.5 LSB max

±0.95 ±0.95 % FS max ±0.317% FSR typical

±0.366 ±0.366 % FS max

Bipolar Zero-Scale Error2 ±2 ±2 LSB max ±0.0125% FSR typical Bipolar Zero-Scale Error Matching Negative Full-Scale Error

±0.95 ±0.95 % FS max ±0.317% FSR typical

Negative Full-Scale Error Matching

±2 ±2 LSB max

±0.366 ±0.366 % FS max

ANALOG INPUT

Input Voltage Ranges ±4 × V ±2 × V

±4 × V

REF

±2 × V

REF

V RNGx bits or RANGE pin = 0

REF

V RNGx bits or RANGE pin = 1

REF

DC Leakage Current ±1 ±1 μA max Input Capacitance

10 10 pF typ ±4 × V

14 14 pF typ ±2 × V

REFERENCE INPUT/OUTPUT

Reference Input Voltage Range 2.5 2.5 V min/max DC Leakage Current ±1 ±1 μA max Input Capacitance

18.5 18.5 pF typ

Reference Output Voltage 2.49/2.51 2.49/2.51 V min/max Long-Term Stability 150 150 ppm typ 1000 hours Reference Temperature Coefficient 25 25 ppm/°C max 6 6 ppm/°C typ

LOGIC INPUTS

Input High Voltage (V Input Low Voltage (V

) 0.7 × V

INH

) 0.3 × V

INL

0.7 × V

DRIVE

0.3 × V

DRIVE

V min

DRIVE

V max

DRIVE

Input Current (IIN) ±10 ±10 μA max Typically 10 nA, VIN = 0 V or V Input Capacitance (CIN)3 10 10 pF max

= 2.7 V to 5.25 V; for ±4 × V

DRIVE

= 250 kSPS, TA = T

SAMPLE

on unselected channels up to 100 kHz

See Tab le 8 for minimum V each range

range when in track

REF

range when in track

REF

= 1

DIS

EN/

range, VDD = 10 V

REF

to T

MIN

for

DD/VSS

DRIVE

MAX

Rev. 0 | Page 7 of 32

AD7656-1/AD7657-1/AD7658-1

Parameter B Version1Y Version

Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage (VOH) V Output Low Voltage (VOL) 0.2 0.2 V max I

− 0.2 V

DRIVE

− 0.2 V min I

DRIVE

= 200 μA

SOURCE

= 200 μA

SINK

Floating-State Leakage Current ±10 ±10 μA max Floating-State Output Capacitance

10 10 pF max

Output Coding Twos complement

CONVERSION RATE

Conversion Time 3.1 3.1 μs max Track-and-Hold Acquisition Time

2, 3

550 550 ns max

Throughput Rate 250 250 kSPS Parallel interface mode only

POWER REQUIREMENTS

VDD 5/15 5/15 V nom min/max For the 4 × V VSS −5/−15 −5/−15 V nom min/max For the 4 × V

range, VDD = 10 V to 16.5 V

REF

range, VDD = −10 V to −16.5 V

REF

AVCC 5 5 V nom DVCC 5 5 V nom V

3/5 3/5 V nom min/max

DRIVE

TOTAL

Normal Mode—Static 18 18 mA max

Normal Mode—Operational 26 26 mA max

ISS (Operational) 0.25 0.25 mA max VSS = −16.5 V, f I

(Operational) 0.25 0.25 mA max VDD = 16.5 V, f

Partial Power-Down Mode 7 7 mA max

Full Power-Down Mode (STBY Pin)

Power Dissipation

Digital inputs = 0 V or V

400 400 μA max

= DVCC = V

= −16.5 V

= 250 kSPS, AVCC = DVCC = V

SAMPLE

= 16.5 V, VSS = −16.5 V

= DVCC = V

= −16.5 V

SCLK on or off, AVCC = DVCC = V

= 16.5 V, VSS = −16.5 V

= DVCC = V

= −16.5 V

= 5.25 V, VDD = 16.5 V,

DRIVE

= 250 kSPS

SAMPLE

= 250 kSPS

SAMPLE

= 5.25 V, VDD = 16.5 V,

DRIVE

= 5.25 V, VDD = 16.5 V,

DRIVE

Normal Mode—Static 94 94 mW max Normal Mode—Operational 140 140 mW max f

= 250 kSPS

SAMPLE

Partial Power-Down Mode 40 40 mW max Full Power-Down Mode (STBY Pin)

The temperature range for the B version is −40°C to +85°C and for the Y version is −40°C to +125°C

See the Terminology section.

Sample tested during initial release to ensure compliance.

Includes I

AVCC

, I

, and I

VDD

VSS

VDRIVE

DVCC

25 25 μW max

DRIVE

= 5.25 V,

DRIVE

= 5.25 V,

Rev. 0 | Page 8 of 32

AD7656-1/AD7657-1/AD7658-1

TIMING SPECIFICATIONS

AVCC/DVCC = 4.75 V to 5.25 V, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V, V T

= T

MIN

to T

, unless otherwise noted.

MAX

Table 4.

Parameter

< 4.75 V V

DRIVE

Limit at t

MIN, tMAX

= 4.75 V to 5.25 V

PARALLEL INTERFACE

3 3 μs typ Conversion time, internal clock

CONVER T

150 150 ns min

QUIET

550 550 ns min Acquisition time

ACQ

t10 25 25 ns min Minimum CONVST low pulse t1 60 60 ns min CONVST high to BUSY high t

2 2 ms max

WAKE -UP

25 25 μs max Partial power-down mode

PARALLEL WRITE OPERATION

t11 15 15 ns min t12 0 0 ns min t13 5 5 ns min t14 5 5 ns min t15 5 5 ns min

PARALLEL READ OPERATION

0 0 ns min t3 0 0 ns min t4 0 0 ns min t5 45 36 ns min t6 45 36 ns max t7 10 10 ns min t8 12 12 ns max t9 6 6 ns min Minimum time between reads

SERIAL INTERFACE

18 18 MHz max Frequency of serial read clock

SCLK

t16 12 12 ns max

22 22 ns max

t18 0.4 × t t19 0.4 × t

0.4 × t

SCLK

0.4 × t

SCLK

ns min SCLK low pulse width

SCLK

ns min SCLK high pulse width

SCLK

t20 10 10 ns min

t21 18 18 ns max

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

A buffer is used on the DOUTx pins (Pin 5 to Pin 7) for this measurement.

200µA I

= 2.7 V to 5.25 V, V

DRIVE

= 2.5 V internal/external,

REF

Unit Description

Minimum quiet time required between bus relinquish and start of next conversion

rising edge to CONVST rising edge

STBY

pulse width

to WR setup time

to WR hold time

CS Data setup time before WR Data hold after WR

BUSY to RD

to RD setup time

to RD hold time

pulse width

delay

Data access time after RD Data hold time after RD Bus relinquish time after RD

Delay from CS disabled

Data access time after SCLK rising edge/CS falling edge

SCLK to data valid hold time after SCLK falling edge

rising edge to DOUTx high impedance

rising edge

falling edge

rising edge

until DOUTx three-state

TO OUTPUT

25pF

200µA I

Figure 2. Load Circuit for Digital Output Timing Specifications

Rev. 0 | Page 9 of 32

1.6V

07017-002

AD7656-1/AD7657-1/AD7658-1

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to AGND, DGND −0.3 V to +16.5 V VSS to AGND, DGND +0.3 V to −16.5 V VDD to AVCC V

− 0.3 V to 16.5 V

AVCC to AGND, DGND −0.3 V to +7 V DVCC to AVCC −0.3 V to AV

+ 0.3 V

DVCC to DGND, AGND −0.3 V to +7 V AGND to DGND −0.3 V to +0.3 V V

to DGND −0.3 V to DVCC + 0.3 V

DRIVE

Analog Input Voltage to AGND1 V Digital Input Voltage to DGND −0.3 V to V Digital Output Voltage to DGND −0.3 V to V

− 0.3 V to VDD + 0.3 V

+ 0.3 V

DRIVE

+ 0.3 V

DRIVE

REFIN/REFOUT to AGND −0.3 V to AVCC + 0.3 V Input Current to Any Pin Except

Supplies

±10 mA

Operating Temperature Range

B Version −40°C to +85°C

Y Version −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Pb/Sn Temperature, Soldering

Reflow (10 sec to 30 sec) 240(+0)°C Pb-Free Temperature, Soldering Reflow 260(+0)°C ESD 700 V

If the analog inputs are driven from alternative VDD and VSS supply circuitry,

a 240 Ω series resistor should be placed on the analog inputs and Schottky diodes should be placed in series with the AD7656-1/AD7657-1/AD7658-1’s VDD and VSS supplies.

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. These specifications apply to a 4-layer board.

Table 6. Thermal Resistance

Package Type θJA θ

Unit

64-Lead LQFP 45 11 °C/W

ESD CAUTION

Rev. 0 | Page 10 of 32

AD7656-1/AD7657-1/AD7658-1

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EN/DIS

DB14/REFBUF

DB10/DOUT C

DB9/DOUT B

DB8/DOUT A

DB7/HBEN/ DCEN

DB6/SCLK

DB5/DCIN A

DB4/DCIN B

DB3/DCIN C

DB2/SEL C

DB1/SEL B

EN/DIS

DB13

DB12

DB11

DGND

DRIVE

DB1563WR/REF

H/S SEL61SER/PAR SEL60AV

PIN 1

AD7656-1/AD7657-1/AD7658-1

19CS20RD21

BUSY

DB0/SEL A

Figure 3. Pin Configuration

AGND58REFCAPC57AGND56REFCAPB55AGND54REFCAPA53AGND52AGND51REFIN/ REFOU

TOP VIEW

(Not to Scale)

STBY

DGND

CONVST C22CONVST B

CONVST A

RANGE

RESET

AGND

W/B

AGND

07017-003

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

54, 56, 58

REFCAPA, REFCAPB, REFCAPC

Reference Capacitor A, Reference Capacitor B, and Reference Capacitor C. Decoupling capacitors are connected to these pins to decouple the reference buffer for each ADC pair. Each REFCAP pin should be decoupled to AGND using a 1 μF capacitor.

33, 36, 39, 42, 45, 48

V1 to V6

Analog Input 1 to Analog Input 6. These pins are single-ended analog inputs. In hardware mode, the analog input range of these channels is determined by the RANGE pin. In software mode, it is determined by the RNGC to RNGA bits of the control register (see Table 1 1).

32, 37, 38, 43, 44, 49, 52, 53, 55, 57, 59

AGND

Analog Ground. This pin is the ground reference point for all analog circuitry on the AD7656-1/ AD7657-1/AD7658-1. All analog input signals and external reference signals should be referred to this pin. All AGND pins should be connected to the AGND plane of the system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

26 DVCC

Digital Power, 4.75 V to 5.25 V. The DV

and AVCC voltages should ideally be at the same potential

and must not be more than 0.3 V apart, even on a transient basis. This supply should be decoupled to DGND by placing a 1 μF decoupling capacitor on the DVCC pin.

9 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface.

8, 25 DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7656-1/AD7657-1/ AD7658-1. Both DGND pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

34, 35, 40, 41, 46, 47, 50, 60

23, 22, 21

CONVST A, CONVST B, CONVST C

Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AV

voltages should ideally be at the same potential and must not be more than 0.3 V apart, even

and

on a transient basis. Conversion Start Input A, Conversion Start Input B, and Conversion Start Input C. These logic inputs

are used to initiate conversions on the ADC pairs. CONVST A is used to initiate simultaneous conversions on V1 and V2. CONVST B is used to initiate simultaneous conversions on V3 and V4. CONVST C is used to initiate simultaneous conversions on V5 and V6. When one of these pins switches from low to high, the track-and-hold switch on the selected ADC pair switches from track to hold, and the conversion is initiated. These inputs can also be used to place the ADC pairs into partial powerdown mode.

Rev. 0 | Page 11 of 32

AD7656-1/AD7657-1/AD7658-1

Pin No. Mnemonic Description

18 BUSY

51 REFIN/REFOUT

17 DB0/SEL A

16 DB1/SEL B

15 DB2/SEL C

14 DB3/DCIN C

13 DB4/DCIN B

12 DB5/DCIN A

11 DB6/SCLK

10 DB7/HBEN/DCEN

Chip Select. This active low logic input frames the data transfer. If both CS and RD are logic low and

the parallel interface is selected, the output bus is enabled and the conversion result is output on the parallel data bus lines. If both CS

and WR are logic low and the parallel interface is selected, DB[15:8] are used to write data to the on-chip control register. When the serial interface is selected, the CS used to frame the serial read transfer and clock out the MSB of the serial output data.

Read Data. If both CS and RD are logic low and the parallel interface is selected, the output bus is

enabled. When the serial interface is selected, the RD line should be held low.

/REF

DIS

EN/

Write Data/Reference Enable and Disable. When the H/S SEL pin is high and both CS and WR are logic low, DB[15:8] are used to write data to the internal control register. When the H

low, this pin is used to enable or disable the internal reference. When H

/S SEL = 0 and REF

/S SEL pin is

DIS

= 0, the

EN/

internal reference is disabled and an external reference should be applied to the REFIN/REFOUT pin. When H

/S SEL = 0 and REF

= 1, the internal reference is enabled and the REFIN/REFOUT pin

EN/

DIS

should be decoupled. See the section. Internal/External Reference Busy Output. This pin transitions to high when a conversion is started and remains high until the

conversion is complete and the conversion data is latched into the output data registers. A new conversion should not be initiated on the AD7656-1/AD7657-1/AD7658-1 when the BUSY signal is high.

Reference Input/Reference Output. The on-chip reference is available via this pin. Alternatively, the internal reference can be disabled and an external reference can be applied to this input. See the Internal/External Reference section. When the internal reference is enabled, this pin should be decoupled using at least a 1 μF decoupling capacitor.

SER/PA R

SEL Serial/Parallel Selection Input. When this pin is low, the parallel interface is selected. When this pin is high,

the serial interface is selected. When the serial interface is selected, DB[10:8] function as DOUT[C:A], DB[0:2] function as DOUT, and DB7 functions as DCEN. When the serial interface is selected, DB15 and DB[13:11] should be tied to DGND.

Data Bit 0/Select DOUT A. When SER/PAR pin. When SER/PAR

SEL = 1, this pin functions as SEL A and is used to configure the serial interface. If

SEL = 0, this pin acts as a three-state parallel digital output

this pin is 1, the serial interface operates with one, two, or three DOUT output pins and enables DOUT A as a serial output. When the serial interface is selected, this pin should always be set to 1.

Data Bit 1/Select DOUT B. When SER/PAR pin. When SER/PA R

SEL = 1, this pin functions as SEL B and is used to configure the serial interface. If

SEL = 0, this pin acts as a three-state parallel digital output

this pin is 1, the serial interface operates with two or three DOUT output pins and enables DOUT B as a serial output. If this pin is 0, the DOUT B is not enabled to operate as a serial data output pin and only one DOUT output pin, DOUT A, is used. Unused serial DOUT pins should be left unconnected.

Data Bit 2/Select DOUT C. When SER/PAR pin. When SER/PA R

SEL = 1, this pin functions as SEL C and is used to configure the serial interface. If

SEL = 0, this pin acts as a three-state parallel digital output

this pin is 1, the serial interface operates with three DOUT output pins and enables DOUT C as a serial output. If this pin is 0, the DOUT C is not enabled to operate as a serial data output pin. Unused serial DOUT pins should be left unconnected.

Data Bit 3/Daisy-Chain Input C. When SER/PAR output pin. When SER/PAR

SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input C. When the serial

SEL = 0, this pin acts as a three-state parallel digital

interface is selected but the device is not used in daisy-chain mode, this pin should be tied to DGND. Data Bit 4/Daisy-Chain Input B. When SER/PAR

output pin. When SER/PAR

SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input B. When the serial

SEL = 0, this pin acts as a three-state parallel digital

interface is selected but the device is not used in daisy-chain mode, this pin should be tied to DGND. Data Bit 5/Daisy-Chain Input A. When SER/PAR output pin. When SER/PAR

SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input A. When the serial

SEL is low, this pin acts as a three-state parallel digital

interface is selected but the device is not used in daisy-chain mode, this pin should be tied to DGND. Data Bit 6/Serial Clock. When SER/PA R

SEL = 0, this pin acts as a three-state parallel digital output pin.

When SER/PA R SEL = 1, this pin functions as SCLK input and is the read serial clock for the serial transfer. Data Bit 7/High Byte Enable/Daisy-Chain Enable. When the parallel interface is selected and the device is

used in word mode (SER/PAR SEL = 0 and W/B = 0), this pin functions as Data Bit 7. When the parallel interface is selected and the device is used in byte mode (SER/PA R

SEL = 0 and W/B = 1), this pin functions as HBEN. If the HBEN pin is logic high, the data is output MSB byte first on DB[15:8]. If the HBEN pin is logic low, the data is output LSB byte first on DB[15:8]. When the serial interface is selected (SER/PA R

SEL = 1), this pin functions as DCEN. If the DCEN pin is logic high, the parts

operate in daisy-chain mode with DB[5:3] functioning as DCIN[A:C]. When the serial interface is selected but the device is not used in daisy-chain mode, this pin should be tied to DGND.

Rev. 0 | Page 12 of 32

AD7656-1/AD7657-1/AD7658-1

Pin No. Mnemonic Description

7 DB8/DOUT A

Data Bit 8/Serial Data Output A. When SER/PA R output pin. When SER/PAR

SEL = 1 and SEL A = 1, this pin functions as DOUT A and outputs serial

conversion data.

6 DB9/DOUT B

Data Bit 9/Serial Data Output B. When SER/PA R output pin. When SER/PAR

SEL = 1 and SEL B = 1, this pin functions as DOUT B and outputs serial

conversion data. This configures the serial interface to have two DOUT output lines.

5 DB10/DOUT C

Data Bit 10/Serial Data Output C. When SER/PA R output pin. When SER/PAR

SEL = 1 and SEL C = 1, this pin functions as DOUT C and outputs serial

conversion data. This configures the serial interface to have three DOUT output lines.

4 DB11

3, 2, 64 DB12, DB13, DB15

Data Bit 11/Digital Ground. When SER/PA R output pin. When SER/PAR

SEL = 1, this pin should be tied to DGND.

Data Bit 12, Data Bit 13, Data Bit 15. When SER/PA R digital input/output pins. When CS

and RD are low, these pins are used to output the conversion result. When CS and WR are low, these pins are used to write to the control register. When SER/PA R SEL = 1, these pins should be tied to DGND. For the AD7657-1, DB15 contains a leading 0. For the AD7658-1, DB15, DB13, and DB12 contain leading 0s.

DB14/REFBUF

Data Bit 14/Reference Buffer Enable

/DIS

and Disable. When SER/PAR SEL = 0, this pin acts as a threestate digital input/output pin. For the AD7657-1 and AD7658-1, DB14 contains a leading 0. When SER/PA R

SEL = 1, this pin can be used to enable or disable the internal reference buffers.

28 RESET

Reset Input. When set to logic high, this pin resets the AD7656-1/AD7657-1/AD7658-1. In software mode, the current conversion is aborted and the internal register is set to all 0s. In hardware mode, the AD7656-1/AD7657-1/AD7658-1 are configured depending on the logic levels on the hardware select pins. In all modes, the parts should receive a RESET pulse after power-up. The RESET high pulse should be typically 100 ns wide. After the RESET pulse, the AD7656-1/AD7657-1/AD7658-1 need to see a valid CONVST pulse to initiate a conversion; this should consist of a high-to-low CONVST edge followed by a low-to-high CONVST edge. The CONVST signal should be high during the RESET pulse. In hardware mode, the user can initiate a RESET pulse between conversion cycles, that is, a 100 ns RESET pulse can be applied to the device after BUSY has transitioned from high to low and the data has been read. The RESET can then be used prior to the next CONVST pulse. Ensure that in such a case RESET is logic low prior to the next CONVST pulse.

27 RANGE

Analog Input Range Selection. Logic input. The logic level on this pin determines the input range of the analog input channels. When this pin is Logic 1 at the falling edge of BUSY, the range for the next conversion is ±2 × V next conversion is ±4 × V

. When this pin is Logic 0 at the falling edge of BUSY, the range for the

REF

. In hardware select mode, the RANGE pin is checked on the falling edge

REF

of BUSY. In software mode (H/S SEL = 1), the RANGE pin can be tied to DGND, and the input range is determined by the RNGA, RNGB, and RNGC bits in the control register.

31 VDD Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. 30 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. 24

STBY

Standby Mode Input. This pin is used to put all six on-chip ADCs into standby mode. The STBY pin is high for normal operation and low for standby operation.

/S SEL Hardware/Software Select Input. Logic input. When H/S SEL = 0, the AD7656-1/AD7657-1/AD7658-1

operate in hardware select mode, and the ADC pairs to be simultaneously sampled are selected by the CONVST pins. When H/S SEL = 1, the ADC pairs to be sampled simultaneously are selected by writing to the control register. When the serial interface is selected, CONVST A is used to initiate conversions on the selected ADC pairs.

/B Word/Byte Input. When this pin is logic low, data can be transferred to and from the AD7656-1/

AD7657-1/AD7658-1 using the parallel data lines DB[15:0]. When this pin is logic high and the parallel interface is selected, byte mode is enabled. In this mode, data is transferred using Data Lines DB[15:8], and DB[7] function as HBEN. To obtain the 16-bit conversion result, 2-byte reads are required. When the serial interface is selected, this pin should be tied to DGND.

SEL = 0, this pin acts as a three-state parallel digital

SEL = 0, these pins act as three-state parallel

Rev. 0 | Page 13 of 32

AD7656-1/AD7657-1/AD7658-1

TYPICAL PERFORMANCE CHARACTERISTICS

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

40 60 80 100 120200

FREQUENCY (kHz)

VDD/VSS = ±15V AV

/DVCC/V

±10V RANGE INTERNAL REFERENCE T

= 25°C

= 250kSPS

SAMPLE

= 10kHz

SNR = 88.44dB SINAD = 88.43d B THD = –111.66dB

Figure 4. AD7656-1 FFT for ±5 V Range (VDD/VSS = ±15 V)

DRIVE

= 5V

07017-004

2.0 VDD/VSS = ±12V

/DVCC/V

1.5

SAMPLE

2 × V

1.0

0.5

DNL (LSB)

–0.5

–1.0

–1.5

–2.0

0 10k 2 0k 30k 40k 50k 60k 65535

= 250kSPS

RANGE

REF

DRIVE

= –40°C

= 5V

DNL WCP = 0.61LSB DNL WCN = –0.82L SB

CODE

Figure 7. AD7656-1 Typical DNL

07017-007

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

40 60 80 100 120200

FREQUENCY (kHz)

Figure 5. AD7656-1 FFT for ±5 V Range (V

2.0

1.5

1.0

0.5

INL (LSB)

–0.5

VDD/VSS = ±12V

/DVCC/V

= 250kSPS

SAMPLE

RANGE

2 × V

REF

DRIVE

= –40°C

= 5V

INL WCP = 0.97LSB INL WCN = –0. 72LSB

VDD/VSS = ±12V AV

/DVCC/V

±5V RANGE INTERNAL REFERENCE T

= 25°C

SAMPLE

= 10kHz

SNR = 88.25dB SINAD = 88.24d B THD = –112.46dB

DD/VSS

DRIVE

= 250kSPS

= ±12 V)

= 5V

2.0 VDD/VSS = ±12V

/DVCC/V

1.6

= 250kSPS

SAMPLE

±5V RANGE

1.2

0.8

0.4

INL (LSB)

–0.4

–0.8

–1.2

–1.6

07017-005

–2.0

0 2000 4000 6000 8000 10000 12000 14000 16000

DRIVE

= 5V

CODE

07017-008

Figure 8. AD7657-1 Typical INL

2.0 VDD/VSS = ±12V

DNL (LS B)

1.5

1.0

0.5

–0.5

SAMPLE

±5V RANGE

/DVCC/V

= 250kSPS

DRIVE

= 5V

–1.0

–1.5

–2.0

0 10k 2 0k 30k 40k 50k 60k 65535

CODE

Figure 6. AD7656-1 Typical INL

07017-006

Rev. 0 | Page 14 of 32

–1.0

–1.5

–2.0

0 2000 4000 6000 8000 10000 12000 14000 16000

ADC CODE

Figure 9. AD7657-1 Typical DNL

07017-009

AD7656-1/AD7657-1/AD7658-1

–

1.0 VDD/VSS = ±12V

0.8

0.6

/DVCC/V

= 250kSPS

SAMPLE

±5V RANGE

DRIVE

= 5V

0.4

0.2

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 10. AD7658-1 Typical INL

1.0

VDD/VSS = ±12V AV

0.8

0.6

/DVCC/V

= 250kSPS

SAMPLE

±5V RANGE

DRIVE

= 5V

0.4

0.2

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 11. AD7658-1 Typical DNL

07017-010

07017-011

= 250kSPS

SAMPLE

= 25°C

–85

INTERNAL REFERENCE

–90

–95

±10V RANGE V

= ±12V

–100

THD (dB)

DD/VSS

/DVCC/V

DRIVE

= 5V

–105

–110

–115

10 100

±5V RANGE V

= ±12V

DD/VSS

/DVCC/V

DRIVE

= 5V

07017-013

ANALOG INPUT FREQUENCY (kHz)

Figure 13. AD7656-1 THD vs. Analog Input Frequency

VDD/VSS = ±16.5V

/DVCC/V

= 25°C

INTERNAL REFERENCE ±4 × V

–90

REF

DRIVE

RANGE

= 5.25V

SOURCE

= 220Ω

= 1000Ω

–100

THD (dB)

–110

SOURCE

–120

10 100

= 10Ω

SOURCE

= 100Ω

SOURCE

= 50Ω

07017-014

ANALOG INPUT FREQUENCY (kHz)

Figure 14. AD7656-1 THD vs. Analog Input Frequency for Various Source

Impedances, ±4 × V

REF

Range

= 250kSPS

SAMPLE

= 25°C

INTERNAL REFERENCE

±5V RANGE V

DD/VSS

SINAD (dB)

= ±12V

/DVCC/V

DRIVE

= 5V

±10V RANGE

= ±12V

DD/VSS

/DVCC/V

DRIVE

10 100

ANALOG INPUT FREQUENCY (kHz)

Figure 12. AD7656-1 SINAD vs. Analog Input Frequency

= 5V

07017-012

VDD/VSS = ±12V

/DVCC/V

= 25°C

–85

INTERNAL REFERENCE ±2 × V

–90

REF

–95

–100

THD (dB)

–105

–110

–115

10 100

DRIVE

RANGE

SOURCE

= 5V

SOURCE

= 220Ω

= 1000Ω

SOURCE

= 10Ω

SOURCE

= 50Ω

= 100Ω

07017-015

ANALOG INPUT FREQUENCY (kHz)

Figure 15. AD7656-1 THD vs. Analog Input Frequency for Various Source

Impedances, ±2 × V

REF

Range

Rev. 0 | Page 15 of 32

AD7656-1/AD7657-1/AD7658-1

–

2.510

2.508

AVCC/DVCC/V V

= ±12V

DD/VSS

DRIVE

= 5V

2.506

2.504

2.502

2.500

2.498

REFERENCE VOL TAGE (V)

2.496

2.494

2.492 –55 125

–35 –15 5 25 45 65 85 105

TEMPERATURE (°C)

Figure 16. Reference Voltage vs. Temperature

3.20

3.15

3.10

3.05

3.00

2.95

2.90

2.85

CONVERSION TIME (µs)

2.80

2.75

2.70 –55 125

–35 –15 5 25 45 65 85 105

TEMPERATURE (°C)

AVCC/DVCC/V

= ±12V

DD/VSS

Figure 17. Conversion Time vs. Temperature

DRIVE

07017-016

= 5V

07017-017

100

= 250kSPS

SAMPLE

±2 × V

RANGE

REF

INTERNAL REFERENCE T

= 25°C

= 10kHz

100nF ON V

PSRR (dB)

30 530

80 130 180 230 280 330 380 430 480

SUPPLY RIPPLE FREQUENCY (kHz)

Figure 19. PSRR vs. Supply Ripple Frequency

±5V RANGE AV

/DVCC/V

SNR (dB)

DD/VSS

= ±12V

DRIVE

= 5V

±10V RANGE AV

/DVCC/V

= ±16.5V

DD/VSS

DRIVE

= 5.25V

= 250kSPS

SAMPLE

= 10kHz

–40 140

–20 0 20 40 60 80 100 120

INTERNAL REFERENCE

TEMPERATURE (° C)

Figure 20. AD7656-1 SNR vs. Temperature

AND V

07017-019

07017-020

3500

3000

2500

2806

3212

VDD/VSS = ±15V AV

/DVCC/V

INTERNAL REFERENCE 8192 SAMPLES

DRIVE

= 5V

2000

1500

1532

1000

NUMBER OF OCCURRENCES

500

–5

392

168

–4 –3 –2 –1 0 1 2

07017-018

CODE

Figure 18. AD7656-1 Histogram of Codes

= 250kSPS

SAMPLE

= 10kHz

INTERNAL REFERENCE

–95

–100

±5V RANGE AV

THD (dB)

–105

DD/VSS

/DVCC/V

= ±12V

DRIVE

= 5V

–110

–115

–120

–60 140

–40 –20 0 4020 60 80 100 120

±10V RANGE AV

/DVCC/V

= ±16.5V

DD/VSS

DRIVE

= 5.25V

TEMPERATURE ( °C)

Figure 21. AD7656-1 THD vs. Temperature

07017-021

Rev. 0 | Page 16 of 32

AD7656-1/AD7657-1/AD7658-1

120

110

100

AVCC/DVCC/V

= ±12V

DD/VSS

= 25°C

INTERNAL REFERENCE

CHANNEL-TO-CHANNEL ISOLATION (dB)

RANGE

±2 × V

REF

30kHz ON SELECT ED CHANNEL

20 40 60 80 100 120 140

= 5V

DRIVE

FREQUENCY OF INPUT NOI SE (kHz)

07017-022

PSRR (dB)

= 250kSPS

SAMPLE

±2 × V

70 110 150 190 230

SUPPLY RIPPLE FREQUENCY (kHz)

RANGE

REF

INTERNAL REFE RENCE T

= 25°C

= 10kHz

1µF ON AV ±100mV SUPPLY RIPPLE AMPLITUDE

SUPPLY PIN

Figure 22. Channel-to-Channel Isolation vs. Frequency of Input Noise Figure 24. PSRR vs. Supply Ripple Frequency for AVCC Supply

±5V RANGE

±10V RANGE

07017-036

DYNAMIC CURRENT (mA)

AVCC/DVCC/V

= 250kSPS

SAMPLE

FOR ±5V RANGE V FOR ±10V RANGE V

–40 –20 0 20 40 60 80 100 120

= 5V

DRIVE

DD/VSS

TEMPERATURE (° C)

= ±12V

= ±16.5V

07017-023

Figure 23. Dynamic Current vs. Temperature

Rev. 0 | Page 17 of 32

AD7656-1/AD7657-1/AD7658-1

TERMINOLOGY

Integral Nonlinearity (INL)

The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale at a ½ LSB below the first code transition and full scale at ½ LSB above the last code transition.

Differential Nonlinearity (DNL)

The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Bipolar Zero Scale Error

The deviation of the midscale transition (all 1s to all 0s) from the ideal V

voltage, that is, AGND − 1 LSB.

Bipolar Zero Scale Error Matching

The difference in bipolar zero code error between any two input channels.

Positive Full-Scale Error

The deviation of the last code transition (011 … 110 to 011 … 111) from the ideal (+4 × V

− 1 LSB, +2 × V

REF

− 1 LSB) after

REF

adjusting for the bipolar zero scale error.

Positive Full-Scale Error Matching

The difference in positive full-scale error between any two input channels.

Negative Full-Scale Error

The deviation of the first code transition (10 … 000 to 10 … 001) from the ideal (−4 × V

+ 1 LSB, −2 × V

REF

+ 1 LSB) after

REF

adjusting for the bipolar zero scale error.

Negative Full-Scale Error Matching

The difference in negative full-scale error between any two input channels.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode at the end of the conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of the conversion. See the Track-and-Hold section for more details.

Signal-to-(Noise + Distortion) Ratio

The measured ratio of signal-to-(noise + distortion) (SINAD) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f

/2, excluding dc).

SAMPLE

The ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical SINAD ratio for an ideal N-bit converter with a sine wave input is given by

SINAD = (6.02 N + 1.76) dB

Therefore, SINAD is 98 dB for a 16-bit converter, 86.04 dB for a 14-bit converter, and 74 dB for a 12-bit converter.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the harmonics to the fundamental. For the AD7656-1/AD7657-1/AD7658-1, it is defined as

22222

++++

VVVVV

THD

log20)dB(

where:

is the rms amplitude of the fundamental.

, V3, V4, V5, and V6 are the rms amplitudes of the second

through sixth harmonics.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the ADC output spectrum (up to f

/2, excluding dc) to the rms

SAMPLE

value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is determined by a noise peak.

Intermodulation Distortion (IMD)

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities create distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The AD7656-1/AD7657-1/AD7658-1 are tested using the CCIF standard in which two input frequencies near the maximum input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals and is expressed in decibels.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 100 kHz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 30 kHz signal.

Power Supply Rejection (PSR)

Variations in power supply affect the full-scale transition but not the linearity of the converter. Power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. See the

Ty pi ca l

Performance Characteristics section.

Rev. 0 | Page 18 of 32

AD7656-1/AD7657-1/AD7658-1

Figure 19 shows the power supply rejection ratio vs. supply ripple frequency for the AD7656-1/AD7657-1/AD7658-1. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC’s V supplies at a frequency sampled, f

PSRR (dB) = 10 log(Pf/Pf

)

SAMPLE

and VSS

where:

Pf is equal to the power at frequency f in the ADC output. Pf

is equal to the power at frequency f

and VSS supplies.

coupled onto the

SAMPLE

Rev. 0 | Page 19 of 32

AD7656-1/AD7657-1/AD7658-1

THEORY OF OPERATION

CONVERTER DETAILS

The AD7656-1/AD7657-1/AD7658-1 are pin- and softwarecompatible, reduced decoupling versions of the AD7656/AD7657/ AD7658 devices. In addition, the AD7656-1/AD7657-1/AD7658-1 are high speed, low power converters that allow the simultaneous sampling of six on-chip ADCs. The analog inputs on the AD7656-1/ AD7657-1/AD7658-1 can accept true bipolar input signals. The RANGE pin or RNGx bits are used to select either ±4 × V ±2 × V

as the input range for the next conversion.

REF

Each AD7656-1/AD7657-1/AD7658-1 contains six SAR ADCs, six track-and-hold amplifiers, an on-chip 2.5 V reference, reference buffers, and high speed parallel and serial interfaces. The parts allow the simultaneous sampling of all six ADCs when the three CONVST pins (CONVST A, CONVST B, and CONVST C) are tied together. Alternatively, the six ADCs can be grouped into three pairs. Each pair has an associated CONVST signal used to initiate simultaneous sampling on each ADC pair, on four ADCs, or on all six ADCs. CONVST A is used to initiate simultaneous sampling on V1 and V2, CONVST B is used to initiate simultaneous sampling on V3 and V4, and CONVST C is used to initiate simultaneous sampling on V5 and V6.

A conversion is initiated on the AD7656-1/AD7657-1/AD7658-1 by pulsing the CONVST input. On the rising edge of CONVST, the track-and-hold amplifier of the selected ADC pair is placed into hold mode and the conversions are started. After the rising edge of CONVST, the BUSY signal goes high to indicate that the conversion is taking place. The conversion clock for the AD7656-1/ AD7657-1/AD7658-1 is internally generated, and the conversion time for the parts is 3 µs. The BUSY signal returns low to indicate the end of a conversion. On the falling edge of BUSY, the trackand-hold amplifier returns to track mode. Data can be read from the output register via the parallel or serial interface.

Track-and-Hold Amplifiers

The track-and-hold amplifiers on the AD7656-1/AD7657-1/ AD7658-1 allow the ADCs to accurately convert an input sine wave of full-scale amplitude to 16-/14-/12-bit resolution, respectively. The input bandwidth of the track-and-hold amplifiers is greater than the Nyquist rate of the ADC, even when the AD7656-1/AD7657-1/AD7658-1 are operating at the maximum throughput rate. The parts can handle input frequencies of up to 4.5 MHz.

The track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of CONVST. The aperture time (that is, the delay time between the external CONVST signal actually going into hold) for the track-and-hold amplifier is 10 ns. This is well matched across all six track-and-hold amplifiers on one device and from device to device. This allows more than six ADCs to be sampled simultaneously. The end of the conversion is signaled by the falling edge of BUSY, and it is at this point that the trackand-hold amplifiers return to track mode and the acquisition time begins.

REF

Rev. 0 | Page 20 of 32

Analog Input

The AD7656-1/AD7657-1/AD7658-1 can handle true bipolar input voltages. The logic level on the RANGE pin or the value written to the RNGx bits in the control register determines the analog input range on the AD7656-1/AD7657-1/AD7658-1 for the next conversion. When the RANGE pin or RNGx bits are 1, the analog input range for the next conversion is ±2 × V

REF

. When the RANGE pin or RNGx bits are 0, the analog input range for the next conversion is ±4 × V

Figure 25. Equivalent Analog Input Structure

REF

7017-024

Figure 25 shows an equivalent circuit of the analog input structure of the AD7656-1/AD7657-1/AD7658-1. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the V

and VSS supply rails by more than

300 mV. Signals exceeding this value cause these diodes to become forward-biased and to start conducting current into the substrate. The maximum current these diodes can conduct without causing irreversible damage to the parts is 10 mA. Capacitor C1 in Figure 25 is typically about 4 pF and can be attributed primarily to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of a switch (that is, a track-and-hold switch). This resistor is typically about 3.5 kΩ. Capacitor C2 is the ADC sampling capacitor and has a capacitance of 10 pF typically.

The AD7656-1/AD7657-1/AD7658-1 require V

and VSS dual

supplies for the high voltage analog input structures. These supplies must be equal to or greater than the analog input range (see Ta b le 8 for the requirements on these supplies for each analog input range). The AD7656-1/AD7657-1/AD7658-1 require a low voltage AV supply of 4.75 V to 5.25 V to power the ADC core, a DV of 4.75 V to 5.25 V for the digital power, and a V

DRIVE

supply of

supply

2.7 V to 5.25 V for the interface power.

To meet the specified performance when using the minimum supply voltage for the selected analog input range, it may be necessary to reduce the throughput rate from the maximum throughput rate.

Table 8. Minimum V

Analog Input Range (V)

±4 × V ±2 × V

2.5 ±10 ±10

REF

2.5 ±5 ±5

REF

Reference Voltage (V)

Supply Voltage Requirements

DD/VSS

Full-Scale Input (V)

Minimum V

(V)

DD/VSS

AD7656-1/AD7657-1/AD7658-1

ADC TRANSFER FUNCTION

The output coding of the AD7656-1/AD7657-1/AD7658-1 is twos complement. The designed code transitions occur midway between successive integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is FSR/65,536 for the AD7656-1, FSR/16,384 for the AD7657-1, and FSR/4096 for the AD7658-1. The ideal transfer characteristic is shown in Figure 26.

011 ... 111 011 ... 110

000 ... 001 000 ... 000

111 .. . 111

ADC CODE

100 ... 010 100 ... 001 100 ... 000

–FSR/2 + 1/2LSB +FSR/2 – 3/2LSB

Figure 26. AD7656-1/AD7657-1/AD7658-1 Transfer Characteristic

AGND – 1LSB

ANALOG INPUT

7017-025

The LSB size is dependent on the analog input range selected (see Tabl e 9).

INTERNAL/EXTERNAL REFERENCE

The REFIN/REFOUT pin allows access to the 2.5 V reference of the AD7656-1/AD7657-1/AD7658-1, or it allows an external reference to be connected to provide the reference source for conversions.

The AD7656-1/AD7657-1/AD7658-1 can each accommodate a

2.5 V external reference range. When using an external reference, the internal reference must be disabled. After a reset, the AD7656-1/ AD7657-1/AD7658-1 default to operating in external reference mode with the internal reference buffers enabled.

The internal reference can be enabled in either hardware or software mode. To enable the internal reference in hardware mode,

set the

internal reference in software mode, set

/S SEL pin to 0 and the REF

pin to 1. To enable the

EN/

DIS

/S SEL to 1 and write to

the control register to set DB9 of the register to 1. For the internal reference mode, the REFIN/REFOUT pin should be decoupled using a 1 µF capacitor.

The AD7656-1/AD7657-1/AD7658-1 each contain three onchip reference buffers. Each of the three ADC pairs has an associated reference buffer. These reference buffers require external decoupling capacitors, using 1 µF capacitors, on the REFCAPA, REFCAPB, and REFCAPC pins. The internal reference buffers can be disabled in software mode by writing to Bit DB8 in the internal control register. If serial interface is selected, the internal reference buffers can be disabled in hardware mode by setting the DB14/REFBUF

pin high. If the internal

/DIS

reference and its buffers are disabled, an external buffered reference should be applied to the REFCAPx pins.

TYPICAL CONNECTION DIAGRAM

Figure 27 shows the typical connection diagram for the AD7656-1/ AD7657-1/AD7658-1, illustrating the reduction in the number and value of decoupling capacitors required. There are eight AV

supply pins on each part. The AVCC supplies are the supplies

used for the AD7656-1/AD7657-1/AD7658-1 conversion process; therefore, they should be well decoupled. The AV is applied to eight AV

pins can be decoupled using just one 1 µF

capacitor The AD7656-1/AD7657-1/AD7658-1 can operate with the internal reference or an externally applied reference. In this configuration, the parts are configured to operate with the external reference. The REFIN/REFOUT pin is decoupled with a 1 µF capacitor. The three internal reference buffers are enabled. Each of the REFCAPx pins is decoupled with a 1 µF capacitor.

If the same supply is being used for the AV

ferrite or small RC filter should be placed between the supply pins.

AGND pins are connected to the AGND plane of the system. The DGND pins are connected to the digital ground plane in the system. The AGND and DGND planes should be connected together at one place in the system. This connection should be as close as possible to the AD7656-1/AD7657-1/AD7658-1 in the system.

supply which

and DVCC supplies, a

Table 9. LSB Size for Each Analog Input Range

Input Range for AD7656-1 Input Range for AD7657-1 Input Range for AD7658-1 Parameter ±10 V ±5 V ±10 V ±5 V ±10 V ±5 V

LSB Size 0.305 mV 0.152 mV 1.22 mV 0.610 mV 4.88 mV 2.44 mV FS Range 20 V/65,536 10 V/65,536 20 V/16,384 10 V/16,384 20 V/4096 10 V/4096

Rev. 0 | Page 21 of 32

AD7656-1/AD7657-1/AD7658-1

ANALOG SUPPLY

9.5V TO +16.5V SUPPLY

2.5V REF

–9.5V TO –16.5V

SUPPLY

VOLTAGE 5V

1µF

SIX ANALO G

INPUTS

1µF

AGND DGND V

AGND

REFCAPA, B, C

AGND

REFIN/OUT

AGND

See Appli cation s Hints Secti on

Figure 27. Typical Connection Diagram

The V processor. The voltage on V

supply is connected to the same supply as the

DRIVE

controls the voltage value of

DRIVE

the output logic signals.

The V

and VSS signals should be decoupled with a minimum 1 µF

decoupling capacitor. These supplies are used for the high voltage analog input structures on the AD7656-1/AD7657-1/AD7658-1 analog inputs.

DRIVING THE ANALOG INPUTS

Together, the driver amplifier and the analog input circuit used for the AD7656-1 must settle for a full-scale step input to a 16-bit level (0.0015%), which is within the specified 550 ns acquisition time of the AD7656-1. The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7656-1. In addition, the driver also needs to have a THD performance suitable for the AD7656-1.

The AD8021 meets these requirements. The AD8021 needs an external compensation capacitor of 10 pF. If a dual version of the AD8021 is required, the AD8022 can be used. The AD8610 and the AD797 can also be used to drive the AD7656-1/AD7657-1/ AD7658-1.

INTERFACE OPTIONS

The AD7656-1/AD7657-1/AD7658-1 provide two interface options: a high speed parallel interface and a high speed serial interface. The required interface mode is selected via the

PA R

SER/

( AD7656-1/AD7657-1/AD7658-1 can be configured into daisychain mode.

SEL pin. The parallel interface can operate in word

/B = 0) or byte (W/B = 1) mode. When in serial mode, the

AD7656-1/ AD7657-1/ AD7658-1

1µF

DRIVE

D0 TO D15

CONVST A, B, C

DGND

RESET

BUSY

SER/PAR

H/S

W/B

RANGE

STBY

DIGITAL SUPPLY VOLTAGE +3V OR +5V

1µF

PARALLEL

INTERFACE

SCHMITT TRIGGER

DRIVE

µP/µC/DSP

Parallel Interface (SER/

PAR

SEL = 0)

The AD7656-1/AD7657-1/AD7658-1 consist of six 16-/14-/ 12-bit ADCs, respectively. A simultaneous sample of all six ADCs can be performed by connecting all three CONVST pins (CONVST A, CONVST B, and CONVST C) together. The AD7656-1/AD7657-1/AD7658-1 need to see a CONVST pulse to initiate a conversion; this should consist of a falling CONVST edge followed by a rising CONVST edge. The rising edge of CONVST initiates simultaneous conversions on the selected ADCs. The AD7656-1/AD7657-1/AD7658-1 each contain an on-chip oscillator that is used to perform the conversions. The conversion time, t

, is 3 µs. The BUSY signal goes low to

CONV

indicate the end of a conversion. The falling edge of the BUSY signal is used to place the track-and-hold amplifier into track mode.

The AD7656-1/AD7657-1/AD7658-1 also allow the six ADCs to be converted simultaneously in pairs by pulsing the three CONVST pins independently. CONVST A is used to initiate simultaneous conversions on V1 and V2, CONVST B is used to initiate simultaneous conversions on V3 and V4, and CONVST C is used to initiate simultaneous conversions on V5 and V6. The conversion results from the simultaneously sampled ADCs are stored in the output data registers.

Data can be read from the AD7656-1/AD7657-1/AD7658-1 via the parallel data bus with standard To read the data over the parallel bus, SER/ tied low. The

and RD input signals are internally gated to

and RD signals (W/B = 0).

PA R

SEL should be

enable the conversion result onto the data bus. The data lines DB0 to DB15 leave their high impedance state when both

and

are logic low.

Rev. 0 | Page 22 of 32

AD7656-1/AD7657-1/AD7658-1

The CS signal can be permanently tied low, and the RD signal can be used to access the conversion results. A read operation can take place after the BUSY signal goes low. The number of required read operations depends on the number of ADCs that are simultaneously sampled (see ). If CONVST A

Figure 28 and CONVST B are simultaneously brought low, four read operations are required to obtain the conversion results from V1, V2, V3, and V4. If CONVST A and CONVST C are simultaneously brought low, four read operations are required to obtain the conversion results from V1, V2, V5, and V6. The conversion results are output in ascending order. For the AD7657-1, DB15 and DB14 contain two leading 0s, and DB[13:0] output the 14-bit conversion result. For the AD7658-1, DB[15:12] contain four leading 0s, and DB[11:0] output the 12-bit conversion result.

When using the three CONVST signals to independently initiate conversions on the three ADC pairs, care should be taken to ensure that a conversion is not initiated on a channel pair when the BUSY signal is high. It is also recommended not to initiate a conversion during a read sequence because doing so

CONVST A, CONVST B, CONVST C

CONV

may affect the performance of the conversion. For the specified performance, it is recommended to perform the read after the conversion. For unused input channel pairs, the associated CONVST pin should be tied to V

DRIVE

If there is only an 8-bit bus available, the AD7656-1/AD7657-1/ AD7658-1 parallel interface can be configured to operate in byte

mode (

/B = 1). In this configuration, the DB7/HBEN/DCEN pin takes on its HBEN function. Each channel conversion result from the AD7656-1/AD7657-1/AD7658-1 can be accessed in two read operations, with eight bits of data provided on DB15 to DB8 for each of the read operations (see ). The

Figure 29 HBEN pin determines whether the read operation first accesses the high byte or the low byte of the 16-bit conversion result. To always access the low byte first on DB15 to DB8, the HBEN pin should be tied low. To always access the high byte first on DB15 to DB8, the HBEN pin should be tied high. In byte mode when all three CONVST pins are pulsed together to initiate simultaneous conversions on all six ADCs, 12 read operations are necessary to read back the six 16-/14-/12-bit conversion results. DB[6:0] should be left unconnected in byte mode.

ACQ

BUSY

DATA

V1 V2 V3 V4 V5 V6

Figure 28. Parallel Interface Timing Diagram (

/B = 0)

QUIET

7017-027

07017-028

/B = 1, HBEN = 0)

DB15 TO DB8

LOW BYTE HIGH BYTE

Figure 29. Parallel Interface—Read Cycle for Byte Mode of Operation. (

Rev. 0 | Page 23 of 32

AD7656-1/AD7657-1/AD7658-1

Software Selection of ADCs

The H/S SEL pin determines the source of the combination of ADCs

that are to be simultaneously sampled. When the

/S SEL pin is logic low, the combination of channels to be simultaneously sampled is determined by the CONVST A, CONVST B, and CONVST C pins. When the

/S SEL pin is logic high, the combination of channels selected for simultaneous sampling is determined by the contents of the DB15 to DB13 control registers. In this mode, a write to the control register is necessary.

The control register is an 8-bit write-only register. Data is written to this register using the pins (see ). The control register is detailed in and . To select an ADC pair to be simultaneously sampled,

Figure 30 Tabl e 10

Tabl e 11

and WR pins and the DB[15:8] data

set the corresponding data line high during the write operation.

DB15 TO DB8

Figure 30. Parallel Interface—Write Cycle for Word Mode (

DATA

07017-029

/B = 0)

The AD7656-1/AD7657-1/AD7658-1 control register allows individual ranges to be programmed on each ADC pair. DB12 to DB10 in the control register are used to program the range on each ADC pair.

After a reset occurs on the AD7656-1/AD7657-1/AD7658-1, the control register contains all 0s.

The CONVST A signal is used to initiate a simultaneous conversion on the combination of channels selected via the control register. The CONVST B and CONVST C signals can be tied low when operating in software mode (

/S SEL = 1). The number of read pulses required depends on the number of ADCs selected in the control register and on whether the devices are operating in word or byte mode. The conversion results are output in ascending order.

During the write operation, Data Bus Bit DB15 to Data Bus Bit DB8 are bidirectional and become inputs to the control register when RD

is logic high and CS and WR are logic low. The logic state on DB15 through DB8 is latched into the control register when WR

goes logic high.

Table 10. Control Register Bit Map

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

VC VB VA RNGC RNGB RNGA REFEN REFBUF

Default All 0s.

Table 11. Control Register Bit Function Descriptions

Bit Mnemonic Description

DB15 VC

This bit is used to select the V5 and V6 analog inputs for the next conversion. When this bit is set to 1, V5 and V6 are simultaneously converted on the next CONVST A rising edge.

DB14 VB

This bit is used to select the V3 and V4 analog inputs for the next conversion. When this bit is set to 1, V3 and V4 are simultaneously converted on the next CONVST A rising edge.

DB13 VA

This bit is used to select the V1 and V2 analog inputs for the next conversion. When this bit is set to 1, V1 and V2 are simultaneously converted on the next CONVST A rising edge.

DB12 RNGC

This bit is used to select the analog input range for the V5 and V6 analog inputs. When this bit is set to 1, the ±2 × V is selected for the next conversion. When this bit is set to 0, the ±4 × V

range is

REF

selected for the next conversion.

DB11 RNGB

This bit is used to select the analog input range for the V3 and V4 analog inputs. When this bit is set to 1, the ±2 × V is selected for the next conversion. When this bit is set to 0, the ±4 × V

range is

REF

selected for the next conversion.

DB10 RNGA

This bit is used to select the analog input range for the V1 and V2 analog inputs. When this bit is set to 1, the ±2 × V is selected for the next conversion. When this bit is set to 0, the ±4 × V

range is

REF

selected for the next conversion.

DB9 REFEN

This bit is used to select the internal reference or an external reference. When this bit is set to 0, the external reference mode is selected. When this bit is set to 1, the internal reference is selected.

DB8 REFBUF

This bit is used to select between using the internal reference buffers and choosing to bypass these reference buffers. When this bit is set to 0, the internal reference buffers are enabled and decoupling is required on the REFCAPx pins. When this bit is set to 1, the internal reference buffers are disabled and a buffered reference should be applied to the REFCAPx pins.

range

REF

range

REF

range

REF

Rev. 0 | Page 24 of 32

AD7656-1/AD7657-1/AD7658-1

Changing the Analog Input Range (H/S SEL = 0)

The AD7656-1/AD7657-1/AD7658-1 RANGE pin allows the user to select either ±2 × V

or ±4 × V

REF

range for the six analog inputs. When the

as the analog input

REF

/S SEL pin is low, the logic state of the RANGE pin is sampled on the falling edge of the BUSY signal to determine the range for the next simultaneous conversion. When the RANGE pin is logic high at the falling edge of the BUSY signal, the range for the next conversion is ±2 × V

. When the RANGE pin is logic low at the falling

REF

edge of the BUSY signal, the range for the next conversion is ±4 × V

. After a RESET pulse, the range is updated on the first

REF

falling BUSY edge.

Changing the Analog Input Range (H/S SEL = 1)

When the H/S SEL pin is high, the range can be changed by writing to the control register. DB[12:10] in the control register are used to select the analog input ranges for the next conversion. Each analog input pair has an associated range bit, allowing independent ranges to be programmed on each ADC pair. When the RNGx bit is set to 1, the range for the next conversion is ±2 × V conversion is ±4 × V

Serial Interface (SER/

. When the RNGx bit is set to 0, the range for the next

REF

SEL = 1)

PAR

By pulsing one, two, or all three CONVST signals, the AD7656-1/ AD7657-1/AD7658-1 use their on-chip trimmed oscillator to simultaneously convert the selected channel pairs on the rising edge of CONVST. After the rising edge of CONVST, the BUSY signal goes high to indicate that the conversion has started. It returns low when the conversion is complete, 3 µs later. The output register is loaded with the new conversion results, and data can be read from the AD7656-1/AD7657-1/AD7658-1. To read the data back from the parts over the serial interface,

PA R

SER/

SEL should be tied high. The CS and SCLK signals are

used to transfer data from the AD7656-1/AD7657-1/AD7658-1. The parts have three DOUT pins: DOUT A, DOUT B, and DOUT C. Data can be read back from each part using one, two, or all three DOUT lines.

Figure 31 shows six simultaneous conversions and the read sequence using three DOUT lines. Also in Figure 31, 32 SCLK transfers are used to access data from the AD7656-1/AD7657-1/ AD7658-1; however, two 16-SCLK individually framed transfers with the

signal can also be used to access the data on the three DOUT lines. When the serial interface is selected and conversion data is clocking out on all three DOUT lines, DB0/SEL A, DB1/SEL B, and DB2/SEL C should be tied to V

. These pins are used to enable the DOUT A to DOUT C

DRIVE

lines, respectively.

If it is required to clock conversion data out on two data output lines, DOUT A and DOUT B should be used. To enable DOUT A and DOUT B, DB0/SEL A and DB1/SEL B should be tied to V

DRIVE

and DB2/SEL C should be tied low. When six simultaneous conversions are performed and only two DOUT lines are used, a 48 SCLK transfer can be used to access the data from the AD7656-1/AD7657-1/AD7658-1. The read sequence is shown in Figure 32 for a simultaneous conversion on all six ADCs using two DOUT lines. If a simultaneous conversion occurred on all six ADCs, and only two DOUT lines are used to read the results from the AD7656-1/AD7657-1/AD7658-1. DOUT A clocks out the result from V1, V2, and V5, whereas DOUT B clocks out the results from V3, V4, and V6.

Data can also be clocked out using just one DOUT line, in which case DOUT A should be used to access the conversion data. To configure the AD7656-1/AD7657-1/AD7658-1 to operate in this mode, DB0/SEL A should be tied to V

, and DB1/SEL B

DRIVE

and DB2/SEL C should be tied low. The disadvantage of using only one DOUT line is that the throughput rate is reduced. Data can be accessed from the AD7656-1/AD7657-1/AD7658-1 using one 96 SCLK transfer, three 32-SCLK individually framed transfers, or six 16-SCLK individually framed transfers. When using the serial interface, the

signal should be tied low and the unused

DOUT line(s) should be left unconnected.

Serial Read Operation

Figure 33 shows the timing diagram for reading data from the AD7656-1/AD7657-1/AD7658-1 when the serial interface is selected. The SCLK input signal provides the clock source for the serial interface. The the AD7656-1/AD7657-1/AD7658-1. The falling edge of

signal goes low to access data from

takes the bus out of three-state and clocks out the MSB of the 16-bit conversion result. The ADCs output 16 bits for each conversion result; the data stream of the AD7656-1 consists of 16 bits of conversion data, provided MSB first. The data stream for the AD7657-1 consists of two leading 0s followed by 14 bits of conversion data, provided MSB first. The data stream for the AD7658-1 consists of four leading 0s and 12 bits of conversion data, provided MSB first.

The first bit of the conversion result is valid on the first SCLK falling edge after the

falling edge. The subsequent 15 data bits are clocked out on the rising edge of the SCLK signal. Data is valid on the SCLK falling edge. To access each conversion result, 16 clock pulses must be provided to the AD7656-1/AD7657-1/ AD7658-1. shows how a 16-SCLK read is used to

Figure 33

access the conversion results.

Rev. 0 | Page 25 of 32

AD7656-1/AD7657-1/AD7658-1

CONVST A, CONVST B, CONVST C

BUSY

DOUT A

SCLK

CONV

ACQ

V1 V2

QUIET

CONVST A, CONVST B, CONVST C

BUSY

DOUT B

DOUT C

SCLK

DOUT A

DOUT B

V5 V6

07017-030

Figure 31. Serial Interface with Three DOUT Lines

07017-031

Figure 32. Serial Interface with Two DOUT Lines

CONV

ACQ

ACQUISITI ON CONVERSI ON ACQUISIT ION

SCLK

DOUT A, DOUT B, DOUT C

DB15 DB14 DB13 DB1 DB0

QUIET

07017-032

Figure 33. Serial Read Operation

Rev. 0 | Page 26 of 32

AD7656-1/AD7657-1/AD7658-1

Daisy-Chain Mode (DCEN = 1, SER/

When reading conversion data back from the AD7656-1/AD7657-1/ AD7658-1 using three/two/one DOUT pins, it is possible to configure the parts to operate in daisy-chain mode by using the DCEN pin. This daisy-chain feature allows multiple AD7656-1/ AD7657-1/AD7658-1 devices to be cascaded together and is useful for reducing the component count and wiring connections. An example connection of two devices is shown in Figure 34. This configuration shows two DOUT lines being used for each device. Simultaneous sampling of the 12 analog inputs is possible by using a common CONVST signal. The DB5, DB4, and DB3 data pins are used as the DCIN[A:C] data input pins for the daisy-chain mode.

The rising edge of CONVST is used to initiate a conversion on the AD7656-1/AD7657-1/AD7658-1. After the BUSY signal has gone low to indicate that the conversion is complete, the user can begin to read the data from the two devices. Figure 35 shows the serial timing diagram when operating two AD7656-1/AD7657-1/ AD7658-1 devices in daisy-chain mode.

The

falling edge is used to frame the serial transfer from the AD7656-1/AD7657-1/AD7658-1 devices, to take the bus out of three-state, and to clock out the MSB of the first conversion result. In the example shown in , all 12 ADC channels are simultaneously sampled. Two DOUT lines are used to read the conversion results in this example. transfer. During the first 48 SCLKs, the conversion data is transferred from Device 2 to Device 1. DOUT A on Device 2 transfers conversion data from V1, V2, and V5 into DCIN A in Device 1; DOUT B on Device 2 transfers conversion results from V3, V4, and V6 to DCIN B in Device 1. During the first 48 SCLKs, Device 1 transfers data into the digital host. DOUT A on Device 1 transfers conversion data from V1, V2, and V5; DOUT B on Device 1 transfers conversion data from V3, V4, and V6. During the last 48 SCLKs, Device 2 clocks out 0s, and Device 1 shifts the data clocked in from Device 2 during the first 48 SCLKs into the digital host. This example can also be implemented using six 16-SCLK individually framed transfers if DCEN remains high during the transfers.

Figure 35

PA R

SEL = 1)

frames a 96 SCLK

Figure 36 shows the timing if two AD7656-1/AD7657-1/AD7658-1 devices are configured in daisy-chain mode and are operating with three DOUT lines. Assuming that a simultaneous sampling of all 12 inputs occurs, the the read operation. During the first 32 SCLKs of this transfer, the conversion results from Device 1 are clocked into the digital host and the conversion results from Device 2 are clocked into Device 1. During the last 32 SCLKs of the transfer, the conversion results from Device 2 are clocked out of Device 1 and into the digital host, and Device 2 clocks out 0s.

frames a 64 SCLK transfer during

Standby/Partial Power-Down Modes of Operation

PAR

(SER/

Each ADC pair can be individually placed into partial powerdown mode by bringing the CONVST signal low before the falling edge of BUSY. To power the ADC pair back up, the CONVST signal should be brought high to tell the ADC pair to power up and place the track-and-hold amplifier into track mode. After the power-up time from partial power-down has elapsed, the CONVST signal should receive a rising edge to initiate a valid conversion. In partial power-down mode, the reference buffers remain powered up. When an ADC pair is in partial power-down mode, conversions can still occur on the other ADCs.

The AD7656-1/AD7657-1/AD7658-1 have a standby mode whereby the devices can be placed into a low power consumption mode (25 µW maximum). The AD7656-1/AD7657-1/AD7658-1 are placed into standby mode by bringing the logic input low and can be powered up again for normal operation by bringing STBY

when the AD7656-1/AD7657-1/AD7658-1 are in standby mode, meaning the user can continue to access the conversion results of the parts. This standby feature can be used to reduce the average power consumed by the AD7656-1/AD7657-1/ AD7658-1 when operating at lower throughput rates. The parts can be placed into standby at the end of each conversion when BUSY goes low and are taken out of standby mode prior to the next conversion. The time for the AD7656-1/AD7657-1/ AD7658-1 to come out of standby is called the wake-up time. The wake-up time limits the maximum throughput rate at which the AD7656-1/AD7657-1/AD7658-1 can operate when powering down between conversions. See the section. Specifications

SEL = 0 or 1)

STBY

logic high. The output data buffers are still operational

Rev. 0 | Page 27 of 32

AD7656-1/AD7657-1/AD7658-1

CONVERT

DIGITAL HO ST

DATA IN1

DATA IN2

SCLK

07017-033

CONVST A, CONVST B, CONVST C

BUSY

CONVST

AD7656-1/ AD7657-1/ AD7658-1

SCLK

DCEN = 0 DEVICE 2

DOUT A

DOUT B

CONVST

DCIN A

DCIN B

AD7656-1/ AD7657-1/ AD7658-1

SCLK

DCEN = 1 DEVICE 1

DOUT A

DOUT B

Figure 34. Daisy-Chain Configuration

CONVST A, CONVST B, CONVST C

SCLK

DEVICE 1, DOUT A

DEVICE 1, DOUT B

DEVICE 2, DOUT A

DEVICE 2, DOUT B

BUSY

SCLK

DEVICE 1, DOUT A

DEVICE 1, DOUT B

DEVICE 1, DOUT C

DEVICE 2, DOUT A

123

MSB V1

MSB V3 LSB V3 MSB V4 LSB V4 MSB V6 LSB V6 MSB V3 LSB V3 MSB V4

MSB V1 LSB V1 MSB V2 LSB V2 MSB V5 LSB V5

MSB V3

15 16 17 31 32 33 47 48 49 63 6564 94 95 96

LSB V1 MSB V2 LSB V2 MSB V5 LSB V5 MSB V1 LSB V1 MSB V2 LSB V5

LSB V3 MSB V4 LSB V4 MSB V6 LSB V6

Figure 35. Daisy-Chain Serial Interface Timing with Two DOUT Lines

123

MSB V1

MSB V3

MSB V5

MSB V1 LSB V1 MSB V2 LSB V2

15 16 17 31 32 33 47 48 49 63 64

LSB V1 MSB V2 LSB V2 M SB V1 LSB V1 MSB V2 LSB V2

LSB V3 MSB V4 LSB V4 M SB V3 LSB V3 MSB V4 LSB V4

LSB V5 MSB V6 LSB V6 M SB V5 LSB V5 MSB V6 LSB V6

LSB V6

07017-034

DEVICE 2, DOUT B

DEVICE 2, DOUT C

MSB V3

MSB V5

LSB V3 MSB V4 LSB V4

LSB V5 MSB V6 LSB V6

Figure 36. Daisy-Chain Serial Interface Timing with Three DOUT Lines

Rev. 0 | Page 28 of 32

7017-035

AD7656-1/AD7657-1/AD7658-1

APPLICATION HINTS

LAYOUT

The printed circuit board that houses the AD7656-1/AD7657-1/ AD7658-1 should be designed so that the analog and digital sections are separated and confined to different areas of the board.

At least one ground plane should be used. It can be common or split between the digital and analog sections. In the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably underneath the AD7656-1/ AD7657-1/AD7658-1, or at least as close as possible to the part.

If the AD7656-1/AD7657-1/AD7658-1 are in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point, a star ground point, which should be established as close as possible to the AD7656-1/AD7657-1/AD7658-1. Good connections should be made to the ground plane. Avoid sharing one connection for multiple ground pins. Individual vias or multiple vias to the ground plane should be used for each ground pin.

Avoid running digital lines under the devices because doing so couples noise onto the die. The analog ground plane should be allowed to run under the AD7656-1/AD7657-1/AD7658-1 to avoid noise coupling. Fast-switching signals like CONVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on layers in close proximity on the board should run at right angles to each other to reduce the effect of feedthrough through the board.

The power supply lines to the AV on the AD7656-1/AD7657-1/AD7658-1 should use as large a trace as possible to provide low impedance paths and reduce the

, DVCC, V

, VDD, and VSS pins

DRIVE

effect of glitches on the power supply lines. Good connections should be made between the AD7656-1/AD7657-1/AD7658-1 supply pins and the power tracks on the board; this should involve the use of a single via or multiple vias for each supply pin.

Good decoupling is also important to lower the supply impedance presented to the AD7656-1/AD7657-1/AD7658-1 and to reduce the magnitude of the supply spikes. The decoupling capacitors should be placed close to, ideally right up against, these pins and their corresponding ground pins. Additionally, low-ESR 1 F capacitors should be placed on each of the supply pins, the REFIN/REFOUT pin, and each REFCAPx pin. Avoid sharing these capacitors between pins, and use vias to connect the capacitors to the power and ground planes. In addition, use wide, short traces between each via and the capacitor pad, or place the vias adjacent to the capacitor pad to minimize parasitic inductances. The AD7656-1/AD7657-1/AD7658-1 offer the user a reduced decoupling solution that is pin and software compatible with AD7656/AD7657/AD7658. The recommended reduced decoupling required for AD7656-1/AD7657-1/AD7658-1 is outlined in Figure 27.

Figure 27 shows an external Schmitt trigger device on the CONVST A, CONVST B, CONVST C inputs. The Schmitt trigger can be placed close to the CONVST pins (decoupled to the digital ground) and is used to eliminate any system noise that couples onto long CONVST A, CONVST B, CONVST C traces from being applied to the CONVST pins. The Schmitt trigger offers noise immunity to any high frequency noise, providing a clean conversion edge to the AD7656-1/AD7657-1/AD7658-1 device in cases where there is large system noise capable of coupling onto the CONVST trace.

Rev. 0 | Page 29 of 32

AD7656-1/AD7657-1/AD7658-1

OUTLINE DIMENSIONS

12.20

PIN 1

12.00 SQ

11. 80

4964

0.75

0.60

0.45

1.60 MAX

10.20

10.00 SQ

9.80

051706-A

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.20

0.09 7°

3.5° 0°

0.08 COPLANARIT Y

COMPLIANT TO JEDEC STANDARDS MS-026-BCD

VIEW A

LEAD PITCH

0.50

BSC

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

Figure 37. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7656BSTZ-1 AD7656BSTZ-1-RL AD7656YSTZ-1 AD7656YSTZ-1-RL AD7657BSTZ-1 AD7657BSTZ-1-RL AD7657YSTZ-1 AD7657YSTZ-1-RL AD7658BSTZ-1 AD7658BSTZ-1-RL AD7658YSTZ-1 AD7658YSTZ-1-RL EVAL-AD7656-1EDZ EVAL-AD7657-1EDZ EVAL-AD7658-1EDZ

Z = RoHS Compliant Part.

−40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2

−40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2

−40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2

−40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2

−40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2

−40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2

Evaluation Board

−40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2

Rev. 0 | Page 30 of 32

AD7656-1/AD7657-1/AD7658-1

NOTES

Rev. 0 | Page 31 of 32

AD7656-1/AD7657-1/AD7658-1

NOTES

Rev. 0 | Page 32 of 32

Datasheet AD7656-1, AD7657-1, AD7658-1 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual