Datasheet AD7653 Datasheet (Analog Devices)

16-Bit 1 MSPS PulSAR

TM

FEATURES

Throughput:

1 MSPS (Warp mode)
800 kSPS (Normal mode)

666 kSPS (Impulse mode)
16-bit resolution
Analog input voltage range: 0 V to 2.5 V
No pipeline delay
Parallel and serial 5 V/3 V interface

®/QSPI

TM

/MICROWIRETM/DSP compatible

SPI
Single 5 V supply operation
Power dissipation

92 mW typ @ 666 kSPS, 138 µW @ 1 kSPS without REF

128 mW typ @ 1 MSPS with REF
48-lead LQFP and 48-lead LFCSP packages
Pin-to-pin compatible with PulSAR ADCs

APPLICATIONS

Data acquisition
Instrumentation
Digital signal processing
Spectrum analysis
Medical instruments
Battery-powered systems
Process control

GENERAL DESCRIPTION

The AD7653* is a 16-bit, 1 MSPS, charge redistribution SAR
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high speed 16-bit sampling
ADC, internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system interface
ports. It features a very high sampling rate mode (Warp), a fast
mode (Normal) for asynchronous conversion rate applications,
and a reduced power mode (Impulse) for low power applica­tions where power is scaled with the throughput. The AD7653 is
fabricated using Analog Devices’ high performance, 0.6 micron
CMOS process, with correspondingly low cost. It is available in
a 48-lead LQFP and a tiny 48-lead LFCSP with operation
specified from –40°C to +85°C.

*

Patent Pending.

Unipolar ADC with Reference

AD7653

FUNCTIONAL BLOCK DIAGRAM

AGND

AVDD

INGND

PDREF

PDBUF

RESET

REFBUFIN

REF

IN

PD

REF REFGND

AD7653

SWITCHED

CAP DAC

CLOCK

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

CNVSTWARP IMPULSE

Figure 1.

Table 1. PulSAR Selection

Type/kSPS 100–250 500–570

Pseudo­Differential

AD7651
AD7660/AD7661

AD7650/AD7652

AD7664/AD7666

True Bipolar AD7663 AD7665 AD7671
True

AD7675 AD7676 AD7677

Differential
18-Bit AD7678 AD7679 AD7674
Multichannel/

Simultaneous

AD7654

AD7655

PRODUCT HIGHLIGHTS

1. Fast Throughput.

The AD7653 is a 1 MSPS, charge redistribution, 16-bit SAR
ADC with internal error correction circuitry.

2. Internal Reference.

The AD7653 has an internal reference with a typical
temperature drift of 7 ppm/°C.

3. Single-Supply Operation.

The AD7653 operates from a single 5 V supply. In Impulse
mode, its power dissipation decreases with the throughput.

4. Serial or Parallel Interface.

Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V and 5 V logic.

SERIAL

PORT

PARALLEL

INTERFACE

DGNDDVDD

OVDD

OGND

16

DATA[15:0]

BUSY

RD

CS

SER/PAR

OB/2C

BYTESWAP

02966-0-001

800–
1000

AD7653
AD7667

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD7653

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 7

Pin Configuration and Function Descriptions............................. 8

Definitions of Specifications ......................................................... 11

Typical Performance Characteristics ........................................... 12

Circuit Information........................................................................ 15

Converter Operation.................................................................. 15

Typical Connection Diagram.................................................... 17

Power Dissipation vs. Throughput........................................... 19

Conversion Control.................................................................... 19

Digital Interface.......................................................................... 20

Parallel Interface......................................................................... 20

Serial Interface............................................................................ 20

Master Serial Interface............................................................... 21

Slave Serial Interface.................................................................. 22

Microprocessor Interfacing....................................................... 24

Application Hints............................................................................ 25

Bipolar and Wider Input Ranges.............................................. 25

Layout .......................................................................................... 25

Evaluating the AD7653’s Performance.................................... 25

Outline Dimensions....................................................................... 26

Ordering Guide........................................................................... 26

REVISION HISTORY

Location Page

9/03—Data Sheet Changed from Rev. 0 to Rev. A

Change to Product Highlights .................................................... 1

Changes to Specifications............................................................ 3

Changes to Absolute Maximum Ratings ................................... 7

Changes to Figure 15.................................................................. 13

Changes to Figure 22.................................................................. 16

Changes to Voltage Reference Input section........................... 18

Changes to Figure 31.................................................................. 20

Rev. A | Page 2 of 28

AD7653

SPECIFICATIONS

Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted

Parameter Conditions Min Typ Max Unit

RESOLUTION 16 Bits
ANALOG INPUT

Voltage Range VIN – V
Operating Input Voltage VIN –0.1 +3 V

0 V

INGND

V

REF

V

–0.1 +0.5 V

INGND

Analog Input CMRR fIN = 10 kHz 65 dB
Input Current 1 MSPS Throughput 12 µA
Input Impedance1

THROUGHPUT SPEED

Complete Cycle In Warp Mode 1 µs
Throughput Rate In Warp Mode 1 1000 kSPS
Time between Conversions In Warp Mode 1 ms
Complete Cycle In Normal Mode 1.25 µs
Throughput Rate In Normal Mode 0 800 kSPS
Complete Cycle In Impulse Mode 1.5 µs
Throughput Rate In Impulse Mode 0 666 kSPS

DC ACCURACY

Integral Linearity Error –6 +6 LSB2
No Missing Codes 15 Bits
Differential Linearity Error –2 +3 LSB
Transition Noise 0.7 LSB
Unipolar Zero Error, T

MIN

to T

3

±25 LSB

MAX

Unipolar Zero Error Temperature Drift ±0.2 ppm/°C
Full-Scale Error, T

MIN

Full-Scale Error Temperature Drift

to T

3

REF = 2.5 V ±0.12 % of FSR

MAX

±0.4

ppm/°C

Power Supply Sensitivity AVDD = 5 V ± 5%, with REF ±2 LSB

AC ACCURACY

Signal-to-Noise fIN = 100 kHz 86 dB4
Spurious Free Dynamic Range fIN = 100 kHz 98 dB
Total Harmonic Distortion fIN = 45 kHz –98 dB

f

= 100 kHz –96 dB

IN

Signal-to-(Noise + Distortion) fIN = 100 kHz 86 dB

–60 dB Input, fIN = 100 kHz 30 dB

–3 dB Input Bandwidth 12 MHz

SAMPLING DYNAMICS

Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 250 ns

REFERENCE

Internal Reference Voltage V

@ 25°C 2.48 2.50 2.52 V

REF

Internal Reference Temperature Drift –40°C to +85°C ±7 ppm/°C
Line Regulation
Turn-On Settling Time C

AVDD = 5 V ± 5%

= 10 µF 5 ms

REF

±24 ppm/V

Temperature Pin

Voltage Output @ 25°C 300 mV
Temperature Sensitivity 1 mV/°C

Output Resistance 4.3 kΩ
External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 1 MSPS Throughput 300 µA

Rev. A | Page 3 of 28

AD7653

Parameter Conditions Min Typ Max Unit

DIGITAL INPUTS

Logic Levels

VIL –0.3 +0.8 V
VIH 2.0 DVDD + 0.3 V
IIL –1 +1 µA
IIH –1 +1 µA

DIGITAL OUTPUTS

Data Format5
Pipeline Delay6

VOL I
VOH I

POWER SUPPLIES

Specified Performance

AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.257 V

Operating Current8 1 MSPS Throughput

AVDD9 With Reference and Buffer 18.7 mA
AVDD10 Reference and Buffer Alone 3 mA
DVDD11 6.7 mA
OVDD11 200 µA

Power Dissipation without REF 666 kSPS Throughput11 92 115 mW

1 kSPS Throughput11 138 µW

Power Dissipation with REF 1 MSPS Throughput8 128 145 mW

TEMPERATURE RANGE12

Specified Performance T

= 1.6 mA 0.4 V

SINK

= –500 µA OVDD – 0.6 V

SOURCE

to T

MIN

–40 +85 °C

MAX

1

See Analog Input section.

2

LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV.

3

See Definitions of Specifications section. These specifications do not include the error contribution from the external reference.

4

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

5

Parallel or serial 16-bit.

6

Conversion results are available immediately after completed conversion.

7

The max should be the minimum of 5.25 V and DVDD + 0.3 V.

8

In Warp mode.

9

With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH.

10

With PDREF, PDBUF LOW and PD HIGH.

11

Impulse Mode. Tested in Parallel Reading mode.

12

Consult factory for extended temperature range.

Rev. A | Page 4 of 28

AD7653

TIMING SPECIFICATIONS

Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted

Parameter

Refer to Figure 26 and Figure 27

Convert Pulse Width
Time between Conversions (Warp Mode/Normal Mode/Impulse Mode)1
CNVST

LOW to BUSY HIGH Delay t3

BUSY HIGH All Modes Except Master Serial Read after Convert

(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
RESET Pulse Width

Refer to Figure 28, Figure 29, and (Parallel Interface Modes)

CNVST

LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) t10

Figure 30

DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time

Refer to Figure 32 and Figure 33 (Master Serial Interface Modes)2

CS

LOW to SYNC Valid Delay t14
CS

LOW to Internal SCLK Valid Delay2
CS

LOW to SDOUT Delay t16
CNVST

LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) t17
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period3
Internal SCLK HIGH3
Internal SCLK LOW3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SCLK Last Edge to SYNC Delay3
CS

HIGH to SYNC HI-Z t25

CS

HIGH to Internal SCLK HI-Z t26

CS

HIGH to SDOUT HI-Z t27

BUSY HIGH in Master Serial Read after Convert3

(Warp Mode/Normal Mode/Impulse Mode)

CNVST

LOW to SYNC Asserted Delay

(Warp Mode/Normal Mode/Impulse Mode)

SYNC Deasserted to BUSY LOW Delay

Refer to and (Slave Serial Interface Modes) 2

Figure 34 Figure 35
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW

1In Warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.

2

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

3

In Serial Master Read during Convert Mode. See for Serial Master Read after Convert mode. Table 4

Symbol

t

1

t

2

t

4

t

5

t

6

t

7

t

8

t

9

t

11

t

12

t

13

t

15

t

18

t

19

t

20

t

21

t

22

t

23

t

24

t

28

t

29

t

30

t

31

t

32

t

33

t

34

t

35

t

36

t

37

Min Typ Max Unit

10 ns
1/1.25/1.5 µs

35 ns

0.75/1/1.25 µs
2 ns
10 ns

0.75/1/1.25 µs
250 ns
10 ns

0.75/1/1.25 µs
12 ns
45 ns
5 15 ns

10 ns
10 ns
10 ns
25/275/525 ns
3 ns
25 40 ns
12 ns
7 ns
4 ns
2 ns
3 ns
10 ns
10 ns
10 ns

See Table 4

0.75/1/1.25 µs
25 ns

5 ns
3 18 ns
5 ns
5 ns
25 ns
10 ns
10 ns

Rev. A | Page 5 of 28

AD7653

Table 4. Serial Clock Timings in Master Read after Convert

DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns
Internal SCLK Period Minimum t19 25 50 100 200 ns
Internal SCLK Period Maximum t19 40 70 140 280 ns
Internal SCLK HIGH Minimum t20 12 22 50 100 ns
Internal SCLK LOW Minimum t21 7 21 49 99 ns
SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns
SDOUT Valid Hold Time Minimum t23 2 4 30 80 ns
SCLK Last Edge to SYNC Delay Minimum t24 3 55 130 290 ns
BUSY HIGH Width Maximum (Warp) t28 1.5 2 3 5.25 µs
BUSY HIGH Width Maximum (Normal) t28 1.75 2.25 3.25 5.55 µs
BUSY HIGH Width Maximum (Impulse) t28 2 2.5 3.5 5.75 µs

Rev. A | Page 6 of 28

AD7653

ABSOLUTE MAXIMUM RATINGS

Table 5. AD7653 Absolute Maximum Ratings1

Parameter Rating

IN2, TEMP2,REF, REFBUFIN,

INGND, REFGND to AGND

AVDD + 0.3 V to
AGND – 0.3 V

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V

TO OUTPUT

PIN

60pF*

* IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD

OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.

C

L

1.6mA

C

L

500µA

DVDD to OVDD –0.3 V to +7 V

Digital Inputs –0.3 V to DVDD + 0.3 V
PDREF, PDBUF3 ±20 mA
Internal Power Dissipation4 700 mW

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, SCLK Outputs C

Internal Power Dissipation5 2.5 W
Junction Temperature 150°C
Storage Temperature Range –65°C to +150°C
Lead Temperature Range

300°C

0.8V

t

DELAY

2V

0.8V

(Soldering 10 sec)

1

Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

2

See section.

Analog Input

3

See Voltage Reference Input section.

4

Specification is for the device in free air:

48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W

5

Specification is for the device in free air:

48-Lead LFCSP; θJA = 26°C/W.

Figure 3. Voltage Reference Levels for Timing

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

I

OL

1.4V

I

OH

L

2V

= 10 pF

t

DELAY

2V

0.8V

02966-0-006

02966-0-007

Rev. A | Page 7 of 28

AD7653

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PDBUF

PDREF

REFBUFIN

TEMP

AVDDINAGND

AGNDNCINGND

REFGND

48

47 46 45 44 39 38 3743 42 41 40

1

AGND

AVDD

NC

BYTESWAP

OB/2C
WARP

IMPULSE

SER/PAR

D0

D1
D2/DIVSCLK0

D3/DIVSCLK1

NC = NO CONNECT

PIN 1
IDENTIFIER

2

3

4

5

6

7

8

9

10

11

12

13 14

D4/EXT/INT

AD7653

TOP VIEW

(Not to Scale)

15 16 17 18 19 20 21 22 23 24

DVDD

OVDD

DGND

OGND

D6/INVSCLK

D5/INVSYNC

D7/RDC/SDIN

Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1, 36,

AGND P Analog Power Ground Pin.

41, 42
2, 44 AVDD P Input Analog Power Pin. Nominally 5 V.
3, 40 NC No Connect.
4 BYTESWAP DI Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on

D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].

5

OB/2C

DI

Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary;
when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift
register.

6 WARP DI Mode Selection. When this pin is HIGH and the IMPULSE pin is LOW, this input selects the fastest

mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in
order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of
the minimum conversion rate.

7 IMPULSE DI Mode Selection. When IMPULSE is HIGH and WARP is LOW, this input selects a reduced power

mode. In this mode, the power dissipation is approximately proportional to the sampling rate.

8

SER/PAR

DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial

interface mode is selected and some bits of the DATA bus are used as a serial port.

9, 10 D[0:1] DO

Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR
impedance.

11, 12 D[2:3]or

DIVSCLK[0:1]

DI/O

When SER/PAR
When SER/PAR

is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.

is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert),
these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that
clocks the data output. In other serial modes, these pins are not used.

13 D4 or

INT

EXT/

DI/O

When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus.
When SER/PAR

is HIGH, this input, part of the serial port, is used as a digital select input for choos­ing the internal data clock or an external data clock. With EXT/INT
selected on the SCLK output. With EXT/INT
external clock signal connected to the SCLK input.

14 D5 or

INVSYNC

DI/O

When SER/PAR
When SER/PAR

is LOW, this output is used as Bit 5 of the parallel port data output bus.

is HIGH, this input, part of the serial port, is used to select the active state of the
SYNC signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When
HIGH, SYNC is active LOW.

REF

36

AGND

35

CNVST

34

PD

33

RESET

32

CS

31

RD

30

DGND

29

BUSY

28

D15

27

D14

26

D13

25

D12

D9/SCLK

D10/SYNC

D8/SDOUT

D11/RDERROR

02966-0-002

is HIGH, these outputs are in high

tied LOW, the internal clock is

set to logic HIGH, output data is synchronized to an

Rev. A | Page 8 of 28

AD7653

Pin No. Mnemonic Type1 Description

15 D6 or

INVSCLK

16 D7 or

RDC/SDIN

17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host interface

19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.
21 D8 or

SDOUT

22 D9 or

SCLK

23 D10 or

SYNC

24 D11 or

RDERROR

25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the

29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion

30 DGND P Must Be Tied to Digital Ground.
31

32

33 RESET DI Reset Input. When set to a logic HIGH, this pin resets the AD7653 and the current conversion, if any,

34 PD DI Power-Down Input. When set to logic HIGH, power consumption is reduced and conversions are

35

RD
CS

CNVST

DI/O

DI/O

DO

DI/O

DO

DO

DI
DI

DI

When SER/PAR
When SER/PAR
in both master and slave modes.
When SER/PAR
When SER/PAR
read mode selection input depending on the state of EXT/INT

When EXT/INT
results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on
DATA with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data
is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT
only when the conversion is complete.

(5 V or 3 V).

When SER/PAR
When SER/PAR
nized to SCLK. Conversion results are stored in an on-chip register. The AD7653 provides the

conversion result, MSB first, from its internal shift register. The DATA format is determined by the
logic level of OB/2C
serial mode when EXT/INT
and valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge
and valid on the next rising edge.

When SER/PAR
When SER/PAR

depending upon the logic state of the EXT/INT
updated depends upon the logic state of the INVSCLK pin.
When SER/PAR

When SER/PAR
synchronization for use with the internal data clock (EXT/INT
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is

valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains
LOW while the SDOUT output is valid.

When SER/PAR
SER/PAR
error flag. In slave mode, when a data read is started and not complete when the following

conversion is complete, the current data is lost and RDERROR is pulsed HIGH.

state of SER/PAR

is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.

Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS

is also used to gate the external clock.

is aborted. If not used, this pin could be tied to DGND.

inhibited after the current one is completed.
Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and

initiates a conversion. In Impulse mode (IMPULSE HIGH, WARP LOW), if CNVST
the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a
conversion is immediately started.

is LOW, this output is used as Bit 6 of the parallel port data output bus.
is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active

is LOW, this output is used as Bit 7 of the parallel port data output bus.
is HIGH, this input, part of the serial port, is used as either an external data input or a

.

is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion

is LOW, this output is used as Bit 8 of the parallel port data output bus.
is HIGH, this output, part of the serial port, is used as a serial data output synchro-

. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In

is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge

is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus.
is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,

pin. The active edge where the data SDOUT is

is LOW, this output is used as Bit 10 of the parallel port data output bus.
is HIGH, this output, part of the serial port, is used as a digital output frame

= logic LOW). When a read sequence is

is LOW, this output is used as Bit 11 of the parallel port data output bus. When

and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read

.

is held LOW when

Rev. A | Page 9 of 28

AD7653

Pin No. Mnemonic Type1 Description

37 REF AI/O Reference Input Voltage. On-chip reference output voltage.
38 REFGND AI Reference Input Analog Ground.
39 INGND AI Analog Input Ground.
43 IN AI Primary Analog Input with a Range of 0 V to 2.5 V.
45 TEMP AO Temperature Sensor Voltage Output.
46 REFBUFIN AI/O Reference Input Voltage. The reference output and the reference buffer input.
47 PDREF DI This pin allows the choice of internal or external voltage references. When LOW, the on-chip

reference is turned on. When HIGH, the internal reference is switched off and an external reference
must be used.

48 PDBUF DI This pin allows the choice of buffering an internal or external reference with the internal buffer.

When LOW, the buffer is selected. When HIGH, the buffer is switched off.

1

AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.

Rev. A | Page 10 of 28

AD7653

DEFINITIONS OF SPECIFICATIONS

Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.

Full-Scale Error

The last transition (from 011…10 to 011…11 in twos
complement coding) should occur for an analog voltage 1½ LSB
below the nominal full scale (2.49994278 V for the 0 V to 2.5 V
range). The full-scale error is the deviation of the actual level of
the last transition from the ideal level.

Unipolar Zero Error

The first transition should occur at a level ½ LSB above analog
ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero
error is the deviation of the actual transition from that point.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula:

ENOB = (S/[N+D]dB – 1.76)/6.02

and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (S/[N+D])

S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.

Aperture Delay

Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the

CNVST

input to when

the input signal is held for a conversion.

Transient Response

Transient response is the time required for the AD7653 to
achieve its rated accuracy after a full-scale step function is
applied to its input.

Overvoltage Recovery

Overvoltage recovery is the time required for the ADC to
recover to full accuracy after an analog input signal 150% of the
full-scale value is reduced to 50% of the full-scale value.

Reference Voltage Temperature Coefficient

Reference voltage temperature coefficient is the change of
internal reference voltage output voltage V over the operating
temperature range and normalized by the output voltage at
25°C, expressed in ppm/°C. The equation follows:

)(–)(

TVTV

12

6

)/( ×

=°

CppmTCV

×°

10

12

)–()C25(

TTV

where:
V(25°C) = V at +25°C

) = V at Temperature 2 (+85°C)

V(T

2

) = V at Temperature 1 (–40°C)

V(T

1

Rev. A | Page 11 of 28

AD7653

TYPICAL PERFORMANCE CHARACTERISTICS

4

2.0

3

2

1

0

INL (LSB)

–1

–2

–3

–4

0

16384 32768 65536

CODE

Figure 5. Integral Nonlinearity vs. Code

140000

120000

100000

80000

60000

COUNTS

40000

20000

15906

00 00

0

7FFB

679

114641

112516

CODE IN HEX

Figure 6. Histogram of 261,120 Conversions of a

DC Input at the Code Transition

0

–20

–40

–60

–80

–100

–120

–140

AMPLITUDE (dB of Full Scale)

–160

–180

0

100

200 300 500400

FREQUENCY (kHz)

Figure 7. FFT Plot

49152

17001

377

8000 8001 80038002

f

= 1000kSPS

S

f

IN

SNR = 86.0dB
THD = 90.3dB
SFDR = 91.5dB
S/[N+D] = 84.8dB

= 101kHz

02966-0-023

80047FFC 7FFD 7FFE 7FFF

02966-0-027

02966-0-029

1.5

1.0

0.5

DNL (LSB)

0

–0.5

–1.0

0

16384 32768 65536

CODE

49152

02966-0-026

Figure 8. Differential Nonlinearity vs. Code

160000

140000

120000

100000

80000

COUNTS

60000

40000

20000

0

0

2856

53

146148

54482

8000 8001 80038002

CODE IN HEX

54473

3099

90

80047FFC 7FFD 7FFE 7FFF

02966-0-028

Figure 9. Histogram of 261,120 Conversions of a

DC Input at the Code Center

SNR

S/[N+D]

02966-0-030

1000

15.0

14.5

14.0

13.5

ENOB (Bits)

13.0

12.5

12.0

90

87

84

81

78

SNR, S/[N+D] (dB)

75

72

1

10

FREQUENCY (kHz)

ENOB

100

Figure 10. SNR, S/(N+D), and ENOB vs. Frequency

Rev. A | Page 12 of 28

AD7653

–50

SFDR

THD

SECOND
HARMONIC

10

FREQUENCY (kHz)

THIRD
HARMONIC

100

1000

02966-0-031

–100

THD, HARMONICS (dB)

–110

–120

–60

–70

–80

–90

1

Figure 11. THD, Harmonics, and SFDR vs. Frequency

92

91

90

88

87

86

85

84

83

SNR, S/[N+D] REFERRED TO FULL SCALE (dB)

82

89

–60

INPUT LEVEL (dB)

SNR

S/[N+D]

02966-A-032

Figure 12. SNR and S/(N+D) vs. Input Level (Referred to Full Scale)

89

88

87

SNR, S/[N+D] (dB)

86

85

–55

SNR

S[N+D]

ENOB

585

TEMPERATURE (°C)

105

02966-0-033

125–35 –15 25 45 65

Figure 13. SNR, S/(N+D), and ENOB vs. Temperature

120

100

80

60

SFDR (dB)

40

20

0

0–50 –40 –30 –20 –10

14.75

14.50

14.25

ENOB (Bits)

14.00

13.75

–95

SECOND
HARMONIC

THIRD
HARMONIC

–105

–115

THD, HARMONICS (dB)

–125

–55

THD

585

TEMPERATURE (°C)

Figure 14. THD and Harmonics vs. Temperature

100000

OPERATING CURRENT (µA)

10000

1000

100

10

0.1

0.01

0.001

AVDD, IMPULSE

1

10

AVDD, WARP/NORMAL

DVDD, WARP/NORMAL

DVDD, IMPULSE

OVDD, ALL MODES

PDREF = PDBUF = HIGH

1000

SAMPLE RATE (SPS)

Figure 15. Operating Current vs. Sample Rate

6

5

4

3

2

1

0

–1

–2

–3

–4

ZERO ERROR, FULL SCALE (LSB)

–5

–6

–55

–15

TEMPERATURE (°C)

FULL SCALE

ZERO ERROR

85

Figure 16. Zero Error, Full Scale with Reference vs. Temperature

105

02966-0-034

02966-0-036

105

02966-0-040

125–35 –15 25 45 65

1000000100 10000 100000

125–35 5 25 45 65

Rev. A | Page 13 of 28

AD7653

2.5020

2.5019

2.5018

2.5017

2.5016

2.5015

2.5014

VREF (V)

2.5013

2.5012

2.5011

2.5010

2.5009

2.5008
–40

–20 0 20 40 60

TEMPERATURE (°C)

Figure 17. Typical Reference Output Voltage vs. Temperature

90

80

60

50

40

30

NUMBER OF UNITS

20

10

0

–30

–26 –22 –18 –1470–10 –6 –2 2 3026221814106

REFERENCE DRIFT (ppm/°C)

Figure 18. Reference Voltage Temperature Coefficient Distribution (335 Units)

80 100 120

02966-0-038

02966-0-039

50

OVDD = 2.7V @ 85°C

40

30

DELAY (ns)

20

12

t

10

0

0

Figure 19. Typical Delay vs. Load Capacitance C

OVDD = 2.7V @ 25°C

CL (pF)

OVDD = 5V @ 85°C

OVDD = 5V @ 25°C

02966-0-035

L

20050 100 150

Rev. A | Page 14 of 28

AD7653

CIRCUIT INFORMATION

IN

REF

REFGND

INGND

MSB

32,768C

16,384C 4C 2C C C

Figure 20. ADC Simplified Schematic

65,536C

LSB

SW

SW

A

COMP

B

SWITCHES

CONTROL

CONTROL

LOGIC

CNVST

BUSY

OUTPUT

CODE

02966-0-005

The AD7653 is a very fast, low power, single supply, precise
16-bit analog-to-digital converter (ADC). The AD7653 features
different modes to optimize performance according to the
application. In Warp mode, the part can convert 1 million
samples per second.

The AD7653 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.

The AD7653 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in
either a 48-lead LQFP or a 48-lead LFCSP that saves space and
allows flexible configurations as either a serial or a parallel
interface. The AD7653 is a pin-to-pin compatible upgrade of the
AD7651/AD7652.

CONVERTER OPERATION

The AD7653 is a successive approximation ADC based on a
charge redistribution DAC. F shows a simplified
schematic of the ADC. The capacitive DAC consists of an array
of 16 binary weighted capacitors and an additional LSB
capacitor. The comparator’s negative input is connected to a
dummy capacitor of the same value as the capacitive DAC array.

During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND
via SWA. All independent switches are connected to the analog
input IN. Thus, the capacitor array is used as a sampling
capacitor and acquires the analog signal on IN. Similarly, the
dummy capacitor acquires the analog signal on INGND.

When

CNVST

goes LOW, a conversion phase is initiated. When

the conversion phase begins, SWA and SWB are opened. The
capacitor array and dummy capacitor are then disconnected

igure 20

from the inputs and connected to REFGND. Therefore, the
differential voltage between IN and INGND captured at the end
of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between REFGND and REF,
the comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4, …VREF/65536). The control logic toggles
these switches, starting with the MSB, to bring the comparator
back into a balanced condition.

After this process is completed, the control logic generates the
ADC output code and brings the BUSY output LOW.

Modes of Operation

The AD7653 features three modes of operations: Warp, Normal,
and Impulse. Each mode is best suited for specific applications.

Warp mode allows the fastest conversion rate up to 1 MSPS.
However in this mode and this mode only, the full specified
accuracy is guaranteed only when the time between conversions
does not exceed 1 ms. If the time between two consecutive
conversions is longer than 1 ms (e.g., after power-up), the first
conversion result should be ignored. This mode makes the
AD7653 ideal for applications where both high accuracy and
fast sample rate are required.

Normal mode is the fastest mode (800 kSPS) without any
limitations on the time between conversions. This mode makes
the AD7653 ideal for asynchronous applications such as data
acquisition systems, where both high accuracy and fast sample
rate are required.

Impulse mode, the lowest power dissipation mode, allows power
saving between conversions. When operating at 1 kSPS, for
example, it typically consumes only 138 µW. This feature makes
the AD7653 ideal for battery-powered applications.

Rev. A | Page 15 of 28

AD7653

Transfer Functions

Using the OB/2C digital input, the AD7653 offers two output
codings: straight binary and twos complement. The LSB size is

/65536, which is about 38.15 µV. The AD7653’s ideal

V

REF

transfer characteristic is shown in and . Table 7

1 LSB = V

111...111

111...110

111...101

ADC CODE (Straight Binary)

000...010

000...001

000...000
1LSB0V

0.5 LSB

Figure 21. ADC Ideal Transfer Function

Figure 21

/65536

REF

ANALOG INPUT

V

REF

V

REF

– 1.5 LSB

– 1 LSB

02966-0-003

Table 7. Output Codes and Ideal Input Voltages

Digital Output Code (Hex)

Description

Analog
Input

Straight
Binary

Twos
Complement

FSR – 1 LSB 2.499962 V FFFF1 7FFF1
FSR – 2 LSB 2.499923 V FFFE 7FFE
Midscale + 1 LSB 1.250038 V 8001 0001
Midscale 1.25 V 8000 0000
Midscale – 1 LSB 1.249962 V 7FFF FFFF
–FSR + 1 LSB 38 µV 0001 8001
–FSR 0 V 00002 80002

1

This is also the code for overrange analog input (VIN – V

V

– V

REFGND

).

REF

2

This is also the code for underrange analog input (VIN below V

INGND

above

INGND

).

ANALOG

SUPPLY

(5V)

ANALOG INPUT

(0VTO 2.5V)

+

4

C

R

15Ω

2

U1

C

C

NOTES

1

THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER.

2

THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.

3

OPTIONAL LOW JITTER.

4

A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M).

SEE VOLTAGE REFERENCE INPUT SECTION.

10µF

100nF

100nF

2.7nF

PDREF

20

Ω

+

AVDD DGND DVDD OVDD OGND

REF

REFBUFIN

REFGND

IN

INGND

GND

1

PDBUF

PD RESET

10µF

AD7653

100nF

SCLK

SDOUT

BUSY

CNVST

OB/2C

SER/PAR

WARP

BYTESWAP

IMPULSE

RDCS

Figure 22. Typical Connection Diagram

100nF

DIGITAL SUPPLY

10

µ

F

SERIAL

PORT

(3.3V OR 5V)

+

µC/µP/DSP

3

D

DVD D

CLOCK

02966-A-004

Rev. A | Page 16 of 28

AD7653

O

TYPICAL CONNECTION DIAGRAM

Figure 22 shows a typical connection diagram for the AD7653.

Analog Input

Figure 23
the AD7653.

The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN and INGND. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 0.3 V. This will cause these diodes to become
forward-biased and start conducting current. These diodes can
handle a forward-biased current of 100 mA maximum. For
instance, these conditions could eventually occur when the
input buffer’s (U1) supplies are different from AVDD. In such a
case, an input buffer with a short-circuit current limitation can
be used to protect the part.

This analog input structure allows the sampling of the different­tial signal between IN and INGND. Unlike other converters,
INGND is sampled at the same time as IN. By using this differ­ential input, small signals common to both inputs are rejected.
For instance, by using INGND to sense a remote signal ground,
ground potential differences between the sensor and the local
ADC ground are eliminated.

During the acquisition phase, the impedance of the analog input
IN can be modeled as a parallel combination of capacitor C1
and the network formed by the series connection of R1 and C2.
C1 is primarily the pin capacitance. R1 is typically 168 Ω and is
a lumped component made up of some serial resistors and the
on resistance of the switches. C2 is typically 60 pF and is mainly
the ADC sampling capacitor. During the conversion phase,

shows an equivalent circuit of the input structure of

AV D D

R INGND

AGND

IN

Figure 23. Equivalent Analog Input Circuit

D1

C1

D2

R1

C2

02966-0-008

when the switches are opened, the input impedance is limited to
C1. R1 and C2 make a 1-pole low-pass filter that reduces
undesirable aliasing effects and limits the noise.

When the source impedance of the driving circuit is low, the
AD7653 can be driven directly. Large source impedances will
significantly affect the ac performance, especially total
harmonic distortion.

Driver Amplifier Choice

Although the AD7653 is easy to drive, the driver amplifier needs
to meet the following requirements:

• The driver amplifier and the AD7653 analog input circuit

must be able to settle for a full-scale step of the capacitor
array at a 16-bit level (0.0015%). In the amplifier’s data
sheet, settling at 0.1% to 0.01% is more commonly
specified. This could differ significantly from the settling
time at a 16-bit level and should be verified prior to driver
selection. The tiny op amp AD8021, which combines
ultralow noise and high gain-bandwidth, meets this settling
time requirement even when used with gains up to 13.

• The noise generated by the driver amplifier needs to be

kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7653. The noise
coming from the driver is filtered by the AD7653 analog
input circuit 1-pole low-pass filter made by R1 and C2 or
by the external filter, if one is used.

• The driver needs to have a THD performance suitable to

that of the AD7653.

The AD8021 meets these requirements and is appropriate for
almost all applications. The AD8021 needs a 10 pF external
compensation capacitor that should have good linearity as an
NPO ceramic or mica type.

The AD8022 could also be used if a dual version is needed and
gain of 1 is present. The AD829 is an alternative in applications
where high frequency (above 100 kHz) performance is not
required. In gain of 1 applications, it requires an 82 pF
compensation capacitor. The AD8610 is an option when low
bias current is needed in low frequency applications.

Rev. A | Page 17 of 28

AD7653

A

T

Voltage Reference Input

The AD7653 allows the choice of either a very low temperature
drift internal voltage reference or an external 2.5 V reference.

For applications that use multiple AD7653s, it is more effective
to use the internal buffer to buffer the reference voltage.

Unlike many ADCs with internal references, the internal
reference of the AD7653 provides excellent performance and
can be used in almost all applications.

To use the internal reference along with the internal buffer,
PDREF and PDBUF should both be LOW. This will produce a

1.207 V voltage on REFBUFIN which, amplified by the buffer,
will result in a 2.5 V reference on the REF pin.

The output impedance of REFBUFIN is 11 k

the reference is enabled.

It is useful to decouple REFBUFIN with

Ω (minimum) when

a 100 nF ceramic capacitor. Thus, the 100 nF capacitor provides
an RC filter for noise reduction.

To use an external reference along with the internal buffer,
PDREF should be HIGH and PDBUF should be LOW. This
powers down the internal reference and allows the 2.5 V
reference to be applied to REFBUFIN.

To use an external reference directly on the REF pin, PDREF
and PDBUF should both be HIGH.

PDREF and PDBUF, respectively, power down the internal
reference and the internal reference. Note that the PDREF and
PDBUF input current should never exceed 20 mA. This could
eventually occur when input voltage is above AVDD (for
instance at power-up). In this case, a 100 Ω series resistor is
recommended.

The internal reference is temperature compensated to 2.5 V ±
20 mV. The reference is trimmed to provide a typical drift of 7

. This typical drift characteristic is shown in .

ppm/°C Figure 17
For improved drift performance, an external reference such as
the AD780 can be used.

The AD7653 voltage reference input REF has a dynamic input
impedance; it should, therefore, be driven by a low impedance
source with efficient decoupling between the REF and REFGND
inputs. This decoupling depends on the choice of the voltage
reference, but usually consists of a low ESR capacitor connected
to REF and REFGND with minimum parasitic inductance. A
10 µF (X5R, 1206 size) ceramic chip capacitor (or 47 µF
tantalum capacitor) is appropriate when using either the
internal reference or one of these recommended reference
voltages:

Care should be taken with the voltage reference’s temperature
coefficient, which directly affects the full-scale accuracy, if this
parameter matters. For instance, a ±15 ppm/°C temperature
coefficient of the reference changes full scale by ±1 LSB/°C.

Note that V
input range is defined in terms of V

can be increased to AVDD – 1.85 V. Since the

REF

, this would essentially

REF

increase the range to 0 V to 3 V with an AVDD above 4.85 V.
The AD780 can be selected with a 3 V reference voltage.

The TEMP pin, which measures the temperature of the AD7653,
can be used as shown in . The output of the TEMP pin

Figure 24
is applied to one of the inputs of the analog switch (e.g.,

ADG779), and the ADC itself is used to measure its own

temperature. This configuration is very useful for improving the
calibration accuracy over the temperature range.

TEMP

AD7653

TEMPERATURE
SENSOR

02966-0-024

NALOG INPU

(UNIPOLAR)

ADG779

IN

AD8021

Figure 24. Temperature Sensor Connection Diagram

C

C

Power Supply

The AD7653 uses three power supply pins: an analog 5 V supply
AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. OVDD allows direct
interface with any logic between 2.7 V and DVDD + 0.3 V. To
reduce the supplies needed, the digital core (DVDD) can be
supplied through a simple RC filter from the analog supply, as
shown in . The AD7653 is independent of power

Figure 22
supply sequencing once OVDD does not exceed DVDD by
more than 0.3 V, and is thus free of supply voltage induced
latch-up.

• The low noise, low temperature drift ADR421 and AD780

• The low power ADR291

• The low cost AD1582

Rev. A | Page 18 of 28

AD7653

POWER DISSIPATION VS. THROUGHPUT

Operating currents are very low during the acquisition phase,
allowing significant power savings when the conversion rate is
reduced (see F ). This power savings depends on the

igure 25
mode used. In Impulse mode, the AD7653 automatically
reduces power consumption at the end of each conversion
phase. This makes the part ideal for very low power battery
applications. The digital interface and the reference remain
active even during the acquisition phase. To reduce operating
digital supply currents even further, digital inputs need to be
driven close to the power supply rails (i.e., DVDD or DGND),
and OVDD should not exceed DVDD by more than 0.3 V.

1000000

100000

10000

1000

POWER DISSIPATION (µW)

100

10

WARP MODE POWER

IMPULSE MODE POWER

10

1000

SAMPLE RATE (SPS)

PDREF = PDBUF = HIGH

Figure 25. Power Dissipation vs. Sampling Rate

1000000100 10000 100000

02966-0-041

CONVERSION CONTROL

Figure 26
process. The AD7653 is controlled by the

initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete.

In Impulse mode, conversions can be automatically initiated. If
CNVST
the acquisition phase and automatically initiates a new con­version. By keeping

conversion process running by itself. It should be noted that the
analog input must be settled when BUSY goes low. Also, at
power-up,

conversion process. In this mode, the AD7653 can run slightly
faster than the guaranteed 666 kSPS limits in Impulse mode.
This feature does not exist in Warp and Normal modes.

Although

special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.

shows the detailed timing diagrams of the conversion

signal, which

CNVST

operates independently of CS and RD.

CNVST

is held LOW when BUSY is LOW, the AD7653 controls

LOW, the AD7653 keeps the

CNVST

CNVST

CNVST

should be brought LOW once to initiate the

is a digital signal, it should be designed with

The

value serial resistor (i.e., 50
close to the output of the component that drives this line.

For applications where SNR is critical, the

have very low jitter. This may be achieved by using a dedicated
oscillator for

high frequency, low jitter clock, as shown in . Figure 22

CNVST

BUSY

MODE

RESET

BUSY

DATA

CNVST

CS = RD = 0

CNVST

BUSY

DATA

BUS

Figure 28. Master Parallel Data Timing for Reading (Continuous Read)

trace should be shielded with ground and a low

CNVST

Ω) termination should be added

signal should

CNVST

generation, or to clock

CNVST

t

t

1

t

t

3

t

5

ACQUIRE CONVERT ACQUIRE CONVERT

4

t

7

2

t

6

t

8

CNVST

Figure 26. Basic Conversion Timing

t

9

t

8

Figure 27. RESET Timing

t

1

t

10

t

t

3

PREVIOUS CONVERSION DATA NEW DATA

4

t

11

with a

02966-0-011

02966-0-011

02966-0-012

Rev. A | Page 19 of 28

AD7653

DIGITAL INTERFACE

The AD7653 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or a parallel inter­face. The serial interface is multiplexed on the parallel data bus.
The AD7653 digital interface also accommodates both 3 V and
5 V logic by simply connecting the OVDD supply pin of the
AD7653 to the host system interface digital supply. Finally, by
using the OB/

binary coding can be used.

The two signals,

have a similar effect because they are OR’d together internally.
When at least one of these signals is HIGH, the interface
outputs are in high impedance. Usually

of each AD7653 in multicircuit applications and is held LOW in
a single AD7653 design.

conversion result on the data bus.

PARALLEL INTERFACE

The AD7653 is configured to use the parallel interface when
SER/

PA R
conversion, which is during the next acquisition phase, or
during the following conversion, as shown in F and
Figure 30
conversion, however, it is recommended that it is read only
during the first half of the conversion phase. This avoids any
potential feedthrough between voltage transients on the digital
interface and the most critical analog conversion circuitry.

The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in , the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].

input pin, both twos complement and straight

2C

and RD, control the interface. CS and RD

CS

allows the selection

CS

is generally used to enable the

RD

is held LOW. The data can be read either after each

igure 29

, respectively. When the data is read during the

Figure 31

CS

RD

BUSY

DATA

BUS

CS = 0

CNVST,

BUSY

DATA

BUS

RD

CURRENT

CONVERSION

t

12

t

13

Figure 29. Slave Parallel Data Timing for Reading

(Read after Convert Mode)

t

1

t

4

t

3

PREVIOUS

CONVERSION

t

12

t

13

Figure 30. Slave Parallel Data Timing for Reading

(Read during Convert Mode)

CS

RD

02966-0-013

02966-0-014

SERIAL INTERFACE

The AD7653 is configured to use the serial interface when
SER/

MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edges of the data clock.

is held HIGH. The AD7653 outputs 16 bits of data,

PA R

Rev. A | Page 20 of 28

BYTESWAP

PINS D[15:8]

PINS D[7:0]

HI-Z

HI-Z

HIGH BYTE LOW BYTE

t

12

LOW BYTE HIGH BYTE

Figure 31. 8-Bit Parallel Interface

HI-Z

t

12

t

13

HI-Z

02966-A-025

AD7653

MASTER SERIAL INTERFACE

Internal Clock

The AD7653 is configured to generate and provide the serial
data clock SCLK when the EXT/

AD7653 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted, if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. F and show
the detailed timing diagrams of these two modes.

CS, RD

t

CNVST

pin is held LOW. The

INT

igure 32

3

Figure 33

EXT/INT = 0

RDC/SDIN = 0 INVSCLK = INVSYNC = 0

Usually, because the AD7653 is used with a fast throughput, the
Master Read During Conversion mode is the most
recommended serial mode. In this mode, the serial clock and
data toggle at appropriate instants, minimizing potential
feedthrough between digital activity and critical conversion
decisions.

In Read After Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.

BUSY

SYNC

SCLK

SDOUT

t

29

t

14

t

15

X

t

16

t

22

t

18

t

19

t

20

123 141516

D15 D14 D2 D1 D0

t

28

t

21

t

23

Figure 32. Master Serial Data Timing for Reading (Read after Convert)

EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0

CS, RD

t

1

CNVST

t

3

BUSY

t

17

SYNC

SCLK

SDOUT

t

14

t

15

t

18

t

16

t

22

t

19

t20t

21

12 3 141516

D15 D14 D2 D1 D0X

t

23

Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)

t

30

t

25

t

24

t

26

t

27

02966-0-015

t

25

t

24

t

26

t

27

02966-0-016

Rev. A | Page 21 of 28

AD7653

S

SLAVE SERIAL INTERFACE

External Clock

The AD7653 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/

HIGH. In this mode, several methods can be used to read the
data. The external serial clock is gated by

. When CS and RD

CS
are both LOW, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally HIGH or normally LOW when
inactive. F and F show the detailed timing

igure 34

igure 35

diagrams of these methods.

RD

BUSY

t

t36t

SCLK

SDOUT

t

31

t

16

1 2 3 14151617 18

X

pin is held

INT

EXT/INT = 1

35

37

t

32

D15 D14 D1

t

34

D13

While the AD7653 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins,
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7653 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is recom­mended that when an external clock is being provided, it is a
discontinuous clock that is toggling only when BUSY is LOW,
or, more importantly, that it does not transition during the latter
half of BUSY HIGH.

INVSCLK = 0

RD = 0

D0

X15 X14

SDIN

CS

CNVST

BUSY

SCLK

DOUT

X15 X14 X13 X1 X0 Y15 Y14

t

33

Figure 34. Slave Serial Data Timing for Reading (Read after Convert)

D1

RD = 0

D0

EXT/INT = 1 INVSCLK = 0

t

3

t

16

t

35

t36t

37

123 141516

t

31

X

D15 D14 D13

t

32

Figure 35. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)

02966-0-017

02966-0-018

Rev. A | Page 22 of 28

AD7653

External Discontinuous Clock Data Read After
Conversion

Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
Figure 34

shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
LOW, the conversion’s result can be read while both

and RD

CS
are LOW. Data is shifted out MSB first with 16 clock pulses and
is valid on the rising and falling edges of the clock.

Among the advantages of this method is the fact that conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 40 MHz, which accommodates both the slow digital host
interface and the fastest serial reading.

Finally, in this mode only, the AD7653 provides a daisy-chain
feature using the RDC/SDIN pin for cascading multiple
converters together. This feature is useful for reducing compo­nent count and wiring connections when desired, as, for
instance, in isolated multiconverter applications.

External Clock Data Read During Conversion

Figure 35 shows the detailed timing diagrams of this method.
During a conversion, while both

and RD are both LOW, the

CS
result of the previous conversion can be read. The data is shifted
out MSB first with 16 clock pulses, and is valid on both the
rising and falling edges of the clock. The 16 bits must be read
before the current conversion is complete; otherwise,
RDERROR is pulsed HIGH and can be used to interrupt the
host interface to prevent incomplete data reading. There is no
daisy-chain feature in this mode, and the RDC/SDIN input
should always be tied either HIGH or LOW.

To reduce performance degradation due to digital activity, a fast
discontinuous clock (at least 18 MHz when Impulse mode is
used, 25 MHz when Normal mode is used, or 40 MHz when
Warp mode is used) is recommended to ensure that all the bits
are read during the first half of the conversion phase. It is also
possible to begin to read data after conversion and continue to
read the last bits after a new conversion has been initiated. This
allows the use of a slower clock speed like 14 MHz in Impulse
mode, 18 MHz in Normal mode, and 25 MHz in Warp mode.

The concatenation of two devices is shown in .
Simultaneous sampling is possible by using a common

Figure 36

CNVST
signal. It should be noted that the RDC/SDIN input is latched
on the edge of SCLK opposite the one used to shift out the data
on SDOUT. Thus, the MSB of the upstream converter follows
the LSB of the downstream converter on the next SCLK cycle.

BUSY
OUT

BUSYBUSY

AD7653

(UPSTREAM)

RDC/SDIN SDOUT

SCLK IN

CS IN

CNVST IN

Figure 36. Two AD7653s in a Daisy-Chain Configuration

#2

CNVST

CS

SCLK

AD7653

#1

(DOWNSTREAM)

SDOUTRDC/SDIN

CNVST

SCLK

CS

DATA
OUT

02966-0-019

Rev. A | Page 23 of 28

AD7653

MICROPROCESSOR INTERFACING

The AD7653 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7653 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7653 to prevent digital noise from coupling
into the ADC. The following section discusses the use of an
AD7653 with an ADSP-219x SPI equipped DSP.

SPI Interface (ADSP-219x)

Figure 37
the SPI equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7653 acts as a slave device and data
must be read after conversion. This mode also allows the daisy­chain feature. The convert command can be initiated in
response to an internal timer interrupt. The reading process can
be initiated in response to the end-of-conversion signal (BUSY
going LOW) using an interrupt line of the DSP. The serial inter-

shows an interface diagram between the AD7653 and

face (SPI) on the ADSP-219x is configured for master mode—
(MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit
(CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00—by
writing to the SPI control register (SPICLTx). To meet all timing
requirements, the SPI clock should be limited to 17 Mbps, which
allows it to read an ADC result in less than 1 µs. When a higher
sampling rate is desired, use of one of the parallel interface
modes is recommended.

DVD D

AD7653*

SER/PAR

EXT/INT

BUSY

RD

INVSCLK

Figure 37. Interfacing the AD7653 to an SPI Interface

CS

SDOUT

SCLK

CNVST

* ADDITIONAL PINS OMITTED FOR CLARITY

ADSP-219x*

PFx

SPIxSEL (PFx)

MISOx

SCKx

PFx or TFSx

02966-0-021

Rev. A | Page 24 of 28

AD7653

APPLICATION HINTS

BIPOLAR AND WIDER INPUT RANGES

In some applications, it is desirable to use a bipolar or wider
analog input range such as ±10 V, ±5 V, or 0 V to 5 V. Although
the AD7653 has only one unipolar range, simple modifications
of input driver circuitry allow bipolar and wider input ranges to
be used without any performance degradation. shows

Figure 38
a connection diagram that allows this. Component values
required and resulting full-scale ranges are shown in .

Table 8

When desired, accurate gain and offset can be calibrated by
acquiring a ground and voltage reference using an analog

U1

C

REF

Figure 38

C

F

R1

2.7nF

100nF

15Ω

IN

AD7653

INGND

REF

REFGND

02966-0-022

multiplexer (U2) as shown in .

U2

R2

R3 R4

ANALOG

INPUT

Figure 38. Using the AD7653 in 16-Bit Bipolar and/or Wider Input Ranges

Table 8. Component Values and Input Ranges

Input Range R1 (Ω) R2 (kΩ) R3 (kΩ) R4 (kΩ)

±10 V 500 4 2.5 2
±5 V 500 2 2.5 1.67
0 V to –5 V 500 1 None 0

LAYOUT

The AD7653 has very good immunity to noise on the power
supplies. However, care should still be taken with regard to
grounding layout.

The printed circuit board that houses the AD7653 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be separated easily. Digital and
analog ground planes should be joined in only one place,
preferably underneath the AD7653, or as close as possible to the
AD7653. If the AD7653 is in a system where multiple devices
require analog-to-digital ground connections, the connection
should still be made at one point only, a star ground point that
should be established as close as possible to the AD7653.

Running digital lines under the device should be avoided since
these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7653 to avoid noise
coupling. Fast switching signals like

CNVST

or clocks should be

shielded with digital ground to avoid radiating noise to other
sections of the board, and should never run near analog signal
paths. Crossover of digital and analog signals should be avoided.
Traces on different but close layers of the board should run at
right angles to each other to will reduce the effect of crosstalk
through the board.

The power supply lines to the AD7653 should use as large a
trace as possible to provide low impedance paths and to reduce
the effect of glitches on the power supply lines. Good
decoupling is also important to lower the supply’s impedance
presented to the AD7653, and to reduce the magnitude of the
supply spikes. Decoupling ceramic capacitors, typically 100 nF,
should be placed on each power supply pin—AVDD, DVDD,
and OVDD—close to, and ideally right up against these pins
and their corresponding ground pins. Additionally, low ESR
10 µF capacitors should be located near the ADC to further
reduce low frequency ripple.

The DVDD supply of the AD7653 can be a separate supply or
can come from the analog supply AVDD or the digital interface
supply OVDD. When the system digital supply is noisy or when
fast switching digital signals are present, if no separate supply is
available, the user should connect DVDD to AVDD through an
RC filter (see F ), and the system supply to OVDD and

igure 22
the remaining digital circuitry. When DVDD is powered from
the system supply, it is useful to insert a bead to further reduce
high frequency spikes.

The AD7653 has five different ground pins: INGND, REFGND,
AGND, DGND, and OGND. INGND is used to sense the analog
input signal. REFGND senses the reference voltage and, because
it carries pulsed currents, should be a low impedance return to
the reference. AGND is the ground to which most internal ADC
analog signals are referenced; it must be connected with the
least resistance to the analog ground plane. DGND must be tied
to the analog or digital ground plane depending on the config­uration. OGND is connected to the digital system ground.

EVALUATING THE AD7653’S PERFORMANCE

A recommended layout for the AD7653 is outlined in the

EVAL-AD7653 evaluation board for the AD7653. The

evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-CONTROL BRD2.

Rev. A | Page 25 of 28

AD7653

OUTLINE DIMENSIONS

1.45

1.40

1.35

0.15

0.05

PIN 1
INDICATOR

10°

6°
2°

SEATING
PLANE

VIEW A

ROTATED 90°CCW

7.00

BSC SQ

0.75

0.60

0.45

SEATING

PLANE

0.20

0.09

7°

°

3.5
0°

0.08 MAX
COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026BBC

1.60
MAX

VIEW A

1

12

0.50

BSC

48

13

Figure 39. 48-Lead Quad Flatpack (LQFP)(ST-48)

Dimensions shown in millimeters

37

36

0.60 MAX

0.60 MAX

9.00 BSC
SQ

PIN 1

TOP VIEW

(PINS DOWN)

0.30

0.23

0.18

37

36

7.00

BSC SQ

25

24

0.27

0.22

0.17

PIN 1

48

INDICATOR

1

5.25

5.10 SQ

4.95

12

0.25 MIN

PADDLE CONNECTED TO AGND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES

1.00

0.85

0.80

12° MAX

SEATING
PLANE

TOP

VIEW

6.75

BSC SQ

0.50

0.40

0.30

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

0.20 REF

0.05 MAX

0.02 NOM

25

24

COPLANARITY

0.08

BOTTOM

VIEW

5.50
REF

13

Figure 40. 48-Lead Frame Chip Scale Package (LFCSP) (CP-48)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7653AST –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7653ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7653ACP –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48
AD7653ACPRL –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48
EVAL-AD7653CB
EVAL-CONTROL BRD2

1

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

2

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

1

2

Evaluation Board
Controller Board

Rev. A | Page 26 of 28

AD7653

NOTES

Rev. A | Page 27 of 28

AD7653

NOTES

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C02966–0–9/03(A)

Rev. A | Page 28 of 28