Datasheet AD7652 Datasheet (Analog Devices)

16-Bit 500 kSPS PulSAR

TM

FEATURES

Throughput: 500 kSPS
16-bit resolution
Analog input voltage range: 0 V to 2.5 V
No pipeline delay
Parallel and serial 5 V/3 V interface

®/QSPI

TM

/MICROWIRETM/DSP compatible

SPI
Single 5 V supply operation
Power dissipation

65 mW typ, 130 µW @ 1 kSPS without REF

80 mW typ with REF
48-lead LQFP and 48-lead LFCSP packages
Pin-to-pin compatible with PulSAR ADCs

APPLICATIONS

Data acquisition
Instrumentation
Digital signal processing
Spectrum analysis
Medical instruments
Battery-powered systems
Process control

GENERAL DESCRIPTION

The AD7652* is a 16-bit, 500 kSPS, charge redistribution SAR
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high speed 16-bit sampling
ADC, an internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system interface
ports.

The AD7652 is fabricated using Analog Devices’ high perform­ance, 0.6 micron CMOS process, with correspondingly low cost,
and is available in a 48-lead LQFP and a tiny 48-lead LFCSP
with operation specified from –40°C to +85°C.

*

Patent Pending.

Unipolar ADC with Reference

AD7652

FUNCTIONAL BLOCK DIAGRAM

REFBUFIN

AGND

AVDD

INGND

PDREF

PDBUF

RESET

REF

IN

PD

Table 1. PulSAR Selection

Type/kSPS 100–250 500–570

Pseudo­Differential

True Bipolar AD7663 AD7665 AD7671
True

Differential
18-Bit AD7678 AD7679 AD7674
Multichannel/

Simultaneous

PRODUCT HIGHLIGHTS

1. Fast Throughput.

The AD7652 is a 500 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.

2. Internal Reference.

The AD7652 has an internal reference with a typical
temperature drift of 7 ppm/°C.

3. Single-Supply Operation.

The AD7652 operates from a single 5 V supply. Its power
dissipation decreases with throughput.

REF REFGND

AD7652

SWITCHED

CAP DAC

CLOCK

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

CNVST

Figure 1. Functional Block Diagram

AD7651
AD7660/AD7661

AD7650/AD7652
AD7664/AD7666

SERIAL

PORT

PARALLEL

INTERFACE

DGNDDVDD

16

AD7675 AD7676 AD7677

AD7654

AD7655

OVDD

OGND

DATA[15:0]

BUSY

RD

CS

SER/PAR

OB/2C

BYTESWAP

02965-0-001

800–
1000

AD7653
AD7667

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

4. Serial or Parallel Interface.

Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V and 5 V logic.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD7652

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 7

Pin Configuration and Function Descriptions............................. 8

Definitions of Specifications ......................................................... 11

Typical Performance Characteristics ........................................... 12

Circuit Information........................................................................ 15

Converter Operation.................................................................. 15

Typical Connection Diagram.................................................... 17

Power Dissipation versus Throughput .................................... 19

Conversion Control.................................................................... 19

Digital Interface.......................................................................... 20

REVISION HISTORY

Revision 0, Initial Version.

Parallel Interface......................................................................... 20

Serial Interface............................................................................ 20

Master Serial Interface............................................................... 21

Slave Serial Interface.................................................................. 22

Microprocessor Interfacing....................................................... 24

Application Hints............................................................................ 25

Bipolar and Wider Input Ranges.............................................. 25

Layout .......................................................................................... 25

Evaluating the AD7652’s Performance.................................... 25

Outline Dimensions....................................................................... 26

Ordering Guide........................................................................... 26

Rev. 0 | Page 2 of 28

AD7652

SPECIFICATIONS

Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted

Parameter Conditions Min Typ Max Unit

RESOLUTION 16 Bits
ANALOG INPUT

Voltage Range VIN – V

Operating Input Voltage VIN –0.1 +3 V

0 V

INGND

V

REF

V

–0.1 +0.5 V

INGND

Analog Input CMRR fIN = 10 kHz 65 dB

Input Current 500 kSPS Throughput 6.1 µA

Input Impedance1
THROUGHPUT SPEED

Complete Cycle 2 µs

Throughput Rate 0 500 kSPS
DC ACCURACY

Integral Linearity Error –6 +6 LSB2

No Missing Codes 15 Bits

Differential Linearity Error –2 +3 LSB

Transition Noise 0.7 LSB

Unipolar Zero Error, T

MIN

to T

3

±5 LSB

MAX

Unipolar Zero Error Temperature Drift3 ±0.24 ppm/°C

Full-Scale Error, T

MIN

to T

3

REF = 2.5 V ±0.12 % of FSR

MAX

Full-Scale Error Temperature Drift ±0.5 ppm/°C

Power Supply Sensitivity AVDD = 5 V ± 5% ±2 LSB
AC ACCURACY

Signal-to-Noise fIN = 100 kHz 86 dB4

Spurious Free Dynamic Range fIN = 100 kHz 98 dB

Total Harmonic Distortion fIN = 45 kHz –98 dB
f

= 100 kHz –96 dB

IN

Signal-to-(Noise + Distortion) fIN = 100 kHz 86 dB
–60 dB Input, fIN = 100 kHz 30 dB

–3 dB Input Bandwidth 12 MHz
SAMPLING DYNAMICS

Aperture Delay 2 ns

Aperture Jitter 5 ps rms

Transient Response Full-Scale Step 750 ns
REFERENCE

Internal Reference Voltage V

@ 25°C 2.48 2.5 2.52 V

REF

Internal Reference Temperature Drift –40°C to +85°C ±7 ppm/°C

Line Regulation

Turn-On Settling Time C

AVDD = 5 V ± 5%

= 10 µF 5 ms

REF

±24 ppm/V

Temperature Pin

Voltage Output @ 25°C 300 mV
Temperature Sensitivity 1 mV/°C

Output Resistance 4.3 kΩ
External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 500 kSPS Throughput 110 µA

Rev. 0 | Page 3 of 28

AD7652

Parameter Conditions Min Typ Max Unit

DIGITAL INPUTS

Logic Levels

VIL –0.3 +0.8 V
VIH 2.0 DVDD + 0.3 V
IIL –1 +1 µA
IIH –1 +1 µA

DIGITAL OUTPUTS

Data Format5
Pipeline Delay6

VOL I
VOH I

POWER SUPPLIES

Specified Performance

AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.257 V

Operating Current 500 kSPS Throughput

AVDD8 With Reference and Buffer 12.2 mA
AVDD9 Reference and Buffer Alone 3 mA
DVDD10 3.8 mA

10

OVDD

102 µA

Power Dissipation without REF10 500 kSPS Throughput 65 75 mW

1 kSPS Throughput 130 µW

Power Dissipation with REF10 500 kSPS Throughput 80 90 mW

TEMPERATURE RANGE11

Specified Performance T

1

See section. Analog Input

2

LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV.

3

See section. These specifications do not include the error contribution from the external reference. Definitions of Specifications

4

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

5

Parallel or Serial 16-Bit.

6

Conversion results are available immediately after completed conversion.

7

The max should be the minimum of 5.25 V and DVDD + 0.3 V.

8

With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH.

9

With PDREF, PDBUF LOW and PD HIGH.

10

Tested in Parallel Reading Mode

11

Consult factory for extended temperature range.

= 1.6 mA 0.4 V

SINK

= –500 µA OVDD – 0.6 V

SOURCE

to T

MIN

–40 +85 °C

MAX

Rev. 0 | Page 4 of 28

TIMING SPECIFICATIONS

Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted

Parameter

Refer to Figure 26 and Figure 27

Convert Pulsewidth
Time between Conversions
CNVST

LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except Master Serial Read after Convert
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth

Refer to Figure 28, Figure 29, and (Parallel Interface Modes)

CNVST

LOW to DATA Valid Delay

Figure 30

DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time

Refer to Figure 32 and Figure 33 (Master Serial Interface Modes)1

CS

LOW to SYNC Valid Delay

CS

LOW to Internal SCLK Valid Delay1

CS

LOW to SDOUT Delay

CNVST

LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period2
Internal SCLK HIGH2
Internal SCLK LOW2
SDOUT Valid Setup Time2
SDOUT Valid Hold Time2
SCLK Last Edge to SYNC Delay2
CS

HIGH to SYNC HI-Z

CS

HIGH to Internal SCLK HI-Z

CS

HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert2
CNVST

LOW to SYNC Asserted Delay

SYNC Deasserted to BUSY LOW Delay

Refer to and (Slave Serial Interface Modes)1

Figure 34 Figure 35
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW

1

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

2

In Serial Master Read during Convert Mode. See Table 4 for serial master read after convert mode.

Symbol

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

14

t

15

t

16

t

17

t

18

t

19

t

20

t

21

t

22

t

23

t

24

t

25

t

26

t

27

t

28

t

29

t

30

t

31

t

32

t

33

t

34

t

35

t

36

t

37

Min Typ Max Unit

10 ns
2 µs
35 ns

1.25 µs
2 ns
10 ns

1.25 µs
750 ns
10 ns

1.25 µs
12 ns
45 ns
5 15 ns

10 ns
10 ns
10 ns
525 ns
3 ns
25 40 ns
12 ns
7 ns
4 ns
2 ns
3 ns
10 ns
10 ns
10 ns
See Table 4

1.25 µs
25 ns

5 ns
3 18 ns
5 ns
5 ns
25 ns
10 ns
10 ns

AD7652

Rev. 0 | Page 5 of 28

AD7652

Table 4. Serial Clock Timings in Master Read after Convert

DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns
Internal SCLK Period Minimum t19 25 50 100 200 ns
Internal SCLK Period Maximum t19 40 70 140 280 ns
Internal SCLK HIGH Minimum t20 12 22 50 100 ns
Internal SCLK LOW Minimum t21 7 21 49 99 ns
SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns
SDOUT Valid Hold Time Minimum t23 2 4 30 80 ns
SCLK Last Edge to SYNC Delay Minimum t24 3 55 130 290 ns
BUSY HIGH Width Maximum t24 2 2.5 3.5 5.75 µs

Rev. 0 | Page 6 of 28

ABSOLUTE MAXIMUM RATINGS

Table 5. AD7652 Stress Ratings1

IN2, TEMP2, REF, REFBUFIN,

INGND, REFGND to AGND

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD –0.3 V to +7 V

Digital Inputs –0.3 V to DVDD + 0.3 V
PDREF, PDBUF

3

Internal Power Dissipation4 700 mW
Internal Power Dissipation5 2.5 W
Junction Temperature 150°C
Storage Temperature Range –65°C to +150°C
Lead Temperature Range

(Soldering 10 sec)

1

Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

2

See Analog Input section.

3

See Voltage Reference Input Section.

4

Specification is for the device in free air:

48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W

5

Specification is for the device in free air:

48-Lead LFCSP; θJA = 26°C/W.

AVDD + 0.3 V to
AGND – 0.3 V

±20 mA

300°C

1.6mA

TO OUTPUT

PIN

C

L

60pF*

500µA

* IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND

SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD

OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.

C

L

I

OL

1.4V

I

OH

02964-0-006

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, SCLK Outputs C

0.8V

t

DELAY

2V

0.8V

L

2V

= 10 pF

t

DELAY

2V

0.8V

02965-0-007

Figure 3. Voltage Reference Levels for Timing

AD7652

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 7 of 28

AD7652

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PDBUF

PDREF

REFBUFIN

TEMP

AVDDINAGND

AGNDNCINGND

REFGND

D8/SDOUT

D9/SCLK

D10/SYNC

REF

D11/RDERROR

36

35

34

33

32

31

30

29

28

27

26

25

02965-0-002

AGND

CNVST

PD

RESET
CS

RD

DGND

BUSY

D15

D14

D13

D12

is HIGH, these outputs are in high

tied LOW, the internal clock is selected

48

47 46 45 44 39 38 3743 42 41 40

1

AGND

AVDD

NC

BYTESWAP

OB/2C

NC

NC

SER/PAR

D0

D1
D2/DIVSCLK0

D3/DIVSCLK1

NC = NO CONNECT

PIN 1
IDENTIFIER

2

3

4

5

6

7

8

9

10

11

12

13 14

D4/EXT/INT

AD7652

TOP VIEW

(Not to Scale)

15 16 17 18 19 20 21 22 23 24

DVDD

OVDD

DGND

OGND

D6/INVSCLK

D5/INVSYNC

D7/RDC/SDIN

Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1, 36,

AGND P Analog Power Ground Pin.

41, 42
2, 44 AVDD P Input Analog Power Pin. Nominally 5 V.
3, 6,

NC No Connect.

7, 40
4 BYTESWAP DI Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on

D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].

5

OB/2C

DI

Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary;
when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register.

8

SER/PAR

DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface

mode is selected and some bits of the DATA bus are used as a serial port.

9, 10 D[0:1] DO

Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR
impedance.

11, 12 D[2:3]or

DIVSCLK[0:1]

DI/O

When SER/PAR
When SER/PAR

is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.

is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these
inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the
data output. In other serial modes, these pins are not used.

13 D4 or

INT

EXT/

DI/O

When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus.
When SER/PAR

is HIGH, this input, part of the serial port, is used as a digital select input for choosing
the internal data clock or an external data clock. With EXT/INT
on the SCLK output. With EXT/INT

set to a logic HIGH, output data is synchronized to an external clock

signal connected to the SCLK input.

14 D5 or

INVSYNC

DI/O

When SER/PAR
When SER/PAR

is LOW, this output is used as Bit 5 of the parallel port data output bus.

is HIGH, this input, part of the serial port, is used to select the active state of the SYNC
signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH, SYNC
is active LOW.

15 D6 or

INVSCLK

DI/O

When SER/PAR
When SER/PAR

is LOW, this output is used as Bit 6 of the parallel port data output bus.

is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in
both master and slave modes.

Rev. 0 | Page 8 of 28

Pin No. Mnemonic Type1 Description

16 D7 or

RDC/SDIN

17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V).
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.
21 D8 or

SDOUT

22 D9 or

SCLK

23 D10 or

SYNC

24 D11 or

RDERROR

25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the

29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is

30 DGND P Must Be Tied to Digital Ground.
31

32

33 RESET DI Reset Input. When set to a logic HIGH, this pin resets the AD7652 and the current conversion, if any, is

34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are

35

37 REF AI/O Reference Input Voltage. On-chip reference output voltage.
38 REFGND AI Reference Input Analog Ground.
39 INGND AI Analog Input Ground.
43 IN AI Primary Analog Input with a Range of 0 V to 2.5 V.

RD
CS

CNVST

DI/O

DO

DI/O

DO

DO

DI
DI

DI

When SER/PAR
When SER/PAR
read mode selection input depending on the state of EXT/INT

When EXT/INT
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA
with a delay of 16 SCLK periods after the initiation of the read sequence.

When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is
output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only
when the conversion is complete.

When SER/PAR
When SER/PAR
to SCLK. Conversion results are stored in an on-chip register. The AD7652 provides the conversion

result, MSB first, from its internal shift register. The DATA format is determined by the logic level of
OB/2C

. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode
when EXT/INT
next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next

rising edge.
When SER/PAR
When SER/PAR

depending upon the logic state of the EXT/INT
depends upon the logic state of the INVSCLK pin.

When SER/PAR
When SER/PAR

synchronization for use with the internal data clock (EXT/INT
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is
valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW
while the SDOUT output is valid.

When SER/PAR
SER/PAR
flag. In slave mode, when a data read is started and not complete when the following conversion is

complete, the current data is lost and RDERROR is pulsed HIGH.

state of SER/PAR.

complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.

Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is

also used to gate the external clock.

aborted. If not used, this pin could be tied to DGND.

inhibited after the current one is completed.
Start Conversion. If CNVST is HIGH when the acquisition phase (t8) is complete, the next falling edge

on CNVST
most appropriate if low sampling jitter is desired. If CNVST
complete, the internal sample/hold is put into the hold state and a conversion is immediately started.

is LOW, this output is used as Bit 7 of the parallel port data output bus.
is HIGH, this input, part of the serial port, is used as either an external data input or a

.

is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results

is LOW, this output is used as Bit 8 of the parallel port data output bus.
is HIGH, this output, part of the serial port, is used as a serial data output synchronized

is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the

is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus.
is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,

pin. The active edge where the data SDOUT is updated

is LOW, this output is used as Bit 10 of the parallel port data output bus.
is HIGH, this output, part of the serial port, is used as a digital output frame

= logic LOW). When a read sequence is

is LOW, this output is used as Bit 11 of the parallel port data output bus. When

and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read error

puts the internal sample/hold into the hold state and initiates a conversion. The mode is

is LOW when the acquisition phase (t8) is

AD7652

Rev. 0 | Page 9 of 28

AD7652

Pin No. Mnemonic Type1 Description

45 TEMP AO Temperature Sensor Voltage Output.
46 REFBUFIN AI/O Reference Input Voltage. The reference output and the reference buffer input.
47 PDREF DI This pin allows the choice of internal or external voltage references. When LOW, the on-chip reference

is turned on. When HIGH, the internal reference is switched off and an external reference must be
used.

48 PDBUF DI This pin allows the choice of buffering an internal or external reference with the internal buffer. When

LOW, the buffer is selected. When HIGH, the buffer is switched off.

1

AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.

Rev. 0 | Page 10 of 28

DEFINITIONS OF SPECIFICATIONS

Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.

Full-Scale Error

The last transition (from 011…10 to 011…11 in twos
complement coding) should occur for an analog voltage 1½ LSB
below the nominal full scale (2.49994278 V for the 0 V to 2.5 V
range). The full-scale error is the deviation of the actual level of
the last transition from the ideal level.

Unipolar Zero Error

The first transition should occur at a level ½ LSB above analog
ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero
error is the deviation of the actual transition from that point.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula:

ENOB = (S/[N+D]dB – 1.76)/6.02

and is expressed in bits.

AD7652

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (S/[N+D])

S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.

Aperture Delay

Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the

the input signal is held for a conversion.

CNVST

Transient Response

Transient response is the time required for the AD7652 to
achieve its rated accuracy after a full-scale step function is
applied to its input.

Overvoltage Recovery

Overvoltage recovery is the time required for the ADC to
recover to full accuracy after an analog input signal 150% of the
full-scale value is reduced to 50% of the full-scale value.

Reference Voltage Temperature Coefficient

Reference voltage temperature coefficient is the change of
internal reference voltage output voltage V over the operating
temperature range and normalized by the output voltage at
25°C, expressed in ppm/°C. The equation follows:

input to when

)(–)(

TVTV

)/( ×

=°

CppmTCV

where:
V(25°C) = V at +25°C

) = V at Temperature 2 (+85°C)

V(T

2

) = V at Temperature 1 (–40°C)

V(T

1

Rev. 0 | Page 11 of 28

12

×°

6

10

12

)–()25(

TTCV

AD7652

TYPICAL PERFORMANCE CHARACTERISTICS

4

2.0

3

2

1

0

INL (LSB)

–1

–2

–3

–4

0

16384 32768 65536

CODE

Figure 5. Integral Nonlinearity vs. Code

140000

120000

100000

80000

60000

COUNTS

40000

20000

00 00

0

7FFB

477

111974

25889

CODE IN HEX

112112

8000 8001 80038002

Figure 6. Histogram of 261,120 Conversions of a

DC Input at the Code Transition

0

–20

–40

–60

–80

–100

–120

–140

AMPLITUDE (dB of Full Scale)

–160

–180

0

50

100 150 250200

FREQUENCY (kHz)

Figure 7. FFT Plot

49152

10598

f
f

SNR = 83.4dB
THD = 90.9dB
SFDR = 91.2dB
S/[N+D] = 82.8dB

70

= 500kSPS

S

= 102kHz

IN

02965-0-023

80047FFC 7FFD 7FFE 7FFF

02965-0-027

02965-0-029

1.5

1.0

0.5

DNL (LSB)

0

–0.5

–1.0

0

16384 32768 65536

CODE

49152

02966-0-026

Figure 8. Differential Nonlinearity vs. Code

160000

140000

120000

100000

80000

COUNTS

60000

40000

20000

0

0

110

8659

144958

64967

8000 8001 80038002

CODE IN HEX

41624

801

10

80047FFC 7FFD 7FFE 7FFF

02965-0-028

Figure 9. Histogram of 261,120 Conversions of a

DC Input at the Code Center

SNR

02965-0-030

1000

14.5

14.0

13.5

ENOB (Bits)

13.0

12.5

88

85

82

S/[N+D]

SNR, S/[N+D] (dB)

79

76

1

10

FREQUENCY (kHz)

ENOB

100

Figure 10. SNR, S/(N+D), and ENOB vs. Frequency

Rev. 0 | Page 12 of 28

AD7652

–50

140

–100

–100

THD, HARMONICS (dB)

–110

–120

–60

–70

–80

–90

1

SFDR

THD

SECOND
HARMONIC

10

FREQUENCY (kHz)

100

THIRD
HARMONIC

02966-0-031

1000

Figure 11. THD, Harmonics, and SFDR vs. Frequency

87

86

85

84

83

SNR, S/[N+D] REFERRED TO FULL SCALE (dB)

82

–60

INPUT LEVEL (dB)

SNR

S/[N+D]

02965-0-032

Figure 12. SNR and S/(N+D) vs. Input Level (Referred to Full Scale)

89

88

87

SNR, S/[N+D] (dB)

86

85

–55

585

TEMPERATURE (°C)

SNR

S[N+D]

ENOB

105

02965-0-033

125–35 –15 25 45 65

Figure 13. SNR, S/(N+D), and ENOB vs. Temperature

0–50 –40 –30 –20 –10

120

100

80

60

40

20

0

14.50

14.38

14.25

14.13

14.00

SFDR (dB)

ENOB (Bits)

–55

THD

SECOND
HARMONIC

THIRD
HARMONIC

585

TEMPERATURE (°C)

–105

–110

THD, HARMONICS (dB)

–115

–120

Figure 14. THD and Harmonics vs. Temperature

10000

1000

100

10

1

0.1

OPERATING CURRENT (µA)

0.01

0.001
10

1000

SAMPLE RATE (SPS)

AVDD

DVDD

PDREF = PDBUF = HIGH

Figure 15. Operating Current vs. Sample Rate

6

5

4

3

2

1

0

–1

–2

–3

–4

ZERO ERROR, FULL SCALE (LSB)

–5

–6

–55

–15

TEMPERATURE (°C)

FULL SCALE

ZERO ERROR

85

Figure 16. Zero Error, Full Scale with Reference vs. Temperature

105

02965-0-034

OVDD

02965-0-036

105

02965-0-040

125–35 –15 25 45 65

1000000100 10000 100000

125–35 5 25 45 65

Rev. 0 | Page 13 of 28

AD7652

2.5000

2.4995

2.4990

2.4985

VREF (V)

2.4980

50

OVDD= 2.7V @ 85°C

40

30

DELAY (ns)

20

12

t

OVDD= 2.7V @ 25°C

OVDD= 5V @ 85°C

OVDD= 5V @ 25°C

2.4975

2.4970
–40

0204060–20 80 120

TEMPERATURE (°C)

100

02965-0-039

Figure 17. Typical Reference Output Voltage vs. Temperature

20

18

16

12

10

8

NUMBER OF UNITS

6

4

2

0

–30

–26 –22 –18 –1414–10 –6 –2 2 3026221814106

REFERENCE DRIFT (ppm/°C)

02965-0-040

Figure 18. Reference Voltage Temperature Coefficient Distribution (100 Units)

10

0

0

CL (pF)

Figure 19. Typical Delay vs. Load Capacitance C

02966-0-035

L

20050 100 150

Rev. 0 | Page 14 of 28

CIRCUIT INFORMATION

IN

REF

REFGND

32,768C

INGND

MSB

16,384C 4C 2C C C

65,536C

Figure 20. ADC Simplified Schematic

LSB

SW

SW

A

COMP

B

SWITCHES

CONTROL

CONTROL

LOGIC

CNVST

BUSY

OUTPUT

CODE

02964-0-005

AD7652

The AD7652 is a very fast, low power, single supply, precise
16-bit analog-to-digital converter (ADC).

The AD7652 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.

The AD7652 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in
either a 48-lead LQFP or a 48-lead LFCSP that saves space and
allows flexible configurations as either a serial or parallel inter­face. The AD7652 is pin-to-pin compatible with PulSAR ADCs.

CONVERTER OPERATION

The AD7652 is a successive-approximation ADC based on a
charge redistribution DAC. F shows a simplified sche­matic of the ADC. The capacitive DAC consists of an array of 16
binary weighted capacitors and an additional LSB capacitor. The
comparator’s negative input is connected to a dummy capacitor
of the same value as the capacitive DAC array.

igure 20

During the acquisition phase, the common terminal of the array
tied to the comparator's positive input is connected to AGND
via SW

. All independent switches are connected to the analog

A

input IN. Thus, the capacitor array is used as a sampling
capacitor and acquires the analog signal on IN. Similarly, the
dummy capacitor acquires the analog signal on INGND.

When
the conversion phase begins, SW

goes LOW, a conversion phase is initiated. When

CNVST

and SWB are opened. The

A

capacitor array and dummy capacitor are then disconnected
from the inputs and connected to REFGND. Therefore, the
differential voltage between IN and INGND captured at the end
of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between REFGND and REF,
the comparator input varies by binary weighted voltage steps

/2, V

(V

REF

REF

/4, …V

/65536). The control logic toggles these

REF

switches, starting with the MSB, to bring the comparator back
into a balanced condition.

After this process is completed, the control logic generates the
ADC output code and brings the BUSY output LOW.

Rev. 0 | Page 15 of 28

AD7652

A

T

Transfer Functions

Using the OB/2C digital input, the AD7652 offers two output
codings: straight binary and twos complement. The LSB size is

/65536, which is about 38.15 µV. The AD7652’s ideal

V

REF

transfer characteristic is shown in and . Figure 21

111...111

111...110

111...101

ADC CODE (Straight Binary)

000...010

000...001

000...000

1 LSB = V

1LSB0V

0.5 LSB

Figure 21. ADC Ideal Transfer Function

/65536

REF

ANALOG INPUT

V

REF

Table 7

V

REF

– 1.5 LSB

– 1 LSB

02964-0-003

Table 7. Output Codes and Ideal Input Voltages

Digital Output Code (Hex)

Description

Analog
Input

Straight
Binary

Twos
Complement

FSR –1 LSB 2.499962 V FFFF1 7FFF1
FSR – 2 LSB 2.499923 V FFFE 7FFE
Midscale + 1 LSB 1.250038 V 8001 0001
Midscale 1.25 V 8000 0000
Midscale – 1 LSB 1.249962 V 7FFF FFFF
–FSR + 1 LSB 38 µV 0001 8001
–FSR 0 V 00002 80002

1

This is also the code for overrange analog input (VIN – V

V

– V

REFGND

).

REF

2

This is also the code for underrange analog input (VIN below V

INGND

above

INGND

).

ANALOG

SUPPLY

NALOG INPU

(0VTO 2.5V)

(5V)

+

4

C

R

15Ω

2

U1

C

C

NOTES

1

THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER.

2

THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.

3

OPTIONAL LOW JITTER.

4

A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M).

SEE VOLTAGE REFERENCE INPUT SECTION.

10µF

100nF

100nF

2.7nF

PDREF

20

Ω

+

AVDD DGND DVDD OVDD OGND

REF

REFBUFIN

REFGND

IN

INGND

GND

1

PDBUF

PD RESET

10µF

100nF

AD7652

CS

BYTESWAP

RD

SCLK

SDOUT

BUSY

CNVST

OB/2C

SER/PAR

Figure 22. Typical Connection Diagram

100nF

+

10

3

D

DVDD

DIGITAL SUPPLY
(3.3V OR 5V)

µ

F

SERIAL

PORT

CLOCK

µC/µP/DSP

02965-0-004

Rev. 0 | Page 16 of 28

O

TYPICAL CONNECTION DIAGRAM

Figure 22 shows a typical connection diagram for the AD7652.

Analog Input

Figure 23
the AD7652.

The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN and INGND. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 0.3 V. This will cause these diodes to become
forward-biased and start conducting current. These diodes can
handle a forward-biased current of 100 mA maximum. For
instance, these conditions could eventually occur when the
input buffer’s (U1) supplies are different from AVDD. In such a
case, an input buffer with a short-circuit current limitation can
be used to protect the part.

This analog input structure allows the sampling of the
differential signal between IN and INGND. Unlike other
converters, INGND is sampled at the same time as IN. By using
this differential input, small signals common to both inputs are
rejected. For instance, by using INGND to sense a remote signal
ground, ground potential differences between the sensor and
the local ADC ground are eliminated.

During the acquisition phase, the impedance of the analog input
IN can be modeled as a parallel combination of capacitor C1
and the network formed by the series connection of R1 and C2.
C1 is primarily the pin capacitance. R1 is typically 168 Ω and is
a lumped component made up of some serial resistors and the
on resistance of the switches. C2 is typically 60 pF and is mainly
the ADC sampling capacitor. During the conversion phase,
when the switches are opened, the input impedance is limited to
C1. R1 and C2 make a 1-pole low-pass filter that reduces
undesirable aliasing effect and limits the noise.

shows an equivalent circuit of the input structure of

AV D D

R INGND

AGND

IN

Figure 23. Equivalent Analog Input Circuit

D1

C1

D2

R1

C2

02965-0-008

AD7652

Driver Amplifier Choice

Although the AD7652 is easy to drive, the driver amplifier needs
to meet the following requirements:

• The driver amplifier and the AD7652 analog input circuit

must be able to settle for a full-scale step of the capacitor
array at a 16-bit level (0.0015%). In the amplifier’s data
sheet, settling at 0.1% to 0.01% is more commonly speci­fied. This could differ significantly from the settling time at
a 16-bit level and should be verified prior to driver
selection. The tiny op amp AD8021, which combines
ultralow noise and high gain-bandwidth, meets this settling
time requirement even when used with gains up to 13.

• The noise generated by the driver amplifier needs to be

kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7652. The noise
coming from the driver is filtered by the AD7652 analog
input circuit 1-pole low-pass filter made by R1 and C2 or
by the external filter, if one is used.

• The driver needs to have a THD performance suitable to

that of the AD7652.

The AD8021 meets these requirements and is appropriate for
almost all applications. The AD8021 needs a 10 pF external
compensation capacitor that should have good linearity as an
NPO ceramic or mica type.

The AD8022 could also be used if a dual version is needed and
gain of +1 is present. The AD829 is an alternative in
applications where high frequency (above 100 kHz)
performance is not required. In gain of 1 applications, it requires
an 82 pF compensation capacitor. The AD8610 is an option
when low bias current is needed in low frequency applications.

When the source impedance of the driving circuit is low, the
AD7652 can be driven directly. Large source impedances will
significantly affect the ac performance, especially total
harmonic distortion.

Rev. 0 | Page 17 of 28

AD7652

A

T

Voltage Reference Input

The AD7652 allows the choice of either a very low temperature
drift internal voltage reference or an external 2.5 V reference.

Unlike many ADCs with internal references, the internal
reference of the AD7652 provides excellent performance and
can be used in almost all applications.

To use the internal reference along with the internal buffer,
PDREF and PDBUF should both be LOW. This will produce a

1.207 V voltage on REFBUFIN which, amplified by the buffer,
will result in a 2.5 V reference on the REF pin.

The output impedance of REFBUFIN is 11 k

the internal reference is enabled.

It is useful to decouple
REFBUFIN with a 100 nF ceramic capacitor. Thus, the 100 nF
capacitor provides an RC filter for noise reduction.

To use an external reference along with the internal buffer,
PDREF should be HIGH and PDBUF should be LOW. This
powers down the internal reference and allows the 2.5 V
reference to be applied to REFBUFIN.

To use an external reference directly on REF pin, PDREF and
PDBUF should both be HIGH.

PDREF and PDBUF respectively power down the internal
reference and the internal reference buffer. Note that the PDREF
and PDBUF input current should never exceed 20 mA. This
could eventually occur when input voltage is above AVDD (for
instance at power up). In this case, a 100 Ω series resistor is
recommended.

The internal reference is temperature compensated to 2.5 V ±
20 mV. The reference is trimmed to provide a typical drift of 7

. This typical drift characteristic is shown in .

ppm/°C Figure 17
For improved drift performance, an external reference such as
the AD780 can be used.

The AD7652 voltage reference input REF has a dynamic input
impedance; it should therefore be driven by a low impedance
source with efficient decoupling between the REF and REFGND
inputs. This decoupling depends on the choice of the voltage
reference but usually consists of a low ESR capacitor connected
to REF and REFGND with minimum parasitic inductance. A
10 µF (X5R, 1206 size) ceramic chip capacitor (or 47 µF tanta­lum capacitor) is appropriate when using either the internal
reference or one of these recommended reference voltages:

Ω (minimum) when

For applications that use multiple AD7652s, it is more effective
to use the internal buffer to buffer the reference voltage.

Care should be taken with the voltage reference’s temperature
coefficient, which directly affects the full-scale accuracy if this
parameter matters. For instance, a ±15 ppm/°C temperature
coefficient of the reference changes full scale by ±1 LSB/°C.

Note that V
input range is defined in terms of V

can be increased to AVDD – 1.85 V. Since the

REF

, this would essentially

REF

increase the range to 0 V to 3 V with an AVDD above 4.85 V.
The AD780 can be selected with a 3 V reference voltage.

The TEMP pin, which measures the temperature of the AD7652,
can be used as shown in . The output of TEMP pin is

Figure 24
applied to one of the inputs of the analog switch (e.g., ADG779),
and the ADC itself is used to measure its own temperature. This
configuration is very useful for improving the calibration
accuracy over the temperature range.

TEMP

AD7652

TEMPERATURE
SENSOR

02965-0-024

NALOG INPU

(UNIPOLAR)

ADG779

IN

AD8021

Figure 24. Temperature Sensor Connection Diagram

C

C

Power Supply

The AD7652 uses three power supply pins: an analog 5 V supply
AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. OVDD allows direct
interface with any logic between 2.7 V and DVDD + 0.3 V. To
reduce the supplies needed, the digital core (DVDD) can be
supplied through a simple RC filter from the analog supply, as
shown in . The AD7652 is independent of power

Figure 22
supply sequencing once OVDD does not exceed DVDD by
more than 0.3 V, and is thus free of supply voltage induced
latch-up.

• The low noise, low temperature drift ADR421 and AD780

• The low power ADR291

• The low cost AD1582

Rev. 0 | Page 18 of 28

POWER DISSIPATION VERSUS THROUGHPUT

Operating currents are very low during the acquisition phase,
allowing significant power savings when the conversion rate is
reduced (see ). The AD7652 automatically reduces its
power consumption at the end of each conversion phase. This
makes the part ideal for very low power battery applications.
The digital interface and the reference remain active even
during the acquisition phase. To reduce operating digital supply
currents even further, digital inputs need to be driven close to
the power supply rails (i.e., DVDD or DGND), and OVDD
should not exceed DVDD by more than 0.3 V.

Figure 25

100000

AD7652

The

CNVST
value serial resistor (i.e., 50
close to the output of the component that drives this line.

For applications where SNR is critical, the
have very low jitter. This may be achieved by using a dedicated

oscillator for
high frequency, low jitter clock, as shown in . Figure 22

CNVST

trace should be shielded with ground and a low

Ω) termination should be added

signal should

CNVST

generation, or to clock

CNVST

t

1

t

2

CNVST

with a

10000

W)

µ

1000

POWER DISSIPATION (

100

10

10

1000

SAMPLE RATE (SPS)

PDREF = PDBUF = HIGH

1000000100 10000 100000

02965-0-037

Figure 25. Power Dissipation vs. Sampling Rate

CONVERSION CONTROL

Figure 26
process. The AD7652 is controlled by the

initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete.

Conversions can be automatically initiated with the AD7652. If
CNVST
the acquisition phase and automatically initiates a new
conversion. By keeping
conversion process running by itself. It should be noted that the
analog input must be settled when BUSY goes LOW. Also, at
power-up,
conversion process. In this mode, the AD7652 can run slightly
faster than the guaranteed 500 kSPS.

Although
special care with fast, clean edges, and levels with minimum

overshoot and undershoot or ringing.

shows the detailed timing diagrams of the conversion

signal, which

CNVST

operates independently of CS and RD.

CNVST

is held LOW when BUSY is LOW, the AD7652 controls

LOW, the AD7652 keeps the

CNVST

CNVST

CNVST

should be brought LOW once to initiate the

is a digital signal, it should be designed with

BUSY

t

3

t

5

MODE

ACQUIRE CONVERT ACQUIRE CONVERT

t

4

t

6

t

7

t

8

Figure 26. Basic Conversion Timing

t

9

RESET

BUSY

DATA

t

8

CNVST

Figure 27. RESET Timing

CS = RD = 0

t

CNVST

BUSY

DATA

BUS

t

3

1

t

10

t

4

t

11

PREVIOUS CONVERSION DATA NEW DATA

Figure 28. Master Parallel Data Timing for Reading (Continuous Read)

02964-0-011

02964-0-011

02964-0-012

Rev. 0 | Page 19 of 28

AD7652

DIGITAL INTERFACE

The AD7652 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or a parallel
interface. The serial interface is multiplexed on the parallel data
bus. The AD7652 digital interface also accommodates both 3 V
and 5 V logic by simply connecting the OVDD supply pin of the
AD7652 to the host system interface digital supply. Finally, by
using the OB/

binary coding can be used.

The two signals,
have a similar effect because they are OR’d together internally.

When at least one of these signals is HIGH, the interface
outputs are in high impedance. Usually CS allows the selection

of each AD7652 in multicircuit applications and is held LOW in
a single AD7652 design.

conversion result on the data bus.

PARALLEL INTERFACE

The AD7652 is configured to use the parallel interface when
SER/

PA R
conversion, which is during the next acquisition phase, or
during the following conversion, as shown in F and
Figure 30
conversion, however, it is recommended that it is read only
during the first half of the conversion phase. This avoids any
potential feedthrough between voltage transients on the digital
interface and the most critical analog conversion circuitry.

The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in , the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].

SERIAL INTERFACE

The AD7652 is configured to use the serial interface when
SER/

PA R
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edges of the data clock.

input pin, both twos complement or straight

2C

and RD, control the interface. CS and RD

CS

is generally used to enable the

RD

is held LOW. The data can be read either after each

igure 29

, respectively. When the data is read during the

Figure 31

is held HIGH. The AD7652 outputs 16 bits of data,

CS

RD

BUSY

DATA

BUS

t

12

CURRENT

CONVERSION

t

13

Figure 29. Slave Parallel Data Timing for Reading (Read after Convert)

CS = 0

CNVST,

BUSY

DATA

BUS

RD

t

t

12

3

t

1

PREVIOUS

CONVERSION

t

4

t

13

Figure 30. Slave Parallel Data Timing for Reading (Read during Convert)

CS

RD

BYTESWAP

PINS D[15:8]

PINS D[7:0]

HI-Z

HI-Z

HIGH BYTE LOW BYTE

t

12

LOW BYTE HIGH BYTE

t

12

Figure 31. 8-Bit Parallel Interface

02964-0-013

02964-0-014

HI-Z

t

13

HI-Z

02965-0-025

Rev. 0 | Page 20 of 28

MASTER SERIAL INTERFACE

Internal Clock

The AD7652 is configured to generate and provide the serial
data clock SCLK when the EXT/

AD7652 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. F and show
the detailed timing diagrams of these two modes.

pin is held LOW. The

INT

igure 32

Figure 33

AD7652

Usually, because the AD7652 is used with a fast throughput,
Master Read During Conversion is the most recommended
serial mode. In this mode mode, the serial clock and data toggle
at appropriate instants, minimizing potential feedthrough
between digital activity and critical conversion decisions.

In Read After Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.

CS, RD

CNVST

BUSY

SYNC

SCLK

SDOUT

EXT/INT = 0

t

3

t

29

t

14

t

20

t

15

X

t

16

t

22

RDC/SDIN = 0 INVSCLK = INVSYNC = 0

t

28

t

30

t

18

t

19

t

21

123 141516

D15 D14 D2 D1 D0

t

23

t

24

t

25

t

26

t

02964-0-015

27

Figure 32. Master Serial Data Timing for Reading (Read after Convert)

EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0

CS, RD

t

1

CNVST

t

3

BUSY

t

17

SYNC

t

14

t

SCLK

SDOUT

t

16

15

t

18

t

22

Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert

t

19

t20t

21

12 3 141516

D15 D14 D2 D1 D0X

t

23

t

24

t

t

t

02964-0-016

25

26

27

Rev. 0 | Page 21 of 28

AD7652

S

SLAVE SERIAL INTERFACE

External Clock

The AD7652 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/

HIGH. In this mode, several methods can be used to read the
data. The external serial clock is gated by

. When CS and RD

CS
are both LOW, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally HIGH or normally LOW when
inactive. F and F show the detailed timing

igure 34

igure 35

diagrams of these methods.

RD

BUSY

t

t36t

SCLK

SDOUT

t

31

t

16

1 2 3 14151617 18

X

pin is held

INT

EXT/INT = 1

35

37

t

32

D15 D14 D1

t

34

D13

While the AD7652 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins or
degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7652 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that is toggling only when BUSY is
LOW, or, more importantly, that it does not transition during the
latter half of BUSY HIGH.

INVSCLK = 0

RD = 0

D0

X15 X14

SDIN

CS

CNVST

BUSY

SCLK

DOUT

X15 X14 X13 X1 X0 Y15 Y14

t

33

Figure 34. Slave Serial Data Timing for Reading (Read after Convert)

D1

RD = 0

D0

EXT/INT = 1 INVSCLK = 0

t

3

t

16

t

35

t36t

37

123 141516

t

31

X

D15 D14 D13

t

32

Figure 35. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)

02964-0-017

02965-0-018

Rev. 0 | Page 22 of 28

External Discontinuous Clock Data Read After
Conversion

Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
Figure 34
After a conversion is complete, indicated by BUSY returning
LOW, the conversion’s result can be read while both

are LOW. Data is shifted out MSB first with 16 clock pulses and
is valid on the rising and falling edges of the clock.

Among the advantages of this method is the fact that conversion
performance is not degraded because there are no voltage tran­sients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 40 MHz, which accommodates both the slow digital host
interface and the fastest serial reading.

Finally, in this mode only, the AD7652 provides a daisy-chain
feature using the RDC/SDIN pin for cascading multiple
converters together. This feature is useful for reducing
component count and wiring connections when desired, as, for
instance, in isolated multiconverter applications.

shows the detailed timing diagrams of this method.

and RD

CS

AD7652

External Clock Data Read During Conversion

Figure 35 shows the detailed timing diagrams of this method.
During a conversion, while both

result of the previous conversion can be read. The data is shifted
out MSB first with 16 clock pulses, and is valid on both the
rising and falling edges of the clock. The 16 bits must be read
before the current conversion is complete; otherwise,
RDERROR is pulsed HIGH and can be used to interrupt the
host interface to prevent incomplete data reading. There is no
daisy-chain feature in this mode and the RDC/SDIN input
should always be tied either HIGH or LOW.

To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 18 MHz is recommended to
ensure that all the bits are read during the first half of the
conversion phase. It is also possible to begin to read data after
conversion and continue to read the last bits after a new
conversion has been initiated. This allows the use of a slower
clock speed like 14 MHz.

and RD are both LOW, the

CS

An example of the concatenation of two devices is shown in
Figure 36
common

. Simultaneous sampling is possible by using a
CNVST

signal. It should be noted that the RDC/SDIN

input is latched on the opposite edge of SCLK of the one used to
shift out the data on SDOUT. Therefore, the MSB of the
“upstream” converter just follows the LSB of the “downstream”
converter on the next SCLK cycle.

BUSY
OUT

BUSYBUSY

AD7652

(UPSTREAM)

RDC/SDIN SDOUT

SCLK IN

CS IN

CNVST IN

Figure 36. Two AD7652s in a Daisy-Chain Configuration

#2

CNVST

CS

SCLK

AD7652

#1

(DOWNSTREAM)

SDOUTRDC/SDIN

CNVST

SCLK

CS

DATA
OUT

02965-0-019

Rev. 0 | Page 23 of 28

AD7652

MICROPROCESSOR INTERFACING

The AD7652 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7652 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7652 to prevent digital noise from coupling
into the ADC. The following section discusses the use of an
AD7652 with an ADSP-219x SPI equipped DSP.

SPI Interface (ADSP-219x)

Figure 37
the SPI equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7652 acts as a slave device and data
must be read after conversion. This mode also allows the daisy­chain feature. The convert command can be initiated in
response to an internal timer interrupt. The reading process can
be initiated in response to the end-of-conversion signal (BUSY
going LOW) using an interrupt line of the DSP. The serial inter­face (SPI) on the ADSP-219x is configured for master mode—

shows an interface diagram between the AD7652 and

(MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit
(CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00—by
writing to the SPI control register (SPICLTx). To meet all timing
requirements, the SPI clock should be limited to 17 Mbps, which
allows it to read an ADC result in less than 1 µs. When a higher
sampling rate is desired, use of one of the parallel interface
modes is recommended.

DVD D

AD7652*

SER/PAR

EXT/INT

BUSY

RD

INVSCLK

Figure 37. Interfacing the AD7652 to an SPI Interface

CS

SDOUT

SCLK

CNVST

* ADDITIONAL PINS OMITTED FOR CLARITY

ADSP-219x*

PFx

SPIxSEL (PFx)

MISOx

SCKx

PFx or TFSx

02965-0-021

Rev. 0 | Page 24 of 28

APPLICATION HINTS

BIPOLAR AND WIDER INPUT RANGES

In some applications, it is desirable to use a bipolar or wider
analog input range such as ±10 V, ±5 V, or 0 V to 5 V. Although
the AD7652 has only one unipolar range, simple modifications
of input driver circuitry allow bipolar and wider input ranges to
be used without any performance degradation. shows
a connection diagram that allows this. Component values
required and resulting full-scale ranges are shown in .

When desired, accurate gain and offset can be calibrated by
acquiring a ground and voltage reference using an analog

U1

C

REF

Figure 38

C

F

R1

100nF

15Ω

2.7nF

multiplexer (U2), as shown in .

U2

R2

R3 R4

ANALOG

INPUT

Figure 38. Using the AD7652 in 16-Bit Bipolar and/or Wider Input Ranges

Table 8. Component Values and Input Ranges

Input Range R1 (Ω) R2 (kΩ) R3 (kΩ) R4 (kΩ)

±10 V 500 4 2.5 2
±5 V 500 2 2.5 1.67
0 V to –5 V 500 1 None 0

LAYOUT

The AD7652 has very good immunity to noise on the power
supplies. However, care should still be taken with regard to
grounding layout.

The printed circuit board that houses the AD7652 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
ground planes that can be separated easily. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7652, or as close as possible to the AD7652.
If the AD7652 is in a system where multiple devices require
analog-to-digital ground connections, the connection should
still be made at one point only, a star ground point that should
be established as close as possible to the AD7652.

Figure 38

Table 8

IN

AD7652

INGND

REF

REFGND

02965-0-022

AD7652

Running digital lines under the device should be avoided since
these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7652 to avoid noise
coupling. Fast switching signals like

shielded with digital ground to avoid radiating noise to other
sections of the board, and should never run near analog signal
paths. Crossover of digital and analog signals should be avoided.
Traces on different but close layers of the board should run at
right angles to each other. This will reduce the effect of crosstalk
through the board.

The power supply lines to the AD7652 should use as large a
trace as possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decoupling is
also important to lower the supply’s impedance presented to the
AD7652 and to reduce the magnitude of the supply spikes.
Decoupling ceramic capacitors, typically 100 nF, should be
placed on each power supply pin—AVDD, DVDD, and
OVDD—close to, and ideally right up against these pins and
their corresponding ground pins. Additionally, low ESR 10 µF
capacitors should be located near the ADC to further reduce
low frequency ripple.

The DVDD supply of the AD7652 can be a separate supply or
can come from the analog supply AVDD or the digital interface
supply OVDD. When the system digital supply is noisy or when
fast switching digital signals are present, if no separate supply is
available, the user should connect DVDD to AVDD through an
RC filter (see F ) and the system supply to OVDD and

igure 22
the remaining digital circuitry. When DVDD is powered from
the system supply, it is useful to insert a bead to further reduce
high frequency spikes.

The AD7652 has five different ground pins: INGND, REFGND,
AGND, DGND, and OGND. INGND is used to sense the analog
input signal. REFGND senses the reference voltage and, because
it carries pulsed currents, should be a low impedance return to
the reference. AGND is the ground to which most internal ADC
analog signals are referenced; it must be connected with the
least resistance to the analog ground plane. DGND must be tied
to the analog or digital ground plane depending on the
configuration. OGND is connected to the digital system
ground.

EVALUATING THE AD7652’S PERFORMANCE

A recommended layout for the AD7652 is outlined in the

EVAL-AD7652 evaluation board for the AD7652. The

evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-CONTROL BRD2.

or clocks should be

CNVST

Rev. 0 | Page 25 of 28

AD7652 Preliminary Technical Data

Q

OUTLINE DIMENSIONS

1.45

1.40

1.35

0.15

0.05

10°

6°
2°

SEATING
PLANE

ROTATED 90°CCW

VIEW A

0.10 MAX
COPLANARITY

0.75

0.60

0.45

SEATING

PLANE

0.20

0.09

7°

3.5°
0°

COMPLIANT TO JEDEC STANDARDS MS-026BBC

1.60
MAX

VIEW A

Figure 39. 48-Lead Quad Flatpack (LQFP) [ST-48]

Dimensions shown in millimeters

BSC SQ

PIN 1
INDICATOR

7.00

0.60 MAX

37

36

0.60 MAX

1

12

0.50
BSC

48

13

9.00 BSC
SQ

PIN 1

TOP VIEW

(PINS DOWN )

0.30

0.23

0.18

37

36

7.00

BSC S

25

24

0.27

0.22

0.17

PIN 1

48

INDICATOR

1

5.25

5.10 SQ

4.95

12

13

PADDLE CONNECTED TO AGND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES

0.25 MIN

1.00

0.85

0.80



12° MAX

SEATING
PLANE

TOP

VIEW

6.75

BSC SQ

0.50

0.40

0.30

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

0.20 REF

0.05 MAX

0.02 NOM

25

24

COPLANARITY

0.08

BOTTOM

VIEW

5.50
REF

Figure 40. 48-Lead Frame Chip Scale Package (LFCSP) [CP-48]

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7652AST –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7652ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7652ACP –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48
AD7652ACPRL –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48
EVAL-AD7652CB
EVAL-CONTROL BRD2

1

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

2

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

1

2

Evaluation Board
Controller Board

Rev. 0 | Page 26 of 28

AD7652

NOTES

Rev. 0 | Page 27 of 28

AD7652

NOTES

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C02965–0–9/03(0)

Rev. 0 | Page 28 of 28