Datasheet AD7643 Datasheet (ANALOG DEVICES)

www.BDTIC.com/ADI

18-Bit, 1.25 MSPS PulSAR® ADC

FEATURES

Throughput: 1.25 MSPS
INL: ±1.5 LSB typical, ±3 LSB maximum (±11 ppm of full scale)
18-bit resolution with no missing codes
Dynamic range: 95 dB typical
SINAD: 93.5 dB typical @ 20 kHz (V
THD: −113 dB typical @ 20 kHz (V

2.048 V internal reference: typical drift 8 ppm/°C; TEMP output
Differential input range: ±V

REF

No pipeline delay (SAR architecture)
Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 2.5 V supply operation
Power dissipation

65 mW typical @ 1.25 MSPS with internal REF

2 μW in power-down mode
Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ
Pin compatible with the AD7641 and other PulSAR ADC’s

APPLICATIONS

Medical instruments
High speed data acquisition/high dynamic data acquisition
Digital signal processing
Spectrum analysis
Instrumentation
Communications
AT E

GENERAL DESCRIPTION

The AD7643 is an 18-bit, 1.25 MSPS, charge redistribution
SAR, fully differential, analog-to-digital converter (ADC) that
operates from a single 2.5 V power supply. The part contains a
high speed, 18-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. The part has no
latency and can be used in asynchronous rate applications. The
AD7643 is hardware factory calibrated and tested to ensure ac
parameters, such as signal-to-noise ratio (SNR), in addition to
the more traditional dc parameters of gain, offset, and linearity.
The AD7643 is only available in Pb-free packages with
operation specified from −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

REF

REF

(V

up to 2.5 V)

REF

= 2.5 V)

= 2.5 V)

AD7643

FUNCTIONAL BLOCK DIAGRAM

TEMP

REFBUFIN

AGND

AVD D

PDREF

PDBUF

RESET

IN+

IN–

PD

REF

CONTROL L OGI C AND

CALIBRATIO N CIRCUITRY

Table 1. PulSAR 48-Lead Selection

Type/kSPS

Pseudo
Differential

True Bipolar

True
Differential

18-Bit
Multichannel/

Simultaneous AD7654 AD7655

PRODUCT HIGHLIGHTS

1. Fast Throughput.

The AD7643 is a 1.25 MSPS, charge redistribution,

it SAR ADC.

18-b

2. Su

perior Linearity.

The AD7643 has no missing 18-bit code.

3. Inter

4. S

5. S

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

nal Reference.
The AD7643 has a 2.048 V internal reference with a typical
drift of ±8 ppm/°C and an on-chip TEMP sensor.

ingle-Supply Operation.

The AD7643 operates from a 2.5 V single supply.

erial or Parallel Interface.
Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial
interface arrangement compatible with 2.5 V, 3.3 V, or
5 V logic.

REF REFGND

AD7643

REF AMP

SWITCHED

CAP DAC

CNVST

100 to
250

AD7651,
AD7660,
AD7661

CLOCK

Figure 1.

500 to
570

AD7650,
AD7652,
AD7664,

SERIAL

PARALLEL

INTERFACE

650 to
1000 >1000

AD7653,
AD7667

AD7666

AD7610,
AD7663

AD7665

AD7612,
AD7671

AD7675 AD7676 AD7677

AD7631,
AD7678

AD7679

AD7634,
AD7674

PORT

DGNDDVDD

18

OVDD

OGND

D[17:0]

MODE0

MODE1

BUSY

RD

CS

D0/OB/2C

AD7621,

AD7622,

AD7623
AD7641,

AD7643

06024-001

AD7643

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Multiplexed Inputs ..................................................................... 17

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Te r mi n ol o g y .................................................................................... 11

Typical Performance Characteristics........................................... 12

Applications Information .............................................................. 15

Circuit Information.................................................................... 15

Converter Operation.................................................................. 15

Driver Amplifier Choice ........................................................... 18

Voltage Reference Input ............................................................ 18

Power Supply............................................................................... 20

Conversion Control ................................................................... 20

Interfaces.......................................................................................... 21

Digital Interface.......................................................................... 21

Parallel Interface......................................................................... 21

Serial interface............................................................................ 22

Master Serial Interface............................................................... 22

Slave Serial Interface .................................................................. 24

Microprocessor Interfacing....................................................... 26

Application Hints ........................................................................... 27

Layout ..........................................................................................27

Evaluating the AD7643 Performance...................................... 27

Outline Dimensions .......................................................................28

Transfer Fu nctions ...................................................................... 16

Typical Con ne ction Diag ram........................................................ 17

Analog Inputs.............................................................................. 17

REVISION HISTORY

4/06—Revision 0: Initial Version

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

AD7643

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SPECIFICATIONS

AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V

Table 2.

Parameter Conditions Min Typ Max Unit

RESOLUTION 18 Bits
ANALOG INPUT

Voltage Range V
Operating Input Voltage V

IN+

IN+

Analog Input CMRR fIN = 100 kHz 58 dB
Input Current 1.25 MSPS throughput 2.5 μA
Input Impedance

2

THROUGHPUT SPEED

Complete Cycle 800 ns
Throughput Rate 1.25 MSPS

DC ACCURACY

Integral Linearity Error

3

−3 ±1.5 +3 LSB
No Missing Codes 18 Bits
Differential Linearity Error −1 +1.25 LSB
Transition Noise V
V
Zero Error, T

MIN

to T

MAX

5

REF

REF

−16 +16 LSB
Zero Error Temperature Drift ±1 ppm/°C
Gain Error, T

MIN

to T

MAX

5

−22 +22 LSB
Gain Error Temperature Drift ±1 ppm/°C
Power Supply Sensitivity AVDD = 2.5 V ± 5% ±16 LSB

AC ACCURACY

Dynamic Range V

REF

Signal-to-Noise fIN = 1 kHz, V
f
f
f

= 20 kHz, V

IN

= 20 kHz, V

IN

= 100 kHz, V

IN

Spurious-Free Dynamic Range fIN = 1 kHz, V
f
f
f

= 20 kHz, V

IN

= 20 kHz, V

IN

= 100 kHz, V

IN

Total Harmonic Distortion fIN = 1 kHz, V
f
f
f

= 20 kHz, V

IN

= 20 kHz, V

IN

= 100 kHz, V

IN

Signal-to-(Noise + Distortion) fIN = 1 kHz, V
f
f
f

= 20 kHz, V

IN

= 20 kHz, V

IN

= 100 kHz, V

IN

−3 dB Input Bandwidth 50 MHz

SAMPLING DYNAMICS

Aperture Delay 1 ns
Aperture Jitter 5 ps rms
Transient Response Full-scale step 250 ns

INTERNAL REFERENCE PDREF = PDBUF = low

Output Voltage REF @ 25°C 2.038 2.048 2.058 V
Temperature Drift −40°C to +85°C ±8 ppm/°C
Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V

= 2.5 V; all specifications T

REF

− V

IN−

, V

to AGND −0.1 AVDD

IN−

MIN

−V

to T

, unless otherwise noted.

MAX

REF

+V

REF

1

V

V

= 2.5 V 1.7 LSB
= 2.048 V 2.0 LSB

= 2.5 V 95 dB

= 2.5 V 93.5 dB

REF

= 2.5 V 93.5 dB

REF

= 2.048 V 92 dB

REF

= 2.5 V 93 dB

REF

= 2.5 V 118 dB

REF

= 2.5 V 114 dB

REF

= 2.048 V 111 dB

REF

= 2.5 V 108 dB

REF

= 2.5 V −114 dB

REF

= 2.5 V −113 dB

REF

= 2.048 V −109 dB

REF

= 2.5 V −105 dB

REF

= 2.5 V 93.5 dB

REF

= 2.5 V 93.5 dB

REF

= 2.048 V 91.8 dB

REF

= 2.5 V 92.5 dB

REF

4

6

Rev. 0 | Page 3 of 28

AD7643

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Parameter Conditions Min Typ Max Unit

Turn-On Settling Time C
REFBUFIN Output Voltage REFBUFIN @ 25°C 1.19 V
REFBUFIN Output Resistance 6.33 kΩ

EXTERNAL REFERENCE PDREF = PDBUF = high

Voltage Range REF 1.8 2.5 AVDD + 0.1 V
Current Drain 1.25 MSPS throughput 100 μA

REFERENCE BUFFER PDREF = high, PDBUF = low

REFBUFIN Input Voltage Range REF = 2.048 V typical 1.05 1.2 1.30 V
REFBUFIN Input Current REFBUFIN = 1.2 V 1 nA

TEMPERATURE PIN

Voltage Output @ 25°C 278 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4.7 kΩ

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format
Pipeline Delay

V

OL

V

OH

7

8

POWER SUPPLIES

Specified Performance

AVDD 2.37 2.5 2.63 V
DVDD 2.37 2.5 2.63 V
OVDD 2.30

Operating Current

11

AVD D

10

DVDD 1.5 mA

12

OVDD

Power Dissipation

10, 11

With Internal Reference 1.25 MSPS throughput 65 80 mW
With External Reference 1.25 MSPS throughput 60 75 mW

In Power-Down Mode

TEMPERATURE RANGE

12

13

Specified Performance T

1

When using an external reference. With the internal reference, the input range is −0.1 V to V

2

See Analog Inputs section.

3

Linearity is tested using endpoints, not best fit.

4

LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 15.63 μV.

5

See Voltage Reference Input section. These specifications do not include the error contribution from the external reference.

6

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

7

Parallel or serial 18-bit.

8

Conversion results are available immediately after completed conversion.

9

See the Absolute Maximum Ratings section.

10

Tested in parallel reading mode.

11

With internal reference, PDREF and PDBUF are low; with external reference, PDREF and PDBUF are high.

12

With all digital inputs forced to OVDD.

13

Consult sales for extended temperature range.

= 10 μF 5 ms

REF

−0.3 +0.6 V

1.7 5.25 V

−1 +1 μA

−1 +1 μA

I

= 500 μA 0.4 V

SINK

I

= −500 μA OVDD − 0.3 V

SOURCE

9

3.6 V

1.25 MSPS throughput
With internal reference 24 mA

0.5 mA

PD = high 2 μW

MIN

to T

MAX

−40 +85 °C

.

REF

Rev. 0 | Page 4 of 28

AD7643

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TIMING SPECIFICATIONS

AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V

Table 3.

Parameter Symbol Min Typ Max Unit

CONVERSION AND RESET (Refer to Figure 30 and Figure 31)

Convert Pulse Width t
Time Between Conversions t
CNVST

Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert) t
Aperture Delay t
End of Conversion to BUSY Low Delay t
Conversion Time t
Acquisition Time t
RESET Pulse Width t
RESET Low to BUSY High Delay
BUSY High Time from RESET Low

2

2

PARALLEL INTERFACE MODES (Refer to Figure 32 to Figure 35 )

CNVST

Low to Data Valid Delay
Data Valid to BUSY Low Delay t
Bus Access Request to Data Valid t
Bus Relinquish Time t

MASTER SERIAL INTERFACE MODES3 (Refer to Figure 36 and Figure 37)

CS

Low to SYNC Valid Delay

CS

Low to Internal SCLK Valid Delay

CS

Low to SDOUT Delay

CNVST

Low to SYNC Delay

3

SYNC Asserted to SCLK First Edge Delay t
Internal SCLK Period
Internal SCLK High
Internal SCLK Low
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
CS

High to SYNC Hi-Z

CS

High to Internal SCLK Hi-Z

CS

High to SDOUT Hi-Z

4

4

4

4

4

4

BUSY High in Master Serial Read After Convert
CNVST

Low to SYNC Asserted Delay
SYNC Deasserted to BUSY Low Delay t

SLAVE SERIAL INTERFACE MODES (Refer to Figure 39 and Figure 40)

External SCLK Set-Up Time t
External SCLK Active Edge to SDOUT Delay t
SDIN Set-Up Time t
SDIN Hold Time t
External SCLK Period t
External SCLK High t
External SCLK Low t

1

See the Conversion Control section.

2

See the Digital Interface section and the RESET section.

3

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

4

In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.

= 2.5 V; all specifications T

REF

4

MIN

to T

, unless otherwise noted.

MAX

1

2

t

3

4

5

6

7

8

9

t

38

t

39

t

10

11

12

13

t

14

t

15

t

16

t

17

18

t

19

t

20

t

21

t

22

t

23

t

24

t

25

t

26

t

27

t

28

t

29

30

31

32

33

34

35

36

37

15 70
800 ns
23 ns

550 ns
1 ns
10 ns
550 ns
250 ns
15 ns
10 ns
500 ns

550 ns
2 ns

20 ns
2 15 ns

10 ns
10 ns
10 ns
135 ns
2 ns

8 20 ns
2 ns
2 ns
1 ns
0 ns
0 ns
10 ns

10 ns
10 ns
See Table 4 ns

508 ns
13 ns

5 ns
1 8 ns
5 ns
5 ns

12.5 ns
5 ns
5 ns

1

ns

Rev. 0 | Page 5 of 28

AD7643

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Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SCLK First Edge Delay Minimum t
Internal SCLK Period Minimum t
Internal SCLK Period Maximum t
Internal SCLK High Minimum t
Internal SCLK Low Minimum t
SDOUT Valid Setup Time Minimum t
SDOUT Valid Hold Time Minimum t
SCLK Last Edge to SYNC Delay Minimum t
BUSY High Width Maximum t

18

19

19

20

21

22

23

24

28

1 3 3 3 ns
8 16 32 64 ns
20 40 70 135 ns
2 8 16 32 ns
2 8 16 32 ns
1 5 5 5 ns
0 0.5 10 30 ns
0 0.5 9 26 ns

0.84 1.14 1.72 2.88 μs

500µA I

OL

TO OUTPUT

PIN

C

L

50pF

500µA I

NOTE
IN SERIAL INT ERFACE MODES, THE S YNC, SCLK, AND
SDOUT TI MING ARE DEFINED WIT H A MAXIMUM LOAD

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

C

L

Figure 2. Load Circuit for Di

SDOUT, SYNC, and SCLK Outputs, C

1.4V

OH

gital Interface Timing,

= 10 pF

L

0.8V

t

DELAY

2V

0.8V

6024-002

Figure 3. Voltage Reference Levels for Timing

2V

t

DELAY

2V

0.8V

6024-003

Rev. 0 | Page 6 of 28

AD7643

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ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs/Outputs

IN+1, IN−, REF, REFBUFIN, TEMP,

INGND, REFGND to AGND

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD −0.3 V to +2.7 V
OVDD −0.3 V to +3.8 V
AVDD to DVDD ±2.8 V
AVDD, DVDD to OVDD −3.8 V to +2.8 V

Digital Inputs −0.3 V to +5.5 V
PDREF, PDBUF
Internal Power Dissipation
Internal Power Dissipation
Junction Temperature 125°C
Storage Temperature Range –65°C to +125°C

1

See Analog Inputs section.

2

See Voltage Reference Input section.

3

Specification is for the device in free air:

48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W.

4

Specification is for the device in free air:

48-Lead LFCSP; θJA = 26°C/W.

2

3

4

AVDD + 0.3 V to
AGND − 0.3 V

±20 mA
700 mW

2.5 W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 7 of 28

AD7643

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PDBUF

PDREF

REFBUFIN

TEMP

AVD D

IN+

AGND

AGNDNCIN–

REFGND

48 47 46 45 44 39 38 3743 42 41 40

1

AGND

AVD D

MODE0

MODE1

D0/OB/ 2C

DGND

DGND

D1/A0

D2/A1

D3

D4/DIVSCLK[0]
D5/DIVSCLK[1]

NC = NO CONNECT

PIN 1
IDENTIFIER

2

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

D6/EXT/INT

D8/INVSCLK

D7/INVSYNC

AD7643

TOP VIEW

(Not to Scale)

DVDD

OVDD

OGND

D9/RDC/SDIN

DGND

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin
No.

1, 36,

Mnemonic Type

AGND P Analog Power Ground Pin.

1

Description

41, 42
2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V.
3, 4 MODE[0:1] DI

Data Output Interface Mode Selection.

Interface MODE# MODE1 MODE0

0 0 0
1 0 1
2 1 0
3 1 1
5

D0/OB/2C

DI/O

When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus
and the data coding is straight binary. In all other modes, this pin allows the choice of straight

2C

binary/twos complement. When OB/

is high, the digital output is straight binary; when low,

the MSB is inverted resulting in a twos complement output from its internal shift register.
6, 7 DGND P Connect to Digital Ground.
8 D1/A0 DI/O

When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this

input pin controls the form in which data is output as shown in Tabl e 7.
9 D2/A1 DI/O When MODE[1:0] = 0, this pin is Bit 2 of the par

When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7.
10 D3 DO

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus.

This pin is always an output, regardless of the interface mode.
11, 12 D[4:5] DI/O
or DIVSCLK[0:1]

When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus.

When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read

after convert mode (EXT/INT

= low, RDC/SDIN = low), these inputs can be used to slow down the

internally generated serial clock that clocks the data output. In other serial modes, these pins are

high impedance outputs.
13 D6 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus.

or EXT/INT

When MODE[1:0] = 3 (serial mode), serial clock source select. This input is used to select the

ternally generated (master) or external (slave) serial data clock.

in

When EXT/INT

When EXT/INT

= low, master mode. The internal serial clock is selected on SCLK output.
= high, slave mode. The output data is synchronized to an external clock signal,

gated by CS, connected to the SCLK input.

REF

36

AGND

CNVST

35

PD

34

33

RESET

32

CS

31

RD

30

DGND

29

BUSY

28

D17

27

D16

26

D15

25

D14

D11/SCLK

D12/SYNC

D10/SDOUT

D13/RDERROR

06024-004

allel port data output bus.

Description

18-bit interface
16-bit interface
8-bit (byte) interface
Serial interface

Rev. 0 | Page 8 of 28

AD7643

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Pin
No. Mnemonic Type

14 D7 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus.
or INVSYNC

15 D8 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus.
or INVSCLK

16 D9 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as bit 9 of the parallel port data output bus.
or RDC

or SDIN

17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P

19 DVDD P Digital Power. Nominally at 2.5 V.
20 DGND P Digital Power Ground.
21 D10 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus.
or SDOUT

22 D11 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus.
or SCLK

23 D12 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus.
or SYNC

24 D13 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.
or RDERROR

25 to
28

29 BUSY DO

30 DGND P Digital Power Ground.

D[14:17] DO

1

Description

When MODE[1:0] = 3 (serial mode), invert sync selec
input is used to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.

When INVSYNC = high, SYNC is active low.

When MODE[1:0] = 3 (serial mode), invert SCLK select. I
invert the SCLK signal.

When MODE[1:0] = 3 (serial mode), read during c
(EXT/INT

When RDC = high, the previous conversion result is output on SDOUT during conversion and
the per

When RDC = low (read after convert), the current result can be output on SDOUT only when
the c

When MODE[1:0] = 3 (serial mode), serial data in.
SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs
onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK
periods after the initiation of the read sequence.

Input/Output Interface Digital Power. Nominally at the same supply as the supply of the
host in

When MODE[1:0] = 3 (serial mode), serial da
data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7643
provides the conversion result, MSB first, from its internal shift register. The data format is
determined by the logic level of OB/2C

In master mode, EXT/INT
In slave mode, EXT/INT

When MODE[1:0] = 3 (serial mode), serial clock. In all serial modes, this pin is used as the serial
da
where the data SDOUT is updated depends on the logic state of the INVSCLK pin.

When MODE[1:0] = 3 (serial mode), frame synchr
this output is used as a digital output frame synchronization for use with the internal data clock.

When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high
while SDOUT output is valid.

When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low
while SDOUT output is valid.

When MODE[1:0] = 3 (serial mode), read error. In serial slave mode (EXT/INT
is used as an incomplete read error flag. If a data read is started and not completed when the

current conversion is complete, the current data is lost and RDERROR is pulsed high.
Bit 14 to Bit 17 of the Parallel Port Data Output Bus.

the interface mode.
Busy Output. Transitions high when a conversion is started and remains high until the conversion

is c
used as a data-ready clock signal.

= low), RDC is used to select the read mode.

iod of SCLK changes (see the Master Serial Interface section).

onversion is complete.

terface (2.5 V or 3 V).

ta output. In serial mode, this pin is used as the serial

.

= low. SDOUT is valid on both edges of SCLK.

= high:
When INVSCLK = low, SDOUT is updated on SCLK rising ed
When INVSCLK = high, SDOUT is updated on SCLK falling ed

ta clock input or output, depending upon the logic state of the EXT/INT

omplete and the data is latched into the on-chip shift register. The falling edge of BUSY can be

t. In serial master mode (EXT/INT

n all serial modes, this input is used to

onvert. When using serial master mode

When using serial slave mode (EXT/INT

ge and valid on the next falling edge.

ge and valid on the next rising edge.

pin. The active edge

onization. In serial master mode (EXT/INT

= high), this output

These pins are always outputs, regardless of

= low), this

= high),

= low),

Rev. 0 | Page 9 of 28

AD7643

www.BDTIC.com/ADI

Pin
No. Mnemonic Type

31

RD

DI

1

Description

Read Data. When CS

and RD are both low, the interface parallel or serial output bus is enabled.

32

33 RESET DI

34 PD DI

35

37 REF AI/O Reference Output/Input.

38 REFGND AI Reference Input Analog Ground.
39 IN− AI Differential Negative Analog Input.
40 NC No Connect.
43 IN+ AI Differential Positive Analog Input.
45 TEMP AO

46 REFBUFIN AI/O Internal Reference Output/Reference Buffer Input.

47 PDREF DI Internal Reference Power-Down Input.

48 PDBUF DI Internal Reference Buffer Power-Down Input.

1

AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.

CS

CNVST

DI

DI

Chip Select. When CS
CS

is also used to gate the external clock in slave serial mode.

Reset Input. When high, resets the AD7643. Current conversion, if any, is aborted. Falling edge of

T enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface

RESE
sec

tion. If not used, this pin can be tied to DGND.

Power-Down Input. When high, powers down the ADC. Power consumption is reduced and

onversions are inhibited after the current one is completed.

c
Conversion Start. A falling edge on CNVST

and initiates a conversion.

When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally

sup

plied voltage reference up to AVDD volts. Decoupling is required with or without the internal

reference and buffer. Refer to the Voltage Reference Input section.

Temperature Sensor Analog Output. Normally, 278 mV @ 25
of 1 mV/°C. This pin can be used to measure the temperature of the AD7643. See the
Temperature Sensor section.

When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical)
band gap output on this pin, which needs external decoupling. The internal fixed gain reference
buffer uses this to produce 2.048 V on the REF pin.

When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high),
ap

plying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section.

When low, the internal reference is enabled.
When high, the internal reference is powered down and an external reference must been used.

When low, the buffer is enabled (must be lo
When high, the buffer is powered down.

and RD are both low, the interface parallel or serial output bus is enabled.

puts the internal sample-and-hold into the hold state

°C with a temperature coefficient

w when using internal reference).

Table 7. Data Bus Interface Definition

MODE MODE1 MODE0

0 0 0 R[0] R[1] R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 18-Bit Parallel
1 0 1

1 0 1

2 1 0

2 1 0

2 1 0

2 1 0

3 1 1

D0/OB/

2C

OB/

2C

OB/

2C

OB/

2C

OB/

2C

OB/

2C

OB/

2C

OB/

D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description

2C

A0 = 0 R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 16-Bit High Word

A0 = 1 R[0] R[1] All Zeros 16-Bit Low Word

A0 = 0 A1 = 0 All Hi-Z R[10:11] R[12:15] R[16:17] 8-Bit High Byte

A0 = 0 A1 = 1 All Hi-Z R[2:3] R[4:7] R[8:9] 8-Bit Mid Byte

A0 = 1 A1 = 0 All Hi-Z R[0:1] All Zeros 8-Bit Low Byte

A0 = 1 A1 = 1 All Hi-Z All Zeros R[0:1] 8-Bit Low Byte

All Hi-Z Serial Interface Serial Interface

Rev. 0 | Page 10 of 28

AD7643

(

M

MAX

www.BDTIC.com/ADI

TERMINOLOGY

Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code

rom a line drawn from negative full scale through positive full

f
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential

onlinearity is the maximum deviation from this ideal value. It

n
is often specified in terms of resolution for which no missing
codes are guaranteed.

Gain Error

The first transition (from 000…00 to 000…01) should occur for

analog voltage ½ LSB above the nominal negative full scale

an
(−2.0479922 V for the ±2.048 V range). The last transition
(from 111…10 to 111…11) should occur for an analog voltage
1½ LSB below the nominal full scale (+2.0479766 V for the
±2.048 V range). The gain error is the deviation of the
difference between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic

mponents to the rms value of a full-scale input signal and is

co
expressed in decibels.

Signal to (Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to

he rms sum of all other spectral components below the Nyquist

t
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.

Spurious-Free Dynamic Range (SFDR)

The difference, in decibels (dB), between the rms amplitude of

e input signal and the peak spurious signal.

th

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave

put. It is related to SINAD and is expressed in bits by

in

ENOB = [(SINA

DdB − 1.76)/6.02]

Aperture Delay

Aperture delay is a measure of the acquisition performance and
is m

easured from the falling edge of the

CNVST

input to when

the input signal is held for a conversion.

Zero Error

The zero error is the difference between the ideal midscale

put voltage (0 V) and the actual voltage producing the

in
midscale output code.

Dynamic Range

It is the ratio of the rms value of the full scale to the rms noise
m

easured with the inputs shorted together. The value for

dynamic range is expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
r

ms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Transi ent Res p ons e

The time required for the AD7643 to achieve its rated accuracy
a

fter a full-scale step function is applied to its input.

Reference Voltage Temperature Coefficient

It is derived from the typical shift of output voltage at 25°C on a
s

ample of parts maximum and minimum reference output

voltage (V ) measured at T , T(25°C), and T . It is

REF MIN MAX

expressed in ppm/°C using

TCV

()

Cppm/ ×

REF

=°

REF

()

()

REFREF

()

C25

)

6

10

TTV

−×°

IN

MinVMaxV

−

where:

V

(Max) = Maximum V

REF

V

(Min) = Minimum V

REF

V

(25°C) = V

REF

T

MAX

T

MIN

= +85°C

= –40°C

REF

at 25°C

REF

REF

at T

at T

MIN

MIN

, T(25°C), or T

, T(25°C), or T

MAX

MAX

Rev. 0 | Page 11 of 28

AD7643

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

3.0

2.5

2.0

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

0 262144

65536 131072 196608

CODE

Figure 5. Integral Nonlinearity vs. Code

40000

COUNTS

35000

30000

25000

20000

15000

10000

5000

013

0

4848

3062

59

228

17320

23521

33606

26875

13376

6371

1295

488

06024-005

σ

= 1.67
= 2.5V

V

REF

16

30

1.25

1.0

0.5

0

DNL (LS B)

–0.5

–1.0

0 262144

65536 131072 196608

CODE

Figure 8. Differential Nonlinearity vs. Code

35000

V

3807

REF

2306

30000

25000

20000

15000

COUNTS

10000

5000

28621

24350

18613

15505

5401

4726

665

305

21 28

0

16141

10173

= 2.048V

297

108

σ

= 2.04

32

06024-008

1FFF0

1FFF1

1FFF2

1FFF3

1FFF4

1FFF5

1FFF6

1FFF7

1FFF8

1FFF9

1FFEF

1FFEE

CODE IN HEX

1FFFA

1FFFB

Figure 6. Histogram of 131,072 Conversions of a DC Input at

the Cod

e Center (External Reference)

2.0486

2.0484

2.0482

2.0480

(V)

2.0478

REF

V

2.0476

2.0474

2.0472

2.0470
–55 125105856545255–15–35

TEMPERATURE (°C)

Figure 7. Typical Reference Voltage Out

put vs. Temperature (2 Units)

1FFFC

1FFFD

20027

20028

1FFFF

1FFFE

06024-006

20029

2002A

2002B

2002C

2002F

2002E

2002D

CODE IN HEX

20030

20031

20032

20033

20034

20035

20036

20037

20038

06024-009

Figure 9. Histogram of 131,072 Conversions of a DC Input at

the Cod

e Center (Internal Reference)

12

10

8

6

4

2

0

–2

–4

–6

ZERO ERROR, GAIN ERROR ( LSB)

–8

–10

06024-007

–12

–55 125105856545255–15–35

TEMPERATURE (°C)

GAIN ERROR

ZERO ERROR

06024-010

Figure 10. Zero Error, Gain Error vs. Temperature

Rev. 0 | Page 12 of 28

AD7643

–

–

www.BDTIC.com/ADI

0

–20

–40

–60

–80

–100

–120

–140

AMPLITUDE (dB of Full Scale)

–160

–180

06

100 200 300 400 500

FREQUENCY (kHz)

f

= 1.25MSPS

S

f

= 20.03kHz

IN

SNR = 93.4dB
THD = –113dB
SFDR = 108dB
SINAD = 93.4dB

00

06024-011

Figure 11. FFT 20 kHz

95

93

91

89

87

85

83

SNR, SINAD (dB)

81

79

77

75

1 1000

10 100

FREQUENCY (kHz)

SINAD

ENOB

SNR

16.0

15.6

15.2

14.8

14.4

14.0

13.6

13.2

12.8

12.4

12.0

ENOB (Bits)

06024-012

Figure 12. SNR, SINAD, and ENOB vs. Frequency

70

SFDR

–80

–90

–100

–110

–120

THD, HARMONICS ( dB)

–130

–140

1 1000

SECOND HARMONIC

10 100

FREQUENCY (kHz)

THD

THIRD HARMONIC

120

110

100

90

80

70

60

50

40

30

20

SFDR (dB)

06024-013

Figure 13. THD, H armonics, and SFDR vs. Freque ncy

0

–20

–40

–60

–80

–100

–120

–140

AMPLITUDE (dB of Full Scale)

–160

–180

0600

100 200 300 400 500

FREQUENCY (kHz)

f

= 1.25MSPS

S

f

= 100.03kHz

IN

SNR = 93dB
THD = –106dB
SFDR = 109dB
SINAD = 92.8dB

06024-014

Figure 14. FFT 100 kHz

95

94

93

92

SNR, SINAD (dB)

91

90

SNR

SINAD

ENOB

–55 125105

TEMPERATURE ( °C)

856545255–15–35

19

18

17

16

ENOB (Bits)

15

06024-015

14

Figure 15. SNR, SINAD, and ENOB vs. Temperature

THD, HARMONICS (dB)

–90

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

–145

85

–55 125105856545255–15–35

THD

SECOND
HARMONIC

TEMPERATURE ( °C)

THIRD
HARMONIC

SFDR

120

110

100

90

80

70

60

SFDR (dB)

06024-016

Figure 16. THD, Harmonics, and SFDR vs. Temperature

Rev. 0 | Page 13 of 28

AD7643

A

www.BDTIC.com/ADI

96.0

95.5

95.0

SNR

94.5

94.0

93.5

SNR, SINAD REFERRED TO FULL SCALE (dB)

93.0

–60 0

SINAD

–50 –40 –30 –20 –10

INPUT LEVEL (dB)

Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale)

16

14

)

12

10

8

6

4

OPERATING CURRENTS (µ

2

0

–35–155 25456585105

TEMPERATURE (°C)

DVDD

OVDD, 3.3V

OVDD, 2.5V

AVDD

Figure 18. Power-Down Operating Currents vs. Temperature

06024-017

125–55

06024-018

100k

AVDD

10k

1k

100

OVDD = 3.3V

10

1

OPERATING CURRENTS (µA)

0.1

0.01
10 10M

100 1k 10k 100k 1M

SAMPLING RATE (SPS)

DVDD

OVDD = 2.5V

PDREF = PDBUF = HIGH

Figure 19. Operating Current vs. Sampling Rate

20

18

16

14

12

DELAY (ns)

12

10

t

8

6

4

OVDD = 2.5V @ 85°C

OVDD = 2.5V @ 2 5°C

0

50 100 150 200

OVDD = 3.3V @ 25°C

OVDD = 3.3V @ 8 5°C

C

(pF)

L

Figure 20. Typical Delay vs. Load Capacitance C

06024-019

06024-020

L

Rev. 0 | Page 14 of 28

AD7643

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

IN+

MSB

131,072C

REF

REFGND

131,072C

IN–

65,536C 4C 2C C C

65,536C

MSB

4C 2C C C

Figure 21. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7643 is a very fast, low power, single-supply, precise
18-bit ADC using successive approximation architecture. The
AD7643 is capable of converting 1,250,000 samples per second
(1.25 MSPS).

The AD7643 provides the user with an on-chip, track-and-hold,

uccessive approximation ADC that does not exhibit any

s
pipeline or latency, making it ideal for multiple multiplexed
channel applications.

The AD7643 can operate from a single 2.5 V supply and
in

terface to either 5 V, 3.3 V, or 2.5 V digital logic. It is housed
in a Pb-free, 48-lead LQFP package or a tiny 48-lead LFCSP
package, which combines space savings with flexibility and
allows the AD7643 to be configured as either a serial or a
parallel interface. The AD7643 is pin-to-pin compatible with
the AD7641 and is a speed upgrade of the AD7674, AD7678,

AD7679.

nd

a

CONVERTER OPERATION

The AD7643 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
s

chematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors that are
connected to the two comparator inputs.

AGND

SWITCHES

COMP

CONTROL

CONTROL

LOGIC

CNVST

BUSY

OUTPUT

CODE

06024-021

LSB

LSB

SW+

SW–

AGND

During the acquisition phase, terminals of the array tied to the

mparator’s input are connected to AGND via SW+ and SW−.

co
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. A
conversion phase is initiated once the acquisition phase is complete

CNVST

and the

input goes low. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the REFGND input. Therefore, the differential voltage between
the inputs (IN+ and IN−) captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between REFGND and REF, the comparator

/2, V

input varies by binary weighted voltage steps (V
throughV

/262144). The control logic toggles these switches,

REF

REF

REF

/4

starting with the MSB first, to bring the comparator back into a
balanced condition. After the completion of this process, the
control logic generates the ADC output code and brings BUSY
output low.

Rev. 0 | Page 15 of 28

AD7643

2

3

4

www.BDTIC.com/ADI

TRANSFER FUNCTIONS

Using the OB/2C digital input, except in 18-bit interface mode,
the AD7643 offers two output codings: straight binary and twos
complement. The LSB size with V
262,144, which is 15.623 μV. Refer to Figure 22 and Tab le 8 for

e ideal transfer characteristic.

th

111. ..111

111.. .110

111. ..10 1

ADC CODE (Straig ht Binary)

000...010

000...001

000...000

–FSR

–FSR + 0.5 L SB

Figure 22. ADC Ideal Transfer Function

ANALOG

SUPPLY (2.5V)

10µF

100nF

= 2.048 V is 2 × V

REF

ANALOG INPUT

+FSR – 1 LSB–FSR + 1 LSB

+FSR – 1.5 LS B

NOTE 5

10Ω

10µF

/

REF

06024-022

100nF 100nF

SUPPLY (2.5V)

Table 8. Output Codes and Ideal Input Voltages

Digital Output Code (Hex)

Description

Analog Input

= 2.048 V

V

REF

Straight
Binar

y

FSR −1 LSB +2.0479844 V 0x3FFFF10x1FFFF
FSR − 2 LSB +2.0479688 V 0x3FFFE 0x1FFFE
Midscale + 1 LSB +15.625 μV 0x20001 0x00001
Midscale 0 V 0x20000 0x00000
Midscale − 1 LSB −15.625 μV 0x1FFFF 0x3FFFF

−FSR + 1 LSB −2.0479844 V 0x00001 0x20001

−FSR −2.048 V 0x0000020x20000

1

DIGITAL

This is also the code for overrange analog input (V

+V

− V

+ V

REFGND

REFGND

).

).

DIGITAL

INTERFACE

SUPPLY

10µF

(2.5V OR 3. 3V)

REF

2

This is also the code for underrange analog input (V

−V

REF

− V

IN+

− V

IN+

Two s
Complement

above

IN−

below

IN−

1

2

AVD D

AGND DGND DVDD O VDD OGND

REF

C

REF

10µF

100nF

NOTE 4

NOTE 2

ANALOG

INPUT +

ANALOG

INPUT –

1. SEE ANALOG INP UTS SECTI ON.
. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIF IER CHOICE SECTION.
. THE CONFIGURAT ION SHOW N IS USING THE INTERNAL REFERENCE. S EE VOLTAGE REFERENCE I NPUT SECTI ON.
. A 10µF CERAMIC CAPACI TOR (X5R, 1206 SIZE) IS RECOMME NDED (FOR EXAMPLE, P ANASONIC ECJ3YB0J106M).

SEE VOLTAGE REFERENCE INPUT SECTION.

5. OPTION, SEE POWER SUPPLY SECTION.

6. OPTION, SEE POWER-UP SECTIO N.

7. OPTIONAL LOW JI TTER CNVST , SEE CONV ERSION CONT ROL SECT ION.

U1

C

NOTE 2

U2

C

15Ω

2.7nF

C

NOTE 1

15Ω

2.7nF

C

NOTE 1

REFBUFIN

REFGND

IN+

IN–

NOTE 3

PD

AD7643

NOTE 3

PDREF

PDBUF

SCLK

SDOUT

BUSY

CNVST

D0/OB/ 2C

MODE0
MODE1

RESET

Figure 23. Typical Connection Diagram

CS

RD

50Ω

50pF

50pF

10kΩ

NOTE 6

SERIAL

PORT

NOTE 7

OVDD

D

CLOCK

MICROCONVERTER/

MICROPROCESSOR/

DSP

06024-023

Rev. 0 | Page 16 of 28

AD7643

A

V

–

www.BDTIC.com/ADI

TYPICAL CONNECTION DIAGRAM

Figure 23 shows a typical connection diagram for the AD7643.
Different circuitry shown in this diagram is optional and is
discussed in the following sections.

ANALOG INPUTS

Figure 24 shows an equivalent circuit of the input structure of
the AD7643.

The two diodes, D
analog inputs IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V, because this causes the diodes to become forward­biased and to start conducting current. These diodes can handle
a forward-biased current of 100 mA maximum. For instance,
these conditions could eventually occur when the input buffer’s
U1 or U2 supplies are different from AVDD. In such a case, an
input buffer with a short-circuit current limitation can be used
to protect the part.

IN+ OR IN–

AGND

The analog input of the AD7643 is a true differential structure.
By using this differential input, small signals common to both
inputs are rejected, as shown in Figure 25, representing the

ypical CMRR over frequency with internal and external references.

t

65

60

55

CMRR (dB)

50

45

1 10000

During the acquisition phase for ac signals, the impedance of
the analog inputs, IN+ and IN−, can be modeled as a parallel
combination of capacitor C
series connection of R
capacitance. R
comprised of some serial resistors and the on resistance of the

and D2, provide ESD protection for the

1

DD

D

1

C

PIN

Figure 24. AD7643 Simplified Analog Input

INT REF

EXT REF

10 100 1000

Figure 25. Analog Input CMRR vs. Frequency

IN

is typically 175 Ω and is a lumped component

IN

D

2

FREQUENCY (kHz)

and the network formed by the

PIN

and CIN. C

is primarily the pin

PIN

C

R

IN

IN

06024-024

06024-025

switches. C
capacitor. During the conversion phase, when the switches are
opened, the input impedance is limited to C
make a 1-pole, low-pass filter that has a typical −3 dB cutoff
frequency of 50 MHz, thereby reducing an undesirable aliasing
effect and limiting the noise coming from the inputs.

Because the input impedance of the AD7643 is very high, the
AD7643
without gain error. To further improve the noise filtering achieved
by the AD7643’s analog input circuit, an external 1-pole RC
filter between the amplifier’s outputs and the ADC analog
inputs can be used, as shown in
i

mpedances significantly affect the ac performance, especially
the total harmonic distortion (THD). The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency, as shown in
Figure 26.

THD (dB)

Figure 26. THD vs. Analog Input Frequency and Source Resistance

MULTIPLEXED INPUTS

When using the full 1.25 MSPS throughput in multiplexed
applications for a full-scale step, the RC filter, as shown in
Figure 23, does not settle in the required acquisition time, t
These values are chosen to optimize the best SNR performance
of the AD7643. To use the full 1.25 MSPS throughput in
multiplexed applications, the RC should be adjusted to satisfy t
(which is ~ 8.5 × RC time constant). However, lowering R and C
increases the RC filter bandwidth and allows more noise into the
AD7643, which degrades SNR. To preserve the SNR performance
in these applications using the RC filter shown in Figure 23,

e AD7643 should be run with t

th

+ t8) ~ 1.12 MSPS.

1/(t

7

is typically 12 pF and is mainly the ADC sampling

IN

. RIN and CIN

PIN

can be driven directly by a low impedance source

Figure 23. However, large source

70

–75

–80

–85

–90

–95

–100

–105

–110

1 10 100 1000

RS = 500Ω

RS = 50Ω

INPUT FREQUENCY (kHz)

> 350 ns; or approximately

8

RS = 100Ω

RS = 10Ω

06024-026

.

8

8

Rev. 0 | Page 17 of 28

AD7643

(

www.BDTIC.com/ADI

DRIVER AMPLIFIER CHOICE

Although the AD7643 is easy to drive, the driver amplifier
needs to meet the following requirements:

• For multichannel, multiplexed applications, the driver

amplifier and the AD7643 analog input circuit must be
able to settle for a full-scale step of the capacitor array at an
18-bit level (0.0004%). In the amplifier’s data sheet, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at an 18-bit level
and should be verified prior to driver selection. The

AD8021 op amp, which combines ultralow noise and high

g

ain bandwidth, meets this settling time requirement even

when used with gains up to 13.

• The noise generated by the driver amplifier needs to be

kept as low as possible to preserve the SNR and transition
noise performance of the AD7643. The noise coming from
the driver is filtered by the AD7643 analog input circuit
1-pole, low-pass filter made by R
external filter, if one is used. The SNR degradation due
to the amplifier is

⎛
⎜

⎜

LOSS

=

20log

⎜
⎜

⎜
⎝

900

π

SNR

where:

is the input bandwidth of the AD7643 (50 MHz) or

f

–3dB

the cutoff frequency of the input RC filter shown in Figure 23
(3.9 MH

N is t

z), if one is used.

he noise factor of the amplifier (1 in buffer

configuration).

and eN− are the equivalent input voltage noise densities

e

N+

of the op amps connected to IN+ and IN−, in nV/√Hz.
This approximation can be used when the resistances used
around the amplifier are small. If larger resistances are
used, their noise contributions should also be root-sum
squared.

For instance, when using op amps with an equivalent input

se density of 2.1 nV/√Hz, such as the AD8021, with a

noi
n

oise gain of 1 when configured as a buffer, degrades the

SNR by only 0.25 dB when using the RC filter in Figure 23,

nd by 2.5 dB without it.

a

and CIN or by the

IN

30

π

f

−

3dB

() ()

Ne

2

N

f

−

3dB

++

+

Ne

2

⎞
⎟

⎟
⎟

22

⎟

⎟

−

N

⎠

The AD8021 meets these requirements and is appropriate for

ost all applications. The AD8021 needs a 10 pF external

alm
co

mpensation capacitor that should have good linearity as an
NPO ceramic or mica type. Moreover, the use of a noninverting
1 gain arrangement is recommended and helps to obtain the
best signal-to-noise ratio.

The AD8022 can also be used when a dual version is needed
a

nd a gain of 1 is present. The AD829 is an alternative in
pplications where high frequency (above 100 kHz) performance is

a
not required. In applications with a gain of 1, an 82 pF
compensation capacitor is required. The AD8610 is an option

hen low bias current is needed in low frequency applications.

w

Single-to-Differential Driver

For applications using unipolar analog signals, a single-ended­to-differential driver, as shown in Figure 27, allows for a
dif

ferential input into the part. This configuration, when

provided an input signal of 0 to V

with midscale at V

±V

REF

/2. The 1-pole filter using R = 15 Ω

REF

, produces a differential

REF

and C = 2.7 nF provides a corner frequency of 3.9 MHz.

If the application can tolerate more noise, the AD8139

ferential driver can be used.

dif

U1

ANALOG INPUT

UNIPOLAR 0VTO 2.048V)

5kΩ

5kΩ

100nF

Figure 27. Single-Ended-to-D

AD8021

10pF

590Ω

590Ω

U2

AD8021

10pF

(Internal Reference Buffer Used)

15Ω

2.7nF

15Ω

2.7nF

ifferential Driver Circuit

IN+

AD7643

IN–

10µF

REF

VOLTAGE REFERENCE INPUT

The AD7643 allows the choice of either a very low temperature
drift internal voltage reference, an external 1.2 V reference that
can be buffered using the internal reference buffer, or an
external reference.

Unlike many ADCs with internal references, the internal

eference of the AD7643 provides excellent performance and

r
can be used in almost all applications.

06024-027

• The driver needs to have a THD performance suitable to

that of the AD7643. Figure 13 gives the THD vs. frequency
t

hat the driver should exceed.

Rev. 0 | Page 18 of 28

AD7643

www.BDTIC.com/ADI

Internal Reference (PDBUF = Low, PDREF = Low)

To use the internal reference, the PDREF and PDBUF inputs
must both be low. This produces a 1.2 V band gap output on
REFBUFIN, which is amplified by the internal buffer and
results in a 2.048 V reference on the REF pin.

The internal reference is temperature compensated to 2.048 V ±

. The reference is trimmed to provide a typical drift of

10 mV
8 ppm/°C. This typical drift characteristic is shown in Figure 7.

The output resistance of REFBUFIN is 6.33 kΩ (minimum)

hen the internal reference is enabled. It is necessary to

w
decouple this with a ceramic capacitor greater than 100 nF.
Therefore, the capacitor provides an RC filter for noise reduction.

Because the output impedance of REFBUFIN is typically

kΩ, relative humidity (among other industrial contaminates)

6.33
can directly affect the drift characteristics of the reference.
Typically, a guard ring is used to reduce the effects of drift
under such circumstances. However, because the AD7643 has a
fine lead pitch, guarding this node is not practical. Therefore, in
these industrial and other types of applications, it is recommended
to use a conformal coating, such as Dow Corning® 1-2577 or
HumiSeal® 1B73.

External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High)

To use an external reference along with the internal buffer,
PDREF should be high and PDBUF should be low. This powers
down the internal reference and allows an external 1.2 V
reference to be applied to REFBUFIN, producing 2.048 V
(typically) on the REF pin.

External 2.5 V Reference (PDBUF = High, PDREF = High)

To use an external 2.5 V reference directly on the REF pin,
PDREF and PDBUF should both be high.

For improved drift performance, an external reference, such as

e AD780 or ADR431, can be used. The advantages of directly

th
usin

g the external voltage reference are:

• The SNR and dynamic range improvement (about 1.7 dB)

resulting from the use of a reference voltage very close to
the supply (2.5 V) instead of a typical 2.048 V reference
when the internal reference is used. This is calculated by

048.2

=

• The power savings when the internal reference is powered

down (PDREF high).

PDREF and PDBUF power down the internal reference and
t

he internal reference buffer, respectively. The input current

of PDREF and PDBUF should never exceed 20 mA. This can

⎛

log20SNR

⎜
⎝

⎞
⎟

50.2

⎠

occur when the driving voltage is above AVDD (for instance, at
power-up). In this case, a 125 Ω series resistor is recommended.

Reference Decoupling

Whether using an internal or external reference, the AD7643
voltage reference input (REF) has a dynamic input impedance;
therefore, it should be driven by a low impedance source with
efficient decoupling between the REF and REFGND inputs.
This decoupling depends on the choice of the voltage reference
but usually consists of a low ESR capacitor connected to REF
and REFGND with minimum parasitic inductance.

A 10 μF (X5R, 1206 size) ceramic chip capacitor (or 47 μF

antalum capacitor) is appropriate when using either the

t
internal reference or one of the recommended reference voltages.

The placement of the reference decoupling is also important to

he performance of the AD7643. The decoupling capacitor

t
should be mounted on the same side as the ADC right at the
REF pin with a thick PCB trace. The REFGND should also connect
to the reference decoupling capacitor with the shortest distance.

For applications that use multiple AD7643 devices, it is more

fective to use an external reference with the internal reference

ef
buffer to buffer the reference voltage. However, because the
reference buffers are not unity gain, ratiometric, simultaneously
sampled designs should use an external reference and external
buffer, such as the
s

ame reference level for all converters.

The voltage reference temperature coefficient (TC) directly

pacts full scale; therefore, in applications where full-scale

im
accuracy matters, care must be taken with the TC. For instance,
a ±4 ppm/°C TC of the reference changes full scale by ±1 LSB/°C.

Note that V
input range is defined in terms of V
increase the range to 0 V to 2.8 V with an AVDD = 2.7 V.

AD8031/AD8032; therefore, preserving the

can be increased to AVDD + 0.1 V. Because the

REF

, this would essentially

REF

Temperature Sensor

The TEMP pin measures the temperature of the AD7643. To
improve the calibration accuracy over the temperature range,
the output of the TEMP pin is applied to one of the inputs of
the analog switch (such as, ADG779), and the ADC itself is

ed to measure its own temperature. This configuration is

us
shown in Figure 28.

ANALOG INPUT

(UNIPOLAR)

ADG779

AD8021

Figure 28. Use of the Temperature Sensor

C

C

IN+

TEMP

AD7643

TEMPERATURE
SENSOR

06024-028

Rev. 0 | Page 19 of 28

AD7643

www.BDTIC.com/ADI

POWER SUPPLY

The AD7643 uses three sets of power supply pins: an analog

2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.3 V
and 5.25 V. To reduce the number of supplies needed, the digital
core (DVDD) can be supplied through a simple RC filter from
the analog supply, as shown in

Power Sequencing

The AD7643 is independent of power supply sequencing and
thus free from supply induced voltage latch-up. In addition, it is
insensitive to power supply variations over a wide frequency
range, as shown in

65.0

62.5

60.0

Figure 29.

Figure 23.

It should be noted that the digital interface remains active even
d

uring the acquisition phase. To reduce the operating digital
supply currents even further, drive the digital inputs close to
the power rails (that is, OVDD and OGND).

CONVERSION CONTROL

The AD7643 is controlled by the

CNVST

on

is all that is necessary to initiate a conversion.
Detailed timing diagrams of the conversion process are shown
in Figure 30. Once initiated, it cannot be restarted or aborted,
e

ven by the power-down input, PD, until the conversion is
complete. The
RD

signals.

CNVST

CNVST

signal operates independently of CS and

t

1

CNVST

t

2

input. A falling edge

57.5

55.0

PSRR (dB)

52.5

50.0

47.5

45.0
1 10000

EXT REF

INT REF

10 100 1000

FREQUENCY (kHz)

Figure 29. PSRR vs. Frequency

06024-029

Power-Up

At power-up, or when returning to operational mode from the
power-down mode (PD = high), the AD7643 engages an
initialization process. During this time, the first 128 conversions
should be ignored or the RESET input could be pulsed to
engage a faster initialization process. Refer to the Digital

nterface

I

section for RESET and timing details.

A simple power-on reset circuit, as shown in Figure 23, can be
us

ed to minimize the digital interface. As OVDD powers up, the
capacitor is shorted and brings RESET high; it is then charged
returning RESET to low. However, this circuit only works when
powering up the AD7643 because the power-down mode
(PD = high) does not power down any of the supplies and as a
result, RESET is low.

BUSY

t

3

t

5

MODE

For optimal performance, the rising edge of
occur after the maximum

t

4

t

6

CONVERT ACQUI REACQUIRE CONVERT

t

7

Figure 30. Basic Conversion Timing

CNVST

t

8

CNVST

should not

low time, t1, or until the end

of conversion.

Although

CNVST

is a digital signal, it should be designed with

special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.

The

trace should be shielded with ground and a low

CNVST

value serial resistor (for example, 50 Ω) termination should be
added close to the output of the component that drives this line.
In addition, a 50 pF capacitor is recommended to further reduce

CNVST

Figure 23.

signal should

the effects of overshoot and undershoot as shown in

For applications where SNR is critical, the
have very low jitter. This can be achieved by using a dedicated

oscillator for

CNVST

generation, or by clocking

CNVST

with a

high frequency, low jitter clock, as shown in Figure 23.

06024-030

Rev. 0 | Page 20 of 28

AD7643

www.BDTIC.com/ADI

INTERFACES

DIGITAL INTERFACE

The AD7643 has a versatile digital interface that can be set up
as either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The AD7643
digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic
with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic
high output voltage. In most applications, the OVDD supply pin
of the AD7643 is connected to the host system interface 2.5 V

2C

or 3.3 V digital supply. By using the D0/OB/
twos complement or straight binary coding can be used.

The two signals

CS

and RD control the interface. When at least

one of these signals is high, the interface outputs are in high

CS

impedance. Usually,

allows the selection of each AD7643 in

multicircuit applications and is held low in a single AD7643

RD

design.

is generally used to enable the conversion result on

the data bus.

RESET

The RESET input is used to reset the AD7643 and generate a
fast initialization. A rising edge on RESET aborts the current
conversion (if any) and tristates the data bus. The falling edge of
RESET clears the data bus and engages the initialization process
indicated by pulsing BUSY high. Conversions can take place
after the falling edge of BUSY. Refer to Figure 31 for the RESET

ming details.

ti

t

9

RESET

input pin, either

CS = RD = 0

CNVST

BUSY

t

DATA

BUS

Figure 32. Master Parallel Data Timing for Reading (Continuous Read)

t

1

t

10

t

3

PREVIO US CONVERSI ON DATA NEW DATA

4

t

11

Slave Parallel Interface

In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 33 and
Figure 34, respectively. When the data is read during the

onversion, it is recommended that it is read-only during the

c
first half of the conversion phase. This avoids any potential
feedthrough between voltage transients on the digital interface
and the most critical analog conversion circuitry.

CS

RD

BUSY

06024-032

CNVST

DATA

BUSY

t

38

t

39

Figure 31. RESET Timing

t

8

PARALLEL INTERFACE

The AD7643 is configured to use the parallel interface for an
18-bit, 16-bit, or 8-bit bus width according to

Master Parallel Interface

Data can be continuously read by tying CS and RD low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications, unless the device is held in RESET.
Figure 32 details the timing for this mode.

Table 7.

Rev. 0 | Page 21 of 28

DATA

BUS

t

Figure 33. Slave Parallel Data Timing for Reading (Read After Convert)

06024-031

CS = 0

CNVST,

RD

BUSY

t

3

DATA

BUS

t

12

Figure 34. Slave Parallel Data Timing for Reading (Read During Convert)

12

CURRENT

CONVERSION

t

1

PREVIOUS

CONVERSION

t

13

t

4

t

13

06024-033

06024-034

AD7643

www.BDTIC.com/ADI

16-Bit and 8-Bit Interface (Master or Slave)

In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2)
interfaces, the A0/A1 pins allow a glueless interface to a 16- or
8-bit bus, as shown in Figure 35. By connecting A0/A1 to an

ess line(s), the data can be read in two words for a 16-bit

addr
interface, or three bytes for an 8-bit interface. This interface can
be used in both master and slave parallel reading modes. Refer

Table 7 for the full details of the interface.

to

CS, RD

MASTER SERIAL INTERFACE

Internal Clock

The AD7643 is configured to generate and provide the serial
data clock SCLK when the EXT/

AD7643 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted. Depending on the read during
convert input, RDC/SDIN, the data can be read after each
conversion or during the following conversion. Figure 36 and
Figure 37 show detailed timing diagrams of these two modes.

pin is held low. The

INT

A1

A0

D[17:2]

D[17:10]

HI-Z

HI-Z

t

Figure 35. 8-Bit and 16-Bit Parallel Interface

HIGH

BYTE

12

HIGH

WORD

t

12

MID

BYTE

LOW

WORD

LOW

BYTE

t

12

HI-Z

HI-Z

t

13

06024-035

SERIAL INTERFACE

The AD7643 is configured to use the serial interface when
MODE[1:0] = 3. The AD7643 outputs 18 bits of data, MSB first,
on the SDOUT pin. This data is synchronized with the 18 clock
pulses provided on the SCLK pin. The output data is valid on
both the rising and falling edge of the data clock.

Usually, because the AD7643 is used with a fast throughput, the
mas

ter read during conversion mode is the most recommended
serial mode. In this mode, the serial clock and data toggle at
appropriate instants, minimizing potential feedthrough between
digital activity and critical conversion decisions. In this mode,
the SCLK period changes because the LSBs require more time
to settle and the SCLK is derived from the SAR conversion cycle.

In read after conversion mode, it should be noted that unlike
o

ther modes, the BUSY signal returns low after the 18 data bits
are pulsed out and not at the end of the conversion phase,
resulting in a longer BUSY width. As a result, the maximum
throughput cannot be achieved in this mode.

In addition, in read after convert mode, the SCLK frequency
ca

n be slowed down to accommodate different hosts using the
DIVSCLK[1:0] inputs. Refer to Tab le 4 for the SCLK timing
det

ails when using these inputs.

Rev. 0 | Page 22 of 28

AD7643

S

www.BDTIC.com/ADI

CS, RD

CNVST

BUSY

SYNC

SCLK

DOUT

EXT/INT = 0

t

3

t

29

t

14

t

15

X

t

16

t

22

RDC/SDIN = 0

t

18

t

19

t

20

123 161718

D17 D16 D2 D1 D0

INVSCLK = INVSYNC = 0

t

28

t

21

t

23

DIVSCLK[1:0] = 0

t

30

t

24

t

25

t

26

t

27

06024-036

Figure 36. Master Serial Data Timing for Reading (Read After Convert)

CS, RD

CNVST

BUSY

EXT/INT = 0

t

1

t

3

RDC/SDIN = 1 INVSCLK = INVSYNC = 0

SYNC

SCLK

SDOUT

t

17

t

14

t

15

t

18

t

16

t

22

t

19

t20t

21

123 161718

D17 D16 D2 D1 D0X

t

23

t

24

t

25

t

26

t

27

6024-037

Figure 37. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)

Rev. 0 | Page 23 of 28

AD7643

www.BDTIC.com/ADI

SLAVE SERIAL INTERFACE

External Clock

The AD7643 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/

INT

pin is

held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by

are both low, the data can be read after each conversion or

RD

. When CS and

CS

during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 39 and Figure 40 show the detailed timing

iagrams of these methods.

d

While the AD7643 is performing a bit decision, it is important

at voltage transients be avoided on digital input/output pins

th
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7643 provides error correction circuitry
that can correct for an improper bit decision made during
the first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided,
a discontinuous clock is toggled only when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.

Finally, in this mode only, the AD7643 provides a daisy-chain

ature using the RDC/SDIN pin for cascading multiple converters

fe
together. This feature is useful for reducing component count
and wiring connections when desired, as, for instance, in
isolated multiconverter applications.

An example of the concatenation of two devices is shown in
Figure 38. Simultaneous sampling is possible by using a
co

mmon

CNVST

signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite to the one used to
shift out the data on SDOUT. Therefore, the MSB of the
upstream converter just follows the LSB of the downstream
converter on the next SCLK cycle.

BUSY
OUT

BUSYBUS Y

AD7643

#2

(UPSTREAM)

RDC/SDIN SDOUT

CNVST

CS

SCLK

AD7643

#1

(DOWNSTREAM)

SDOUTRDC/SDIN

CNVST

SCLK

CS

DATA
OUT

External Discontinuous Clock Data Read After Conversion

Figure 39 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the conversion result can be read while both

and RD are

CS

low. Data is shifted out MSB first with 18 clock pulses and is
valid on the rising and falling edges of the clock.

Among the advantages of this method is the fact that conversion

erformance is not degraded because there are no voltage

p
transients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 80 MHz, which accommodates both the slow digital host
interface and the fast serial reading.

It is also possible to begin to read data after conversion and
c

ontinue to read the last bits after a new conversion is initiated.
In this reading mode, it is recommended to pause digital
activity just prior to initiating a conversion (SCLK should be
held high or low). Once the conversion has begun, the reading
can continue. Also, in this mode, the use of a slower clock speed
can be used to read the data because the total reading time is the
acquisition time, t

+ half of the conversion time, t7 (t8 + ½ × t7, see

8

the External Clock Data Read During Previous Conversion

on).

secti

SCLK IN

CS IN

CNVST IN

Figure 38. Two AD7643 Devices in a Daisy-Chain Configuration

06024-038

External Clock Data Read During Previous Conversion

Figure 40 shows the detailed timing diagrams of this method.

CS

During a conversion, while

and RD are both low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 18 clock pulses and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete; otherwise, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain
feature in this mode, and the RDC/SDIN input should always
be tied either high or low.

To reduce performance degradation due to digital activity, a fast
dis

continuous clock of at least 67 MHz is recommended to
ensure that all the bits are read during the first half of the SAR
conversion phase, t

, because the ADC can correct for errors

7

introduced by digital activity during this time.

Rev. 0 | Page 24 of 28

AD7643

S

S

www.BDTIC.com/ADI

D0

RD = 0

X17 X16

BUSY

SCLK

DOUT

CS

EXT/INT = 1

t

35

t36t

37

123 1617181920

t

31

X

D17 D16 D1

t

16

t

32

D15

t

34

INVSCLK = 0

SDIN

t

33

X17 X16 X15 X1 X0 Y17 Y16

06024-039

Figure 39. Slave Serial Data Timing for Reading (Read After Convert)

t

31

17 18

D2

RD = 0

D1

D0

6024-040

CS

CNVST

BUSY

SCLK

DOUT

EXT/INT = 1 INVSCLK = 0

t

3

t

35

t

t

36

37

1

t

32

X

t

16

2

D17 D16 D15

3

4

16

Figure 40. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)

Rev. 0 | Page 25 of 28

AD7643

www.BDTIC.com/ADI

MICROPROCESSOR INTERFACING

The AD7643 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and ac signal processing
applications interfacing to a digital signal processor. The
AD7643 is designed to interface with a parallel 8-bit or 16-bit
wide interface or with a general-purpose serial port or I/O ports
on a microcontroller. A variety of external buffers can be used
with the AD7643 to prevent digital noise from coupling into the
ADC. The
o

f the AD7643 with the ADSP-219x SPI-equipped DSP.

SPI Interface (ADSP-219x) section illustrates the use

SPI Interface (ADSP-219x)

Figure 41 shows an interface diagram between the AD7643 and
an SPI-equipped DSP, the ADSP-219x. To accommodate the
slower speed of the DSP, the AD7643 acts as a slave device and
data must be read after conversion. This mode also allows the
daisy-chain feature. The convert command can be initiated in
response to an internal timer interrupt. The 18-bit output data
are read with three SPI byte access. The reading process can be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial
peripheral interface (SPI) on the ADSP-219x is configured for
master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock
phase bit (CPHA) = 1, and the SPI interrupt enable (TIMOD) =
00 by writing to the SPI control register (SPICLTx). It should be
noted that to meet all timing requirements, the SPI clock should
be limited to 17 Mbps, allowing it to read an ADC result in less
than 1 μs. When a higher sampling rate is desired, it is
recommended to use one of the parallel interface modes.

DVDD

AD7643

MODE0
MODE1

EXT/INT

RD

INVSCLK

BUSY

SDOUT

SCLK

CNVST

CS

ADSP-219x

PFx

SPIxSEL (PFx)

MISOx

SCKx

PFx OR TFSx

1

1

ADDITIONAL PINS OMITTED FO R CLARITY.

Figure 41. Interfacing the AD7643 to ADSP-219x

06024-041

Rev. 0 | Page 26 of 28

AD7643

www.BDTIC.com/ADI

APPLICATION HINTS

LAYOUT

While the AD7643 has very good immunity to noise on the
power supplies, exercise care with the grounding layout. To
facilitate the use of ground planes that can be easily separated,
design the printed circuit board that houses the AD7643 so that
the analog and digital sections are separated and confined to
certain areas of the board. Digital and analog ground planes
should be joined in only one place, preferably underneath the
AD7643, or as close as possible to the AD7643. If the AD7643 is
in a system where multiple devices require analog-to-digital
ground connections, the connections should still be made at
one point only, a star ground point, established as close as
possible to the AD7643.

To prevent coupling noise onto the die, avoid radiating noise,
an

d reduce feedthrough:

• Do not run digital lines under the device.

• Run the analog ground plane under the AD7643.

The DVDD supply of the AD7643 can be either a separate
supply

or come from the analog supply, AVDD, or from the
digital interface supply, OVDD. When the system digital supply
is noisy, or fast switching digital signals are present, and no
separate supply is available, it is recommended to connect the
DVDD digital supply to the analog supply AVDD through an
RC filter, and to connect the system supply to the interface
digital supply OVDD and the remaining digital circuitry. Refer

Figure 23 for an example of this configuration. When DVDD

to
is p

owered from the system supply, it is useful to insert a bead

to further reduce high frequency spikes.

The AD7643 has four different ground pins: REFGND, AGND,
D

GND, and OGND. REFGND senses the reference voltage and,
because it carries pulsed currents, should have a low impedance
return to the reference. AGND is the ground to which most
internal ADC analog signals are referenced; it must be connected
with the least resistance to the analog ground plane. DGND
must be tied to the analog or digital ground plane depending on the
configuration. OGND is connected to the digital system ground.

• Shield fast switching signals, like

digital ground to avoid radiating noise to other sections of
the board, and never run them near analog signal paths.

• Avoid crossover of digital and analog signals.

• Run traces on different but close layers of the board, at right

angles to each other, to reduce the effect of feedthrough
through the board.

The power supply lines to the AD7643 should use as large a

race as possible to provide low impedance paths and reduce the

t
effect of glitches on the power supply lines. Good decoupling is
also important to lower the impedance of the supplies presented
to the AD7643, and to reduce the magnitude of the supply
spikes. Decoupling ceramic capacitors, typically 100 nF, should
be placed on each of the power supplies pins, AVDD, DVDD,
and OVDD. The capacitors should be placed close to, and
ideally right up against, these pins and their corresponding
ground pins. Additionally, low ESR 10 μF capacitors should be
located in the vicinity of the ADC to further reduce low
frequency ripple.

CNVST

or clocks, with

The layout of the decoupling of the reference voltage is
important. To minimize parasitic inductances, place the
decoupling capacitor close to the ADC and connect it with
short, thick traces.

EVALUATING THE AD7643 PERFORMANCE

A recommended layout for the AD7643 is outlined in the
documentation of the EVAL-AD7643-CB evaluation board for
th

e AD7643. The evaluation board package includes a fully
assembled and tested evaluation board, documentation, and
software for controlling the board from a PC via the EVAL-

NTROL BRD3

CO

.

Rev. 0 | Page 27 of 28

AD7643

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.30

0.23

0.18
PIN 1

48

INDICATOR

1

BSC SQ

PIN 1
INDICATOR

7.00

0.60 MAX

37

36

0.60 MAX

1.00

0.85

0.80

12° MAX

SEATING
PLANE

TOP

VIEW

Figure 42. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

(BOTTOM VIEW)

25

24

EXPOSED

P

A

D

5.50
REF

6.75

BSC SQ

0.50

0.40

0.30

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

7

mm × 7 mm Body, Very Thin Quad (CP-48-1)

0.20 REF

0.05 MAX

0.02 NOM
COPLANARIT Y

0.08

Dimensions shown in millimeters

0.75

0.60

0.45

0.20

0.09
7°

3.5°
0°

0.08 MAX
COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026-BBC

1.60
MAX

VIEW A

1

12

0.50
BSC

LEAD PITCH

48

13

9.00

BSC SQ

PIN 1

TOP VIEW

(PINS DOWN)

Figure 43. 48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)

Dim

ensions shown in millimeters

5.25

5.10 SQ

4.95

12

13

0.25 MIN

PADDLE CONNECTED TO AGND.
THIS CO NNECT ION I S NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES.

37

36

7.00

BSC SQ

25

24

0.27

0.22

0.17

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7643BCPZ
AD7643BCPZRL
AD7643BSTZ
AD7643BSTZRL
EVAL-AD7643CB
EVAL-CONTROL BRD3

1

Z = Pb-free part.

2

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes.

3

This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators.

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06024–0–4/06(0)

1

1

1

1

2

3

−40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1

−40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1

−40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48

−40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48
Evaluation Board
Controller Board

T

Rev. 0 | Page 28 of 28

TTT