CMOS Dual 8-Bit
a
FEATURES
On-Chip Latches for Both DACs
+12 V to +15 V Operation
DACs Matched to 1%
Four Quadrant Multiplication
TTL/CMOS Compatible from +12 V to +15 V
Latch Free (Protection Schottkys not Required)
APPLICATIONS
Disk Drives
Programmable Filters
X-Y Graphics
Gain/Attenuation
GENERAL DESCRIPTION
The AD7628 is a monolithic dual 8-bit digital/analog converter
featuring excellent DAC-to-DAC matching. It is available in
small 0.3" wide 20-pin DIPs and in 20-terminal surface mount
packages.
Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.
Data is transferred into either of the two DAC data latches via a
common 8-bit TTL/CMOS compatible input port. Control input
DAC A/DAC B determines which DAC is to be loaded.
The AD7628’s load cycle is similar to the write cycle of a random access memory, and the device is bus compatible with most
8-bit microprocessors, including 6502, 6809, 8085, Z80.
The device operates from a +12 V to +15 V power supply and is
TTL-compatible over this range. Power dissipation is a low
20 mW.
Both DACs offer excellent four quadrant multiplication characteristics with a separate reference input and feedback resistor for
each DAC.
Buffered Multiplying DAC
AD7628
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. DAC to DAC matching: since both of the AD7628 DACs
are fabricated at the same time on the same chip, precise
matching and tracking between DAC A and DAC B is inherent. The AD7628’s matched CMOS DACs make a whole
new range of applications circuits possible, particularly in the
audio, graphics and process control areas.
2. Small package size: combining the inputs to the on-chip
DAC latches into a common data bus and adding a
DAC B select line has allowed the AD7628 to be packaged in
a small 20-pin 0.3" wide DIP, 20-pin SOIC, 20-terminal
PLCC and 20-terminal LCC.
3. TTL-Compatibility: All digital inputs are TTL-compatible
over a +12 V to +15 V power supply range.
DAC A/
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1996
AD7628–SPECIFICA TIONS
(V
= +10.8 V to +15.75 V, V
DD
otherwise noted)
REF
A = V
B = +10 V; OUT A = OUT B = 0 V unless
REF
Parameter TA = +258C1to +858C to +1258C
STATIC PERFORMANCE
2
TA = –408CT
= –558C
A
1
Units Test Conditions/Comments
Resolution 8 8 8 Bits
Relative Accuracy ± 1/2 ± 1/2 ± 1/2 LSB max This is an Endpoint Linearity Specification
Differential Nonlinearity ± 1 ± 1 ± l LSB max All Grades Guaranteed Monotonic Over
Full Operating Temperature Range
Gain Error ±2 ±3 ±3 LSB max Measured Using Internal RFB A and RFB B.
Both DAC Latches Loaded with 11111111.
Gain Error is Adjustable Using Circuits
Gain Temperature Coefficient
3
of Figures 4 and 5.
∆Gain/∆Temperature ± 0.0035 ± 0.0035 %/°C max
Output Leakage Current
OUT A (Pin 2) ±50 ±200 ±200 nA max DAC Latches Loaded with 00000000
OUT B (Pin 20) ±50 ±200 ±200 nA max
Input Resistance (V
V
A/V
REF
B Input Resistance
REF
Match ±1 ±1 ±1 % max
DIGITAL INPUTS
Input High Voltage (VIH) 2.4 2.4 2.4 V min
Input Low Voltage (VIL) 0.8 0.8 0.8 V max
Input Current (IIN) ±1 ±10 ±10 µA max VIN = 0 or V
Input Capacitance
DB0–DB7 10 10 10 pF max
A, V
REF
4
B)88 8kΩ min Input Resistance TC = –300 ppm/°C, Typical
REF
15 15 15 kΩ max Input Resistance is 11 kΩ
DD
WR, CS, DACA/DACB 15 15 15 pF max
SWITCHING CHARACTERISTICS
3
See Timing Diagram
Chip Select to Write Set Up Time (tCS) 160 160 210 ns min
Chip Select to Write Hold Time (tCH) 10 10 10 ns min
DAC Select to Write Set Up Time (tAS) 160 160 210 ns min
DAC Select to Write Hold Time (tAH) 10 10 10 ns min
Data Valid to Write Set Up Time (tDS) 160 160 210 ns min
Data Valid to Write Hold Time (tDH) 10 10 10 ns min
Write Pulse Width (tWR) 150 170 210 ns min
POWER SUPPLY See Figure 3
IDD, K Grade 2 2 mA All Digital Inputs VIL or V
B, T Grades 2 2.5 2.5 mA All Digital Inputs VIL or V
All Grades 100 500 500 µA All Digital Inputs 0 V or V
IH
IH
DD
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance only and are not
subject to test. VDD = +10.8 V to +15.75 V. (Measured Using Recommended PC Board Layout (Figure 7) and AD644 as Output Amplifiers)
TA = –408CT
Parameter TA = +258C1to +858C
DC SUPPLY REJECTION
(∆GAIN/∆VDD) 0.01 0.02 0.02 % per % max ∆V
1
CURRENT SETTLING TIME 350 400 400 ns max To 1/2 LSB OutA/OutB Load = 100 Ω.
DIGITAL-TO-ANALOG GLITCH
IMPULSE 330 nV sec typ For Code Transition 00000000 to 11111111
OUTPUT CAPACITANCE
C
A 25 25 25 pF max DAC Latches Loaded with 00000000
OUT
C
B 25 25 25 pF max
OUT
C
A 60 60 60 pF max DAC Latches Loaded with 11111111
OUT
C
B 60 60 60 pF max
OUT
AC FEEDTHROUGH
V
A to OUT A –70 –65 –65 dB max V
REF
V
B to OUT B –70 –65 –65 dB max @ 10 kHz
REF
CHANNEL-TO-CHANNEL ISOLATION Both DAC Latches Loaded with 11111111.
V
A to OUT B –80 dB typ V
REF
V
B to OUTA –80 dB typ V
REF
DIGITAL CROSSTALK 60 nV sec typ Measured for Code Transition 00000000
HARMONIC DISTORTION –85 dB typ VIN = 6 V rms @ 1 kHz
NOTES
1
Temperature Ranges are K Version; –40°C to +85°C; B Version; –40 °C to +85 °C; T Version; –55 °C to +125 °C.
2
Specification applies to both DACs in AD7628.
3
Guaranteed by design but not production tested.
4
Logic inputs are MOS Gates. Typical input current (+25°C) is less than 1 nA.
Specifications subject to change without notice.
= –558C
A
to +1258πC1Units Test Conditions/Comments
= ±5%
DD
WR = CS = 0 V.
DB0–DB7 = 0 V to VDD or VDD to 0 V
A, V
REF
REF
V
REF
REF
V
REF
B = 20 V p-p Sine Wave
REF
A = 20 V p-p Sine Wave @ 10 kHz
B = 0 V See Figure 6.
B = 20 V p-p Sine Wave @ 10 kHz
A = 0 V See Figure 6.
to 11111111
–2–
REV. A
AD7628
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V
DD
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . V
Digital Input Voltage to DGND . . . . . . –0.3 V, V
V
, V
to AGND . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
PIN20
B to AGND . . . . . . . . . . . . . . . . . . . . . . .±25 V
REF
B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V
RFB
V
V
PIN2
REF
RFB
A, V
A, V
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
DD
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial (K) Grades . . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B) Grades . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T) Grades . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
ORDERING GUIDE
Temperature Relative Gain Package
1
Model
Range Accuracy Error Option
AD7628KN –40°C to +85°C ±1/2 LSB ±2 LSB N-20
AD7628KP –40°C to +85°C ±1/2 LSB ±2 LSB P-20A
AD7628KR –40°C to +85°C ±1/2 LSB ±2 LSB R-20
AD7628BQ –40°C to +85°C ±1/2 LSB ±2 LSB Q-20
AD7628TQ –55°C to +125° C ±1/2 LSB ±2 LSB Q-20
AD7628TE –55°C to +125°C ±1/2 LSB ±2 LSB E-20A
NOTES
1
To order MIL-STD-883, Class B process parts, add /883B to part number.
Contact your local sales office for military data sheet.
2
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = SOIC.
TERMINOLOGY
Relative Accuracy:
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after adjusting for zero and full-scale, and is normally expressed in
LSBs or as a percentage of full-scale reading.
Differential Nonlinearity:
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB max over
the operating temperature range ensures monotonicity.
Gain Error:
Gain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC latches after offset error has been adjusted out. Gain
error of both DACs is adjustable to zero with external resistance.
Output Capacitance:
Capacitance from OUT A or OUT B to AGND.
Digital-to-Analog Glitch Impulse:
2
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs,
depending upon whether the glitch is measured as a current or
voltage signal. Glitch impulse is measured with V
REF
A, V
= AGND.
Channel-to-Channel Isolation:
The proportion of input signal from one DAC’s reference input
that appears at the output of the other DAC, expressed as a
ratio in dB.
Digital Crosstalk:
The glitch energy transferred to the output of one converter due
to a change in digital input code to the other converter. Specified in nV secs.
REF
B
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7628 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
DIP, SOIC
1
AGND
2
OUT A
3
RFB A
4
A
V
REF
DGND
DAC A/DAC B
(MSB) DB7
DB6 DB1
DB5
DB4
AD7628
5
6
(Not to Scale)
7
813
912
10 11
TOP VIEW
20
19
18
17
16
15
14
OUT B
RFB B
V
B
REF
V
DD
WR
CS
DB0 (LSB)
DB2
DB3
V
REF
DGND
DAC A /DAC B
DB7 (MSB)
DB6
PIN CONFIGURATIONS
LCCC
A
4
5
6
7
8
OUT A
RFB A
AD7628
TOP VIEW
(Not to Scale)
DB5
DB4
AGND
12 1391110
DB3
OUT B
1931220
DB2
RFB B
DB1
18
V
17
V
16
WR
CS
15
14
DB0 (LSB)
REF
DD
–3–
B
V
REF
DGND
DAC A/DAC B
DB7 (MSB)
DB6
PLCC
OUT A
OUT B
AGND
DB3
RFB B
19312 20
V
B
18
REF
V
17
DD
WR
16
CS
15
DB0 (LSB)
14
12 1391110
DB1
DB2
RFB A
A
4
5
AD7628
6
TOP VIEW
(Not to Scale)
7
8
DB5
DB4
AD7628
INTERFACE LOGIC INFORMATION
DAC Selection
Both DAC latches share a common 8-bit input port. The control input
DAC A/DAC B selects which DAC can accept data
from the input port.
Mode Selection
Inputs CS and WR control the operating mode of the selected
DAC. See Mode Selection Table below.
Write Mode
When CS and WR are both low, the selected DAC is in the write
mode. The input data latches of the selected DAC are transparent and its analog output responds to activity on DB0–DB7.
Hold Mode
The selected DAC latch retains the data that was present on
DB0–DB7 just prior to
CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches.
Mode Selection Table
DAC A/
DAC B CS WR DAC A DAC B
L L L WRITE HOLD
H L L HOLD WRITE
X H X HOLD HOLD
X X H HOLD HOLD
L = Low State, H = High State, X = Don’t Care
WRITE CYCLE TIMING DIAGRAM
weighted currents are switched between the DAC output and
AGND, thus maintaining fixed currents in each ladder leg independent of switch state.
EQUIVALENT CIRCUIT ANALYSIS
Figure 2 shows an approximate equivalent circuit for one of
the AD7628’s D/A converters, in this case DAC A. A similar
equivalent circuit can be drawn for DAC B. Note that AGND
(Pin 1) is common for both DAC A and DAC B.
The current source I
LEAKAGE
is composed of surface and junction leakages and, as with most semiconductor devices, approximately doubles every 10°C. The resistor Ro, as shown in Figure 2, is the equivalent output resistance of the device, which
varies with input code (excluding all 0s code) from 0.8R to 2R.
R is typically 11 kΩ. C
is the capacitance due to the N-channel
OUT
switches and varies from about 50 pF to 120 pF, depending on
the digital input. g(V
age generator due to the reference input voltage V
A, N) is the Thevenin equivalent volt-
REF
A and the
REF
transfer function of the R-2R ladder.
For further information on CMOS multiplying D/A converters,
refer to “CMOS DAC Application Guide, 2ND Edition” available from Analog Devices, Publication Number G872a–15–4/86.
Figure 2. Equivalent Analog Output Circuit of DAC A
CIRCUIT INFORMATION—D/A SECTION
The AD7628 contains two identical 8-bit multiplying D/A converters, DAC A and DAC B. Each DAC consists of a highly
stable thin film R-2R ladder and eight N-channel current steering
switches. A simplified D/A circuit for DAC A is shown in Figure
1. An inverted R-2R ladder structure is used; that is, binary
CIRCUIT INFORMATION–DIGITAL SECTION
The input buffers are simple CMOS level-shifters designed so
that when the AD7628 is operated with V
from 10.8 V to
DD
15.75 V, the buffer converts TTL input levels (2.4 V and 0.8 V)
into CMOS logic levels. When V
is in the region of 1.0 volt to
IN
2.0 volts, the input buffers operate in their linear region and
pass a quiescent current (see Figure 3). To minimize power supply currents, it is recommended that the digital input voltages be as
close to the supply rails (V
and DGND) as practicably possible.
DD
The AD7628 may be operated with any supply voltage in the
range 10.8 ≤ V
≤ 15.75 volts.
DD
Figure 1. Simplified Functional Circuit for DAC A
Figure 3. Typical Plot of Supply Current, IDD vs. Logic
Input Voltage V
to VDD = +15 V
IN
–4–
REV. A
Figure 4. Dual DAC Unipolar Binary Operation (2 Quadrant Multiplication). See Table I.
AD7628
Figure 5. Dual DAC Bipolar Operation (4 Quadrant Multiplication). See Table II.
Table I. Unipolar Binary Code Table
DAC Latch Contents Analog Output
MSB LSB (DAC A or DAC B)
255
–V
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
NOTE: 1 LSB = (2–8)(VIN) =
1
V
()
IN
256
IN
256
–V
–V
–V
–V
–V
129
IN
256
128
IN
256
127
IN
256
IN
256
IN
256
V
IN
= –
2
1
0
= 0
Table III. Recommended Trim Resistor Values
Trim
Resistor K/B/T
Table II. Bipolar (Offset Binary) Code Table
DAC Latch Contents Analog Output
MSB LSB (DAC A or DAC B)
127
+V
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
IN
128
+V
1
IN
128
1 0 0 0 0 0 0 0 0
1
–V
IN
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
NOTE: 1 LSB = (2–7)(VIN) =
1
V
()
IN
128
–V
–V
128
127
IN
128
128
IN
128
REV. A
R1; R3 500
R2; R4 150
–5–
AD7628
APPLICATIONS INFORMATION
Application Hints
To ensure system performance consistent with AD7628 specifications, careful attention must be given to the following points:
1. GENERAL GROUND MANAGEMENT: AC or transient
voltages between the AD7628 AGND and DGND can cause
noise injection into the analog output. The simplest method
of ensuring that voltages at AGND and DGND are equal is
to tie AGND and DGND together at the AD7628. In more
omplex systems where the AGND–DGND intertie is on the
backplane, it is recommended that diodes be connected in
inverse parallel between the AD7628 AGND and DGND
pins (1N914 or equivalent).
2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a
code-dependent output resistance which, in turn, causes a
code-dependent amplifier noise gain. The effect is a codedependent differential nonlinearity term at the amplifier
output that depends on V
(VOS is amplifier input offset
OS
voltage). This differential nonlinearity term adds to the R/2R
differential nonlinearity. To maintain monotonic operation, it
is recommended that amplifier V
be no greater than 10% of
OS
1 LSB over the temperature range of interest.
3. HIGH FREQUENCY CONSIDERATIONS: The output
capacitance of a CMOS DAC works in conjunction with the
amplifier feedback resistance to add a pole to the open loop
response. This can cause ringing or oscillation. Stability can
be restored by adding a phase compensation capacitor in
parallel with the feedback resistor.
Figure 7 shows a printed circuit layout for the AD7628 and the
AD644 dual op amp, which minimizes feedthrough and crosstalk.
SINGLE SUPPLY APPLICATIONS
The AD7628 DAC R-2R ladder termination resistors are connected to AGND within the device. This arrangement is particularly convenient for single supply operation because AGND
may be biased at any voltage between DGND and V
. Figure
DD
8 shows a circuit that provides two +5 V to +8 V analog outputs
by biasing AGND +5 V up from DGND. The two DAC reference inputs are tied together and a reference input voltage is obtained without a buffer amplifier by making use of the constant
and matched impedances of the DAC A and DAC B reference
inputs. Current flows through the two DAC R-2R ladders into
R1, and R1 is adjusted until the V
A and V
REF
B inputs are
REF
at +2 V. The two analog output voltages range from +5 V to
+8 V for DAC codes 00000000 to l l l l l l l l .
DYNAMIC PERFORMANCE
The dynamic performance of the two DACs in the AD7628 will
depend on the gain and phase characteristics of the output amplifiers, together with the optimum choice of the PC board layout and decoupling components. Figure 6 shows the relationship
between input frequency and channel-to-channel isolation.
Figure 6. Channel-to-Channel Isolation
Figure 8. AD7628 Single Supply Operation
Figure 9 shows DAC A of the AD7628 connected in a positive
reference, voltage switching mode. This configuration is useful
because V
operation. However, to retain specified linearity, V
is the same polarity as VIN, allowing single supply
OUT
must be in
IN
the range 0 V to +2.5 V and the output buffered or loaded with
a high impedance (see Figure 10). Note that the input voltage is
connected to the DAC OUT A, and the output voltage is taken
from the DAC V
Figure 9. AD7628 Single Supply, Voltage Switching Mode
REF
A pin.
Figure 7. Suggested PC Board Layout for AD7628 with
AD644 Dual Op Amp
Figure 10. Typical AD7628 Performance in Single Supply
Voltage Switching Mode
–6–
REV. A
MICROPROCESSOR INTERFACE
Figure 11. AD7628 Dual DAC to 6800 CPU Interface
PROGRAMMABLE WINDOW COMPARATOR
AD7628
Figure 12. AD7628 Dual DAC to 8085 CPU Interface
In the circuit of Figure 13, the AD7628 is used to implement a
programmable window comparator. DACs A and B are loaded
with the required upper and lower voltage limits for the test,
respectively. If the test input is not within the programmed limits, the pass/fail output will indicate a fail (logic zero).
Figure 13. Digitally Programmable Window Comparator
(Upper and Lower Limit Detector)
PROGRAMMABLE STATE VARIABLE FILTER
Figure 14. Digitally Controlled State Variable Filter
In this state, variable or universal filter configuration (Figure
14) for DACs A1 and B1 control the gain and Q of the filter
characteristic, while DACs A2 and B2 control the cutoff frequency, f
expression for f
. DACs A2 and B2 must track accurately for the simple
C
to hold. This is readily accomplished by the
C
AD7628. Op amps are 2 × AD644. C3 compensates for the
effects of op amp gain-bandwidth limitations.
CIRCUIT EQUATIONS
C1 = C2, R1 = R2, R4 = R
fC =
Q =
AO = –
NOTE
DAC equivalent resistance equals
1
π
R1C
2
1
R
R
3
F
.
R
R
4
FBB1
R
F
R
S
256 × DAC Ladder resistance
()
DAC Digital Code
5
The filter provides low pass, high pass and band pass outputs
and is ideally suited for applications where microprocessor control of filter parameters is required, e.g., equalizer, tone controls, etc.
Programmable range for component values shown is f
= 0 kHz
C
to 15 kHz and Q = 0.3 to 4.5.
REV. A
–7–
AD7628
DIGITALLY CONTROLLED DUAL TELEPHONE ATTENUATOR
In this configuration, the AD7628 functions as a 2-channel
digitally controlled attenuator; ideal for stereo audio and telephone signal level control applications. Table IV gives input
codes vs. attenuation for a 0 dB to 15.5 dB range.
Input Code = 256 × 10 exp
Attenuation, dB
−
20
Figure 15. Digitally Controlled Dual Telephone Attenuator
MECHANICAL INFORMATION
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Pin Cerdip (Q Suffix)
C1029a–8–3/88
20-Pin Plastic DIP (N Suffix)
Table IV. Attenuation vs. DAC A, DAC B Code for the
Circuit of Figure 15
DAC Input Code in DAC Input Code in
Attn. dB Code Decimal Attn. dB Code Decimal
0.0 1 1 1 1 1 1 1 1 255 8.0 0 1 1 0 0 1 1 0 102
0.5 1 1 1 1 0 0 1 0 242 8.5 0 1 1 0 0 0 0 0 96
1.0 1 1 1 0 0 1 0 0 228 9.0 0 1 0 1 1 0 1 1 91
1.5 1 1 0 1 0 1 1 1 215 9.5 0 1 0 1 0 1 1 0 86
2.0 1 1 0 0 1 0 1 1 203 10.0 0 1 0 1 0 0 0 1 81
2.5 1 1 0 0 0 0 0 0 192 10.5 0 1 0 0 1 1 0 0 76
3.0 1 0 1 1 0 1 0 1 181 11.0 0 1 0 0 1 0 0 0 72
3.5 1 0 1 0 1 0 1 1 171 11.5 0 1 0 0 0 1 0 0 68
4.0 1 0 1 0 0 0 1 0 162 12.0 0 1 0 0 0 0 0 0 64
4.5 1 0 0 1 1 0 0 0 152 12.5 0 0 1 1 1 1 0 1 61
5.0 1 0 0 1 0 0 0 0 144 13.0 0 0 1 1 1 0 0 1 57
5.5 1 0 0 0 1 0 0 0 136 13.5 0 0 1 1 0 1 1 0 54
6.0 1 0 0 0 0 0 0 0 128 14.0 0 0 1 1 0 0 1 51
6.5 0 1 1 1 0 0 1 121 14.5 0 0 1 1 0 0 0 0 48
7.0 0 1 1 1 0 0 1 0 114 15.0 0 0 1 0 1 1 1 0 46
7.5 0 1 1 0 1 1 0 0 108 15.5 0 0 1 0 1 0 1 1 43
20-Terminal
Leadless Chip
Carrier (E Suffix)
20-Terminal
Plastic Leaded
Chip Carrier (P Suffix)
PRINTED IN U.S.A.
–8–
REV. A
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