Datasheet ad7625 Datasheet (ANALOG DEVICES)

16-Bit, 6 MSPS, PulSAR

V

FEATURES

Throughput: 6 MSPS
SNR: 93 dB
INL: ±0.45 LSB typical, ±1 LSB maximum
DNL: ±0.3 LSB typical, ±0.5 LSB maximum
Power dissipation: 135 mW
32-lead LFCSP (5 mm × 5 mm)
SAR architecture

No latency/no pipeline delay
16-bit resolution with no missing codes
Zero error: ±1.5 LSB
Differential input voltage: ±4.096 V
Serial LVDS interface

Self-clocked mode

Echoed-clock mode

Can use LVDS or CMOS for conversion control (CNV signal)
Reference options

Internal: 4.096 V

External (1.2 V) buffered to 4.096 V

External: 4.096 V

APPLICATIONS

High dynamic range telecommunications
Receivers
Digital imaging systems
High speed data acquisition
Spectrum analysis
Test equipment

Differential ADC

AD7625

FUNCTIONAL BLOCK DIAGRAM

CAP
DAC

CM

÷2

SAR

CLOCK

Figure 1.

LOGIC

SERIAL

LVDS

VIO

CNV+, CNV–

D+, D–

DCO+, DCO–

CLK+, CLK–

REFIN REF

1.2V

BAND GAP

IN+

IN–

AD7625

GENERAL DESCRIPTION

The AD7625 is a 16-bit, 6 MSPS, charge redistribution successive
approximation register (SAR) based architecture analog-to-digital
converter (ADC). SAR architecture allows unmatched perfor­mance both in noise (93 dB SNR) and in linearity (1 LSB). The
AD7625 contains a high speed, 16-bit sampling ADC, an internal
conversion clock, and an internal buffered reference. On the
CNV± rising edge, it samples the voltage difference between the
IN+ and IN− pins. The voltages on these pins swing in opposite
phase between 0 V and REF. The 4.096 V reference voltage, REF,
can be generated internally or applied externally.

All converted results are available on a single LVDS self-clocked
or echoed-clock serial interface, reducing external hardware
connections.

The AD7625 is housed in a 32-lead, 5 mm × 5 mm LFCSP with
operation specified from −40°C to +85°C.

7652-001

Table 1. Fast PulSAR® ADC Selection

Input Type Resolution (Bits) 1 MSPS to <2 MSPS 2 MSPS to 3 MSPS 6 MSPS

Differential (Ground Sense) 16 AD7653
16 AD7667
16 AD7980
16 AD7983
True Bipolar 16 AD7671
Differential (Antiphase) 16 AD7677 AD7621 AD7625
16 AD7623 AD7622
18 AD7643 AD7641
18 AD7982
18 AD7984

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

AD7625

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 12

Theory of Operation ...................................................................... 13

Circuit Information .................................................................... 13

Converter Information .............................................................. 13

Transfer Functions ..................................................................... 14

Analog Inputs ............................................................................. 14

Typical Connection Diagram ................................................... 15

Driving the AD7625 ................................................................... 16

Voltage Reference Options ........................................................ 17

Power Supply ............................................................................... 18

Digital Interface .......................................................................... 19

Applications Information .............................................................. 21

Layout, Decoupling, and Grounding ....................................... 21

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 22

REVISION HISTORY

1/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD7625

SPECIFICATIONS

VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.5 V; REF = 4.096 V; all specifications T

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

RESOLUTION 16 Bits
ANALOG INPUT

Voltage Range V

Operating Input Voltage V

− V

IN+

IN+

−V

IN−

, V

to GND −0.1 V

IN−

Common-Mode Input Range V

Common-Mode Rejection Ratio fIN = 1 MHz 60 dB

Input Current Midscale input 77 µA

THROUGHPUT

Complete Cycle 166 ns

Throughput Rate 0.1 6 MSPS

DC ACCURACY

Integral Linearity Error −1 ±0.45 +1 LSB

No Missing Codes 16 Bits

Differential Linearity Error −0.5 ±0.3 +0.5 LSB

Transition Noise 0.6 LSB

Zero Error T

MIN

to T

−4 ±1.5 +4 LSB

MAX

Zero Error Drift 0.5 ppm/°C

Gain Error T

MIN

to T

8 20 LSB

MAX

Gain Error Drift 0.4 ppm/°C

Power Supply Sensitivity

1

VDD1 = 5 V ± 5% 0.4 LSB

VDD2 = 2.5 V ± 5% 0.2 LSB
AC ACCURACY

External Reference fIN = 20 kHz

Dynamic Range 92.5 93.2 dB
Signal-to-Noise Ratio 92 93 dB
Spurious-Free Dynamic Range 106 dB
Total Harmonic Distortion −105.5 dB
Signal-to-(Noise + Distortion) 91.5 92 dB

Internal Reference fIN = 20 kHz

Dynamic Range 92.5 93.2 dB
Signal-to-Noise Ratio 91.5 92.9 dB
Spurious-Free Dynamic Range 106 dB
Total Harmonic Distortion −105.5 dB
Signal-to-(Noise + Distortion) 91 92.5 dB

−3 dB Input Bandwidth 100 MHz

Aperture Jitter 0.25 ps rms

INTERNAL REFERENCE

Output Voltage REFIN @ 25°C 1.2 V

Temperature Drift −40°C to +85°C ±15 ppm/°C

REFERENCE BUFFER

REFIN Input Voltage Range 1.2 V

REF Output Voltage Range 4.076 4.096 4.116 V

Line Regulation VDD1 ± 5%, VDD2 ± 5% 5 mV

EXTERNAL REFERENCE

Voltage Range REF 4.096 V

VCM PIN @ 25°C

Output Voltage REF/2 V

Output Impedance 4 5 6 kΩ

MIN

to T

REF

REF

, unless otherwise noted.

MAX

+V

/2 − 0.05 V

/2 V

REF

V

REF

+ 0.1 V

REF

/2 + 0.05 V

REF

Rev. 0 | Page 3 of 24

AD7625

Parameter Test Conditions/Comments Min Typ Max Unit

LVDS I/O (ANSI-644)

Data Format Serial LVDS twos complement
Differential Output Voltage, VOD R
Common-Mode Output Voltage, V

OCM

Differential Input Voltage, VID 100 650 mV
Common-Mode Input Voltage, V

ICM

POWER SUPPLIES

Specified Performance

VDD1 4.75 5 5.25 V
VDD2 2.37 2.5 2.63 V
VIO 2.37 2.5 2.63 V

Operating Currents

Static—Not Converting

VDD1 4.5 7.8 mA
VDD2 17 22.7 mA
VIO

With Internal Reference 6 MSPS throughput

VDD1 11 15.4 mA
VDD2 21.5 28.3 mA
VIO

Without Internal Reference 6 MSPS throughput

VDD1 9 12.1 mA
VDD2 21 26 mA
VIO

Power Dissipation

3

Static—Not Converting 95 130 mW
With Internal Reference 6 MSPS throughput 145 190 mW
Without Internal Reference 6 MSPS throughput 135 165 mW

Energy per Conversion 6 MSPS throughput 22 nJ/sample

TEMPERATURE RANGE

Specified Performance T

1

Using an external reference.

2

The ANSI-644 LVDS specification has a minimum output common mode (V

3

Power dissipation is for the AD7625 device only. In self-clocked interface mode, 9 mW is dissipated in the 100 Ω terminator. In echoed-clock interface mode, 18 mW is

dissipated in two 100 Ω terminators.

= 100 Ω 200 350 454 mV

L

2

R

= 100 Ω 850 1250 1375 mV

L

800 1575 mV

Self-clocked mode and echoed-

11 13 mA

clock mode

Self-clocked mode and echoed-

13.5 16 mA

clock mode

Self-clocked mode and echoed-

13.5 16 mA

clock mode

to T

MIN

−40 +85 °C

MAX

) of 1125 mV.

OCM

Rev. 0 | Page 4 of 24

AD7625

TIMING SPECIFICATIONS

VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications T

Table 3.

Parameter Symbol Min Typ Max Unit

Time Between Conversions
Acquisition Time t
CNV± High Time t
CNV± to D± (MSB) Delay t
CNV± to Last CLK± (LSB) Delay t
CLK± Period

2

t

CLK± Frequency f
CLK± to DCO± Delay (Echoed-Clock Mode) t
DCO± to D± Delay (Echoed-Clock Mode) t
CLK± to D± Delay t

1

The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of t

2

For the minimum CLK period, the window available to read data is t

mode, n = 16; in self-clocked interface mode, n = 18.

1

t

CYC

ACQ

CNVH

MSB

CLKL

CLK

CLK

DCO

D

CLKD

CYC

− t

166 10,000 ns
40 ns
10 40 ns
145 ns
110 ns
(t

− t

CYC

MSB

250 300 MHz
0 4 7 ns
0 1 ns
0 4 7 ns

+ t

. Divide this time by the number of bits (n) that are read. In echoed-clock interface

MSB

CLK

to T

MIN

+ t

)/n 4 3.33 ns

CLK

, unless otherwise noted.

MAX

, the subsequent conversion result is invalid.

CYC

Rev. 0 | Page 5 of 24

AD7625

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Analog Inputs/Outputs

IN+, IN− to GND1

−0.3 V to REF + 0.3 V or

±130 mA
REF2 to GND −0.3 V to +6 V
VCM, CAP2 to GND −0.3 V to +6 V
CAP1, REFIN to GND −0.3 V to +2.7 V

Supply Voltage

VDD1 −0.3 V to +6 V
VDD2, VIO −0.3 V to +3 V

Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Input Current to Any Pin Except

Supplies

3

Operating Temperature Range

±10 mA

−40°C to +85°C

(Commercial)

Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
ESD 1 kV

1

See the Analog Inputs section.

2

Keep CNV+/CNV− low for any external REF voltage > 4.3 V applied

to the REF pin.

3

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type θJA θ

Unit

JC

32-Lead LFCSP_VQ 40 4 °C/W

ESD CAUTION

Rev. 0 | Page 6 of 24

AD7625

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

P2

F

REF

GND

RE

REF

CA

GND

CAP2

CAP2

29

28

27

26

31

30

32

25

VDD1

1
2
3
4
5
6
7
8

PIN 1
INDICATOR

AD7625

TOP VIEW

(Not to Scale)

9

11

10

12

D–

D+

VIO

CNV+

13

14

15

GND

DCO–

DCO+

VDD2
CAP1

REFIN

EN0

EN1
VDD2
CNV–

NOTES

1. CONNECT T HE EXPOSED P AD TO THE G ROUND
PLANE OF T HE PCB USING MULTIPLE VIAS.

GND

24

IN+

23

IN–

22

VCM

21

VDD1

20

VDD1

19

VDD2

18

CLK+

17

16

CLK–

07652-002

Figure 2.

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type

1

Description

1 VDD1 P Analog 5 V Supply. Decouple the 5 V supply with a 100 nF capacitor.
2 VDD2 P

Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor. The 2.5 V supply source should

supply this pin first and then be traced to the other VDD2 pins (Pin 7 and Pin 18).
3 CAP1 AO Connect this pin to a 10 nF capacitor.
4 REFIN AI/O

Prebuffer Reference Voltage. When using the internal reference, this pin outputs the band gap voltage

and is nominally at 1.2 V. It can be overdriven with an external reference voltage such as the ADR280.

In either internal or external reference mode, a 10 F capacitor is required. If using an external 4.096 V

reference (connected to REF), this pin is a no connect and does not require any capacitor.
5, 6 EN0, EN1 DI Enable Pins. The logic levels of these pins set the operation of the device as follows:

EN1 = 0, EN0 = 0: Illegal state.

EN1 = 0, EN0 = 1: Enable internal buffer, disable internal reference. An external 1.2 V reference

connected to the REFIN pin is required.

EN1 = 1, EN0 = 0: Disable internal reference and reference buffer. An external 4.096 V reference

connected to the REF pin is required.

EN1 = 1, EN0 = 1: Enable internal reference and reference buffer.
7 VDD2 P Digital 2.5 V Supply. Decouple this pin with a 100 nF capacitor.
8, 9 CNV−, CNV+ DI

Convert Input. These pins act as the conversion control pin. On the rising edge of these pins, the

analog inputs are sampled and a conversion cycle is initiated. CNV+ works as a CMOS input when

CNV− is grounded; otherwise, CNV+ and CNV− are differential LVDS inputs.
10, 11 D−, D+ DO LVDS Data Outputs. The conversion data is output serially on these pins.
12 VIO P Input/Output Interface Supply. Use a 2.5 V supply and decouple this pin with a 100 nF capacitor.
13 GND P Ground. Return path for the 100 nF capacitor connected to Pin 12.
14, 15 DCO−, DCO+ DO

LVDS Buffered Clock Outputs. When DCO+ is grounded, the self-clocked interface mode is selected.

In this mode, the 16-bit results on D± are preceded by a 2-bit header (10) to allow synchronization of

the data by the digital host with simple logic. When DCO+ is not grounded, the echoed-clock inter-

face mode is selected. In this mode, DCO± is a copy of CLK±. The data bits are output on the falling

edge of DCO+ and can be latched in the digital host on the next rising edge of DCO+.
16, 17 CLK−, CLK+ DI LVDS Clock Inputs. This clock shifts out the conversion results on the falling edge of CLK+.
18 VDD2 P Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor.
19, 20 VDD1 P

Analog 5 V Supply. Isolate these pins from Pin 1 with a ferrite bead and decouple them with a 100 nF

capacitor.
21 VCM AO

Common-Mode Output. When using any reference scheme, this pin produces one-half the voltage

present on the REF pin, which can be useful for driving the common mode of the input amplifiers.
22 IN− AI Differential Negative Analog Input. Referenced to and must be driven 180° out of phase with IN+.
23 IN+ AI Differential Positive Analog Input. Referenced to and must be driven 180° out of phase with IN−.
24 GND P Ground.

Rev. 0 | Page 7 of 24

AD7625

Pin No. Mnemonic Type

25, 26, 28 CAP2 AO

1

Description

Connect all three CAP2 pins together and decouple them with the shortest trace possible to a single

10 F, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 27 (GND).
27 GND P Ground. Return path for the 10 F capacitor connected to Pin 25, Pin 26, and Pin 28.
29, 30, 32 REF AI/O

Buffered Reference Voltage. When using the internal reference or the 1.2 V external reference (REFIN

input), the 4.096 V system reference is produced at this pin. When using an external reference, such

as the ADR434 or the ADR444, the internal reference buffer must be disabled. In either case, connect

all three REF pins together and decouple them with the shortest trace possible to a single 10 F, low

ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 31 (GND).
31 GND P Ground. Return path for the 10 F capacitor connected to Pin 29, Pin 30, and Pin 32.
EP Exposed Pad

The exposed pad is located on the underside of the package. Connect the exposed pad to the

ground plane of the PCB using multiple vias. See the Exposed Paddle section for more information.

1

AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DO = digital output; P = power.

Rev. 0 | Page 8 of 24

AD7625

TYPICAL PERFORMANCE CHARACTERISTICS

0

–20

–40

–60

–80

–100

AMPLI TUDE (d B)

–120

–140

–160

–180

0 0.5 1.0 1.5 2.0 2.5 3.0

FREQUENCY (MHz )

Figure 3. FFT 2 kHz Input Tone, Full View

07652-005

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 5 10 15 20 25 30 35 40 45

FREQUENCY (kHz)

INPUT TO NE = 2kHz

SNR = 93.16dB
SINAD = 92.09d B
THD = –110.45dB

SFDR = 111.37d B

Figure 6. FFT 2 kHz Input Tone, Zoom In on Input Tone and Harmonics

07652-006

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 0. 5 1.0 1.5 2.0 2.5 3. 0

FREQUENCY (MHz)

INPUT TO NE = 50kHz

SNR = 93.04dB
SINAD = 92.63dB
THD = –103.57d B

SFDR = –102.69dB

Figure 4. FFT 50 kHz Input Tone

0.5

0.4

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 16,384 32,768 49,152 65,536

CODE

Figure 5. Differential Nonlinearity vs. Code

07652-007

07652-015

0

–20

–40

–60

–80

–100

AMPLITUDE (dB)

–120

–140

–160

–180

0 0. 5 1.0 1.5 2.0 2.5 3.0

FREQUENCY (MHz)

INPUT TO NE = 100kHz

SNR = 92.91dB

SINAD = 92.55dB

THD = –103.11d B

SFDR = –103.41dB

Figure 7. FFT 100 kHz Input Tone

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 16,384 32,768 49, 152 65,536

CODE

Figure 8. Integral Nonlinearity vs. Code

07652-008

07652-014

Rev. 0 | Page 9 of 24

AD7625

–

–

94

–96

–98

–100

–102

–104

–106

THD (dB)

–108

–110

–112

–114

–116

0 20 40 60 80 100 120

–1dBFS

INPUT FREQ UENCY (kHz)

–0.5dBFS

–3dBFS

–10dBFS

–5dBFS

07652-012

Figure 9. THD at Input Amplitudes of −0.5 dBFS to −10 dBFS vs. Frequency

100.5

–101.0

–101.5

–102.0

THD (dB)

–102.5

–103.0

–103.5

–60 –40 –20 0 20 40 60 80 100 120

INTERNAL REF

EXTERNAL REF

TEMPERATURE ( °C)

Figure 12. THD vs. Temperature (−0.5 dB, 20 kHz Input Tone)

07652-021

93.8

93.6

93.4

93.2

93.0

92.8

92.6

SNR, DYNAMIC RANGE ( dB)

92.4

92.2

SNR vs. TEMP EXTERNAL REF
SNR vs. TEMP I NTERNAL REF

–60 –40 –20 0 20 40 60 80 100 120

DYNR vs. TEMP I NTERNAL REF
DYNR vs. TEMP EXTERNAL REF

TEMPERATURE ( °C)

Figure 10. Dynamic Range and SNR vs. Temperature

(−0.5 dB, 20 kHz Input Tone)

120

100

80

60

40

20

0

INPUT CURRENT (µ A)

–20

–40

–60

–4–6 –2 0 2 4 6

DIFFERENTIAL INPUT VOLTAGE (V)

IN+

IN–

Figure 11. Input Current (IN+, IN−) vs. Differential Input Voltage (6 MSPS)

93.2

93.0

92.8

92.6

92.4

SINAD (dB)

92.2

92.0

91.8

91.6

07652-018

SINAD vs. TEMP INTERNAL RE F

–60 –40 –20 0 20 40 60 80 100 120

SINAD vs. TEMP EXTERNAL REF

TEMPERATURE (° C)

07652-019

Figure 13. SINAD vs. Temperature

(−0.5 dB, 20 kHz Input Tone)

12

10

8

6

4

2

ZERO ERROR AND GAIN ERROR (LSB)

0

–60 –40 –20 0 20 40 60 80 100 120

07652-010

GAIN ERROR

ZERO ERROR

TEMPERATURE (° C)

07652-020

Figure 14. Zero Error and Gain Error vs. Temperature

Rev. 0 | Page 10 of 24

AD7625

250,000

200,000

150,000

262,144 SAMPLES
STD DEVIATI ON = 0.4829

201,320

140,000

120,000

100,000

80,000

128,084

129,601

262,144 SAMPLES
STD DEVIATI ON = 0 .5329

COUNT

100,000

50,000

0

0

FEC7 FEC8 FEC9 FECA F ECB FECC F ECD

30,651

54

CODE (HEX)

Figure 15. Histogram of 262,144 Conversions of a DC Input

at the Code Center (Internal Reference)

250,000

200,000

150,000

COUNT

100,000

50,000

41

0

0

FEC8 FEC9 FECA FECB FECC FECD FECE

201,614

30,206

CODE (HE X)

Figure 16. Histogram of 262,144 Conversions of a DC Input

at the Code Center (External Reference)

30,073

46

262,144 SAMPLES
STD DEVIATION = 0.4814

30,250

33

60,000

COUNT

40,000

20,000

2130

0

07652-022

00

0

FEC6 FEC7 FEC8 FEC9 FECA FECB

CODE (HEX)

2329

07652-023

Figure 17. Histogram of 262,144 Conversions of a DC Input

at the Code Transition (Internal Reference)

0

07652-024

Rev. 0 | Page 11 of 24

AD7625

TERMINOLOGY

Common-Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of an 80 mV p-p sine wave
applied to the common-mode voltage of V
frequency f

.

S

CMRR (dB) = 10log(Pf/Pf

)

S

IN+

and V

IN−

at

where:

Pf is the power at frequency f in the ADC output.
Pf

is the power at frequency fS in the ADC output.

S

Differential Nonlinearity (DNL) Error

In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.

Integral Nonlinearity (INL) Error

Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is meas­ured from the middle of each code to the true straight line.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured for an input typically at −60 dB. The
value for dynamic range is expressed in decibels.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by

ENOB = [(SINAD

− 1.76)/6.02]

dB

Gain Error

The first transition (from 100 … 000 to 100 …001) should occur
at a level ½ LSB above nominal negative full scale (−4.0959375 V
for the ±4.096 V range). The last transition (from 011 … 110 to
011 … 111) should occur for an analog voltage 1½ LSB below
the nominal full scale (+4.0959375 V for the ±4.096 V range).
The gain error is the deviation of the difference between the
actual level of the last transition and the actual level of the first
transition from the difference between the ideal levels.

Least Significant Bit (LSB)

The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For a fully differential input
ADC with N bits of resolution, the LSB expressed in volts is

V

LSB2(V) =

INp-p

N

Power Supply Rejection Ratio (PSRR)

Variations in power supply affect the full-scale transition but not
the linearity of the converter. PSRR is the maximum change in
the full-scale transition point due to a change in power supply
voltage from the nominal value.

Reference Voltage Temperature Coefficient

The reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (V
ured at T

, T(25°C), and T

MIN

REF

Cppm/ ×

=°

)(TCV

. It is expressed in ppm/°C as

MAX

((

REFREF

C25

REF

×°

MAX

MIN

) meas-

REF

)MinV–)MaxV

6

10

)T–T()(V

where:

(Max) = maximum V

V

REF

(Min) = minimum V

V

REF

V

(25°C) = V

REF

T

MAX

T

MIN

= +85°C.

= −40°C.

REF

at 25°C.

REF

REF

at T

at T

MIN

MIN

, T(25°C), or T

, T(25°C), or T

MAX

MAX

.

.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Signal-to-(Noise + Distortion) (SINAD) Ratio

SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.

Zero Error

Zero error is the difference between the ideal midscale input
voltage (0 V) and the actual voltage producing the midscale
output code.

Rev. 0 | Page 12 of 24

AD7625

THEORY OF OPERATION

IN+

MSB

REF

(4.096V)

GND

IN–

32,768C 16,384C 4C 2C C C

32,768C 16,384C 4C 2C C C

MSB

Figure 18. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7625 is a 6 MSPS, high precision, power efficient, 16-bit
ADC that uses SAR based architecture to provide performance
of 93 dB SNR, ±0.45 LSB INL, and ±0.3 LSB DNL.

The AD7625 is capable of converting 6,000,000 samples per
second (6 MSPS). The device typically consumes 135 mW. The
AD7625 offers the added functionality of a high performance
on-chip reference and on-chip reference buffer.

The AD7625 is specified for use with 5 V and 2.5 V supplies
(VDD1, VDD2). The interface from the digital host to the
AD7625 uses 2.5 V logic only. The AD7625 uses an LVDS
interface to transfer data conversions. The CNV+ and CNV−
inputs to the part activate the conversion of the analog input.
The CNV+ and CNV− pins can be applied using a CMOS or
LVDS sou r c e .

The AD7625 is housed in a space-saving, 32-lead, 5 mm ×
5 mm LFCSP.

CONVERTER INFORMATION

The AD7625 is a 6 MSPS ADC that uses SAR based architecture
incorporating a charge redistribution DAC. Figure 18 shows a
simplified schematic of the ADC. The capacitive DAC consists
of two identical arrays of 16 binary weighted capacitors that are
connected to the two comparator inputs.

During the acquisition phase, the terminals of the array tied
to the input of the comparator are connected to GND via SW+
and SW−. All independent switches are connected to the analog
inputs. In this way, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. A conversion phase is initiated when the acquisition
phase is complete and the CNV± input goes logic high. Note
that the AD7625 can receive a CMOS (CNV+) or LVDS format
(CNV±) signal.

GND

LSB

LSB

SWITCHES

COMP

CONTRO L

CONTROL

CNV+, CNV–

CONVERSION

CONTROL

LOGIC

CLK+, CLK–

DCO+, DCO–

D+, D–

OUTPUT CODE

LVDS INTERF ACE

DATA TRANSFER

SW+

SW–

GND

When the conversion phase begins, SW+ and SW− are opened
first. The two capacitor arrays are then disconnected from the
inputs and connected to the GND input. Therefore, the differential
voltage between the inputs (IN+ and IN−) captured at the end
of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between GND and 4.096 V
(the reference voltage), the comparator input varies by binary
weighted voltage steps (V

REF

/4 … V

REF

/65,536). The

REF

/2, V
control logic toggles these switches, MSB first, to bring the
comparator back into a balanced condition. At the completion
of this process, the control logic generates the ADC output code.

The AD7625 digital interface uses low voltage differential
signaling (LVDS) to enable high data transfer rates.

The AD7625 conversion result is available for reading after t
(time from the conversion start until MSB is available) has
elapsed. The user must apply a burst LVDS CLK± signal to the
AD7625 to transfer data to the digital host.

The CLK± signal outputs the ADC conversion result onto the
data output D±. The bursting of the CLK± signal is illustrated
in Figure 29 and Figure 30 and is characterized as follows: The
differential voltage on CLK± should be held to create logic low
in the time between t

CLKL

and t

MSB

.

The AD7625 has two data read modes. For more information
about the echoed-clock and self-clocked interface modes, see
the Digital Interface section.

07652-030

MSB

Rev. 0 | Page 13 of 24

AD7625

V

TRANSFER FUNCTIONS

The AD7625 uses a 4.096 V reference. The AD7625 converts
the differential voltage of the antiphase analog inputs (IN+ and
IN−) into a digital output. The analog inputs, IN+ and IN−,
require a 2.048 V common-mode voltage (REF/2).

The 16-bit conversion result is in MSB first, twos complement
format.

The ideal transfer functions for the AD7625 are shown in
Figure 19 and Table 7.

011 ... 111
011 ... 110
011 ... 101

ADC CODE (TWO S COMPLEMENT)

100 ... 010

100 ... 001

100 ... 000

–FSR

–FSR + 1LSB

–FSR + 0.5L SB

+FSR – 1.5L SB

ANALOG INPUT

Figure 19. ADC Ideal Transfer Functions (FSR = Full-Scale Range)

Table 7. Output Codes and Ideal Input Voltages

Analog Input

Digital Output Code
Twos Complement (Hex)

Description

(IN+ − IN−)
REF = 4.096 V

FSR − 1 LSB +4.0959375 V 0x1FFF
Midscale + 1 LSB +62.5 μV 0x0001
Midscale 0 V 0x0000
Midscale − 1 LSB −62.5 μV 0xFFFF

−FSR + 1 LSB −4.0959375 V 0x1001

−FSR −4.096 V 0x1000

+FSR – 1LSB

07652-031

ANALOG INPUTS

The analog inputs, IN+ and IN−, applied to the AD7625 must be
180° out of phase with each other. Figure 20 shows an equivalent
circuit of the input structure of the AD7625.

The two diodes provide ESD protection for the analog inputs,
IN+ and IN−. Care must be taken to ensure that the analog input
signal does not exceed the reference voltage by more than 0.3 V.
If the analog input signal exceeds this level, the diodes become
forward-biased and start conducting current. These diodes can
handle a forward-biased current of 130 mA maximum. However,
if the supplies of the input buffer (for example, the supplies of
the ADA4899-1 in Figure 24) are different from those of the
reference, the analog input signal may eventually exceed the
supply rails by more than 0.3 V. In such a case (for example, an
input buffer with a short circuit), the current limitation can be
used to protect the part.

DD1

IN+
OR
IN–

Figure 20. Equivalent Analog Input Circuit

The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these differ­ential inputs, signals common to both inputs are rejected. The
AD7625 shows some degradation in THD with higher analog
input frequencies.

85

80

75

70

65

60

CMRR (dB)

55

50

45

40

1 10 100 1k 10k 100k 1M 10M

INPUT COMMON-MODE FREQUENCY (Hz)

Figure 21. Analog Input CMRR vs. Frequency

250Ω

CNV

25pF

7652-032

07652-009

Rev. 0 | Page 14 of 24

AD7625

TYPICAL CONNECTION DIAGRAM

VDD2

(2.5V)

100nF

8

ADR280

VIO

CONTROL F OR

ENABLE

VDD2
(2.5V)

V+

VDD1

(5V)

100nF

10nF

10µF

10kΩ

PINS

100nF

CONVERS ION

CONTROL

CMOS (CNV+ ONLY)

LVDS CNV+ AND CNV–

USING 100Ω

TERMINATION RESI STOR

8

ADR434
ADR444

CAPACITOR ON OUTPUT

FOR STABILITY

1

VDD1

2

VDD2

3

CAP1

4

3

10kΩ

OR

REFIN

5

EN0

6

EN1

7

VDD2

4

8 9 10 11 12 13 14 15 16 17

C

REF

1, 2

10µF

32 31 30 29 28 27 26 25

REF

REF

GND

REF

PADDLE

AD7625

CNV–

CNV+

D–

D+

VIO

100Ω

100Ω

VIO

(2.5V)

1

10µF

GND

CAP2

GND

CAP2

CAP2

DCO–

DCO+

5

CLK–

GND

IN+

IN–

VCM

VDD1

VDD1

VDD2

24

23

22

21

20

19

18

100nF

IN+

SEE THE DRIVING

IN–

THE AD7625 SECTI ON

VCM

FERRITE

BEAD

100nF

6

VDD2
(2.5V)

VDD1
(5V)

7

CLK+

100Ω

100Ω

DIGITAL INTERF ACE SIGNALS

DIGITAL HOS T

LVDS TRANSMIT AND RECEIVE

1

SEE THE LAYOUT, DECOUPLING, AND G ROUNDING SECT ION.

2

C

IS USU ALLY A 10µF CERAMIC CAPACIT OR

REF

3

USE PULL-UP OR PULL-DOWN RESIS TORS TO CONTROL EN0, EN1 DURING P OWER-UP. EN0 AND EN1 INPUTS CAN BE

FIXED IN HARDWARE OR CONTRO LLED USI NG A DIGIT AL HOST (EN0 = 0 AND EN1 = 0 IS AN I LLEGAL STATE).

4

OPTIO N TO USE A CMOS (CNV+) OR LV DS (CNV±) INPUT TO CONTRO L CONVERSI ONS.

5

TO ENABLE SELF-CLO CKED MODE, T IE DCO+ TO GND USING A PULL-DOWN RESISTOR.

6

CONNECT PIN 19 AND PIN 20 TO VDD1 SUPPLY; ISOLATE FROM PIN 1 USING A FERRI TE BEAD SIM ILAR TO WURTH 74279266.

7

SEE THE DRIVING THE AD7625 S ECTION FOR DETAIL S ON AMPLI FIER CONFIGURATI ONS.

8

SEE THE VO LTAGE REF ERENCE OPTI ONS SECTI ON FOR DET AILS.

WITH LOW ESR AND ESL.

Figure 22. Typical Application Diagram

07652-027

Rev. 0 | Page 15 of 24

AD7625

DRIVING THE AD7625

Differential Analog Input Source

Figure 24 shows an ADA4899-1 driving each differential input
to the AD7625.

Single-Ended-to-Differential Driver

For applications using unipolar analog signals, a single-ended­to-differential driver, as shown in Figure 23, allows for a differ­ential input into the part. This configuration, when provided
with an input signal of 0 V to 4.096 V, produces a differential
±4.096 V with midscale at 2.048 V. The one-pole filter using
R = 33 Ω and C = 56 pF provides a corner frequency of 86 MHz.
The VCM output of the AD7625 can be buffered and then used
to provide the required 2.048 V common-mode voltage.

ANALOG INPUT

(UNIPOL AR 0V TO 4. 096V)

Figure 23. Single-Ended-to-Differential Driver Circuit

100nF

ADA4899-1

U1

50Ω

590Ω

590Ω

U2

ADA4899-1

33Ω

33Ω

V+

V–

56pF

IN+

AD7625

IN–

VCM

56pF

100nF

AD8031, AD8032

07652-033

1

REF

+V

S

33Ω

0V TO V

REF

ADA4899-1

V

TO 0V

REF

ADA4899-1

VCM

BUFFERED VCM PI N OUTPUT
GIVES T HE REQUIRE D 2.048V
COMMON-MODE SUPPLY FOR
ANALOG INPUT S.

1

SEE THE VOL TAGE REFERENCE OPTI ONS SECTI ON. CONNECTION TO EXTERNAL REFERENCE SIGNALS

IS DEPENDENT ON THE EN1 AND EN0 SE TTINGS.

2

C

IS USUALL Y A 10µF CERAMIC CAPACI TOR

REF

THE REF AND REF IN PINS ARE DECO UPLED REGARDL ESS OF E N1 AND EN0 SETTI NGS.

–V

+V

–V

56pF

S

S

33Ω

56pF

S

+V

S

0.1µF

AD8031, AD8032

–V

S

WITH LOW ESL AND ESR.

IN+

IN–

C

REF

10µF

2

REF

AD7625

GND

REFIN

VCM

2.048V

C

REF

10µF

2

REF

1

07652-025

Figure 24. Driving the AD7625 from a Differential Analog Source

Rev. 0 | Page 16 of 24

AD7625

VOLTAGE REFERENCE OPTIONS

The AD7625 allows flexible options for creating and buffering
the reference voltage. The AD7625 conversions refer to 4.096 V
only. The various options creating this 4.096 V reference are
controlled by the EN1 and EN0 pins (see Tabl e 8).

A

V+

Table 8. Voltage Reference Options1

Option EN1 EN0 Reference Mode

A 1 1

Use internal reference and internal
reference buffer (both are enabled).

B 0 1

Use external 1.2 V reference with
internal reference buffer enabled.
The internal reference is disabled.

C 1 0

Use external 4.096 V reference with
an external reference buffer. The
internal reference and reference
buffer are disabled.

1

EN1 = 0 and EN0 = 0 is an illegal state.

SETTING EN1 = 1 AND EN0 = 1 ENABLES THE INT ERNAL
REFERENCE AND REFERENCE BUFFER. DECOUPLE
THE REF AND REFI N PINS EXTERNALLY.

V+

DISABLES THE INTERNAL REF ERENCE

AND REFERENCE BUFFER. CONNECT THE

ADR434
ADR444

V–

SETTING EN1 = 1 AND EN0 = 0

BUFFERED 4.096V SIGNAL T O

THE REF PIN.

10µF

C

REF

IN+

10µF

REFIN

AD7625

IN–

ADR280

B

SETTING EN1 = 0 AND EN0 = 1
DISABLES THE INTERNAL REF ERENCE
AND ENABLES THE INTERNAL REFERE NCE BUFFER.
CONNECT A 1.2V REFERENCE TO THE REFIN P IN. THE 1. 2V
APPLIED TO THE REFI N PIN IS BUFFERED INTERNAL LY
TO CREATE A 4.096V REFERENCE FOR THE ADC.

V+

7652-026

Figure 25. Voltage Reference Options

Rev. 0 | Page 17 of 24

AD7625

POWER SUPPLY

The AD7625 uses both 5 V (VDD1) and 2.5 V (VDD2) power
supplies, as well as a digital input/output interface supply (VIO).
VIO allows a direct interface with 2.5 V logic only. VIO and
VDD2 can be taken from the same 2.5 V source; however, it is
best practice to isolate the VIO and VDD2 pins using separate
traces and also to decouple each pin separately.

The 5 V and 2.5 V supplies required for the AD7625 can be
generated using Analog Devices, Inc., low dropout regulators
(LDOs) such as the ADP3330-2.5, ADP3330-5, ADP3334, and

ADP1708.

90

VDD2

85

80

VDD1

75

70

PSRR (dB)

65

60

55

50

1 10 100 1k 10k

SUPPLY FREQ UENCY (Hz)

Figure 26. PSRR vs. Supply Frequency

(350 mV pp Ripple on VDD2, 600 mV Ripple on VDD1)

Power-Up

When powering up the AD7625 device, first apply the VIO
voltage to the device so that the EN1 and EN0 values can be set
for the reference option in use. Connect the EN0 and EN1 pins
to pull-up/pull-down resistors to ensure that one or both of
these pins is set to a nonzero value. EN0 = 0 and EN1 = 0 is an
illegal state that must be avoided.

INTERNAL REFERENCE USED

07652-011

After VIO is established, apply the 2.5 V VDD2 supply to the
device followed by the 5 V VDD1 supply and then an external
reference (depending on the reference setting being used).
Finally, apply the analog inputs to the ADC.

25

20

15

10

CURRENT (mA)

5

0

0 1000 2000 3000 4000 5000 6000 7000

VDD2 INTERNAL REF

VDD2 EXTERNAL REF

VIO

VDD1 INTERNAL REF

VDD1 EXTERNAL REF

SAMPLING RAT E (kSPS)

Figure 27. Current Consumption vs. Sampling Rate

150

140

130

120

110

100

90

POWER DISSIPATIO N (mW)

80

70

60

0 1000 2000 3000 4000 5000 6000 7000

INTERNAL REF

EXTERNAL REF

SAMPLING RAT E (kSPS)

Figure 28. Power Dissipation vs. Sampling Rate

07652-016

07652-017

Rev. 0 | Page 18 of 24

AD7625

A

DIGITAL INTERFACE

Conversion Control

All analog-to-digital conversions are controlled by the CNV
signal. This signal can be applied in the form of a CNV+/CNV−
LVDS signal, or it can be applied in the form of a 2.5 V CMOS
logic signal to the CNV+ pin. The conversion is initiated by the
rising edge of the CNV signal.

After the AD7625 is powered up, the first conversion result
generated is invalid. Subsequent conversion results are valid
provided that the time between conversions does not exceed
the maximum specification for t

The two methods for acquiring the digital data output of the
AD7625 via the LVDS interface are described in the following
sections.

Echoed-Clock Interface Mode

The digital operation of the AD7625 in echoed-clock interface
mode is shown in Figure 29. This interface mode, requiring
only a shift register on the digital host, can be used with many
digital hosts (FPGA, shift register, microprocessor, and so on).
It requires three LVDS pairs (D±, CLK±, and DCO±) between
each AD7625 and the digital host.

CNV–

CNV+

.

CYC

SAMPLE N S

t

CNVH

t

CYC

t

ACQ

The clock DCO± is a buffered copy of CLK± and is synchronous
to the data, D±, which is updated on the falling edge of DCO+
(t

). By maintaining good propagation delay matching between

D

D± and DCO± through the board and the digital host, DCO±
can be used to latch D± with good timing margin for the shift
register.

Conversions are initiated by a CNV± pulse. The CNV± pulse
must be returned low (≤t

maximum) for valid operation.

CNVH

After a conversion begins, it continues until completion. Addi­tional CNV± pulses are ignored during the conversion phase.
After the time t
CLK±. Note that t

elapses, the host should begin to burst the

MSB

is the maximum time for the MSB of the

MSB

new conversion result and should be used as the gating device
for CLK±. The echoed clock, DCO±, and the data, D±, are
driven in phase, with D± being updated on the falling edge of
DCO+; the host should use the rising edge of DCO+ to capture
D±. The only requirement is that the 16 CLK pulses finish
before the time t
data is lost. From the time t

elapses for the next conversion phase or the

CLKL

to t

CLKL

, D± and DCO± are

MSB

driven to 0s. Set CLK± to idle low between CLK± bursts.

MPLE N + 1

CLK–

CLK+

DCO–

DCO+

D+

D–

ACQUISITION

t

CLK

t

DCO

t

CLKD

ACQUISITION ACQUISITION

1615

1615 1 16152

t

MSB

D1

N – 1

D0

N – 1

0

116152 123

t

D

D15ND14

N

Figure 29. Echoed-Clock Interface Mode Timing Diagram

Rev. 0 | Page 19 of 24

t

CLKL

D1

N

1

23

D15

D0

N

0

N + 1

D14

N + 1

D13

N + 1

7652-003

AD7625

A

Self-Clocked Interface Mode

The digital operation of the AD7625 in self-clocked interface
mode is shown in Figure 30. This interface mode reduces the
number of wires between ADCs and the digital host to two LVDS
pairs per AD7625 (CLK± and D±) or to a single pair if sharing a
common CLK± using multiple AD7625 devices. Self-clocked
interface mode facilitates the design of boards that use multiple
AD7625 devices. The digital host can adapt the interfacing
scheme to account for differing propagation delays between
each AD7625 device and the digital host.

The self-clocked interface mode consists of preceding the results
of each ADC word with a 2-bit header on the data, D±. This
header is used to synchronize D± of each conversion in the
digital host. Synchronization is accomplished by one simple
state machine per AD7625 device. For example, if the state
machine is running at the same speed as CLK± with three
phases, the state machine measures when the Logic 1 of the
header occurs.

CNV–

CNV+

SAMPLE N

t

CNVH

t

CYC

t

ACQ

Conversions are initiated by a CNV± pulse. The CNV± pulse
must be returned low (≤t

maximum) for valid operation.

CNVH

After a conversion begins, it continues until completion. Addi­tional CNV± pulses are ignored during the conversion phase.
After the time t
CLK±. Note that t

elapses, the host should begin to burst the

MSB

is the maximum time for the first bit of

MSB

the header and should be used as the gating device for CLK±.
CLK± is also used internally on the host to begin the internal
synchronization state machine. The next header bit and conversion
results are output on subsequent falling edges of CLK±. The
only requirement is that the 18 CLK± pulses finish before the
time t

elapses for the next conversion phase or the data is

CLKL

lost. Set CLK± to idle high between bursts of 18 CLK± pulses.

S

MPLE N + 1

CLK–

CLK+

D+

D–

ACQUISITION

t

CLKD

ACQUISITION

D15

t

CLKL

18173

D14

N

N

D1

D0

N

N

t

CLK

1817 1 42

t

MSB

D1

N – 1

D0

N – 1

0

0

1

ACQUISITION

1

23

00

1

D15

N + 1

07652-004

Figure 30. Self-Clocked Interface Mode Timing Diagram

Rev. 0 | Page 20 of 24

AD7625

APPLICATIONS INFORMATION

LAYOUT, DECOUPLING, AND GROUNDING

When laying out the printed circuit board (PCB) for the AD7625,
follow the practices described in this section to obtain the maxi­mum performance from the converter.

Exposed Paddle

The AD7625 has an exposed paddle on the underside of the
package.

• Solder the paddle directly to the PCB.

• Connect the paddle to the ground plane of the board using

multiple vias, as shown in Figure 31.

• Decouple all supply pins except for Pin 12 (VIO) directly to

the paddle, minimizing the current return path.

• Pin 13 and Pin 24 can be connected directly to the paddle.

Use vias to ground at the point where these pins connect to
the paddle.

VDD1 Supply Routing and Decoupling

The VDD1 supply is connected to Pin 1, Pin 19, and Pin 20. The
supply should be decoupled using a 100 nF capacitor at Pin 1.
The user can connect this supply trace to Pin 19 and Pin 20. Use
a series ferrite bead to connect the VDD1 supply from Pin 1 to
Pin 19 and Pin 20. The ferrite bead isolates any high frequency
noise or ringing on the VDD1 supply. Decouple the VDD1

supply to Pin 19 and Pin 20 using a 100 nF capacitor to GND.
This GND connection can be placed a short distance away from
the exposed paddle.

VIO Supply Decoupling

Decouple the VIO supply applied to Pin 12 to ground at Pin 13.

Layout and Decoupling of Pin 25 to Pin 32

Connect the outputs of Pin 25, Pin 26, and Pin 28 together and
decouple them to Pin 27 using a 10 μF capacitor with low ESR
and low ESL.

Reduce the inductance of the path connecting Pin 25, Pin 26,
and Pin 28 by widening the PCB traces connecting these pins.

A similar approach should be taken in the connections used for
the reference pins of the AD7625. Connect Pin 29, Pin 30, and
Pin 32 together using widened PCB traces to reduce inductance.
In internal or external reference mode, a 4.096 V reference voltage
is output on Pin 29, Pin 30, and Pin 32. Decouple these pins to
Pin 31 using a 10 μF capacitor with low ESR and low ESL.

Figure 31 shows an example of the recommended layout for
the underside of the AD7625 device. Note the extended signal
trace connections and the outline of the capacitors decoupling
the signals applied to the REF pins (Pin 29, Pin 30, and Pin 32)
and to the CAP2 pins (Pin 25, Pin 26, and Pin 28).

24 23 22 21 20 19 18 17

4.096V

EXTERNAL REFERENCE

(ADR434 OR ADR444)

Figure 31. PCB Layout and Decoupling Recommendations for Pin 24 to Pin 32

25

26

27

28

29

30

31

32

Paddle

12345678

16

15

14

13

12

11

10

9

07652-013

Rev. 0 | Page 21 of 24

AD7625

C

OUTLINE DIMENSIONS

0.08

0.60 MAX

25

24

EXPOSED

PAD

(BOTTOM VIEW)

17

16

3.50 REF

FOR PROPER CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

PIN 1

32

9

INDICATOR

1

3.25

3.10 SQ

2.95

8

0.25 MIN

011708-A

5.00

INDI

1.00

0.85

0.80

PIN 1

ATO R

12° MAX

SEATING
PLANE

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

4.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARIT Y

Figure 32. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7625BCPZ
AD7625BCPZ-RL7
EVAL-AD7625EDZ
EVAL-CED1Z

1

Z = RoHS Compliant Part.

2

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CED1Z for evaluation/demonstration purposes.

3

This board allows the PC to control and communicate with all Analog Devices evaluation boards with model numbers ending with the ED designator.

1

−40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2

1

−40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2

1, 2

Evaluation Board

1, 3

Converter Evaluation and Development Board

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AD7625

NOTES

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AD7625

NOTES

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07652-0-1/09(0)

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