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16-Bit, 1.33 MSPS PulSAR® ADC
FEATURES
Throughput: 1.33 MSPS
2.048 V internal reference
Differential input range: ±V
INL: ±1 LSB
typical
16-bit resolution with no missing codes
SINAD: 88 dB typical @ 100 kHz
THD: −97 dB typical @ 100 kHz
No pipeline delay (SAR architecture)
Parallel (16- or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
2.5 V single-supply operation
Power dissipation: 45 mW typical @ 1.33 MSPS
48-lead LQFP and LFCSP_VQ packages
Speed upgrade of the AD7677
APPLICATIONS
Medical instruments
High speed data acquisition
Digital signal processing
Communications
Instrumentation
Spectrum analysis
AT E
REF
(V
up to 2.5 V)
REF
AD7623
FUNCTIONAL BLOCK DIAGRAM
AGND
AVDD
IN+
IN–
PDREF
PDBUF
PD
RESET
TEMP
REFBUFIN
REF
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
REF AMP
SWITCHED
CAP DAC
CNVST
REF REFGND
AD7623
INTERFACE
CLOCK
Figure 1.
Table 1. PulSAR Selection
Type/kSPS 100 to 250 500 to 570
Pseudo
Differential
AD7651
AD7660/61
AD7650/52
AD7664/66
True Bipolar AD7663 AD7665 AD7671
True
AD7675 AD7676 AD7677 AD7621
Differential
18-Bit AD7678 AD7679 AD7674 AD7641
Multichannel/
AD7654 AD7655
Simultaneous
DGNDDVDD
OVDD
OGND
SERIAL
PORT
16
D[15:0]
PARALLEL
SER/PAR
BUSY
RD
CS
OB/2C
BYTESWAP
800 to
1000 >1000
AD7653
AD7667
AD7623
05574-001
GENERAL DESCRIPTION
The AD7623 is a 16-bit, 1.33 MSPS, charge redistribution SAR,
fully differential analog-to-digital converter (ADC) that
operates from a single 2.5 V power supply. It contains a high
speed 16-bit sampling ADC, an internal conversion clock, an
internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. Power consumption is automatically scaled with throughput, making it ideal
for battery-powered applications. It is available in 48-lead, low
profile quad flat package (LQFP) and a lead frame chip-scale
(LFCSP_VQ) package. Operation is specified from
−40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
PRODUCT HIGHLIGHTS
1. Fast Throughput.
The AD7623 is a 1.33 MSPS, charge redistribution,
16-bit SAR ADC.
2. Sup
3. Int
4. S
5. Se
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
erior Linearity.
The AD7623 has no missing 16-bit code.
ernal Reference.
The AD7623 has a 2.048 V internal reference with a
typical drift of ±7 ppm/°C.
ingle-Supply Operation.
The AD7623 operates from a 2.5 V single supply and
typically dissipates 45 mW. Its power dissipation decreases
with the throughput.
rial or Parallel Interface.
Versatile parallel (16- or 8-bit bus) or 2-wire serial interface
arrangement compatible with 2.5 V, 3.3 V, or 5 V logic.
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AD7623
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TABLE OF CONTENTS
Features.............................................................................................. 1
Analog Inputs .............................................................................17
Applications....................................................................................... 1
Functional Block Diagram ..............................................................1
General Description......................................................................... 1
Product Highlights........................................................................... 1
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Serial Clock Timing Specifications............................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology ....................................................................................11
Typical Performance Characteristics ...........................................12
Theory of Operation ......................................................................15
Circuit Information.................................................................... 15
Converter Operation.................................................................. 15
Driver Amplifier Choice ........................................................... 17
Voltage Reference Input ............................................................ 18
Power Supply............................................................................... 19
Power Dissipation vs. Throughput .......................................... 20
Conversion Control................................................................... 20
Interfaces.......................................................................................... 21
Digital Interface.......................................................................... 21
Parallel Interface......................................................................... 21
Serial Interface............................................................................ 22
Master Serial Interface............................................................... 22
Slave Serial Interface.................................................................. 24
Microprocessor Interfacing....................................................... 26
Application ...................................................................................... 27
Layout .......................................................................................... 27
Evaluating the AD7623 Performance...................................... 27
Transfer Functions......................................................................16
Typical Connection Diagram ................................................... 17
REVISION HISTORY
7/05—Revision 0: Initial Version
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Rev. 0 | Page 2 of 28
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AD7623
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SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range
VIN+ − VIN−
Operating Input Voltage VIN+, VIN− to AGND −0.1 AVDD
Analog Input CMRR fIN = 100 kHz 55 dB
Input Current 1.33 MSPS throughput 10 μA
Input Impedance
2
THROUGHPUT SPEED
Complete Cycle 750 ns
Throughput Rate 0 1.33 MSPS
DC ACCURACY
Integral Linearity Error
3
V
No Missing Codes V
Differential Linearity Error V
Transition Noise V
Transition Noise V
Zero Error, T
MIN
to T
MAX
5
−30 +30 LSB
Zero Error Temperature Drift ±1 ppm/°C
Gain Error, T
MIN
to T
MAX
5
−0.38 +0.38 % of FSR
Gain Error Temperature Drift ±2 ppm/°C
Power Supply Sensitivity AVDD = 2.5 V ± 5% ±2 LSB
AC ACCURACY
Dynamic Range fIN = 20 kHz 90 dB
Signal-to-Noise fIN = 20 kHz 88 89.5 dB
f
f
IN
IN
Spurious-Free Dynamic Range fIN = 20 kHz 97 dB
f
IN
Total Harmonic Distortion fIN = 20 kHz –97 dB
f
IN
Signal-to-(Noise + Distortion) fIN = 20 kHz 87.5 88.5 dB
f
f
IN
IN
–3 dB Input Bandwidth 50 MHz
SAMPLING DYNAMICS
Aperture Delay 1 ns
Aperture Jitter 5 ps rms
Transient Response Full-scale step 50 ns
INTERNAL REFERENCE PDREF = PDBUF = low
Output Voltage REF @ 25°C 2.038 2.048 2.058 V
Temperature Drift –40°C to +85°C ±7 ppm/°C
Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V
Turn-On Settling Time C
REFBUFIN Output Voltage REFBUFIN @ 25°C 1.2 V
REFBUFIN Output Resistance 6.33 kΩ
= 2.5 V; all specifications T
REF
= 2.048 V, PDREF = high −2 ±1 +2 LSB
REF
= 2.048 V, PDREF = high 16 Bits
REF
= 2.048 V, PDREF = high −1 +2 LSB
REF
= 2.5 V 0.70 LSB
REF
= 2.048 V 0.82 LSB
REF
= 20 kHz, V
= 2.048 V 86 88 dB
REF
MIN
to T
−V
, unless otherwise noted.
MAX
+V
REF
V
REF
1
= 100 kHz 89 dB
= 100 kHz 96 dB
= 100 kHz −95 dB
= 20 kHz, V
= 2.048 V 87.5 dB
REF
= 100 kHz 88 dB
= 10 μF 5 ms
REF
V
4
6
Rev. 0 | Page 3 of 28
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AD7623
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Parameter Conditions Min Typ Max Unit
EXTERNAL REFERENCE PDREF = PDBUF = high
Voltage Range REF 1.8 2.048 AVDD V
Current Drain 1.33 MSPS throughput 100 μA
REFERENCE BUFFER PDREF = high, PDBUF = low
REFBUFIN Input Voltage Range 1.05 1.2 1.30 V
TEMPERATURE PIN
Voltage Output @ 25°C 273 mV
Temperature Sensitivity 0.85 mV/°C
Output Resistance 4.7 kΩ
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.6 V
VIH 1.7 5.25 V
IIL –1 +1 μA
IIH –1 +1 μA
DIGITAL OUTPUTS
Data Format
Pipeline Delay
VOL I
VOH I
POWER SUPPLIES
Specified Performance
AVDD 2.37 2.5 2.63 V
DVDD 2.37 2.5 2.63 V
OVDD 2.30
Operating Current
AVD D
DVDD 1.6 mA
OVDD 0.6 mA
Power Dissipation
With Internal Reference
Without Internal Reference
In Power-Down Mode12 PD = high 600 μW
TEMPERATURE RANGE
Specified Performance T
1
When using an external reference. With the internal reference, the input range is from −0.1 V to V
2
See the Analog Inputs section.
3
Linearity is tested using endpoints, not best fit. Tested with an external reference at 2.048 V.
4
LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 62.5 μV.
5
See the Terminology section. These specifications do not include the error contribution from the external reference.
6
All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
7
Parallel or serial 16-bit.
8
Conversion results are available immediately after completed conversion.
9
See the Absolute Maximum Ratings section.
10
Tested in parallel reading mode.
11
With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high.
12
With all digital inputs forced to OVDD.
13
Consult sales for extended temperature range.
7
8
10
11
10
11
11
13
= 500 μA 0.4 V
SINK
= –500 μA OVDD − 0.3 V
SOURCE
9
3.6 V
1.33 MSPS throughput
With internal reference 15 mA
1.33 MSPS throughput 50 55 mW
1.33 MSPS throughput 45 53 mW
to T
MIN
–40 +85 °C
MAX
.
REF
Rev. 0 | Page 4 of 28
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TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (Refer to Figure 31 and Figure 32)
Convert Pulse Width t1 15 70
Time Between Conversions t2 750 ns
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert) t4 560 ns
Aperture Delay t5 1 ns
End of Conversion to BUSY Low Delay t6 10 ns
Conversion Time t7 560 ns
Acquisition Time t8 125 ns
RESET Pulse Width t9 15 ns
RESET Low to BUSY High Delay
BUSY High Time from RESET Low
2
2
PARALLEL INTERFACE MODES (Refer to Figure 33 to Figure 35).
CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay t11 2 ns
Bus Access Request to DATA Valid t12 20 ns
Bus Relinquish Time t13 2 15 ns
MASTER SERIAL INTERFACE MODES3 (Refer to Figure 37 and Figure 38)
CS Low to SYNC Valid Delay
CS Low to Internal SCLK Valid Delay
3
CS Low to SDOUT Delay
CNVST Low to SYNC Delay
SYNC Asserted to SCLK First Edge Delay t18 0.5 ns
Internal SCLK Period
Internal SCLK High
Internal SCLK Low
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
4
4
4
4
4
4
CS High to SYNC HI-Z
CS High to Internal SCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read after Convert
CNVST Low to SYNC Asserted Delay
SYNC Deasserted to BUSY Low Delay t30 13 ns
SLAVE SERIAL INTERFACE MODES3 (Refer to Figure 40 and Figure 41)
External SCLK Setup Time t31 5 ns
External SCLK Active Edge to SDOUT Delay t32 1 8 ns
SDIN Setup Time t33 5 ns
SDIN Hold Time t34 5 ns
External SCLK Period t35 12.5 ns
External SCLK High t36 5 ns
External SCLK Low t37 5 ns
1
See the Conversion Control section.
2
See the Digital Interface and RESET sections.
3
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
4
In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
= 2.5 V; all specifications T
REF
4
to T
MIN
23 ns
t
3
, unless otherwise noted.
MAX
1
ns
t38 10 ns
t39 600 ns
560 ns
t
10
10 ns
t
14
t15 10 ns
10 ns
t
16
263 ns
t
17
t19 8 12 ns
t20 2 ns
t21 3 ns
t22 1 ns
t23 0 ns
t24 0 ns
10 ns
t
25
10 ns
t
26
10 ns
t
27
t28 See Table 4
500 ns
t
29
Rev. 0 | Page 5 of 28
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SERIAL CLOCK TIMING SPECIFICATIONS
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t18 0.5 3 3 3 ns
Internal SCLK Period Minimum t19 8 16 32 64 ns
Internal SCLK Period Maximum t19 12 25 50 100 ns
Internal SCLK High Minimum t20 2 6 15 31 ns
Internal SCLK Low Minimum t21 3 7 16 32 ns
SDOUT Valid Setup Time Minimum t22 1 5 5 5 ns
SDOUT Valid Hold Time Minimum t23 0 0.5 10 28 ns
SCLK Last Edge to SYNC Delay Minimum t24 0 0.5 9 26 ns
BUSY High Width Maximum t28 0.780 1.000 1.440 2.320 μs
500μAI
TO OUTPUT
PIN
C
L
50pF
500μAI
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT ARE DEFINED WITH A MAXIMUM LOAD.
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
C
L
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, C
OL
1.4V
OH
05574-002
= 10 pF
L
0.8V
t
DELAY
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
2V
t
DELAY
2V
0.8V
05574-003
Rev. 0 | Page 6 of 28
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ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs/Outputs
IN+1, IN−, REF, REFBUFIN, TEMP,
INGND, REFGND to AGND
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD –0.3 V to +2.7 V
OVDD –0.3 V to +3.8 V
AVDD to DVDD ±2.8 V
AVDD to OVDD +2.8 V to −3.8 V
OVDD to DVDD
Digital Inputs −0.3 V to +5.5 V
PDREF, PDBUF
Internal Power Dissipation
Internal Power Dissipation
Junction Temperature 125°C
Storage Temperature Range –65°C to +125°C
1
See the Analog Inputs section.
2
See the Power Supply section.
3
See the Voltage Reference Input section.
4
Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W,
θJC = 30°C/W.
5
Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W.
2
3
4
5
AVDD + 0.3 V to
AGND − 0.3 V
≤ +0.3 V if DVDD < 2.3 V
±20 mA
700 mW
2.5 W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
Rev. 0 | Page 7 of 28
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PDBUF
PDREF
REFBUFIN
TEMP
AVDD
IN+
AGND
OVDD
OGND
AGNDNCIN–
DVDD
DGND
D8/SDOUT
48 47 46 45 44 39 38 3743 42 41 40
1
AGND
AVDD
NC
BYTESWAP
OB/2C
DGND
DGND
SER/PAR
D0
D1
D2/DIVSCLK[0]
D3/DIVSCLK[1]
NC = NO CONNECT
PIN 1
IDENTIFIER
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
D4/EXT/INT
(Not to Scale)
D6/INVSCLK
D5/INVSYNC
D7/RDC/SDIN
AD7623
TOP VIEW
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1Description
1, 41, 42 AGND P Analog Power Ground Pin.
2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V.
3, 40 NC
4 BYTESWAP DI
No Connect.
Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
5
OB/2C
DI
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary;
when low, the MSB is inverted resulting in a twos complement output from its internal shift register.
6, 7 DGND P
8
SER/PA R
DI
Digital Power Ground.
Serial/Parallel Selection Input. When high, the serial interface is selected and some bits of the data bus
are used as a serial port; the remaining data bits are high impedance outputs. When SER/PA R
the parallel port is selected.
9, 10 D[0:1] DO
11, 12 D[2:3] DI/O
or
DIVSCLK[0:1]
Bit 0 and Bit 1 of the Parallel Port Data Output Bus.
When SER/PA R
When SER/PA R
mode (EXT/INT
= low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
= high, serial clock division selection. When using serial master read after convert
= low, RDC/SDIN = low), these inputs can be used to slow down the internally
generated serial clock that clocks the data output. In other serial modes, these pins are high
impedance outputs.
13 D4 DI/O
or EXT/INT
When SER/PA R
When SER/PA R
= low, this output is used as Bit 4 of the parallel port data output bus.
= high, serial clock source select. This input is used to select the internally generated
(master ) or external (slave) serial data clock.
When EXT/INT
= low, master mode. The internal serial clock is selected on SCLK output.
When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal, gated
by CS
, connected to the SCLK input.
D9/SCLK
REFGND
D10/SYNC
REF
36
35
34
33
32
31
30
29
28
27
26
25
D11/RDERROR
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D15
D14
D13
D12
05574-004
= low,
14 D5 DI/O
or INVSYNC
When SER/PA R
When SER/PA R
= low, this output is used as Bit 5 of the parallel port data output bus.
= high, invert sync select. In serial master mode (EXT/INT = low), this input is used to
select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
15 D6 DI/O
When SER/
PA R
= low, this output is used as Bit 6 of the parallel port data output bus.
or INVSCLK Invert SCLK Select. In all serial modes, this input is used to invert the SCLK signal.
Rev. 0 | Page 8 of 28
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Pin No. Mnemonic Type1Description
16 D7 DI/O Bit 7 of the Parallel Port Data Output Bus.
or RDC
or SDIN
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P
19 DVDD P Digital Power. Nominally at 2.5 V.
20 DGND P Digital Power Ground.
21 D8 DO
or SDOUT
22 D9 DI/O
or SCLK
23 D10 DO
or SYNC
24 D11 DO
or RDERROR
25 to 28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus.
29 BUSY DO
30 DGND P Digital Power Ground.
31
RD
DI
When SER/PA R
used to select the read mode.
When RDC = high, the previous conversion result is read during current conversion and the period of
SCLK changes (see the Master Serial Interface section).
When RDC = low (read after convert), the current result is read after conversion.
Serial Data In. When using serial slave mode, (EXT/INT
daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data
level on SDIN is output on SDOUT with a delay of 16 SCLK periods after the initiation of the read
sequence.
Input/Output Interface Digital Power. Nominally at the same sup
(2.5 V or 3 V).
When SER/PA R
When SER/PA R
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7623 provides the
conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/2C.
In master mode, (EXT/INT
In slave mode, (EXT/INT
When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
Parallel Port Data Output Bus Bit 9. When SER/PA R
data output bus.
Serial Clock. When SER/PAR
clock input or output, dependent on the logic state of the EXT/INT
SDOUT is updated depends on the logic state of the INVSCLK pin.
When SER/PA R
When SER/PA R
used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low
SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while
SDOUT output is valid.
Parallel Port Data Output Bus Bit 11. When SER/PA R
port data output bus.
Read Error. When SER/PAR
as an incomplete read error flag. If a data read is started and not completed when the current
conversion is complete, the current data is lost and RDERROR is pulsed high.
Busy Output. Transitions high when a conversion is started, and remains high until the conversion is
omplete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used
c
as a data ready clock signal.
Read Data. When CS
= high, read during convert. When using serial master mode (EXT/INT = low), RDC is
= high), SDIN could be used as a data input to
ply as the supply of the host interface
= low, this output is used as Bit 8 of the parallel port data output bus.
= high, serial data output. In serial mode, this pin is used as the serial data output
= low). SDOUT is valid on both edges of SCLK.
= high):
= low, this output is used as Bit 9 of the parallel port
= high, serial clock. In all serial modes, this pin is used as the serial data
pin. The active edge where the data
= low, this output is used as Bit 10 of the parallel port data output bus.
= high, frame synchronization. In serial master mode (EXT/INT= low), this output is
, SYNC is driven high and remains high while
= low, this output is used as Bit 11 of the parallel
= high, read error. In serial slave mode (EXT/INT = high), this output is used
and RD are both low, the interface parallel or serial output bus is enabled.
32
33 RESET DI
34 PD DI
CS
DI
Chip Select. When CS
also used to gate the external clock in slave serial mode.
Reset Input. When high, reset the AD7623. Current conversion if any is aborted. Falling edge of RESET
enables the cali
not used
Power-Down Input. When high, power down the ADC. Power consumption is reduced and conversions
ar
, this pin can be tied to DGND.
e inhibited after the current one is completed.
and RD are both low, the interface parallel or serial output bus is enabled. CS is
bration mode indicated by pulsing BUSY high. Refer to the Digital Interface section. If
Rev. 0 | Page 9 of 28
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Pin No. Mnemonic Type1Description
35
36 AGND P Analog Power Ground Pin.
37 REF AI/O
38 REFGND AI Reference Input Analog Ground.
39 IN− AI Differential Negative Analog Input.
43 IN+ AI Differential Positive Analog Input.
45 TEMP AO Temperature Sensor Analog Output.
46 REFBUFIN AI/O
47 PDREF DI
48 PDBUF DI
1
AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
CNVST
DI
Conversion Start. A falling edge on CNVST
initiates a conversion.
Reference Output/Input.
hen PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 2.048 V on this pin.
W
When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally
supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal
reference and buffer. Refer to the Voltage Reference Input section.
Internal Reference Output/Reference Buffer Input.
hen PDREF/PDBUF = low, the internal reference and buffer are enabled, producing the 1.2 V (typical)
W
band gap output on this pin, which needs external decoupling. The internal fixed gain reference buffer
uses this to produce 2.048V on the REF pin.
When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high),
applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section.
Internal Reference Power-Down Input.
When low
When high, the internal reference is powered down, and an external reference must be used.
Internal Reference Buffer Power-Down Input.
When low
When high, the buffer is powered-down.
, the internal reference is enabled.
, the buffer is enabled (must be low when using internal reference).
puts the internal sample-and-hold into the hold state and
Rev. 0 | Page 10 of 28
Page 11
AD7623
www.BDTIC.com/ADI
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full-scale through positive fullscale. The point used as negative full-scale occurs ½ LSB before
the first code transition. Positive full-scale is defined as a level
1½ LSBs beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
n an ideal ADC, code transitions are 1 LSB apart. Differential
I
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Gain Error
irst transition (from 000…00 to 000…01) should occur for
The f
an analog voltage ½ LSB above the nominal negative full-scale
(−2.0479688 V for the ±2.048 V range). The last transition
(from 111…10 to 111…11) should occur for an analog voltage
1½ LSBs below the nominal full-scale (2.0479531 V for the
±2.048 V range). The gain error is the deviation of the
difference between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels.
Zero Error
The zer
o error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.
Dynamic Range
D
ynamic range is the ratio of the rms value of the full-scale to
the rms noise measured with the inputs shorted together. The
value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
S
NR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
INAD is the ratio of the rms value of the actual input signal to
S
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
ference, in decibels (dB), between the rms amplitude of
The dif
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
OB is a measurement of the resolution with a sine wave
EN
input. It is related to SINAD and is expressed in bits by
− 1.76)/6.02]
ENOB = [(SI
NAD
dB
Aperture Delay
A
perture delay is a measure of the acquisition performance
measured from the falling edge of the
CNVST
input to when
the input signal is held for a conversion.
Transi ent Res p onse
The t
ime required for the AD7623 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Reference Voltage Temperature Coefficient
ence voltage temperature coefficient is derived from the
Refer
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (V
measured at T
MIN
REF
, T(25°C), and T
)(TCV
Cppm/ ×
=°
REF
. It is expressed in ppm/°C as
MAX
((
REFREF
×°
C25
MAX
MIN
)
REF
)MinV–)MaxV
6
10
)T–T()(V
where:
(Max) = maximum V
V
REF
(Min) = minimum V
V
REF
V
(25°C) = V
REF
T
MAX
T
MIN
= +85°C.
= –40°C.
REF
at 25°C.
REF
REF
at T
at T
MIN
MIN
, T (25°C), or T
, T (25°C), or T
MAX
MAX
.
.
Total Harmonic Distortion (THD)
HD is the ratio of the rms sum of the first five harmonic
T
components to the rms value of a full-scale input signal and is
expressed in decibels.
Rev. 0 | Page 11 of 28
Page 12
AD7623
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.5
1.0
1.5
1.0
0.5
0
INL (LSB)
–0.5
–1.0
–1.5
–2.0
0 65536
16384 32768 49152
CODE
Figure 5. Integral Nonlinearity vs. Code
160k
140k
120k
100k
80k
COUNTS
60k
40k
20k
011
0
7FFC 8004
2406
7FFD 7FFE 7FFF 8000 8001 8002 8003
147157
58814
CODE IN HEX
50472
2258
σ
= 0.70
20
Figure 6. Histogram of 261,120 Conversions of a DC Input
ode Center (External 2.5V Reference)
at the C
2.0530
2.0525
2.0520
2.0515
2.0510
2.0505
VREF (V)
2.0500
2.0495
2.0490
2.0485
2.0480
–55 125
–35 –15 5 25 45 65 85 105
TEMPERATURE (°C)
Figure 7. Typical Reference Voltage Output vs. Temperature (3 Units)
05574-005
05574-006
05574-007
0.5
DNL (LSB)
0
–0.5
–1.0
0 65536
16384 32768 49152
CODE
Figure 8. Differential Nonlinearity vs. Code
160k
140k
120k
100k
80k
COUNTS
60k
40k
20k
0
0
7FFC 8004
5928
119
7FFD 7FFE 7FFF 8000 8001 8002 8003
126114
59008
CODE IN HEX
62565
7217
168
σ
= 0.82
1
Figure 9. Histogram of 261,120 Conversions of a DC Input
at the Code Center (Internal Reference)
10
8
6
4
2
0
–2
–4
–6
–8
ZERO ERROR, FULL-SCALE ERROR (LSB)
–10
–FS
ZERO
ERROR
+FS
–55 125
–35 –15 5 25 45 65 85 105
TEMPERATURE (°C)
Figure 10. Zero Error, Positive and Negative Full Scale vs. Temperature
05574-008
05574-009
05574-010
Rev. 0 | Page 12 of 28
Page 13
AD7623
www.BDTIC.com/ADI
0
–20
–40
–60
–80
–100
–120
–140
AMPLITUDE (dB of Full Scale)
–160
–180
0 600
FREQUENCY (kHz)
Figure 11. FFT 20 kHz
92
90
SINAD
88
ENOB
86
SNR, SINAD (dB)
84
f
S
f
IN
SNR = 89.4dB
THD = –104.1dB
SFDR = 107.2dB
SINAD = 89.3dB
SNR
= 1.33MSPS
= 20.03kHz
500100 200 300 400
15.4
15.0
14.6
14.2
13.8
05574-011
ENOB (Bits)
0
–20
–40
–60
–80
–100
–120
–140
AMPLITUDE (dB of Full Scale)
–160
–180
0 600
FREQUENCY (kHz)
Figure 14. FFT 100 kHz
90
89
88
87
86
85
SNR, SINAD (dB)
84
83
SNR
SINAD
ENOB
f
= 1.33MSPS
S
f
= 100.13kHz
IN
SNR = 89.2dB
THD = –95.6dB
SFDR = 96dB
SINAD = 88.4dB
500100 200 300 400
05574-014
15.5
15.0
14.5
ENOB (Bits)
14.0
82
1 1000
10 100
FREQUENCY (kHz)
Figure 12. SNR, SINAD and ENOB vs. Frequency
–70
–75
SFDR
–80
–85
–90
THD
–95
THIRD
–100
HARMONIC
–105
THD, HARMONICS (dB)
–110
SECOND
HARMONIC
–115
–120
1 1000
10 100
FREQUENCY (kHz)
Figure 13. THD, Harmonics, and SFDR vs. Frequency
13.4
120
110
100
90
80
70
60
50
40
30
20
05574-012
SFDR (dB)
05574-013
82
–55 125
–35 –15 5 25 45 65 85 105
TEMPERATURE (°C)
Figure 15. SNR, SINAD, and ENOB vs. Temperature
–80
–85
–90
–95
–100
–105
–110
–115
THD, HARMONICS (dB)
–120
–125
–130
–55 125
SFDR
THD
THIRD
HARMONIC
SECOND
HARMONIC
–35–155 25456585105
TEMPERATURE (°C)
Figure 16. THD, Harmonics, and SFDR vs. Temperature
13.5
100
95
90
85
80
75
70
65
60
55
50
05574-015
SFDR (dB)
05574-016
Rev. 0 | Page 13 of 28
Page 14
AD7623
www.BDTIC.com/ADI
91.0
90.5
90.0
89.5
SNR, SINAD REFERRED TO FULL-SCALE (dB)
89.0
–60 0
Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale)
SNR
SINAD
–50 –40 –30 –20 –10
INPUT LEVEL (dB)
05574-017
100k
PDREF = PDBUF = HIGH
10k
A)
μ
1k
100
10
OPERATING CURRENTS (
1
0.1
10 100 1k 10k 100M 1M 10M
AVDD
OVDD = 3.3V
DVDD
SAMPLING RATE (SPS)
OVDD, 2.5V
Figure 19. Operating Currents vs. Sample Rate
00574-019
16
14
12
10
8
6
DVDD, OVDD (μA)
4
2
0
–55 –35 –15 5 25 45 65 85 105 125
AVDD
OVDD, 3.3V
OVDD, 2.5V
DVDD
TEMPERATURE (°C)
Figure 18. Power-Down Operating Currents vs. Temperature
280
270
260
250
240
230
220
210
200
AVDD (μA)
05574-018
20
18
16
14
12
DELAY (ns)
12
10
t
8
6
4
0 50 100 150 200
CL (pF)
OVDD = 2.5V @ 85°C
OVDD = 2.5V @ 25°C
OVDD = 3.3V @ 85°C
OVDD = 3.3V @ 25°C
Figure 20. Typical Delay vs. Load Capacitance C
05574-020
L
Rev. 0 | Page 14 of 28
Page 15
AD7623
www.BDTIC.com/ADI
THEORY OF OPERATION
IN+
MSB
32,768C 16,384C 4C 2C C C
REF
REFGND
32,768C 16,384C 4C 2C C C
MSB
IN–
Figure 21. ADC Simplified Schematic
AGND
LSB
LSB
AGND
SW+
SW–
COMP
SWITCHES
CONTROL
CONTROL
LOGIC
CNVST
BUSY
OUTPUT
CODE
05574-021
CIRCUIT INFORMATION
The AD7623 is a very fast, low power, single-supply, precise,
16-bit analog-to-digital converter (ADC) using successive
approximation architecture. The AD7623 is capable of
converting 1,330,000 samples per second (1.33 MSPS).
The AD7623 provides the user with an on-chip track-and-hold,
s
uccessive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
The AD7623 can be operated from a single 2.5 V supply and
be
interfaced to either 5 V, 3.3 V, or 2.5 V digital logic. It
is housed in 48-lead LQFP or tiny LFCSP packages that
combine space savings with flexibility, allowing the AD7623
to be configured as either a serial or parallel interface. The
AD7623 is pin-to-pin-compatible with, and a speed upgrade
of, the AD7677.
CONVERTER OPERATION
The AD7623 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
s
chematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
mparator’s input are connected to AGND via SW+ and SW−.
co
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN− inputs. A conversion
phase is initiated once the acquisition phase is complete and the
CNVST
input goes low. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the
REFGND input. Therefore, the differential voltage between the
inputs (IN+ and IN−) captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between REFGND and REF, the
comparator input varies by binary weighted voltage steps
(V
/2, V
REF
/4 through V
REF
/65536). The control logic toggles
REF
these switches, starting with the MSB first, in order to bring the
comparator back into a balanced condition.
After the completion of this process, the control logic generates
t
he ADC output code and brings BUSY output low.
The AD7623 automatically powers down circuits after
co
nversion, making the AD7623 ideal for battery-powered
applications.
Rev. 0 | Page 15 of 28
Page 16
AD7623
2
3
4
www.BDTIC.com/ADI
TRANSFER FUNCTIONS
Using the OB/2C digital input, the AD7623 offers two output
codings: straight binary and twos complement. The LSB size
with V
Figure 22 and Table 7 for the ideal transfer characteristic.
= 2.048 V is 2 × V
REF
111...111
111...110
111...101
ADC CODE (Straight Binary)
000...010
000...001
000...000
–FSR
–FSR+0.5 LSB
ANALOG
SUPPLY (2.5V)
/65536, which is 62.5 μV. Refer to
REF
ANALOG INPUT
+FSR–1.5 LSB
Figure 22. ADC Ideal Transfer Function
NOTE 5
10μF
100nF
10Ω
+FSR–1 LSB–FSR+1 LSB
05574-022
10μF
100nF 100nF
SUPPLY (2.5V)
Table 7. Output Codes and Ideal Input Voltages
Description
V
= 2.048 V
REF
FSR −1 LSB +2.047938 V 0xFFFF1
FSR − 2 LSB +2.047875 V 0xFFFE 0x7FFE
Midscale + 1 LSB +62.5 μV 0x8001 0x0001
Midscale 0 V 0x8000 0x0000
Midscale − 1 LSB −62.5 μV 0x7FFF 0xFFFF
−FSR + 1 LSB −2.047938 V 0x0001 0x8001
−FSR −2.048 V 0x00002
1
This is also the code for overrange analog input (V
V
− V
Analog Input
REF
2
This is also the code for underrange analog input (V
−V
DIGITAL
).
REFGND
+ V
REFGND
).
(2.5V OR 3.3V)
10μF
REF
Straight
Binary
DIGITAL
INTERFACE
SUPPLY
Digital Output Code
Twos
Complement
1
0x7FFF
2
0x8000
− V
above
IN+
IN−
− V
below
IN+
IN−
AVDD
AGND DGND DVDD OVDD OGND
REF
C
REF
10μF
100nF
NOTE 4
NOTE 2
ANALOG
INPUT +
ANALOG
INPUT –
1. SEE ANALOG INPUT SECTION.
. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION.
. A 10μF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ3YB0J106M).
SEE VOLTAGE REFERENCE INPUT SECTION.
5. OPTION, SEE POWER SUPPLY SECTION.
6. OPTION, SEE POWER-UP SECTION.
7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
U1
C
NOTE 2
U2
C
10Ω
C
C
1nF
NOTE 1
10Ω
1nF
NOTE 1
REFBUFIN
REFGND
IN+
IN–
NOTE 3
AD7623
PD
PDREF
NOTE 3
PDBUF
SCLK
SDOUT
BUSY
CNVST
OB/2C
SER/PAR
CS
RD
RESET
Figure 23. Typical Connection Diagram
50Ω
50pF
50pF
10kΩ
NOTE 6
SERIAL
PORT
NOTE 7
OVDD
D
CLOCK
MICROCONVERTER/
MICROPROCESSOR/
DSP
05574-023
Rev. 0 | Page 16 of 28
Page 17
AD7623
www.BDTIC.com/ADI
TYPICAL CONNECTION DIAGRAM
Figure 23 shows a typical connection diagram for the AD7623.
Different circuitry from that shown in this diagram are optional
and are discussed in the Analog Inputs section.
ANALOG INPUTS
Figure 24 shows an equivalent circuit of the input structure of
the AD7623.
The two diodes, D
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V, because this causes the diodes to become forwardbiased and to start conducting current. These diodes can handle
a forward-biased current of 100 mA maximum. For instance,
these conditions could eventually occur when the input buffer’s
U1 or U2 supplies are different from AVDD. In such a case, an
input buffer with a short-circuit current limitation can be used
to protect the part.
IN+ OR IN–
AGND
The analog inputs of the AD7623 are a true differential
structure. By using this differential input, small signals common
to both inputs are rejected, as shown in Figure 25, representing
t
he typical CMRR over frequency with internal and external
references.
75
70
65
60
CMRR (dB)
55
50
45
1 10 100 1000 10000
During the acquisition phase for ac signals, the impedance of
the analog inputs, IN+ and IN−, can be modeled as a parallel
combination of Capacitor C
series connection of R
capacitance. R
and D2, provide ESD protection for the
1
AVDD
D
1
C
PIN
Figure 24. AD7623 Simplified Analog Input
Figure 25. Analog Input CMRR vs. Frequency
is typically 350 Ω and is a lumped component
IN
D
EXT REF
FREQUENCY (kHz)
PIN
and CIN. C
IN
2
INT REF
and the network formed by the
is primarily the pin
PIN
C
R
IN
IN
05574-024
05574-025
comprised of some serial resistors and the on resistance of the
switches. C
is typically 12 pF and is primarily the ADC
IN
sampling capacitor. During the conversion phase, when the
switches are opened, the input impedance is limited to C
make a one-pole, low-pass filter that has a typical −3 dB
and C
IN
PIN
. RIN
cutoff frequency of 50 MHz, thereby reducing an undesirable
aliasing effect while limiting noise from the inputs.
Since the input impedance of the AD7623 is very high, the
AD7623 can
be directly driven by a low impedance source
without gain error. To further improve the noise filtering
achieved by the AD7623 analog input circuit, an external,
one-pole RC filter between the amplifier’s outputs and the ADC
analog inputs can be used, as shown in
rge source impedances significantly affect the ac performance,
la
Figure 23. However,
especially total harmonic distortion (THD). The maximum
source impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency, as shown in
Figure 26.
–60
PDBUF = PDREF = LOW
–65
–70
RS = 500
–75
–80
THD (dB)
–85
–90
–95
–100
1 10 100 1k
Figure 26. THD vs. Analog Input Frequency and Source Resistance
INPUT FREQUENCY (kHz)
Ω
RS = 10
RS = 100
RS = 50
Ω
Ω
Ω
05574-026
DRIVER AMPLIFIER CHOICE
Although the AD7623 is easy to drive, the driver amplifier must
meet the following requirements:
• T
ogether, the driver amplifier and the AD7623 analog
input circuit must be able to settle for a full-scale step of
the capacitor array at a 16-bit level (0.0015%). In the
amplifier data sheet, settling at 0.1% to 0.01% is more
commonly specified. This could differ significantly from
the settling time at a 16-bit level and should be verified
prior to driver selection. The AD8021 op amp, which
combines ultralow noise and high gain bandwidth, meets
this settling time requirement even when used with gains
up to 13.
• The
noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7623. The noise coming from
the driver is filtered by the AD7623 analog input circuit
Rev. 0 | Page 17 of 28
Page 18
AD7623
)
www.BDTIC.com/ADI
one-pole, low-pass filter made by R
external filter, if one is used. The SNR degradation due to
the amplifier is
⎛
⎜
20
logSNR
=
LOSS
⎜
⎜
2809
⎝
where:
f
is the input bandwidth of the AD7623 (50 MHz) or the
–3dB
cutoff frequency of the input filter (16 MHz), if one is used.
N is t
he noise factor of the amplifier (+1 in buffer
configuration).
e
is the equivalent input voltage noise density of the op
N
amp, in nV/√Hz.
For instance, a driver with an equivalent input noise
den
sity of 2.1 nV/√Hz, like the AD8021 with a noise gain
of +1 when configured as a buffer, degrades the SNR by
only 0.33 dB when using the RC filter in
thout using it.
1 dB wi
• The dr
iver needs to have a THD performance suitable to
that of the AD7623. Figure 13 gives the THD vs. frequency
hat the driver should exceed.
t
The AD8021 meets these requirements and is appropriate for
ost all applications. The AD8021 needs a 10 pF external
alm
compensation capacitor that should have good linearity as an
NPO ceramic or mica type. Moreover, the use of a noninverting
+1 gain arrangement is recommended and helps to obtain the
best signal-to-noise ratio.
The AD8022 can also be used when a dual version is needed
a
nd a gain of 1 is present. The AD829 is an alternative in
applications where high frequency (above 100 kHz) performance
is not required.
In applications with a gain of 1, an 82 pF compensation
pacitor is required. The AD8610 is an option when low bias
ca
current is needed in low frequency applications.
Single-to-Differential Driver
For applications using unipolar analog signals, a single-endedto-differential driver, as shown in Figure 27, allows for a
ferential input into the part. This configuration, when
dif
provided an input signal of 0 to V
±V
with midscale at V
REF
REF
REF
/2. The one-pole filter using R = 10 Ω
and C = 1 nF provides a corner frequency of 16 MHz.
and CIN or by the
IN
53
π+
dB
−23
⎞
⎟
⎟
⎟
()
Nef
N
⎠
Figure 23, and by
, produces a differential
U1
ANALOG INPUT
(UNIPOLAR 0V TO 2.048V
1kΩ
1kΩ
100nF
Figure 27. Single-Ended-to-Dif
AD8021
10pF
590Ω
590Ω
U2
AD8021
10pF
(Internal Reference Buffer Used)
10Ω
1nF
10Ω
1nF
ferential Driver Circuit
IN+
AD7623
IN–
10μF
REF
VOLTAGE REFERENCE INPUT
The AD7623 allows the choice of either a very low temperature
drift internal voltage reference or an external reference.
Unlike many ADCs with internal references, the internal
r
eference of the AD7623 provides excellent performance and
can be used in almost all applications.
Internal Reference (PDBUF = Low, PDREF = Low)
To use the internal reference, the PDREF and PDBUF inputs
must be low. This produces a 1.2 V band gap output on
REFBUFIN which, amplified by the internal buffer, results in a
2.048 V reference on the REF pin.
The internal reference is temperature-compensated to
2.048 V ± 10 mV
drift of 7 ppm/°C. This typical drift characteristic is shown
in Figure 7.
The output resistance of the REFBUFIN is 6.33 kΩ (minimum)
hen the internal reference is enabled. It is necessary to
w
decouple this with a ceramic capacitor greater than 100 nF.
Thus, the capacitor provides an RC filter for noise reduction.
Since the output impedance of REFBUFIN is typically 6.33 kΩ,
r
elative humidity (among other industrial contaminates) can
directly affect the drift characteristics of the reference. Typically,
a guard ring is used to reduce the effects of drift under such
circumstances. However, since the AD7623 has a fine lead pitch,
guarding this node is not practical. Therefore, in these
industrial and other types of applications, it is recommended to
use a conformal coating, such as Dow Corning 1-2577 or
Humiseal 1B73.
. The reference is trimmed to provide a typical
05574-027
If the application can tolerate more noise, the AD8139 different
ial driver can be used.
External 1.2 V Reference and Internal Buffer (PDREF = High, PBBUF = Low)
To use an external reference with the internal buffer, PDREF
should be high and PDBUF should be low. This powers down
the internal reference and allows the 1.2 V reference to be
applied to REFBUFIN.
Rev. 0 | Page 18 of 28
Page 19
AD7623
www.BDTIC.com/ADI
External Reference (PDBUF = High, PRBUF = High)
To use an external reference directly on the REF pin, PDREF
and PDBUF should both be high. PDREF and PDBUF power
down the internal reference and the internal reference buffer,
respectively.
For improved drift performance, an external reference, such as
th
e AD780 or ADR431, can be used. The advantages of directly
using the external voltage reference are:
• S
NR and dynamic range improvement (about 1.7 dB)
resulting from the use of a reference voltage very close to
the supply (2.5 V) instead of a typical 2.048 V reference
when the internal reference is used. This is calculated by
50.2
⎞
⎛
=
log20SNR
⎜
⎝
ower savings when the internal reference is powered
• P
⎟
048.2
⎠
down (PBREF = PDBUF = high).
Reference Decoupling
Whether using an internal or external reference, the AD7623
voltage reference input (REF) has a dynamic input impedance;
therefore, it should be driven by a low impedance source with
efficient decoupling between the REF and REFGND inputs.
This decoupling depends on the choice of the voltage reference,
but usually consists of a low ESR capacitor connected to REF
and REFGND with minimum parasitic inductance. A 10 μF
(X5R, 1206 size) ceramic chip capacitor (or 47 μF tantalum
capacitor) is appropriate when using either the internal
reference or one of these recommended reference voltages:
• The lo
• The
• The lo
w noise, low temperature drift ADR431 and AD780
low power ADR291
w cost AD1582
The placement of the reference decoupling is also important to
th
e performance of the AD7623. The decoupling capacitor
should be mounted on the same side as the ADC right at the
REF pin with a thick PCB trace. The REFGND should also
connect to the reference decoupling capacitor with the shortest
distance.
Temperature Sensor
The TEMP pin measures the temperature of the AD7623. To
improve the calibration accuracy over the temperature range,
the output of the TEMP pin is applied to one of the inputs of
the analog switch (such as ADG779), and the ADC itself is used
to measure its own temperature. This configuration is shown
in
Figure 28.
ANALOG INPUT
(UNIPOLAR)
ADG779
AD8021
Figure 28. Use of the Temperature Sensor
C
C
IN+
TEMP
AD7623
TEMPERATURE
SENSOR
POWER SUPPLY
The AD7623 uses three sets of power supply pins: an analog
2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.3 V
and 5.25 V. To reduce the number of supplies needed, the digital
core (DVDD) can be supplied through a simple RC filter from
the analog supply, as shown in
Power Sequencing
The AD7623 is independent of power supply sequencing once
OVDD does not exceed DVDD by more than 0.3 V until
DVDD = 2.3 V during any time; for instance, at power-up or
power-down (see the
dditionally, it is very insensitive to power supply variations
A
Absolute Maximum Ratings section).
over a wide frequency range as shown in
75
70
65
60
PSRR (dB)
55
EXT REF
Figure 23.
Figure 29.
INT REF
05574-028
For applications that use multiple AD7623 devices, it is more
ef
fective to use the internal reference buffer to buffer the
reference voltage.
50
45
1 10 100 1k 10k
The voltage reference temperature coefficient (TC) directly
pacts full scale; therefore, in applications where full-scale
im
Figure 29. PSRR vs. Frequency
accuracy matters, care must be taken with the TC. For instance,
a ±15 ppm/°C TC of the reference changes full-scale by ±1 LSB/°C.
Rev. 0 | Page 19 of 28
FREQUENCY (kHz)
05574-029
Page 20
AD7623
www.BDTIC.com/ADI
Power-Up
At power-up, or returning to operational mode from the powerdown mode (PD = high), the AD7623 engages an initialization
process. During this time, the first 128 conversions should be
ignored or the RESET input could be pulsed to engage a faster
initialization process. Refer to the
RES
ET and timing details.
A simple power-on reset circuit, as shown in Figure 23, can be
ed to minimize the digital interface. As OVDD powers up, the
us
capacitor is shorted and brings RESET high; it is then charged,
returning RESET to low. However, this circuit only works when
powering up the AD7623 because the power-down mode
(PD = high) does not power down any of the supplies. As a
result, RESET is low.
POWER DISSIPATION VS. THROUGHPUT
The AD7623 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows a significant
power savings when the conversion rate is reduced (see
eature makes the AD7623 ideal for very low power,
This f
battery-operated applications.
It should be noted that the digital interface remains active even
uring the acquisition phase. To reduce the operating digital
d
supply currents even further, drive the digital inputs close to the
power rails (that is, OVDD and OGND).
100k
PDREF = PDBUF = HIGH
10k
Digital Interface section for
Figure 30).
CONVERSION CONTROL
t
2
t
CNVST
CNVST
input. A falling edge
6
t
8
CNVST
should not
low time, t1, or until the end
Figure 23.
The AD7623 is controlled by the
CNVST
on
is all that is necessary to initiate a conversion.
Detailed timing diagrams of the conversion process are shown
in Figure 31. Once initiated, it cannot be restarted or aborted,
ven by the power-down input, PD, until the conversion is
e
t
3
t
5
CNVST
signal operates independently of CS and
t
1
t
4
CONVERT ACQUIREACQUIRE CONVERT
t
7
Figure 31. Basic Conversion Timing
complete. The
RD
signals.
CNVST
BUSY
MODE
For optimal performance, the rising edge of
occur after the maximum
of conversion.
Although
CNVST
is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot, undershoot, or ringing.
The
CNVST
trace should be shielded with ground, and a low
value (such as 50 Ω) serial resistor termination should be added
close to the output of the component that drives this line. Also,
a 60 pF capacitor is recommended to further reduce the effects
of overshoot and undershoot, as shown in
05574-031
For applications where SNR is critical, the
1k
POWER DISSIPATION (μW)
have very low jitter. This can be achieved by using a dedicated
oscillator for
CNVST
generation, or by clocking
high frequency, low jitter clock, as shown in Figure 23.
100
100 1k 10k 100k 1M 10M
Figure 30. Power Dissipati
SAMPLING RATE (SPS)
on vs. Sample Rate
05574-030
Rev. 0 | Page 20 of 28
CNVST
signal should
CNVST
with a
Page 21
AD7623
www.BDTIC.com/ADI
INTERFACES
DIGITAL INTERFACE
The AD7623 has a versatile digital interface that can be set up
as either a serial or parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The
AD7623 digital interface also accommodates 2.5 V, 3.3 V, or 5 V
logic with either OVDD at 2.5 V or 3.3 V. OVDD defines the
logic high output voltage. In most applications, the OVDD
supply pin of the AD7623 is connected to the host system
interface 2.5 V or 3.3 V digital supply. Finally, by using the
2C
OB/
input pin, both twos complement or straight binary
coding can be used.
CS
The two signals,
one of these signals is high, the interface outputs are in high
impedance. Usually,
multicircuit applications and is held low in a single AD7623
RD
design.
is generally used to enable the conversion result on
the data bus.
RESET
The RESET input is used to reset the AD7623 and generate a
fast initialization. A rising edge on RESET aborts the current
conversion (if any) and tristates the data bus. The falling edge of
RESET clears the data bus and engages the initialization process
indicated by pulsing BUSY high. Conversions can take place
after the falling edge of BUSY. Refer to
ti
ming details.
RESET
CNVST
DATA
and RD, control the interface. When at least
CS
allows the selection of each AD7623 in
Figure 32 for the RESET
t
9
PARALLEL INTERFACE
The AD7623 is configured to use the parallel interface when
PA R
SER/
Master Parallel Interface
Data can be continuously read by tying CS and RD low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 33 details the timing for this mode.
CS = RD = 0
CNVST
BUSY
DATA
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 34 and
Figure 35, respectively. When the data is read during the
co
first half of the conversion phase. This avoids any potential
feedthrough between voltage transients on the digital interface
and the most critical analog conversion circuitry.
is held low.
t
1
t
10
t
t
3
BUS
Figure 33. Master Parallel Data Timing for Reading (Continuous Read)
PREVIOUS CONVERSION DATA NEW DATA
4
t
11
nversion, it is recommended that it is read-only during the
CS
05574-033
BUSY
t
38
t
39
Figure 32. RESET Timing
t
8
05574-032
Rev. 0 | Page 21 of 28
RD
BUSY
DATA
BUS
t
12
Figure 34. Slave Parallel Data Timing for Reading (Read After Convert)
CURRENT
CONVERSION
t
13
05574-034
Page 22
AD7623
www.BDTIC.com/ADI
CS = 0
CNVST,
RD
BUSY
t
DATA
BUS
t
Figure 35. Slave Parallel Data Timing for Reading (Read During Convert)
8-Bit Interface (Master or Slave)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 36, when BYTESWAP is low, the LSB byte is
on D[7:0] and the MSB is output on D[15:8]. When
output
BYTESWAP is high, the LSB and MSB bytes are swapped, and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0]. This
interface can be used in both master and slave parallel reading
modes.
CS
RD
BYTESWAP
PINS D[15:8]
PINS D[7:0]
HI-Z
HI-Z
Figure 36. 8-Bit and 16-Bit Parallel Interface
3
12
t
1
t
4
PREVIOUS
CONVERSION
t
13
HIGH BYTE LOW BYTE
t
12
LOW BYTE HIGH BYTE
t
12
HI-Z
t
13
HI-Z
05574-035
05574-036
SERIAL INTERFACE
The AD7623 is configured to use the serial interface when
PA R
SER/
is held high. The AD7623 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7623 is configured to generate and provide the serial
INT
data clock SCLK when the EXT/
AD7623 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted, if desired. Depending on the read
during convert input, RDC/SDIN, the data can be read after
each conversion or during the following conversion.
a
nd Figure 38 show detailed timing diagrams of these two
mo
des.
Usually, because the AD7623 is used with a fast throughput, the
ter read during conversion mode is the most recommended
mas
serial mode. In this mode, the serial clock and data toggle at
appropriate instants, minimizing potential feedthrough between
digital activity and critical conversion decisions. In this mode,
the SCLK period changes since the LSBs require more time to
settle and the SCLK is derived from the SAR conversion cycle.
In read after conversion mode, unlike other modes, the BUSY
nal returns low after the 16 data bits are pulsed out and not at
sig
the end of the conversion phase, resulting in a longer BUSY
width. As a result, the maximum throughput cannot be
achieved in this mode.
pin is held low. The
Figure 37
Rev. 0 | Page 22 of 28
Page 23
AD7623
S
www.BDTIC.com/ADI
CS, RD
CNVST
BUSY
SYNC
SCLK
DOUT
EXT/INT = 0
t
3
t
29
t
14
t
20
t
15
X
t
16
t
22
Figure 37. Master Serial Data Timing for Reading (Read After Convert)
RDC/SDIN = 0 INVSCLK = INVSYNC = 0
t
28
t
30
t
18
t
19
t
21
123 141516
D15 D14 D2 D1 D0
t
23
t
24
t
25
t
26
t
27
05574-037
CS, RD
CNVST
BUSY
EXT/INT = 0
t
1
t
3
RDC/SDIN = 1 INVSCLK = INVSYNC = 0
SYNC
SCLK
SDOUT
t
17
t
14
t
15
t
18
t
16
t
22
t
19
t20t
21
123 141516
D15 D14 D2 D1 D0X
t
23
t
24
Figure 38. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
t
25
t
26
t
27
05574-038
Rev. 0 | Page 23 of 28
Page 24
AD7623
www.BDTIC.com/ADI
SLAVE SERIAL INTERFACE
External Clock
The AD7623 is configured to accept an externally supplied
INT
serial data clock on the SCLK pin when the EXT/
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by
RD
are both low, the data can be read after each conversion or
CS
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive.
d
Figure 40 and Figure 41 show the detailed timing
iagrams of these methods.
While the AD7623 is performing a bit decision, it is important
at voltage transients be avoided on digital input/output pins,
th
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7623 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a
discontinuous clock that is toggling only when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.
External Discontinuous Clock Data Read After Conversion
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave
modes. Figure 40 shows the detailed timing diagrams of this
m
ethod. After a conversion is complete, indicated by BUSY
returning low, the conversion result can be read while both
are low. Data is shifted out MSB first with 16 clock
and
RD
pulses and is valid on the rising and falling edges of the clock.
pin is
. When CS and
CS
An example of the concatenation of two devices is shown in
Figure 39. Simultaneous sampling is possible by using a
CNVST
mmon
co
signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite to the one used to
shift out the data on SDOUT. Hence, the MSB of the upstream
converter just follows the LSB of the downstream converter on
the next SCLK cycle.
BUSY
OUT
BUSYBUSY
AD7623
#2
(UPSTREAM)
RDC/SDIN SDOUT
CNVST
CS
SCLK
SCLK IN
CS IN
CNVST IN
Figure 39. Two AD7623 Devices in a Daisy-Chain Configuration
AD7623
#1
(DOWNSTREAM)
SDOUTRDC/SDIN
CNVST
SCLK
CS
DATA
OUT
00574-039
External Clock Data Read During Previous Conversion
Figure 41 shows the detailed timing diagrams of this method.
CS
During a conversion, while both
and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses, and is valid on both the rising
and falling edge of the clock. The 16 bits have to be read before
the current conversion is complete; otherwise, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain
feature in this mode, and RDC/SDIN input should always be
tied either high or low.
One advantage of this method is that conversion performance
ot degraded because there are no voltage transients on the
is n
digital interface during the conversion process. Another
advantage is the ability to read the data at any speed up to
To reduce performance degradation due to digital activity, a fast
dis
continuous clock of at least 40 MHz is recommended to
ensure that all the bits are read during the first half of the SAR
conversion phase.
80 MHz, which accommodates both the slow digital host
interface and the fastest serial reading.
Finally, in this mode only, the AD7623 provides a daisy-chain
f
eature using the RDC/SDIN pin for cascading multiple con-
It is also possible to begin to read data after conversion and
co
ntinue to read the last bits after a new conversion has been
initiated.
verters together. This feature is useful for reducing component
count and wiring connections when desired, as, for instance, in
isolated multiconverter applications.
Rev. 0 | Page 24 of 28
Page 25
AD7623
S
www.BDTIC.com/ADI
CS
BUSY
SCLK
SDOUT
EXT/INT = 1
t
35
t36t
37
123 1415161718
t
31
X
D15 D14 D1
t
16
t
32
D13
t
34
INVSCLK = 0
RD = 0
D0
X15 X14
SDIN
t
33
X15 X14 X13 X1 X0 Y15 Y14
Figure 40. Slave Serial Data Timing for Reading (Read After Convert)
05574-040
t
31
15 16
D2
RD = 0
D1
D0
05574-041
CS
CNVST
BUSY
SCLK
DOUT
EXT/INT = 1 INVSCLK = 0
t
3
t
35
t
t
36
37
1
t
32
X
t
16
2
D15 D14 D13
4
3
14
Figure 41. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
Rev. 0 | Page 25 of 28
Page 26
AD7623
www.BDTIC.com/ADI
MICROPROCESSOR INTERFACING
The AD7623 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and ac signal
processing applications interfacing to a digital signal processor.
The AD7623 is designed to interface with a parallel 8-bit or
16-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7623 to prevent digital noise from coupling
into the ADC. The
th
e use of the AD7623 with an ADSP-219x SPI-equipped DSP.
SPI Interface (ADSP-219x)
Figure 42 shows an interface diagram between the AD7623 and
an SPI-equipped DSP, ADSP-219x. To accommodate the slower
speed of the DSP, the AD7623 acts as a slave device, and data
must be read after conversion. This mode also allows the daisychain feature. The convert command could be initiated in
response to an internal timer interrupt.
SPI Interface (ADSP-219x) section shows
The reading process can be initiated in response to the end-of-
nversion signal (BUSY going low) using an interrupt line of
co
the DSP. The serial peripheral interface (SPI) on the ADSP-219x
is configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt
enable (TIMOD) = 00 by writing to the SPI control register
(SPICLTx).
It should be noted that to meet all timing requirements, the SPI
lock should be limited to 17 Mb/s allowing it to read an ADC
c
result in less than 1 μs. When a higher sampling rate is desired,
use one of the parallel interface modes.
DVDD
AD7623*
SER/PAR
EXT/INT
RD
INVSCLK
BUSY
CS
SDOUT
SCLK
CNVST
ADSP-219x*
PFx
SPIxSEL (PFx)
MISOx
SCKx
PFx OR TFSx
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 42. Interfacing the AD7623 to SPI Interface
05574-042
Rev. 0 | Page 26 of 28
Page 27
AD7623
www.BDTIC.com/ADI
APPLICATION
LAYOUT
While the AD7623 has very good immunity to noise on the
power supplies, exercise care with the grounding layout. To
facilitate the use of ground planes that can be easily separated,
design the printed circuit board that houses the AD7623 so that
the analog and digital sections are separated and confined to
certain areas of the board. Digital and analog ground planes
should be joined in only one place, preferably underneath the
AD7623, or as close as possible to the AD7623. If the AD7623 is
in a system where multiple devices require analog-to-digital
ground connections, the connections should still be made at
one point only, a star ground point, established as close as
possible to the AD7623.
To prevent coupling noise onto the die, avoid radiating noise,
d to reduce feedthrough:
an
• D
o not run digital lines under the device.
• Do r
un the analog ground plane under the AD7623.
CNVST
o shield fast switching signals, like
• D
digital ground to avoid radiating noise to other sections of
the board, and never run them near analog signal paths.
• A
void crossover of digital and analog signals.
• R
un traces on different but close layers of the board, at right
angles to each other, to reduce the effect of feedthrough
through the board.
The power supply lines to the AD7623 should use as large a
race as possible to provide low impedance paths and reduce the
t
effect of glitches on the power supply lines. Good decoupling is
also important to lower the impedance of the supplies presented
to the AD7623, and to reduce the magnitude of the supply
spikes. Decoupling ceramic capacitors, typically 100 nF, should
be placed on each of the power supplies pins, AVDD, DVDD,
and OVDD. The capacitors should be placed close to, and
ideally right up against, these pins and their corresponding
ground pins. Additionally, low ESR 10 μF capacitors should be
located in the vicinity of the ADC to further reduce low
frequency ripple.
or clocks, with
The DVDD supply of the AD7623 can be either a separate
pply or come from the analog supply, AVDD, or from the
su
digital interface supply, OVDD. When the system digital supply
is noisy, or fast switching digital signals are present, and no
separate supply is available, it is recommended to connect the
DVDD digital supply to the analog supply AVDD through an
RC filter, and to connect the system supply to the interface
digital supply OVDD and the remaining digital circuitry. Refer
to
Figure 23 for an example of this configuration. When DVDD
is
powered from the system supply, it is useful to insert a bead
to further reduce high frequency spikes.
The AD7623 has four different ground pins: REFGND, AGND,
D
GND, and OGND. REFGND senses the reference voltage and,
because it carries pulsed currents, should be a low impedance
return to the reference. AGND is the ground to which most
internal ADC analog signals are referenced; it must be
connected with the least resistance to the analog ground plane.
DGND must be tied to the analog or digital ground plane
depending on the configuration. OGND is connected to the
digital system ground.
The layout of the decoupling of the reference voltage is
portant. To minimize parasitic inductances, place the
im
decoupling capacitor close to the ADC and connect it with
short, thick traces.
EVALUATING THE AD7623 PERFORMANCE
A recommended layout for the AD7623 is outlined in the
documentation of the EVAL-AD7623CB evaluation board
for the AD7623. The evaluation board package includes a fully
assembled and tested evaluation board, documentation, and
software for controlling the board from a PC via the
EVAL-CONTROL BRD3.
Rev. 0 | Page 27 of 28
Page 28
AD7623
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
1.45
1.40
1.35
0.15
SEATING
0.05
PLANE
VIEW A
ROTATED 90° CCW
0.75
0.60
0.45
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
1.60
MAX
VIEW A
12
0.50
BSC
LEAD PITCH
Figure 43. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
1.00
0.85
0.80
12° MAX
SEATING
PLANE
BSC SQ
PIN 1
INDICATOR
7.00
TOP
VIEW
0.60 MAX
6.75
BSC SQ
0.50
0.40
0.30
0.80 MAX
0.65 TYP
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
0.20 REF
0.05 MAX
0.02 NOM
0.60 MAX
37
36
25
24
COPLANARITY
0.08
(BOTTOM VIEW)
Figure 44. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD7623ACP −40°C to +85°C 48-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-48-1
AD7623ACPRL −40°C to +85°C 48-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-48-1
AD7623ACPZ
AD7623ACPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale (LFCSP_VQ)
AD7623AST −40°C to +85°C 48-Lead Low Profile Quad Flatpack (LQFP) ST-48
AD7623ASTRL −40°C to +85°C 48-Lead Low Profile Quad Flatpack (LQFP)
AD7623ASTZ −40°C to +85°C 48-Lead Low Profile Quad Flatpack (LQFP)
AD7623ASTZRL −40°C to +85°C 48-Lead Low Profile Quad Flatpack (LQFP) ST-48
EVAL-AD7623CB Evaluation Board
EVAL-CONTROL BRD3 Controller Board
1
Z = Pb-free part.
2
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes.
3
This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designator.
1
1
1
1
2
−40°C to +85°C 48-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-48-1
3
48
1
PIN 1
(PINS DOWN)
13
EXPOSED
P
A
5.50
REF
9.00
BSC SQ
TOP VIEW
0.30
0.23
0.18
D
37
36
7.00
BSC SQ
25
24
0.27
0.22
0.17
PIN 1
INDICATOR
48
1
5.25
5.10 SQ
4.95
12
13
0.25 MIN
PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES
CP-48-1
ST-48
ST-48
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05574–0–7/05(0)
Rev. 0 | Page 28 of 28
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