Datasheet AD7622 Datasheet (ANALOG DEVICES)

16-Bit, 1.5 LSB INL, 2 MSPS PulSAR® ADC

FEATURES

Throughput

2 MSPS (wideband warp and warp mode)

1.5 MSPS (normal mode)
INL: ±0.5 LSB typical, ±1.5 LSB maximum (±23 ppm of FSR)
16-bit resolution with no missing codes
Dynamic range: 92.5 dB typical
SINAD: 91 dB minimum @ 20 kHz (V
THD: −115 dB typical @ 20 kHz (V

2.048 V internal reference: typical drift
Differential input range: ±V

REF

(V
No pipeline delay (SAR architecture)
Parallel (16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 2.5 V supply operation
Power dissipation

70 mW typical @ 2 MSPS with internal REF

2 μW in power-down mode
Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ
Pin compatible with other PulSAR 48-lead ADCs

APPLICATIONS

Medical instruments
High speed data acquisition/high dynamic data acquisition
Digital signal processing
Spectrum analysis
Instrumentation
Communications
AT E

GENERAL DESCRIPTION

The AD7622 is a 16-bit, 2 MSPS, charge redistribution SAR,
fully differential, analog-to-digital converter (ADC) that
operates from a single 2.5 V power supply. The part contains a
high speed, 16-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. It features two
very high sampling rate modes (wideband warp and warp) and
a fast mode (normal) for asynchronous rate applications. The
AD7622 is hardware factory calibrated and tested to ensure ac
parameters, such as signal-to-noise ratio (SNR), in addition to
the more traditional dc parameters of gain, offset, and linearity.
The AD7622 is available in Pb-free only packages with
operation specified from −40°C to +85°C.

= 2.5 V)

REF

= 2.5 V)

REF

8 ppm/°C; TEMP output

up to 2.5 V)

REF

AD7622

FUNCTIONAL BLOCK DIAGRAM

REF AMP

SWITCHED

CAP DAC

NORMAL

REF REFG ND

AD7622

INTERFACE

CLOCK

CNVST

Figure 1.

AGND

AVD D

IN+

IN–

PDREF

PDBUF

PD

RESET

REFBUFIN

TEMP

REF

CONTROL LO GIC AND

CALIBRATION CIRCUITRY

WAR P

Table 1. PulSAR 48-Lead ADC Selection

Type/kSPS

Pseudo
Differential

100 to
250

AD7651,
AD7660,
AD7661

500 to
570

AD7650,
AD7652,
AD7664,
AD7666

True Bipolar

AD7610,

AD7665

AD7663

True

AD7675 AD7676 AD7677

Differential

18-Bit
Multichannel/

AD7631,
AD7678

AD7679

Simultaneous AD7654 AD7655

1.50

1.00

0.50

0

INL (LSB)

–0.50

–1.00

–1.50

0 16384 32768 49152 65536

Figure 2. Integral Nonlinearity vs. Code

POSITIVE INL = +0.43 LSB
NEGATIVE INL = –0. 49 LSB

CODE

SERIAL

PORT

PARALLEL

650 to
1000

AD7653,
AD7667

AD7612,
AD7671

AD7634,
AD7674

DGNDDVDD

16

OVDD

OGND

D[15:0]

SER/PAR

BUSY

RD

CS

OB/2C

BYTESWAP

06023-001

>1000

AD7621,

AD7622,

AD7623
AD7641,

AD7643

06023-005

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD7622

TABLE OF CONTENTS

Features .............................................................................................. 1

Multiplexed Inputs ..................................................................... 17

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Te r mi n ol o g y .................................................................................... 11

Typical Performance Characteristics........................................... 12

Applications Information .............................................................. 15

Circuit Information.................................................................... 15

Converter Operation.................................................................. 15

Modes of Operation ................................................................... 15

Driver Amplifier Choice ........................................................... 18

Voltage Reference Input ............................................................ 19

Power Supply............................................................................... 20

Conversion Control ................................................................... 20

Interfaces.......................................................................................... 21

Digital Interface.......................................................................... 21

Parallel Interface......................................................................... 21

Serial interface............................................................................ 22

Master Serial Interface............................................................... 22

Slave Serial Interface .................................................................. 24

Microprocessor Interfacing....................................................... 26

Application Hints ........................................................................... 27

Layout ..........................................................................................27

Evaluating the AD7622 Performance...................................... 27

Outline Dimensions .......................................................................28

Transfer Fu nctions ...................................................................... 16

Typical Con ne ction Diag ram........................................................ 17

Analog Inputs.............................................................................. 17

REVISION HISTORY

6/06—Revision 0: Initial Version

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

AD7622

SPECIFICATIONS

AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V

Table 2.

Parameter Conditions Min Typ Max Unit

RESOLUTION 16 Bits
ANALOG INPUT

Voltage Range V
Operating Input Voltage V

IN+

IN+

Analog Input CMRR fIN = 100 kHz 58 dB
Input Current 2 MSPS throughput 3.5 μA
Input Impedance

2

THROUGHPUT SPEED

Complete Cycle Wideband warp, warp modes 500 ns
Throughput Rate Wideband warp, warp modes 0.001 2 MSPS
Time Between Conversions Wideband warp, warp modes 1 ms
Complete Cycle Normal mode 667 ns
Throughput Rate Normal mode 0 1.5 MSPS

DC ACCURACY

Integral Linearity Error

3

T

MIN

No Missing Codes 16 Bits
Differential Linearity Error −1 +1.25 LSB
Transition Noise V
Transition Noise V
Zero Error, T

MIN

to T

MAX

5

REF

REF

−10 +10 LSB
Zero Error Temperature Drift ±0.5 ppm/°C
Gain Error, T

MIN

to T

MAX

5

−8 +8 LSB
Gain Error Temperature Drift ±0.5 ppm/°C
Power Supply Sensitivity AVDD = 2.5 V ± 5% ±4 LSB

AC ACCURACY

Dynamic Range V

REF

Signal-to-Noise fIN = 20 kHz, V
f
f

= 20 kHz, V

IN

= 100 kHz, V

IN

Spurious-Free Dynamic Range fIN = 20 kHz, V
f
f

= 20 kHz, V

IN

= 100 kHz, V

IN

Total Harmonic Distortion fIN = 20 kHz, V
f
f

= 20 kHz, V

IN

= 100 kHz, V

IN

Signal-to-(Noise + Distortion) fIN = 20 kHz, V
f
f

= 20 kHz, V

IN

= 100 kHz, V

IN

−3 dB Input Bandwidth 50 MHz

SAMPLING DYNAMICS

Aperture Delay 1 ns
Aperture Jitter 5 ps rms
Transient Response Full-scale step 140 ns

INTERNAL REFERENCE PDREF = PDBUF = low

Output Voltage REF @ 25°C 2.038 2.048 2.058 V
Temperature Drift −40°C to +85°C ±8 ppm/°C
Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V
Turn-On Settling Time C

REF

= 2.5 V; all specifications T

REF

− V

IN−

, V

to AGND −0.1 AVDD

IN−

to T

= −40°C to +85°C −1.5 ±0.5 +1.5 LSB

MAX

MIN

−V

to T

REF

, unless otherwise noted.

MAX

+V

REF

1

V

V

= 2.5 V 0.5 LSB
= 2.048 V 0.6 LSB

= 2.5 V 91.5 92.5 dB

= 2.5 V 91 92 dB

REF

= 2.048 V 89.5 90.5 dB

REF

= 2.5 V 91 dB

REF

= 2.5 V 117 dB

REF

= 2.048 V 110 dB

REF

= 2.5 V 101 dB

REF

= 2.5 V −115 dB

REF

= 2.048 V −109 dB

REF

= 2.5 V −100 dB

REF

= 2.5 V 91 92 dB

REF

= 2.048 V 89.5 90.5 dB

REF

= 2.5 V 91 dB

REF

= 10 μF 5 ms

4

6

Rev. 0 | Page 3 of 28

AD7622

Parameter Conditions Min Typ Max Unit

REFBUFIN Output Voltage REFBUFIN @ 25°C 1.19 V
REFBUFIN Output Resistance 6.33 kΩ

EXTERNAL REFERENCE PDREF = PDBUF = high

Voltage Range REF 1.8 2.5 AVDD + 0.1 V
Current Drain 2 MSPS throughput 150 μA

REFERENCE BUFFER PDREF = high, PDBUF = low

REFBUFIN Input Voltage Range REF = 2.048 V typ 1.05 1.2 1.30 V
REFBUFIN Input Current REFBUFIN = 1.2 V 1 nA

TEMPERATURE PIN

Voltage Output @ 25°C 278 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4.7 kΩ

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format7
Pipeline Delay

V

OL

V

OH

8

POWER SUPPLIES

Specified Performance

AVDD 2.37 2.5 2.63 V
DVDD 2.37 2.5 2.63 V
OVDD 2.30

Operating Current

11

AVD D

10

AVDD Without internal reference 23 mA
DVDD 2.5 mA

12

OVDD

Power Dissipation

With Internal Reference
Without Internal Reference

In Power-Down Mode

TEMPERATURE RANGE

11

10

10

12

13

Specified Performance T

1

When using an external reference. With the internal reference, the input range is −0.1 V to V

2

See Analog Inputs section.

3

Linearity is tested using endpoints, not best fit.

4

LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 62.5 μV.

5

See Voltage Reference Input section. These specifications do not include the error contribution from the external reference.

6

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

7

Parallel or serial 16-bit.

8

Conversion results are available immediately after completed conversion.

9

See the Absolute Maximum Ratings section.

10

In wideband and warp modes. Tested in parallel reading mode.

11

With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high.

12

With all digital inputs forced to OVDD.

13

Consult sales for extended temperature range.

−0.3 +0.6 V

1.7 5.25 V

−1 +1 μA

−1 +1 μA

I

= 500 μA 0.4 V

SINK

I

= −500 μA OVDD − 0.3 V

SOURCE

9

3.6 V
2 MSPS throughput
With internal reference 24 mA

1 mA

2 MSPS throughput 70 85 mW
2 MSPS throughput 65 80 mW
PD = high 2 μW

MIN

to T

MAX

−40 +85 °C

.

REF

Rev. 0 | Page 4 of 28

AD7622

TIMING SPECIFICATIONS

AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V

Table 3.

Parameter Symbol Min Typ Max Unit

CONVERSION AND RESET (Refer to Figure 31 and Figure 32)

Convert Pulse Width t
Time Between Conversions (Warp Mode2/Normal Mode3) t
CNVST

Low to BUSY High Delay

BUSY High All Modes (Except Master Serial Read After Convert)

Warp Mode/Normal Mode t
Aperture Delay t
End of Conversion to BUSY Low Delay t
Conversion Time (Warp Mode/Normal Mode) t
Acquisition Time (Warp Mode/Normal Mode) t
RESET Pulse Width t
RESET Low to BUSY High Delay
BUSY High Time from RESET Low

4

4

PARALLEL INTERFACE MODES (Refer to Figure 33 to Figure 36 )

CNVST

Low to Data Valid Delay (Warp Mode/Normal Mode)
Data Valid to BUSY Low Delay t
Bus Access Request to Data Valid t
Bus Relinquish Time t

MASTER SERIAL INTERFACE MODES5 (Refer to Figure 37 and Figure 38)

CS

Low to SYNC Valid Delay

CS

Low to Internal SCLK Valid Delay

CS

Low to SDOUT Delay

CNVST

Low to SYNC Delay (Warp Mode/Normal Mode)

5

SYNC Asserted to SCLK First Edge Delay t
Internal SCLK Period
Internal SCLK High
Internal SCLK Low
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
CS

High to SYNC HI-Z

CS

High to Internal SCLK HI-Z

CS

High to SDOUT HI-Z

6

6

6

6

6

6

BUSY High in Master Serial Read After Convert
CNVST

Low to SYNC Asserted Delay (Warp Mode/Normal Mode)
SYNC Deasserted to BUSY Low Delay t

SLAVE SERIAL INTERFACE MODES (Refer to Figure 40 and Figure 41)

External SCLK Setup Time t
External SCLK Active Edge to SDOUT Delay t
SDIN Setup Time t
SDIN Hold Time t
External SCLK Period t
External SCLK High t
External SCLK Low t

See Notes on next page.

= 2.5 V; all specifications T

REF

6

to T

MIN

1

2

t

3

4

5

6

7

8

9

t

38

t

39

t

10

11

12

13

t

14

t

15

t

16

t

17

18

t

19

t

20

t

21

t

22

t

23

t

24

t

25

t

26

t

27

t

28

t

29

30

31

32

33

34

35

36

37

, unless otherwise noted.

MAX

15 70

1

ns
500/667 ns
23 ns

360/485 ns
1 ns
10 ns
360/485 ns
140/182 ns
15 ns
10 ns
500 ns

360/485 ns
2 ns

20 ns
2 15 ns

10 ns
10 ns
10 ns
15/135 ns
2 ns

8 20 ns
2 ns
3 ns
1 ns
0 ns
0 ns
10 ns

10 ns
10 ns
See Table 4 ns

375/500 ns
13 ns

5 ns
1 8 ns
5 ns
5 ns

12.5 ns
5 ns
5 ns

Rev. 0 | Page 5 of 28

AD7622

1

See the Conversion Control section.

2

All timings for wideband warp mode are the same as warp mode.

3

In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.

4

See the Digital Interface section and the RESET section.

5

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

6

In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SCLK First Edge Delay Minimum t
Internal SCLK Period Minimum t
Internal SCLK Period Maximum t
Internal SCLK High Minimum t
Internal SCLK Low Minimum t
SDOUT Valid Setup Time Minimum t
SDOUT Valid Hold Time Minimum t
SCLK Last Edge to SYNC Delay Minimum t

18

19

19

20

21

22

23

24

BUSY High Width Maximum

Warp Mode t
Normal Mode t

28

28

3 3 3 3 ns
8 16 32 64 ns
20 40 60 140 ns
2 8 16 32 ns
2 8 16 32 ns
1 5 15 5 ns
0 0.5 10 28 ns
0 0.5 9 26 ns

0.64 0.92 1.47 2.57 μs

0.76 1.04 1.59 2.69 μs

500µA I

TO OUTPUT

PIN

C

L

50pF

500µA I

NOTE
IN SERIAL INT ERFACE MODES, THE S YNC, SCLK, AND
SDOUT TI MING ARE DEFINED WIT H A MAXIMUM LOAD

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

C

L

OL

1.4V

OH

Figure 3. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SCLK Outputs, C

= 10 pF

L

0.8V

t

DELAY

2V

0.8V

6023-002

Figure 4. Voltage Reference Levels for Timing

2V

t

DELAY

2V

0.8V

6023-003

Rev. 0 | Page 6 of 28

AD7622

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs/Outputs

IN+1, IN−, REF, REFBUFIN, TEMP,

INGND, REFGND to AGND

AVDD + 0.3 V to
AGND − 0.3 V

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD −0.3 V to +2.7 V
OVDD −0.3 V to +3.8 V
AVDD to DVDD ±2.8 V

AVDD, DVDD to OVDD −3.8 V to +2.8 V
Digital Inputs −0.3 V to +5.5 V
PDREF, PDBUF
Internal Power Dissipation
Internal Power Dissipation

2

3

4

±20 mA
700 mW

2.5 W
Junction Temperature 125°C
Storage Temperature Range –65°C to +125°C

1

See Analog Inputs section.

2

See Voltage Reference Input section.

3

Specification is for the device in free air:

48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W.

4

Specification is for the device in free air:

48-Lead LFCSP; θJA = 26°C/W.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 7 of 28

AD7622

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PDBUF

PDREF

REFBUFIN

TEMP

AVD D

IN+

AGND

AGNDNCIN–

REFGND

48 47 46 45 44 39 38 3743 42 41 40

1

AGND

AVD D

DGND

BYTESWAP

OB/2C

WAR P

NORMAL

SER/PAR

D0

D1

D2/DIVSCL K[0]
D3/DIVSCL K[1]

NC = NO CONNECT

PIN 1
IDENTIFIER

2

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

D4/EXT/INT

D6/INVSCLK

D5/INVSYNC

AD7622

TOP VIEW

(Not to Scale)

DVDD

OVDD

OGND

D7/RDC/SDIN

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin
No.

1, 36,

Mnemonic Type

AGND P Analog Power Ground.

1

Description

41, 42
2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V.
3 DGND P Digital Power Ground.
4 BYTESWAP DI

Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].

5

OB/

2C

DI

Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary;
when low, the MSB is inverted resulting in a twos complement output from its internal shift register.

6 WARP DI

Conversion Mode Selection. When WARP = high and
mode with slightly improved linearity and THD. When WARP = high and
warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and

a minimum conversion rate must be applied to guarantee full specified accuracy.

7

NORMAL

DI

Conversion Mode Selection. When

NORMAL = low and WARP = low, this input selects normal mode

where full accuracy is maintained independent of the minimum conversion rate.

8

SER/

PA R

DI/O Serial/Parallel Selection Input.

When SER/

PA R = high, the serial interface is selected and some bits of the data bus are used as a

serial port; the remaining data bits are high impedance outputs.

9, 10 D[0:1] DO

When SER/
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of

PA R = low, the parallel port is selected.

the interface mode.
11, 12 D[2:3] DI/O
or DIVSCLK[0:1]

When SER/

When SER/

(EXT/

PA R = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
PA R = high, serial clock division selection. When using serial master read after convert mode

INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated

serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
13 D4 DI/O

or EXT/

INT

When SER/

When SER/

PA R = low, this output is used as Bit 4 of the parallel port data output bus.
PA R = high, serial clock source select. This input is used to select the internally generated

(master) or external (slave) serial data clock.

When EXT/

When EXT/

INT = low, master mode. The internal serial clock is selected on SCLK output.
INT = high, slave mode. The output data is synchronized to an external clock signal,

gated by CS, connected to the SCLK input.

DGND

REF

36

AGND

CNVST

35

34

PD

33

RESET

32

CS

31

RD

30

DGND

29

BUSY

28

D15

27

D14

26

D13

25

D12

D9/SCLK

D10/SYNC

D8/SDOUT

06023-004

D11/RDERROR

NORMAL = high, this selects wideband warp

NORMAL = low, this selects

Rev. 0 | Page 8 of 28

AD7622

Pin
No. Mnemonic Type

14 D5 DI/O
or INVSYNC

15 D6 DI/O
or INVSCLK

16 D7 DI/O
or RDC

or SDIN

17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P

19 DVDD P Digital Power. Nominally at 2.5 V.
20 DGND P Digital Power Ground.
21 D8 DO

or SDOUT

22 D9 DI/O
or SCLK

23 D10 DO
or SYNC

24 D11 DO
or RDERROR

25 to

D[12:15] DO

28
29 BUSY DO

30 DGND P Digital Power Ground.

1

Description

When SER/
When SER/

PA R = low, this output is used as Bit 5 of the parallel port data output bus.

PA R = high, invert sync select. In serial master mode (EXT/INT = low), this input is used
to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.

When INVSYNC = high, SYNC is active low.
When SER/
When SER/

PA R = low, this output is used as Bit 6 of the parallel port data output bus.

PA R] = high, invert SCLK select. In all serial modes, this input is used to
invert the SCLK signal.

When SER/
When SER/

PA R = low, this output is used as bit 7 of the parallel port data output bus.

PA R = high, read during convert. When using serial master mode (EXT/INT = low),
RDC is used to select the read mode.

When RDC = high, the previous conversion result is output on SDOUT during conversion and
the period of SCLK changes (see the

Master Serial Interface section).

When RDC = low (read after convert), the current result can be output on SDOUT only when
the conversion is complete.

When SER/

PA R = low, serial data in. When using serial slave mode, (EXT/INT = high), SDIN could be
used as a data input to daisy-chain the conversion results from two or more ADCs onto a single
SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SCLK periods after

the initiation of the read sequence. If not used, connect to OVDD or OGND.

Input/Output Interface Digital Power. Nominally at the same supply as the supply of the
host interface (2.5 V or 3 V).

When SER/
When SER/

PA R = low, this output is used as Bit 8 of the parallel port data output bus.

PA R = high, serial data output. In serial mode, this pin is used as the serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7622 provides the

conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/2C.

In master mode, EXT/
In slave mode, EXT/

INT = low, SDOUT is valid on both edges of SCLK.

INT = high:
When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.

When SER/
When SER/

data clock input or output, depending upon the logic state of the EXT/

PA R = low, this output is used as Bit 9 of the parallel port data output bus.
PA R = high, serial clock. In all serial modes, this pin is used as the serial

INT pin. The active edge

where the data SDOUT is updated, depends on the logic state of the INVSCLK pin.
When SER/
When SER/

PA R = low, this output is used as Bit 10 of the parallel port data output bus.
PA R = high, frame synchronization. In serial master mode (EXT/INT= low),

this output is used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high

while SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low

while SDOUT output is valid.
When SER/
When SER/

PA R = low, this output is used as Bit 11 of the parallel port data output bus.

PA R = high, read error. In serial slave mode (EXT/INT = high), this output
is used as an incomplete read error flag. If a data read is started and not completed when the
current conversion is complete, the current data is lost and RDERROR is pulsed high.

Bit 12 to Bit 15 of the parallel port data output bus. These pins are always outputs, regardless of
the interface mode.

Busy Output. Transitions high when a conversion is started and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal.

2

2

Rev. 0 | Page 9 of 28

AD7622

Pin
No. Mnemonic Type

31

RD

DI

1

Description

Read Data. When

CS and RD are both low, the interface parallel or serial output bus is enabled.

32

CS

33 RESET DI

DI

Chip Select. When
CS

is also used to gate the external clock in slave serial mode.

CS and RD are both low, the interface parallel or serial output bus is enabled.

Reset Input. When high, resets the AD7622. Current conversion, if any, is aborted. Falling edge of
RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the

RESET section.

If not used, this pin can be tied to DGND.

34 PD DI

Power-Down Input. When high, power downs the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed.

35

CNVST

DI

Conversion Start. A falling edge on

CNVST puts the internal sample-and-hold into the hold state

and initiates a conversion.

37 REF AI/O Reference Output/Input.

When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally

supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal
reference and buffer. Refer to the

Voltage Reference Input section.
38 REFGND AI Reference Input Analog Ground.
39 IN− AI Differential Negative Analog Input.
40 NC No Connect.
43 IN+ AI Differential Positive Analog Input.
45 TEMP AO

Temperature Sensor Analog Output. Normally, 278 mV @ 25°C with a temperature coefficient of
1 mV/°C. This pin can be used to measure the temperature of the AD7622. See the
Temperature Sensor section.

46 REFBUFIN AI/O Internal Reference Output/Reference Buffer Input.

When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical)
band gap output on this pin, which needs external decoupling. The internal fixed gain reference
buffer uses this to produce 2.048 V on the REF pin.

When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high),
applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the

Voltage Reference Input section.

47 PDREF DI Internal Reference Power-Down Input.

When low, the internal reference is enabled.
When high, the internal reference is powered down and an external reference must been used.

48 PDBUF DI Internal Reference Buffer Power-Down Input.

When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.

1

AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.

2

With an SCLK period ≥ (2 × t32). With an SCLK period < (2 × t32), SDOUT is valid on the next rising edge with INVSCLK = low and next falling edge with INVSCLK = high.

Rev. 0 | Page 10 of 28

AD7622

TERMINOLOGY

Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.

Gain Error

The first transition (from 000…00 to 000…01) should occur for
an analog voltage ½ LSB above the nominal negative full scale
(−2.0479688 V for the ±2.048 V range). The last transition
(from 111…10 to 111…11) should occur for an analog voltage
1½ LSB below the nominal full scale (+2.0479531 V for the
±2.048 V range). The gain error is the deviation of the
difference between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.

Signal to (Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.

Spurious-Free Dynamic Range (SFDR)

The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by

ENOB = [(SINADdB − 1.76)/6.02]

Aperture Delay

Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the

CNVST

input to when

the input signal is held for a conversion.

Zero Error

The zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.

Dynamic Range

It is the ratio of the rms value of the full scale to the rms noise
measured with the inputs shorted together. The value for
dynamic range is expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Transi ent Res p ons e

The time required for the AD7622 to achieve its rated accuracy
after a full-scale step function is applied to its input.

Reference Voltage Temperature Coefficient

It is derived from the typical shift of output voltage at 25°C on a
sample of parts maximum and minimum reference output
voltage (V ) measured at T , T(25°C), and T . It is

REF MIN MAX

expressed in ppm/°C using

−

()

TCV

REF

=°

Cppm/ ×

()()

()

C25

REF

MinVMaxV

REFREF

()

−×°

TTV

MIN

MAX

10

6

where:

(Max) = Maximum V

V

REF

V

(Min) = Minimum V

REF

V

(25°C) = V

REF

T

MAX

T

MIN

= +85°C

= –40°C

REF

at 25°C

REF

REF

at T

at T

MIN

MIN

, T(25°C), or T

, T(25°C), or T

MAX

MAX

Rev. 0 | Page 11 of 28

AD7622

TYPICAL PERFORMANCE CHARACTERISTICS

1.50

1.00

0.50

0

INL (LSB)

–0.50

–1.00

–1.50

0 16384 32768 49152 65536

POSITIVE INL = +0.43 LSB
NEGATIVE INL = –0. 49 LSB

CODE

Figure 6. Integral Nonlinearity vs. Code

06023-005

1.25

1.00

0.75

0.50

0.25

0

DNL (LSB)

–0.25

–0.50

–0.75

–1.00

0 16384 32768 49152 65536

CODE

Figure 9. Differential Nonlinearity vs. Code

06023-008

250000

200000

150000

COUNTS

100000

50000

196433

27695

00

0

7FF8 7F F9 7FFA 7FFB 7FFC 7FF D 7FFE 7FFF 8000

44

CODES IN HEX

36872

σ = 0.5

V

REF

76

Figure 7. Histogram of 261,120 Conversions of a DC Input at

the Code Center (External Reference)

2.0486

2.0484

2.0482

2.0480

(V)

2.0478

REF

V

2.0476

= 2.5V

00

200000

171449

160000

120000

COUNTS

80000

50640

40000

06023-006

00

0

7FF8 7F F9 7FFA 7FFB 7FFC 7FF D 7FFE 7FFF 8000

784

CODES IN HEX

37789

V

457

σ = 0.5

= 2.048V

REF

10

06023-009

Figure 10. Histogram of 261,120 Conversions of a DC Input at

the Code Center (Internal Reference)

4

3

2

1

0

–1

GAIN ERROR

ZERO ERROR

2.0474

2.0472

2.0470
–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (° C)

Figure 8. Typical Reference Voltage Output vs. Temperature (2 Units)

Rev. 0 | Page 12 of 28

–2

ZERO ERROR, GAIN ERRO R (LSB)

–3

06023-007

–4

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (° C)

06023-010

Figure 11. Zero Error, Gain Error vs. Temperature

AD7622

–

–

0

–20

–40

–60

–80

–100

–120

–140

AMPLIT UDE (dB of Full Scale)

–160

–180

0 100 200 300 400 500 600 700 800 900 1000

FREQUENCY (kHz)

f
f

SNR = 92dB
THD = –117dB
SFDR = 103dB
SINAD = 92dB

Figure 12. FFT 20 kHz

95

93

91

89

87

85

83

SNR, SINAD (dB)

81

79

77

75

1 10 100 1000

SINAD

ENOB

FREQUENCY (kHz)

Figure 13. SNR, SINAD, and ENOB vs. Frequency

70

–80

–90

–100

–110

–120

THD, HARMONI CS (dB)

–130

THIRD HARMONIC

–140

1 10 100 1000

THD

SECOND HARMONIC

FREQUENCY (kHz)

Figure 14. THD, H armonics, and SFDR vs. Freque ncy

= 2MSPS

S

= 20.1kHz

IN

SNR

SFDR

16.0

15.6

15.2

14.8

14.4

14.0

13.6

13.2

12.8

12.4

12.0

120

110

100

90

80

70

60

50

40

30

20

06023-011

ENOB (Bits)

06023-012

SFDR (dB)

06023-013

0

f

= 2MSPS

–20

–40

–60

–80

–100

–120

–140

AMPLITUDE (dB of Full Scale)

–160

–180

0 100 200 300 400 500 600 700 800 900 1000

FREQUENCY (kHz)

S

f

=100.7kHz

IN

SNR = 91dB
THD = –100dB
SFDR = 101dB
SINAD = 90.5dB

Figure 15. FFT 100 kHz

94

93

92

91

90

89

SNR, SINAD (d B)

88

87

86

–55 –35 –15 5 25 45 65 85 105 125

SNR

SINAD

ENOB

TEMPERATURE (°C)

Figure 16. SNR, SINAD, and ENOB vs. Temperature

80

–90

–100

–110

–120

THD, HARMONICS (dB)

–130

–140

–55 –35 –15 5 25 45 65 85 105 125

SFDR

SECOND
HARMONIC

THIRD
HARMONIC

TEMPERATURE (°C)

THD

Figure 17. THD, Harmonics, and SFDR vs. Temperature

16.0

15.5

15.0

14.5

14.0

120

110

100

90

80

70

60

06023-014

ENOB (Bits)

06023-015

SFDR (dB)

06023-016

Rev. 0 | Page 13 of 28

AD7622

93.0

92.5

SINAD

92.0

91.5

SNR, SINAD REFE RRED TO FULL SCALE (dB)

91.0
–60 –50 –40 –30 –20 –10 0

SNR

INPUT LEVEL (dB)

Figure 18. SNR and SINAD vs. Input Level (Referred to Full Scale)

16

14

12

10

8

6

4

OPERATING CURRENTS (µA)

2

0
–55 125

–35–155 25456585105

TEMPERATURE (° C)

DVDD

OVDD, 3.3V

OVDD, 2.5V

AVDD

Figure 19. Power-Down Operating Currents vs. Temperature

06023-017

06023-018

100k

AVDD

10k

1k

100

OVDD = 3.3V, ALL MO DES

10

1

OPERATING CURRENTS (µA)

0.1

0.01
10 10M

100 1k 10k 100k 1M

OVDD = 2.5V, ALL MODE S

SAMPLING RATE (SPS)

DVDD

PDREF = PDBUF = HIGH

Figure 20. Operating Currents vs. Sample Rate

20

18

16

14

12

DELAY (ns)

12

10

t

8

6

4

OVDD = 2.5V @ 85°C

OVDD = 2.5V @ 2 5°C

4

50 100 150 200

OVDD = 3.3V @ 25°C

OVDD = 3.3V @ 8 5°C

C

(pF)

L

Figure 21. Typical Delay vs. Load Capacitance C

06023-019

06023-020

L

Rev. 0 | Page 14 of 28

AD7622

APPLICATIONS INFORMATION

IN+

MSB

32,768C 16,384C 4C 2C C C

REF

REFGND

32,768C 16,384C 4C 2C C C

MSB

IN–

Figure 22. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7622 is a very fast, low power, single-supply, precise
16-bit ADC using successive approximation architecture. The
AD7622 features different modes to optimize performances
according to the applications. In warp mode, the AD7622 is
capable of converting 2,000,000 samples per second (2 MSPS).

The AD7622 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.

The AD7622 can operate from a single 2.5 V supply and
interface to either 5 V, 3.3 V, or 2.5 V digital logic. It is housed
in a 48-lead LQFP package or a tiny 48-lead LFCSP package,
which combines space savings with flexibility and allows the
AD7622 to be configured as either a serial or a parallel
interface. The AD7622 is pin-to-pin compatible with other
PulSAR ADC’s and is a speed upgrade of the

AD7677.

CONVERTER OPERATION

The AD7622 is a successive approximation ADC based on a
charge redistribution DAC.
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors that are
connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. A
conversion phase is initiated once the acquisition phase is complete
and the

CNVST

input goes low. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the REFGND input. Therefore, the differential voltage between
the inputs (IN+ and IN−) captured at the end of the acquisition
phase is applied to the comparator inputs, causing the

Figure 22 shows the simplified

AGND

SWITCHES

COMP

CONTROL

CONTROL

LOGIC

CNVST

BUSY

OUTPUT
CODE

6023-021

LSB

LSB

SW+

SW–

AGND

comparator to become unbalanced. By switching each element
of the capacitor array between REFGND and REF, the comparator
input varies by binary weighted voltage steps (V
throughV

/65536). The control logic toggles these switches,

REF

REF

/2, V

REF

/4

starting with the MSB first, to bring the comparator back into a
balanced condition. After the completion of this process, the
control logic generates the ADC output code and brings BUSY
output low.

MODES OF OPERATION

The AD7622 features three modes of operations: wideband
warp, warp, and normal. Each of these modes is more suitable
for specific applications.

The wideband warp (WARP = high,
warp (WARP = high,

NORMAL

NORMAL

= low) modes allow the fastest
conversion rate of up to 2 MSPS. However, in these modes, the
full specified accuracy is guaranteed only when the time between
conversions does not exceed 1 ms. If the time between two
consecutive conversions is longer than 1 ms (for instance after
power-up), the first conversion result should be ignored. These
modes make the AD7622 ideal for applications where both high
accuracy and fast sample rates are required. Wideband warp
mode offers slightly improved linearity and THD over warp mode.

Normal mode (

NORMAL

= low, WARP = low) is the fastest
mode (1.5 MSPS) without any limitation on time between
conversions. This mode makes the AD7622 ideal for
asynchronous applications, such as data acquisition systems,
where both high accuracy and fast sample rates are required.

= high) and

Rev. 0 | Page 15 of 28

AD7622

TRANSFER FUNCTIONS

Using the OB/2C digital input, the AD7622 offers two output
codings: straight binary and twos complement. The LSB size
with V
Figure 23 and Tabl e 7 for the ideal transfer characteristic.

= 2.048 V is 2 × V

REF

111. ..111

111.. .110

111. ..10 1

ADC CODE (Straig ht Binary)

000...010

000...001

000...000

–FSR

–FSR + 0.5 L SB

Figure 23. ADC Ideal Transfer Function

ANALOG

SUPPLY (2.5V)

10µF

/ 65536 which is 62.5 μV. Refer to

REF

+FSR – 1 LSB–FSR + 1 LSB

ANALOG INPUT

100nF

+FSR – 1.5 LS B

NOTE 5

10Ω

10µF

100nF 100nF

06023-022

SUPPLY (2.5V)

Table 7. Output Codes and Ideal Input Voltages

Digital Output Code (Hex)

Description

Analog Input

= 2.048 V

V

REF

FSR −1 LSB +2.047938 V 0xFFFF

Straight
Binary

1

FSR − 2 LSB +2.047875 V 0xFFFE 0x7FFE
Midscale + 1 LSB +62.5 μV 0x8001 0x0001
Midscale 0 V 0x8000 0x0000
Midscale − 1 LSB −62.5 μV 0x7FFF 0xFFFF

−FSR + 1 LSB −2.047938 V 0x0001 0x8001

−FSR −2.048 V 0x0000

1

This is also the code for overrange analog input (V

+V

− V

+ V

REFGND

REFGND

).

).

10µF

REF

2

This is also the code for underrange analog input (V

−V

REF

DIGITAL

DIGITAL

INTERFACE

SUPPLY

(2.5V OR 3.3V)

2

− V

IN+

IN−

− V

IN+

Two s
Complement

1

0x7FFF

2

0x8000

above

below

IN−

AVDD

AGND DGND DVDD OVDD OGND

REF

C

REF

10µF

100nF

NOTE 4

NOTE 2

ANALOG

INPUT +

ANALOG

INPUT –

1. SEE ANALOG I NPUTS SECT ION.

2. THE AD8021 IS RECOM MENDED. SEE DRIVER AMPLIFIER CHO ICE SECTI ON.

3. THE CONFIG URATION SHO WN IS USI NG THE INT ERNAL REFE RENCE. SEE VOLTAGE REFERENCE INPUT SECTION.

4. A 10µF CERAMIC CAP ACITOR ( X5R, 1206 SIZ E) IS RECO MMENDED (F OR EXAMPL E, PANASONIC ECJ3YB0J106M).
SEE VOLTAGE REFERENCE INPUT SECTION.

5. OPTION, SEE POWER SUPPLY SECTION.

6. OPTION, SEE POWER-UP SECTION.

7. OPTIONAL LOW JI TTER CNVST , SEE CO NVERSION CO NTROL S ECTION.

U1

C

NOTE 2

U2

C

15Ω

2.7nF

C

NOTE 1

15Ω

2.7nF

C

NOTE 1

REFBUFIN

REFGND

IN+

IN–

NOTE 3

PD

AD7622

NOTE 3

PDREF

PDBUF

SCLK

SDOUT

BUSY

CNVST

OB/2C

SER/PAR

WARP

NORMAL

RESET

Figure 24. Typical Connection Diagram

CS

RD

50Ω

50pF

50pF

10kΩ

NOTE 6

SERIAL

PORT

NOTE 7

OVDD

D

CLOCK

MICROCONVERTER/
MICROPROCESSOR/

DSP

06023-023

Rev. 0 | Page 16 of 28

AD7622

A

V

–

TYPICAL CONNECTION DIAGRAM

Figure 24 shows a typical connection diagram for the AD7622.
Different circuitry shown in this diagram is optional and is
discussed in the following sections.

ANALOG INPUTS

Figure 25 shows an equivalent circuit of the input structure of
the AD7622.

The two diodes, D
analog inputs IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V, because this causes the diodes to become forward­biased and to start conducting current. These diodes can handle
a forward-biased current of 100 mA maximum. For instance,
these conditions could eventually occur when the input buffer’s
U1 or U2 supplies are different from AVDD. In such a case, an
input buffer with a short-circuit current limitation can be used
to protect the part.

IN+ OR IN–

AGND

The analog input of the AD7622 is a true differential structure.
By using this differential input, small signals common to both
inputs are rejected, as shown in
typical CMRR over frequency with internal and external references.

75

70

65

60

CMRR (dB)

55

50

45

1 10000

During the acquisition phase for ac signals, the impedance of
the analog inputs, IN+ and IN−, can be modeled as a parallel
combination of capacitor C
series connection of R
capacitance. R
comprised of some serial resistors and the on resistance of the

and D2, provide ESD protection for the

1

DD

D

1

C

PIN

D

2

C

R

IN

IN

Figure 25. AD7622 Simplified Analog Input

Figure 26, representing the

EXT REF

INT REF

10 100 1000

FREQUENCY (kHz)

Figure 26. Analog Input CMRR vs. Frequency

and the network formed by the

PIN

and CIN. C

IN

is typically 175 Ω and is a lumped component

IN

is primarily the pin

PIN

06023-024

06023-025

switches. C
capacitor. During the conversion phase, when the switches are
opened, the input impedance is limited to C
make a 1-pole, low-pass filter that has a typical −3 dB cutoff
frequency of 50 MHz, thereby reducing an undesirable aliasing
effect and limiting the noise coming from the inputs.

Because the input impedance of the AD7622 is very high, the
AD7622 can be directly driven by a low impedance source
without gain error. To further improve the noise filtering achieved
by the AD7622’s analog input circuit, an external 1-pole RC
filter between the amplifier’s outputs and the ADC analog
inputs can be used, as shown in
impedances significantly affect the ac performance, especially
the total harmonic distortion (THD). The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency, as shown in
Figure 27.

THD (dB)

Figure 27. THD vs. Analog Input Frequency and Source Resistance

MULTIPLEXED INPUTS

When using the full 2 MSPS throughput in multiplexed
applications for a full-scale step, the RC filter, as shown in
Figure 24, does not settle in the required acquisition time, t8.
These values are chosen to optimize the best SNR performance
of the AD7622. To use the full 2 MSPS throughput in multiplexed
applications, the RC should be adjusted to satisfy t
~ 7 × RC time constant). However, lowering R and C increases
the RC filter bandwidth and allows more noise into the AD7622,
which degrades SNR. To preserve the SNR performance in these
applications using the RC filter shown in
should be run with t

1.55 MSPS in wideband and warp modes.

is typically 12 pF and is mainly the ADC sampling

IN

. RIN and CIN

PIN

Figure 24. However, large source

60

–65

–70

–75

–80

–85

–90

–95

–100

–105

1 1000

RS = 500Ω

R

= 50Ω

R

S

= 15Ω

R

S

10 100

INPUT FREQ UENCY (kHz)

= 100Ω

S

Figure 24, the AD7622

> 280 ns; or approximately 1/(t7 + t8) ~

8

(which is

8

06023-026

Rev. 0 | Page 17 of 28

AD7622

(

DRIVER AMPLIFIER CHOICE

Although the AD7622 is easy to drive, the driver amplifier
needs to meet the following requirements:

• For multichannel, multiplexed applications, the driver

amplifier and the AD7622 analog input circuit must be
able to settle for a full-scale step of the capacitor array at an
16-bit level (0.0015%). In the amplifier’s data sheet, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection. The

AD8021 op amp, which combines ultralow noise and high

gain bandwidth, meets this settling time requirement even
when used with gains up to 13.

• The noise generated by the driver amplifier needs to be

kept as low as possible to preserve the SNR and transition
noise performance of the AD7622. The noise coming from
the driver is filtered by the AD7622 analog input circuit
1-pole, low-pass filter made by R
external filter, if one is used. The SNR degradation due
to the amplifier is

⎛
⎜

SNR

LOSS

=

20log

⎜
⎜
⎜

⎜
⎝

45

f

π

−

where:

f

is the input bandwidth of the AD7622 (50 MHz) or

–3dB

the cutoff frequency of the input RC filter shown in
(3.9 MHz), if one is used.

N is the noise factor of the amplifier (1 in buffer
configuration).

and eN− are the equivalent input voltage noise densities

e

N+

of the op amps connected to IN+ and IN−, in nV/√Hz.
This approximation can be used when the resistances used
around the amplifier are small. If larger resistances are
used, their noise contributions should also be root-sum
squared.

For instance, when using op amps with an equivalent input
noise density of 2.1 nV/√Hz, such as the
noise gain of 1 when configured as a buffer, degrades the
SNR by only 0.1 dB when using the RC filter in
and by 1.3 dB without it.

• The driver needs to have a THD performance suitable to

that of the AD7622.

Figure 14 gives the THD vs. frequency

that the driver should exceed.

and CIN or by the

IN

45

f

π

−

3dB

() ()

Ne

+

N

2

3dB

++

2

Ne

222

−

N

Figure 24

AD8021, with a

Figure 24,

⎞
⎟

⎟
⎟
⎟

⎟
⎠

The AD8021 meets these requirements and is appropriate for
almost all applications. The

AD8021 needs a 10 pF external

compensation capacitor that should have good linearity as an
NPO ceramic or mica type. Moreover, the use of a noninverting
1 gain arrangement is recommended and helps to obtain the
best signal-to-noise ratio.

AD8022 can also be used when a dual version is needed

The
and a gain of 1 is present. The

AD829 is an alternative in

applications where high frequency (above 100 kHz) performance is
not required. In applications with a gain of 1, an 82 pF
compensation capacitor is required. The

AD8610 is an option

when low bias current is needed in low frequency applications.

Refer to

Table 8 for some recommended op amps.

Table 8. Recommended Driver Amplifiers

Amplifier Typical Application

ADA4841-x

Very low noise, low distortion, low power,

low frequency

AD829 Very low noise, low frequency
AD8021 Very low noise, high frequency
AD8022 Very low noise, high frequency, dual
AD8610/AD8620 Low bias current, low frequency, single/dual

Single-to-Differential Driver

For applications using unipolar analog signals, a single-ended­to-differential driver, as shown in

Figure 28, allows for a
differential input into the part. This configuration, when
provided an input signal of 0 to V
±V

with midscale at V

REF

/2. The 1-pole filter using R = 15 Ω

REF

, produces a differential

REF

and C = 2.7nF provides a corner frequency of 3.9 MHz.

If the application can tolerate more noise, the

AD8139

differential driver can be used.

U1

ANALOG INPUT

UNIPOLAR 0VTO 2.048V)

5kΩ

5kΩ

100nF

Figure 28. Single-Ended-to-Differential Driver Circuit

AD8021

10pF

590Ω

590Ω

U2

AD8021

10pF

(Internal Reference Buffer Used)

15Ω

2.7nF

15Ω

2.7nF

IN+

AD7622

IN–

10µF

REF

06023-041

Rev. 0 | Page 18 of 28

AD7622

VOLTAGE REFERENCE INPUT

The AD7622 allows the choice of either a very low temperature
drift internal voltage reference, an external 1.2 V reference that
can be buffered using the internal reference buffer, or an
external reference.

Unlike many ADCs with internal references, the internal
reference of the AD7622 provides excellent performance and
can be used in almost all applications.

Internal Reference (PDBUF = Low, PDREF = Low)

To use the internal reference, the PDREF and PDBUF inputs
must both be low. This produces a 1.2 V band gap output on
REFBUFIN, which is amplified by the internal buffer and
results in a 2.048 V reference on the REF pin.

The internal reference is temperature compensated to 2.048 V ±
10 mV. The reference is trimmed to provide a typical drift of
8 ppm/°C. This typical drift characteristic is shown in

The output resistance of REFBUFIN is 6.33 kΩ (minimum)
when the internal reference is enabled. It is necessary to
decouple this with a ceramic capacitor greater than 100 nF.
Therefore, the capacitor provides an RC filter for noise reduction.

Because the output impedance of REFBUFIN is typically

6.33 kΩ, relative humidity (among other industrial contaminates)
can directly affect the drift characteristics of the reference.
Typically, a guard ring is used to reduce the effects of drift
under such circumstances. However, because the AD7622 has a
fine lead pitch, guarding this node is not practical. Therefore, in
these industrial and other types of applications, it is recommended
to use a conformal coating, such as Dow Corning® 1-2577 or
HumiSeal® 1B73.

External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High)

To use an external reference along with the internal buffer,
PDREF should be high and PDBUF should be low. This powers
down the internal reference and allows an external 1.2 V
reference to be applied to REFBUFIN, producing 2.048 V
(typically) on the REF pin.

External 2.5 V Reference (PDBUF = High, PDREF = High)

To use an external 2.5 V reference directly on the REF pin,
PDREF and PDBUF should both be high.

For improved drift performance, an external reference, such as
the

AD780, ADR421, ADR431, or ADR441, can be used.

Figure 8.

The advantages of directly using the external voltage reference are:

• The SNR and dynamic range improvement (about 1.7 dB)

resulting from the use of a reference voltage very close to
the supply (2.5 V) instead of a typical 2.048 V reference
when the internal reference is used. This is calculated by

048.2

=

• The power savings when the internal reference is powered

down (PDREF high).

PDREF and PDBUF power down the internal reference and
the internal reference buffer, respectively. The input current
of PDREF and PDBUF should never exceed 20 mA. This can
occur when the driving voltage is above AVDD (for instance, at
power-up). In this case, a 125 Ω series resistor is recommended.

⎜
⎝

⎛

log20SNR

⎞
⎟

50.2

⎠

Reference Decoupling

Whether using an internal or external reference, the AD7622
voltage reference input (REF) has a dynamic input impedance;
therefore, it should be driven by a low impedance source with
efficient decoupling between the REF and REFGND inputs.
This decoupling depends on the choice of the voltage reference
but usually consists of a low ESR capacitor connected to REF
and REFGND with minimum parasitic inductance. A 10 μF
(X5R, 1206 size) ceramic chip capacitor (or 47 μF tantalum
capacitor) is appropriate when using either the internal
reference or one of the recommended reference voltages.

The placement of the reference decoupling is also important to
the performance of the AD7622. The decoupling capacitor
should be mounted on the same side as the ADC right at the
REF pin with a thick PCB trace. The REFGND should also connect
to the reference decoupling capacitor with the shortest distance.

For applications that use multiple AD7622 devices, it is more
effective to use an external reference with the internal reference
buffer to buffer the reference voltage. However, because the
reference buffers are not unity gain, ratiometric, simultaneously
sampled designs should use an external reference and external
buffer, such as the
same reference level for all converters.

The voltage reference temperature coefficient (TC) directly
impacts full scale; therefore, in applications where full-scale
accuracy matters, care must be taken with the TC. For instance,
a ±15 ppm/°C TC of the reference changes full scale by ±1 LSB/°C.

Note that V
input range is defined in terms of V
increase the range to 0 V to 2.8 V with an AVDD = 2.7 V.

AD8031/AD8032; therefore, preserving the

can be increased to AVDD + 0.1 V. Because the

REF

, this would essentially

REF

Rev. 0 | Page 19 of 28

AD7622

Temperature Sensor

The TEMP pin measures the temperature of the AD7622. To
improve the calibration accuracy over the temperature range,
the output of the TEMP pin is applied to one of the inputs of
the analog switch (such as,

ADG779), and the ADC itself is

used to measure its own temperature. This configuration is
shown in

Figure 29.

ANALOG I NPUT

(UNIPOLAR)

IN+

TEMP

AD7622

TEMPERATURE
SENSOR

ADG779

AD8021

Figure 29. Use of the Temperature Sensor

C

C

06023-027

POWER SUPPLY

The AD7622 uses three sets of power supply pins: an analog

2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.3 V
and 5.25 V. To reduce the number of supplies needed, the digital
core (DVDD) can be supplied through a simple RC filter from
the analog supply, as shown in

Figure 24.

A simple power-on reset circuit, as shown in
used to minimize the digital interface. As OVDD powers up, the
capacitor is shorted and brings RESET high; it is then charged
returning RESET to low. However, this circuit only works when
powering up the AD7622 because the power-down mode
(PD = high) does not power down any of the supplies and as a
result, RESET is low.

It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, drive the digital inputs close to
the power rails (that is, OVDD and OGND).

CONVERSION CONTROL

The AD7622 is controlled by the

CNVST

on

is all that is necessary to initiate a conversion.
Detailed timing diagrams of the conversion process are shown
in

Figure 31. Once initiated, it cannot be restarted or aborted,
even by the power-down input, PD, until the conversion is
complete. The
RD

signals.

CNVST

signal operates independently of CS and

t

1

CNVST

t

2

Figure 24, can be

input. A falling edge

Power Sequencing

The AD7622 is independent of power supply sequencing and
thus free from supply induced voltage latch-up. In addition, it is
very insensitive to power supply variations over a wide
frequency range, as shown in

65.0

62.5

60.0

57.5

55.0

PSRR (dB)

52.5

50.0

47.5

45.0
1 10000

10 100 1000

Figure 30. PSRR vs. Frequency

Figure 30.

EXT REF

INT REF

FREQUENCY (kHz)

06023-029

Power-Up

At power-up, or when returning to operational mode from the
power-down mode (PD = high), the AD7622 engages an
initialization process. During this time, the first 128 conversions
should be ignored or the RESET input could be pulsed to
engage a faster initialization process. Refer to the
Interface

section for RESET and timing details.

Digital

CNVST

BUSY

t

3

t

5

MODE

For optimal performance, the rising edge of
occur after the maximum

t

4

t

6

CONVERT ACQUIREACQUIRE CONVERT

t

7

Figure 31. Basic Conversion Timing

CNVST

t

8

CNVST

should not

low time, t1, or until the end

of conversion.

Although

CNVST

is a digital signal, it should be designed with

special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.

The

trace should be shielded with ground and a low

CNVST

value serial resistor (for example, 50 Ω) termination should be
added close to the output of the component that drives this line.
In addition, a 50 pF capacitor is recommended to further reduce
the effects of overshoot and undershoot as shown in

For applications where SNR is critical, the

CNVST

Figure 24.

signal should

have very low jitter. This can be achieved by using a dedicated
oscillator for

CNVST

high frequency, low jitter clock, as shown in

generation, or by clocking

Figure 24.

CNVST

with a

06023-030

Rev. 0 | Page 20 of 28

AD7622

INTERFACES

DIGITAL INTERFACE

The AD7622 has a versatile digital interface that can be set up
as either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The AD7622
digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic
with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic
high output voltage. In most applications, the OVDD supply pin
of the AD7622 is connected to the host system interface 2.5 V
or 3.3 V digital supply. By using the OB/
twos complement or straight binary coding can be used.

The two signals

CS

and RD control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually,

CS

allows the selection of each AD7622 in

multicircuit applications and is held low in a single AD7622

RD

design.

is generally used to enable the conversion result on

the data bus.

RESET

The RESET input is used to reset the AD7622 and generate a
fast initialization. A rising edge on RESET aborts the current
conversion (if any) and tristates the data bus. The falling edge of
RESET clears the data bus and engages the initialization process
indicated by pulsing BUSY high. Conversions can take place
after the falling edge of BUSY. Refer to
timing details.

t

9

RESET

2C

input pin, either

Figure 32 for the RESET

CS = RD = 0

CNVST

BUSY

DATA

BUS

t

t

1

t

10

t

3

PREVIOUS CONVERSI ON DATA NEW DATA

4

t

11

Figure 33. Master Parallel Data Timing for Reading (Continuous Read)

Slave Parallel Interface

In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in

Figure 34 and
Figure 35, respectively. When the data is read during the
conversion, it is recommended that it is read-only during the
first half of the conversion phase. This avoids any potential
feedthrough between voltage transients on the digital interface
and the most critical analog conversion circuitry.

CS

RD

BUSY

04761-032

CNVST

DATA

BUSY

t

38

t

39

t

8

Figure 32. RESET Timing

PARALLEL INTERFACE

The AD7622 is configured to use the parallel interface when

PA R

SER/

Master Parallel Interface

Data can be continuously read by tying CS and RD low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications, unless the device is held in RESET.
Figure 33 details the timing for this mode.

is held low.

Rev. 0 | Page 21 of 28

DATA

BUS

t

12

CURRENT

CONVERSION

t

13

04761-033

Figure 34. Slave Parallel Data Timing for Reading (Read After Convert)

06023-031

CS = 0

CNVST,

BUSY

DATA

RD

BUS

t

3

t

12

t

1

PREVIOUS

CONVERSION

t

4

t

13

06023-042

Figure 35. Slave Parallel Data Timing for Reading (Read During Convert)

AD7622

8-Bit Interface (Master or Slave)

The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in

Figure 36, when BYTESWAP is low, the LSB byte is
output on D[7:0] and the MSB is output on D[15:8]. When
BYTESWAP is high, the LSB and MSB bytes are swapped, and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0]. This
interface can be used in both master and slave parallel reading
modes.

MASTER SERIAL INTERFACE

Internal Clock

The AD7622 is configured to generate and provide the serial
data clock SCLK when the EXT/

also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted. Depending on the state of the read during
convert input, RDC/SDIN, the data can be read after each
conversion or during the following conversion.
Figure 38 show detailed timing diagrams of these two modes.

pin = low. The AD7622

INT

Figure 37 and

CS

RD

BYTESWAP

PINS D[15:8]

PINS D[7:0]

HI-Z

HI-Z

Figure 36. 8-Bit and 16-Bit Parallel Interface

HIGH BYTE LOW BYTE

t

12

LOW BYTE HIGH BYTE

t

12

t

13

HI-Z

HI-Z

SERIAL INTERFACE

The AD7622 is configured to use the serial interface when
SER/

first, on the SDOUT pin. This data is synchronized with the
16 clock pulses provided on the SCLK pin. The output data is
valid on both the rising and falling edge of the data clock.

= high. The AD7622 outputs 16 bits of data, MSB

PA R

Usually, because the AD7622 is used with a fast throughput, the
master read during conversion mode, RDC/SDIN = high, is the
most recommended serial mode. In this mode, the serial clock
and data toggle at appropriate instants, minimizing potential
feedthrough between digital activity and critical conversion
decisions. In this mode, the SCLK period changes because the
LSBs require more time to settle and the SCLK is derived from the
SAR conversion cycle.

In read after conversion mode, RDC/SDIN = low, it should be

06023-034

noted that unlike other modes, the BUSY signal returns low
after the 16 data bits are pulsed out and not at the end of the
conversion phase, resulting in a longer BUSY width. As a result,
the maximum throughput cannot be achieved in this mode.

In addition, in read after convert mode, the SCLK frequency
can be slowed down to accommodate different hosts using the
DIVSCLK[1:0] inputs. Refer to

Table 4 for the SCLK timing

details when using these inputs.

Rev. 0 | Page 22 of 28

AD7622

S

CS, RD

CNVST

BUSY

SYNC

SCLK

DOUT

EXT/INT = 0

t

3

t

29

t

14

t

20

t

15

X

t

16

t

22

RDC/SDIN = 0 INVSCLK = INVSYNC = 0

t

28

t

30

t

18

t

19

t

21

1 2 3 14 15 16

D15 D14 D2 D1 D0

t

23

t

24

t

25

t

26

t

27

06023-035

Figure 37. Master Serial Data Timing for Reading (Read After Convert)

CS, RD

CNVST

BUSY

EXT/INT = 0

t

1

t

3

RDC/SDIN = 1 INVSCLK = I NVSYNC = 0

SYNC

SCLK

SDOUT

t

17

t

14

t

15

t

18

t

16

t

22

t

19

t20t

21

123 141516

D15 D14 D2 D1 D0X

t

23

t

24

t

25

t

26

t

27

06023-036

Figure 38. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)

Rev. 0 | Page 23 of 28

AD7622

SLAVE SERIAL INTERFACE

External Clock

The AD7622 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/

INT

pin is

held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by

are both low, the data can be read after each conversion or

RD

. When CS and

CS

during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive.

Figure 40 and Figure 41 show the detailed timing

diagrams of these methods.

While the AD7622 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7622 provides error correction circuitry
that can correct for an improper bit decision made during
the first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided,
a discontinuous clock is toggled only when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.

Finally, in this mode only, the AD7622 provides a daisy-chain
feature using the RDC/SDIN pin for cascading multiple converters
together. This feature is useful for reducing component count
and wiring connections when desired, as, for instance, in
isolated multiconverter applications.

An example of the concatenation of two devices is shown in
Figure 39. Simultaneous sampling is possible by using a
common

CNVST

signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite to the one used to
shift out the data on SDOUT. Therefore, the MSB of the
upstream converter just follows the LSB of the downstream
converter on the next SCLK cycle.

BUSY
OUT

BUSY

AD7622

#1

(DOWNSTREAM)

SDOUTRDC/SDIN

CNVST

SCLK

CS

DATA
OUT

AD7622

(UPSTREAM)

RDC/SDIN

BUSY

#2

SDOUT

CNVST

CS

SCLK

External Discontinuous Clock Data Read After Conversion

Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave
modes.

Figure 40 shows the detailed timing diagrams of this
method. After a conversion is complete, indicated by BUSY
returning low, the conversion result can be read while both

are low. Data is shifted out MSB first with 16 clock

and

RD

CS

pulses and is valid on the rising and falling edges of the clock.

Among the advantages of this method is the fact that conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 80 MHz, which accommodates both the slow digital host
interface and the fast serial reading.

It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion is initiated.
In this reading mode, it is recommended to pause digital
activity just prior to initiating a conversion (SCLK should be
held high or low). Once the conversion has begun, the reading
can continue. In addition, in this mode, the use of a slower
clock speed can be used to read the data because the total
reading time is the acquisition time, t
time, t

(t8 + ½ × t7, see the External Clock Data Read During

7

Previous Conversion

section).

+ half of the conversion

8

SCLK IN

CS IN

CNVST IN

Figure 39. Two AD7622 Devices in a Daisy-Chain Configuration

06023-037

External Clock Data Read During Previous Conversion

Figure 41 shows the detailed timing diagrams of this method.
During a conversion, while

CS

and RD are both low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses and is valid on both the rising
and falling edge of the clock. The 16 bits have to be read before
the current conversion is complete; otherwise, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain
feature in this mode, and the RDC/SDIN input should always
be tied either high or low.

To reduce performance degradation due to digital activity, a fast
discontinuous clock (at least 60 MHz when normal mode is
used, or 80 MHz when warp mode is used) is recommended to
ensure that all the bits are read during the first half of the SAR
conversion phase.

If the maximum throughput is not used, thus allowing more
acquisition time, then the use of a slower clock speed can be
used to read the data.

Rev. 0 | Page 24 of 28

AD7622

S

S

CS

BUSY

SCLK

DOUT

SDIN

EXT/INT = 1

t

35

t36t

37

123 1415161718

t

31

X

D15 D14 D1

t

16

X15 X14 X13 X1 X0 Y15 Y14

t

33

t

32

D13

t

34

INVSCLK = 0

RD = 0

D0

X15 X14

06023-038

Figure 40. Slave Serial Data Timing for Reading (Read After Convert)

CS

CNVST

EXT/INT = 1 INVSCLK = 0

RD = 0

BUSY

t

SCLK

DOUT

3

t

16

t

35

t36t

37

123 141516

t

31

X

D15 D14 D13

t

32

D1

D0

06023-039

Figure 41. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)

Rev. 0 | Page 25 of 28

AD7622

MICROPROCESSOR INTERFACING

The AD7622 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and ac signal processing
applications interfacing to a digital signal processor. The
AD7622 is designed to interface with a parallel 8-bit or 16-bit
wide interface or with a general-purpose serial port or I/O ports
on a microcontroller. A variety of external buffers can be used
with the AD7622 to prevent digital noise from coupling into the
ADC. The
of the AD7622 with the ADSP-219x SPI-equipped DSP.

SPI Interface (ADSP-219x) section illustrates the use

SPI Interface (ADSP-219x)

Figure 42 shows an interface diagram between the AD7622 and
an SPI-equipped DSP, the ADSP-219x. To accommodate the
slower speed of the DSP, the AD7622 acts as a slave device and
data must be read after conversion. This mode also allows the
daisy-chain feature. The convert command can be initiated in
response to an internal timer interrupt. The 16-bit output data
are read with three SPI byte access. The reading process can be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial peripheral
interface (SPI) on the ADSP-219x is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock phase
bit (CPHA) = 1, and the SPI interrupt enable (TIMOD) = 00 by
writing to the SPI control register (SPICLTx). It should be noted
that to meet all timing requirements, the SPI clock should be
limited to 17 Mbps, allowing it to read an ADC result in less
than 1 μs. When a higher sampling rate is desired, it is
recommended to use one of the parallel interface modes.

DVDD

AD7622

MODE0

BUSY

MODE1

EXT/INT

RD

INVSCLK

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 42. Interfacing the AD7622 to ADSP-219x

CS

SDOUT

SCLK

CNVST

ADSP-219x

PFx

SPIxSEL (PFx)

MISOx

SCKx

PFx OR TFSx

1

06023-040

Rev. 0 | Page 26 of 28

AD7622

APPLICATION HINTS

LAYOUT

While the AD7622 has very good immunity to noise on the
power supplies, exercise care with the grounding layout. To
facilitate the use of ground planes that can be easily separated,
design the printed circuit board that houses the AD7622 so that
the analog and digital sections are separated and confined to
certain areas of the board. Digital and analog ground planes
should be joined in only one place, preferably underneath the
AD7622, or as close as possible to the AD7622. If the AD7622 is
in a system where multiple devices require analog-to-digital
ground connections, the connections should still be made at
one point only, a star ground point, established as close as
possible to the AD7622.

To prevent coupling noise onto the die, avoid radiating noise,
and reduce feedthrough:

• Do not run digital lines under the device.

• Run the analog ground plane under the AD7622.

The DVDD supply of the AD7622 can be either a separate
supply or come from the analog supply, AVDD, or from the
digital interface supply, OVDD. When the system digital supply
is noisy, or fast switching digital signals are present, and no
separate supply is available, it is recommended to connect the
DVDD digital supply to the analog supply AVDD through an
RC filter, and to connect the system supply to the interface
digital supply OVDD and the remaining digital circuitry. Refer
to

Figure 24 for an example of this configuration. When DVDD
is powered from the system supply, it is useful to insert a bead
to further reduce high frequency spikes.

The AD7622 has four different ground pins: REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage and,
because it carries pulsed currents, should have a low impedance
return to the reference. AGND is the ground to which most
internal ADC analog signals are referenced; it must be connected
with the least resistance to the analog ground plane. DGND
must be tied to the analog or digital ground plane depending on the
configuration. OGND is connected to the digital system ground.

• Shield fast switching signals, like

digital ground to avoid radiating noise to other sections of
the board, and never run them near analog signal paths.

• Avoid crossover of digital and analog signals.

• Run traces on different but close layers of the board, at right

angles to each other, to reduce the effect of feedthrough
through the board.

The power supply lines to the AD7622 should use as large a
trace as possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decoupling is
also important to lower the impedance of the supplies presented
to the AD7622, and to reduce the magnitude of the supply
spikes. Decoupling ceramic capacitors, typically 100 nF, should
be placed on each of the power supplies pins, AVDD, DVDD,
and OVDD. The capacitors should be placed close to, and
ideally right up against, these pins and their corresponding
ground pins. Additionally, low ESR 10 μF capacitors should be
located in the vicinity of the ADC to further reduce low
frequency ripple.

CNVST

or clocks, with

The layout of the decoupling of the reference voltage is
important. To minimize parasitic inductances, place the
decoupling capacitor close to the ADC and connect it with
short, thick traces.

EVALUATING THE AD7622 PERFORMANCE

A recommended layout for the AD7622 is outlined in the
documentation of the EVAL-AD7622-CB evaluation board for
the AD7622. The evaluation board package includes a fully
assembled and tested evaluation board, documentation, and
software for controlling the board from a PC via the

CONTROL BRD3

.

EVAL-

Rev. 0 | Page 27 of 28

AD7622

OUTLINE DIMENSIONS

0.30

0.23

0.18
PIN 1

48

INDICATOR

1

BSC SQ

PIN 1
INDICATOR

7.00

0.60 MAX

37

36

0.60 MAX

1.00

0.85

0.80

12° MAX

SEATING
PLANE

TOP

VIEW

Figure 43. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

(BOTTOM VIEW)

25

24

EXPOSED

P

A

D

5.50
REF

6.75

BSC SQ

0.50

0.40

0.30

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

0.20 REF

0.05 MAX

0.02 NOM
COPLANARIT Y

0.08

7 mm × 7 mm Body, Very Thin Quad (CP-48-1)

Dimensions shown in millimeters

0.75

0.60

0.45

0.20

0.09
7°

3.5°
0°

0.08 MAX
COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026-BBC

1.60
MAX

VIEW A

48

1

12

13

0.50
BSC

LEAD PITCH

BSC SQ

PIN 1

TOP VIEW

(PINS DOWN)

Figure 44. 48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)

Dimensions shown in millimeters

5.25

5.10 SQ

4.95

12

13

9.00

0.25 MIN

PADDLE CONNECTED TO AGND.
THIS CO NNECT ION I S NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES.

37

36

7.00

BSC SQ

25

24

0.27

0.22

0.17

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7622BCPZ
AD7622BCPZRL
AD7622BSTZ
AD7622BSTZRL
EVAL-AD7622CB
EVAL-CONTROL BRD3

1

Z = Pb-free part.

2

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes.

3

This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators.

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06023–0–6/06(0)

1

1

1

1

2

3

−40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1

−40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1

−40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48

−40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48
Evaluation Board
Controller Board

T

Rev. 0 | Page 28 of 28

TTT