Datasheet AD7607 Datasheet (ANALOG DEVICES)

8-Channel DAS with 14-Bit, Bipolar Input,

A

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FEATURES

8 simultaneously sampled inputs
True bipolar analog input ranges: ±10 V, ±5 V
Single 5 V analog supply and 2.3 V to 5.25 V V
Fully integrated data acquisition solution

Analog input clamp protection
Input buffer with 1 MΩ analog input impedance
Second-order antialiasing analog filter
On-chip accurate reference and reference buffer
14-bit ADC with 200 kSPS on all channels

Flexible parallel/serial interface

SPI/QSPI™/MICROWIRE™/DSP compatible
Pin-compatible solutions from 14 bits to 18 bits
Performance

7 kV ESD rating on analog input channels

Fast throughput rate: 200 kSPS for all channels

85.5 dB SNR at 50 kSPS

INL ±0.25 LSB, DNL ±0.25 LSB

Low power: 100 mW at 200 kSPS

Standby mode: 25 mW typical
64-lead LQFP package

DRIVE

Simultaneous Sampling ADC

AD7607

APPLICATIONS

Power-line monitoring and protection systems
Multiphase motor control
Instrumentation and control systems
Multiaxis positioning systems
Data acquisition systems (DAS)

Table 1. High Resolution, Bipolar Input, Simultaneous
Sampling DAS Solutions

Single-Ended

Resolution

Inputs

18 Bits AD7608 8
16 Bits AD7606 8
AD7606-6 6
AD7606-4 4
14 Bits AD7607 8

Number of Simultaneous
Sampling Channels

FUNCTIONAL BLOCK DIAGRAM

V

CC

CC

T/H

T/H

T/H

T/H

T/H

T/H

8:1

MUX

REGCAP

2.5V
LDO

14-BIT

SAR

REGCAP

2.5V
LDO

DIGI TAL

FILTER

REFCAPB

PARALLEL/

SERIAL

INTERFACE

REFCAPA

SERIAL

PARALLEL

2.5V
REF

REFIN/REFOUT

REF SELECT

AGND

OS 2

OS 1

OS 0

D

A

OUT

D

B

OUT

RD/SCLK

CS

PAR/SER/ BYTE SEL

V

DRIVE

DB[15:0]

AD7607

T/H

T/H

CONVST A CONVST B RESET RANGE

CLK OSC

CONTROL

INPUTS

BUSY

FRSTDATA

08096-001

Figure 1.

V1GND

V2GND

V3GND

V4GND

V5GND

V6GND

V7GND

V8GND

AV

R

1MΩ

1MΩ

1MΩ

1MΩ

1MΩ

1MΩ

1MΩ

1MΩ

1MΩ

1MΩ

1MΩ

1MΩ

1MΩ

1MΩ

1MΩ

1MΩ

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

FB

FB

FB

FB

FB

FB

FB

FB

FB

FB

FB

FB

FB

FB

FB

FB

SECOND-

ORDER LPF

SECOND-

ORDER LPF

SECOND-

ORDER LPF

SECOND-

ORDER LPF

SECOND-

ORDER LPF

SECOND-

ORDER LPF

SECOND-

ORDER LPF

SECOND-

ORDER LPF

AGND

V1

CLAMP

CLAMP

V2

CLAMP

CLAMP

V3

CLAMP

CLAMP

V4

CLAMP

CLAMP

V5

CLAMP

CLAMP

V6

CLAMP

CLAMP

V7

CLAMP

CLAMP

V8

CLAMP

CLAMP

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

AD7607

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications ..................................................................................... 4

Timing Specifications .................................................................. 6

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 14

Terminology .................................................................................... 18

Theory of Operation ...................................................................... 19

Converter Details ........................................................................ 19

Analog Input ............................................................................... 19

ADC Transfer Function ............................................................. 20

Internal/External Reference ...................................................... 21

Typical Connection Diagram ................................................... 22

Power-Down Modes .................................................................. 22

Conversion Control ................................................................... 23

Digital Interface .............................................................................. 24

Parallel Interface (

Parallel Byte Interface (

Serial Interface (

Reading During Conversion ..................................................... 25

Digital Filter ................................................................................ 26

Layout Guidelines ........................................................................... 29

Outline Dimensions ....................................................................... 31

Ordering Guide .......................................................................... 31

PA R

/SER/BYTE SEL = 0) .......................... 24

PA R

/SER/BYTE SEL = 1, DB15 = 1) .. 24

PA R

/SER/BYTE SEL = 1) ............................. 24

REVISION HISTORY

7/10—Rev. 0 to Rev. A

Change to Table 1 .............................................................................. 1

7/10—Revision 0: Initial Version

Rev. A | Page 2 of 32

AD7607

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GENERAL DESCRIPTION

The AD76071 is a 14-bit, simultaneous sampling, analog-to­digital data acquisition system (DAS). The part contains analog
input clamp protection; a second-order antialiasing filter; a track­and-hold amplifier; a 14-bit charge redistribution, successive
approximation analog-to-digital converter (ADC); a flexible
digital filter; a 2.5 V reference and reference buffer; and high
speed serial and parallel interfaces.

The AD7607 operates from a single 5 V supply and can accom­modate ±10 V and ±5 V true bipolar input signals while sampling
at throughput rates of up to 200 kSPS for all channels. The input

1

Patent pending.

clamp protection circuitry can tolerate voltages of up to ±16.5 V.
The AD7607 has 1 MΩ analog input impedance, regardless of
sampling frequency. The single supply operation, on-chip
filtering, and high input impedance eliminate the need for
driver op amps and external bipolar supplies. The AD7607
antialiasing filter has a 3 dB cutoff frequency of 22 kHz and
provides 40 dB antialias rejection when sampling at 200 kSPS.
The flexible digital filter is pin driven and can be used to
simplify external filtering.

Rev. A | Page 3 of 32

AD7607

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SPECIFICATIONS

V

= 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, V

REF

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE fIN = 1 kHz sine wave, unless otherwise noted

Signal-to-(Noise + Distortion) (SINAD)2, 3No oversampling; ±10 V range 84 84.5 dB
No oversampling; ±5 V range 83.5 84.5 dB
Signal-to-Noise Ratio (SNR)2 Oversampling by 4, fIN = 130 Hz 85.5 dB
No oversampling 84.5 dB
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)

2

−107 −95 dB

2

−108 dB

Intermodulation Distortion (IMD)2 fa = 1 kHz, fb = 1.1 kHz

Second-Order Terms −110 dB
Third-Order Terms −106 dB

Channel-to-Channel Isolation

2

f

on unselected channels up to 160 kHz −95 dB

IN

ANALOG INPUT FILTER

Full Power Bandwidth −3 dB, ±10 V range 23 kHz

−3 dB, ±5 V range 15 kHz

−0.1 dB, ±10 V range 10 kHz

−0.1 dB, ±5 V range 5 kHz
t

GROUP DELAY

±10 V Range 11 µs

±5 V Range 15 µs

DC ACCURACY

Resolution No missing codes 14 Bits
Differential Nonlinearity
Integral Nonlinearity
Positive/Negative Full-Scale Error

2

±0.25 ±0.95 LSB

2

±0.25 ±0.5 LSB

2, 5

External reference ±2 ±9 LSB

Internal reference ±2 LSB
Positive Full-Scale Error Drift

2

External reference ±2 ppm/°C

Internal reference ±7 ppm/°C
Negative Full-Scale Error Drift External reference ±4 ppm/°C
Internal reference ±8 ppm/°C
Positive/Negative Full-Scale Error

Matching

2

±10 V range 2 8 LSB

±5 V range 4 10 LSB

2, 6

Bipolar Zero Code Error

±10 V range ±0.5 ±2 LSB

±5 V range ±1 ±3.5 LSB

2

Bipolar Zero Code Error Drift

±10 V range 10 µV/°C
±5 V range 5 µV/°C
Bipolar Zero Code Error Matching ±10 V range 1 2.5 LSB
±5 V range 3 6 LSB
Total Unadjusted Error (TUE) ±10 V range ±0.5 LSB
±5 V range ±1 LSB

ANALOG INPUT

Input Voltage Ranges RANGE = 1 ±10 V
RANGE = 0 ±5 V
Input Current +10 V 5.4 µA
+5 V 2.5 µA
Input Capacitance

7

5 pF
Input Impedance See the Analog Input section 1 MΩ

= 2.3 V to 5.25 V, f

DRIVE

= 200 kSPS, TA = T

SAMPLE

MIN

to T

, unless otherwise noted.1

MAX

4

Rev. A | Page 4 of 32

AD7607

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Parameter Test Conditions/Comments Min Typ Max Unit

REFERENCE INPUT/OUTPUT

Reference Input Voltage Range 2.475 2.5 2.525 V
DC Leakage Current ±1 µA
Input Capacitance
Reference Output Voltage REFIN/REFOUT

Reference Temperature Coefficient ±10 ppm/°C

LOGIC INPUTS

Input High Voltage (V
Input Low Voltage (V
Input Current (IIN) ±2 µA
Input Capacitance (CIN)7 5 pF

LOGIC OUTPUTS

Output High Voltage (VOH) I
Output Low Voltage (VOL) I
Floating-State Leakage Current ±1 ±20 µA
Floating-State Output Capacitance
Output Coding Twos complement

CONVERSION RATE

Conversion Time All eight channels included; see Tabl e 3 4 µs
Track-and-Hold Acquisition Time 1 µs
Throughput Rate All eight channels included 200 kSPS

POWER REQUIREMENTS

AVCC 4.75 5.25 V
V

2.3 5.25 V

DRIVE

I

Digital inputs = 0 V or V

TOTAL

Normal Mode (Static) 16 22 mA
Normal Mode (Operational)
Standby Mode 5 8 mA
Shutdown Mode 2 6 µA

Power Dissipation

Normal Mode (Static) 80 115.5 mW
Normal Mode (Operational) 100 142 mW
Standby Mode 25 42 mW
Shutdown Mode 10 31.5 µW

1

Temperature range for the B version is −40°C to +85°C.

2

See the Terminology section.

3

This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with V

and THD typically reduces by 3 dB.

4

LSB means least significant bit. With ±5 V input range, 1 LSB = 610.35 µV. With ±10 V input range, 1 LSB = 1.22 mV.

5

This specification includes the full temperature range variation and contribution from the internal reference buffer but does not include the error contribution from

the external reference.

6

Bipolar zero code error is calculated with respect to the analog input voltage.

7

Sample tested during initial release to ensure compliance.

8

Operational power/current figure includes contribution when running in oversampling mode.

7

REF SELECT = 1 7.5 pF

2.49/

V

2.505

) 0.9 × V

INH

) 0.1 × V

INL

= 100 µA V

SOURCE

= 100 µA 0.2 V

SINK

7

5 pF

DRIVE

8

20 27 mA

8

DRIVE

V

DRIVE

V

DRIVE

− 0.2 V

= 5 V, SNR typically reduces by 1.5 dB

DRIVE

Rev. A | Page 5 of 32

AD7607

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TIMING SPECIFICATIONS

AVCC = 4.75 V to 5.25 V, V

Table 3.

Limit at T
Parameter Min Typ Max Unit Description

PARALLEL/SERIAL/BYTE MODE

t

1/throughput rate

CYCLE

5 µs

5 µs Serial mode reading during conversion; V

9.1 µs Serial mode reading after a conversion; V
t

Conversion time

CONV

3.45 4 4.15 µs Oversampling off

7.87 9.1 µs Oversampling by 2

16.05 18.8 µs Oversampling by 4
33 39 µs Oversampling by 8
66 78 µs Oversampling by 16
133 158 µs Oversampling by 32
257 315 µs Oversampling by 64
t

WAKE -UP S TANDBY

t

WAKE -UP S HUTDO WN

100 µs

Internal Reference 30 ms

External Reference 13 ms

t

50 ns RESET high pulse width

RESET

t

20 ns BUSY to OS x pin setup time

OS_SETUP

t

OS_HOLD

t1 40 ns CONVST x high to BUSY high
t2 25 ns Minimum CONVST x low pulse
t3 25 ns Minimum CONVST x high pulse
t4 0 ns

2

t

5

t6 25 ns
t7 25 ns Minimum delay between RESET low to CONVST x high

PARALLEL/BYTE READ

OPERATION
t8 0 ns
t9 0 ns

t10
16 ns V

21 ns V
25 ns V
32 ns V
t11 15 ns
t12 22 ns

= 2.3 V to 5.25 V, V

DRIVE

20 ns BUSY to OS x pin hold time

0.5 ms Maximum delay allowed between CONVST A, CONVST B rising edges

= 2.5 V external reference/internal reference, TA = T

REF

, T

MIN

MAX

Parallel mode, reading during or after conversion; or serial mode (V

3.3 V to 5.25 V), reading during a conversion using D

rising edge to CONVST x rising edge; power-up time from

STBY
standby mode

rising edge to CONVST x rising edge; power-up time from

STBY
shutdown mode

rising edge to CONVST x rising edge; power-up time from

STBY
shutdown mode

BUSY falling edge to CS

Maximum time between last CS

to RD setup time

CS

to RD hold time

CS

low pulse width

RD

above 4.75 V

DRIVE

above 3.3 V

DRIVE

above 2.7 V

DRIVE

above 2.3 V

DRIVE

high pulse width

RD

high pulse width (see ); Figure 5 CS and RD linked

CS

to T

MIN

, unless otherwise noted.1

MAX

= 2.7 V

DRIVE

= 2.3 V, D

DRIVE

falling edge setup time

rising edge and BUSY falling edge

A and D

OUT

OUT

A and D

OUT

OUT

DRIVE

B lines

B lines

=

Rev. A | Page 6 of 32

AD7607

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Limit at T
Parameter Min Typ Max Unit Description

t13
16 ns V
20 ns V
25 ns V
30 ns V

3

t

14

16 ns V
21 ns V
25 ns V
32 ns V
t15 6 ns
t16 6 ns

t17 22 ns

SERIAL READ OPERATION

f

Frequency of serial read clock

SCLK

23.5 MHz V
17 MHz V

14.5 MHz V

11.5 MHz V
t18

15 ns V
20 ns V
30 ns V

3

t

19

Data access time after SCLK rising edge
17 ns V
23 ns V
27 ns V
34 ns V
t20 0.4 t
t21 0.4 t

ns SCLK low pulse width

SCLK

ns SCLK high pulse width

SCLK

t22 7 SCLK rising edge to D
t23 22 ns

FRSTDATA OPERATION

t24
15 ns V

20 ns V
25 ns V
30 ns V
t25 ns

15 ns V
20 ns V
25 ns V
30 ns V
t26
16 ns V
20 ns V
25 ns V
30 ns V

MIN

, T

MAX

Delay from CS

above 4.75 V

DRIVE

above 3.3 V

DRIVE

above 2.7 V

DRIVE

above 2.3 V

DRIVE

Data access time after RD

above 4.75 V

DRIVE

above 3.3 V

DRIVE

above 2.7 V

DRIVE

above 2.3 V

DRIVE

Data hold time after RD

to DB[15:0] hold time

CS
Delay from CS

above 4.75 V

DRIVE

above 3.3 V

DRIVE

above 2.7 V

DRIVE

above 2.3 V

DRIVE

Delay from CS

until DB[15:0] three-state disabled

falling edge

falling edge

rising edge to DB[15:0] three-state enabled

until D

OUT

A/D

B three-state disabled/delay from CS

OUT

until MSB valid

above 4.75 V

DRIVE

above 3.3 V

DRIVE

= 2.3 V to 2.7 V

DRIVE

above 4.75 V

DRIVE

above 3.3 V

DRIVE

above 2.7 V

DRIVE

above 2.3 V

DRIVE

A/D

B valid hold time

OUT

B three-state enabled

OUT

rising edge to D

CS

Delay from CS

above 4.75 V

DRIVE

above 3.3 V

DRIVE

above 2.7 V

DRIVE

above 2.3 V

DRIVE

OUT

A/D

OUT

falling edge until FRSTDATA three-state disabled

Delay from CS falling edge until FRSTDATA high, serial mode

above 4.75 V

DRIVE

above 3.3 V

DRIVE

above 2.7 V

DRIVE

above 2.3 V

DRIVE

Delay from RD

above 4.75 V

DRIVE

above 3.3 V

DRIVE

above 2.7 V

DRIVE

above 2.3 V

DRIVE

falling edge to FRSTDATA high

Rev. A | Page 7 of 32

AD7607

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Limit at T
Parameter Min Typ Max Unit Description

t27
19 ns V
24 ns V
t28 Delay from 16th SCLK falling edge to FRSTDATA low
17 ns V
22 ns V
t29 24 ns

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of V

2

The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <3 LSB performance matching between channel sets.

3

A buffer, which is equivalent to a load of 20 pF on the output pins, is used on the data output pins for these measurements.

Timing Diagrams

CONVST A,

CONVST B

CONVST A,

CONVST B

BUSY

CS

RESET

CONVST A,

CONVST B

CONVST A,

CONVST B

BUSY

, T

MIN

MAX

Delay from RD

= 3.3 V to 5.25 V

DRIVE

= 2.3 V to 2.7 V

DRIVE

= 3.3 V to 5.25 V

DRIVE

= 2.3 V to 2.7 V

DRIVE

Delay from CS

t

5

t

CYCLE

t

3

t

t

1

t

7

t

RESET

Figure 2. CONVST Timing—Reading After a Conversion

t

5

t

1

CONV

t

CYCLE

t

CONV

t

3

falling edge to FRSTDATA low

rising edge until FRSTDATA three-state enabled

) and timed from a voltage level of 1.6 V.

DRIVE

t

2

t

4

08096-002

t

2

t

6

CS

RESET

t

7

t

RESET

Figure 3. CONVST Timing—Reading During a Conversion

CS

t

8

t

10

RD

DATA:

DB[15:0]

FRSTDATA

t

13

INVALID V1 V2 V3 V7 V8V4

t

26

t

24

t

11

t

14

t

27

Figure 4. Parallel Mode, Separate

Rev. A | Page 8 of 32

CS

and RD Pulses

08096-003

t

9

t

16

t

t

15

17

t

29

08096-004

AD7607

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t

12

CS AND RD

t

16

t

17

DATA:

DB[15:0]

t

13

V1 V2 V3 V4 V5 V6 V7 V8

FRSTDATA

Figure 5. Linked Parallel Mode,

CS

and RD

08096-005

CS

SCLK

D

OUT

D

OUT

FRSTDATA

t

t

A,

B

18

19

DB13 DB12 DB11 DB1 DB0

t

25

t21t

20

t

22

t

28

t

23

t

29

08096-006

Figure 6. Serial Read Operation (Channel 1)

CS

RD

DATA: DB[7:0]

FRSTDATA

t

t

t

8

t

10

13

INVALID

24

HIGH

BYTE V1

t

26

t

14

LOW

BYTE V1

t

27

t

15

HIGH

BYTE V8

t

11

LOW

BYTE V8

t

29

t

9

t

16

t

17

08096-007

Figure 7. BYTE Mode Read Operation

Rev. A | Page 9 of 32

AD7607

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

AVCC to AGND −0.3 V to +7 V
V

to AGND −0.3 V to AVCC + 0.3 V

DRIVE

Analog Input Voltage to AGND1 ±16.5 V
Digital Input Voltage to AGND −0.3 V to V
Digital Output Voltage to AGND −0.3 V to V
REFIN to AGND −0.3 V to AVCC + 0.3 V
Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range

B Version −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Pb/SN Temperature, Soldering

Reflow (10 sec to 30 sec) 240 (+ 0)°C
Pb-Free Temperature, Soldering Reflow 260 (+ 0)°C
ESD (All Pins Except Analog Inputs) 2 kV
ESD (Analog Input Pins Only) 7 kV

1

Transient currents of up to 100 mA do not cause SCR latch-up.

DRIVE

DRIVE

+ 0.3 V
+ 0.3 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. These
specifications apply to a 4-layer board.

Table 5. Thermal Resistance

Package Type θJA θ

64-Lead LQFP 45 11 °C/W

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Unit

JC

Rev. A | Page 10 of 32

AD7607

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ANALOG INPUT

DECOUPL ING C AP PIN

POWER SUPPLY

GROUND PIN

DATA OUTPUT

DIGITAL OUTPUT

DIGITAL INPUT

REFERENCE INPUT /OUTPUT

PAR/SER/BYTE SEL

Table 6. Pin Function Descriptions

Pin No. Type

1, 37, 38, 48 P AVCC

1

Mnemonic Description

Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end
amplifiers and to the ADC core. These supply pins should be decoupled to AGND.

2, 26, 35, 40,
41, 47

P AGND

Analog Ground. These pins are the ground reference points for all analog circuitry on the AD7607.
All analog input signals and external reference signals should be referred to these pins. All six of
these AGND pins should connect to the AGND plane of a system.

5, 4, 3 DI OS[2:0]

Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio.
OS 2 is the MSB control bit, and OS 0 is the LSB control bit. See the Digital Filter section for more
details about the oversampling mode of operation and Table 9 for oversampling bit decoding.

6 DI

/SER/

PA R
BYTE SEL

Parallel/Serial/Byte Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel
interface is selected. If this pin is tied to a logic high, the serial interface is selected. Parallel byte
interface mode is selected when this pin is logic high and DB15/BYTE SEL is logic high (see Table 8).

In serial mode, the RD
DB8/D

DB[6:0] pins should be tied to ground.
In byte mode, DB15, in conjunction with PA R
of operation (see ). DB14 is used as the HBEN pin. DB[7:0] transfer the 16-bit conversion

results in two

7 DI

Standby Mode Input. This pin is used to place the AD7607 into one of two power-down modes:

STBY

standby mode or shutdown mode. The power-down mode entered depends on the state of the
RANGE pin, as shown in Tabl e 7. When in standby mode, all circuitry, except the on-chip reference,
regulators, and regulator buffers, is powered down. When in shutdown mode, all circuitry is powered
down.

8 DI RANGE

Analog Input Range Selection. Logic input. The polarity on this pin determines the input range
of the analog input channels. If this pin is tied to a logic high, the analog input range is ±10 V for all
channels. If this pin is tied to a logic low, the analog input range is ±5 V for all channels. A logic
change on this pin has an immediate effect on the analog input range. Changing this pin during
a conversion is not recommended. See the Analog Input section for more information.

V1GND

V2

V2GND

DB10

V1

AV

48

CC

47

AGND

46

REFGND

45

REFCAPB

44

REFCAPA

43

REFGND

42

REFIN/REF OUT

41

AGND

40

AGND

39

REGCAP

AV

38

CC

AV

37

CC

36

REGCAP

35

AGND

34

REF SELECT

33

DB15/BYTE SEL

DB13

DB12

DB11

DB14/HBEN

08096-008

AV

AGND

OS 0

OS 1

OS 2

STBY

RANGE

CONVST A

CONVST B

RESET

RD/SCLK

CS

BUSY

FRSTDATA

DB0

V8

V8GND

64 63 62 61 60 59 58 57

1

CC

PIN 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17 18 19 20 21 22 23 24 25

DB1

DB2

V7GND

DB3

V7

DB4

V6GND

AD7607

TOP VIEW

(Not to Scale)

DB5

DB6

V5

V4V6V3

V3GND

V4GND

V5GND

56 55 54 53 52 51 50 49

26 27 28 29 30 31 32

A

B

DB9

OUT

OUT

DRIVE

V

AGND

DB8/D

DB7/D

Figure 8. Pin Configuration

/SCLK pin functions as the serial clock input. The DB7/D

B pin function as serial data outputs. When the serial interface is selected, the DB[15:9] and

OUT

A pin and the

OUT

/SER/BYTE SEL, is used to select the parallel byte mode

Table 8

RD

operations, with DB0 as the LSB of the data transfers.

Rev. A | Page 11 of 32

AD7607

http://www.BDTIC.com/ADI

Pin No. Type

9, 10 DI

1

Mnemonic Description

CONVST A,
CONVST B

Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to
initiate conversions on the analog input channels. For simultaneous sampling of all 8 input channels
CONVST A and CONVST B can be shorted together and a single convert start signal applied.

Alternatively, CONVST A can be used to initiate simultaneous sampling for V1, V2, V3, and V4; and
CONVST B can be used to initiate simultaneous sampling on the other analog inputs (V5, V6, V7,
and V8). This is possible only when oversampling is not switched on.

When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold
circuitry for their respective analog inputs is set to hold.

11 DI RESET

Reset Input. When set to logic high, the rising edge of RESET resets the AD7607. The part should
receive a RESET pulse after power-up. The RESET high pulse should typically be 50 ns wide. If a
RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied
during a read, the contents of the output registers reset to all zeros.

12 DI

/SCLK Parallel Data Read Control Input When the Parallel Interface Is Selected (RD)/Serial Clock Input When

RD

the Serial Interface is Selected (SCLK). When both CS
output bus is enabled. In serial mode, this pin acts as the serial clock input for data transfers.
The CS
MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the
D

A and D

OUT

13 DI

Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic

CS

low in parallel mode, the DB[15:0] output bus is enabled and the conversion result is output on
the parallel data bus lines. In serial mode, CS is used to frame the serial read transfer and clock
out the MSB of the serial output data.

14 DO BUSY

Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges
and indicates that the conversion process has started. The BUSY output remains high until the
conversion process for all channels is complete. The falling edge of BUSY signals that the
conversion data is being latched into the output data registers and is available to read after a
Time t
occurs. Rising edges on CONVST A or CONVST B have no effect while the BUSY signal is high.

15 DO FRSTDATA

Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back
on the parallel, parallel byte, or serial interface. When the CS
pin is in three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode,
the falling edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high, which
indicates that the result from V1 is available on the output data bus. The FRSTDATA output returns
to a logic low following the next falling edge of RD
edge of CS
edge after the CS

22 to 16 DO DB[6:0]

Parallel Output Data Bits, DB6 to DB0. When PAR
parallel digital input/output pins. When CS
of the conversion result. When PA R /SER/BYTE SEL = 1, these pins should be tied to DGND. When
operating in parallel byte interface mode, DB[7:0] outputs the 14-bit conversion result in two RD
operations. DB7 is the MSB, and DB0 is the LSB.

23 P V

DRIVE

Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the
operating voltage of the interface. This pin is nominally at the same supply as the supply of the host
interface (that is, DSP and FPGA).

24 DO DB7/D

OUT

A

Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (D
this pins acts as a three-state parallel digital input/ output pin. When CS
used to output DB7 of the conversion result. When PA R
D

A and outputs serial conversion data (see the section for more details).

OUT

When operating in parallel byte mode, DB7 is the MSB of the byte.

25 DO DB8/D

OUT

B

Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (D
this pin acts as a three-state parallel digital input/output pin. When CS
used to output DB8 of the conversion result. When PA R / SER/BYTE SEL = 1, this pin functions
as D

OUT

31 to 27 DO DB[13:9]

Parallel Output Data Bits, DB13 to DB9. When PA R
parallel digital input/output pins. When CS
DB9 of the conversion result. When PA R

and RD are logic low in parallel mode, the

falling edge takes the D

B serial data outputs. For more information, see the section. Conversion Control

OUT

. Any data read while BUSY is high must be completed before the falling edge of BUSY

4

A and D

OUT

B data output lines out of tristate and clocks out the

OUT

input is high, the FRSTDATA output

. In serial mode, FRSTDATA goes high on the falling

because this clocks out the MSB of V1 on D

A. It returns low on the 14th SCLK falling

OUT

falling edge. See the section for more details. Conversion Control

/SER/BYTE SEL = 0, these pins act as three-state

and RD are low, these pins are used to output DB6 to DB0

A). When PA R /SER/BYTE SEL = 0,

OUT

and RD are low, this pin is

/SER/BYTE SEL = 1, this pin functions as

Conversion Control

B). When PA R /SER/BYTE SEL = 0,

OUT

and RD are low, this pin is

B and outputs serial conversion data (see the section for more details). Conversion Control

/SER/BYTE SEL = 0, these pins act as three-state

and RD are low, these pins are used to output DB13 to

/SER/BYTE SEL = 1, these pins should be tied to DGND.

Rev. A | Page 12 of 32

AD7607

http://www.BDTIC.com/ADI

Pin No. Type

32 DO/DI DB14/HBEN

33 DO/DI

34 DI REF SELECT

36, 39 P REGCAP

42 REF

43, 46 REF REFGND Reference Ground Pins. These pins should be connected to AGND.
44, 45 REF

49, 51, 53,
55, 57, 59,
61, 63

50, 52, 54,
56, 58, 60,
62, 64

1

P = power supply, DI = digital input, DO = digital output, REF = reference input/output, AI = analog input, GND = ground.

1

Mnemonic Description

Parallel Output Data Bit 14 (DB14)/High Byte Enable (HBEN). When PA R
acts as a three-state parallel digital output pin. When CS
DB14 of the conversion result, which is a sign extended bit of the MSB, DB13. When PAR
SEL = 1 and DB15/BYTE SEL = 1, the AD7607 operates in parallel byte interface mode, in which the

HBEN pin is used to select if the most significant byte (MSB) or the least significant byte (LSB) of the
conversion result is output first. When HBEN = 1, the MSB byte is output first, followed by the LSB
byte. When HBEN = 0, the LSB byte is output first, followed by the MSB byte.

DB15/
BYTE SEL

REFIN/
REFOUT

REFCAPA,
REFCAPB

AI V1 to V8

AI GND

V1GND to
V8GND

Parallel Output Data Bit 15 (DB15)/Parallel Byte Mode Select (BYTE SEL). When PA R
0, this pin acts as a three-state parallel digital output pin. When CS
output DB15, which is a sign extended bit of the MSB, DB13, of the conversion result. When PAR /
SER/BYTE SEL = 1, the BYTE SEL pin is used to select between serial interface mode or parallel byte
interface mode (see ). When Table 8 PAR
operates in serial interface mode. When PAR
operates in parallel byte interface mode.
Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the internal

reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and
an external reference voltage must be applied to the REFIN/REFOUT pin.

Decoupling Capacitor Pin for Voltage Output from Internal Regulator. These output pins should be
decoupled separately to AGND using a 1 F capacitor. The voltage on these pins is in the range of

2.5 V to 2.7 V.
Reference Input (REFIN)/Reference Output (REFOUT). The gained up on-chip reference of 2.5 V

is available on this pin for external use if the REF SELECT pin is set to a logic high. Alternatively, the
internal reference can be disabled by setting the REF SELECT pin to a logic low, and an external
reference of 2.5 V can be applied to this input (see the Internal/External Reference section).
Decoupling is required on this pin for both the internal or external reference options. A 10 µF
capacitor should be applied from this pin to ground close to the REFGND pins.

Reference Buffer Output Force/Sense Pins. These pins must be connected together and
decoupled to AGND using a low ESR 10 F ceramic capacitor.

Analog Inputs. These pins are single-ended analog inputs. The analog input range of these
channels is determined by the RANGE pin.

Analog Input Ground Pins. These pins correspond to Analog Input Pin V1 to Analog Input Pin V8.
All analog input AGND pins should connect to the AGND plane of a system.

and RD are low, this pin is used to output

and RD are low, this pin is used to

/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0, the AD7607

/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7607

/SER/BYTE SEL = 0, this pin

/SER/BYTE

/SER/BYTE SEL =

Rev. A | Page 13 of 32

AD7607

http://www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

0

–20

–40

–60

–80

SNR (dB)

–100

–120

–140

–160

0 102030405060708090100

INPUT FREQ UENCY (kHz)

AVCC = V
INTERNAL REFERENCE

f

SAMPLE

T

= 25°C

A

±10V RANGE
SNR: 85.07dB
THD: –107.33dB
16,384 POINT FFT

f

= 1kHz

IN

= 5V

DRIVE

= 200kSPS

Figure 9. FFT ± 10 V Range

08096-018

0.5

0.4

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 2000 4000 6000 8000 10,000 12,000 14,000 16,000

AVCC = V
INTERNAL REFERENCE

f

SAMPLE

= 25°C

T

A

±10V RANGE

CODE

DRIVE

= 200kSPS

Figure 12. Typical DNL ± 10 V Range

= 5V

08096-020

0

–20

–40

–60

–80

SNR (dB)

–100

–120

–140

–160

0 102030405060708090100

INPUT FEQUENCY (kHz)

AVCC = V
INTERNAL REFERENCE

f

SAMPLE

T

= 25°C

A

±5V RANGE
SNR: 84.82dB
THD: –107.51d B
16,384 POINT FFT

f

= 1kHz

IN

= 5V

DRIVE

= 200kSPS

Figure 10. FFT Plot ± 5 V Range

0.5

0.4

0.3

0.2

0.1

0

INL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 2000 4000 6000 8000 10,000 12,000 14,000

AVCC = V
INTERNAL REFERENCE

f

SAMPLE

T

= 25°C

A

±10V RANGE

CODE

= 5V

DRIVE

= 200kSPS

Figure 11. Typical INL ± 10 V Range

16,000

0.5

0.4

0.3

0.2

0.1

0

INL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 2000 4000 6000 8000 10,000 12,000 14, 000 16,000

8096-017

AVCC = V
INTERNAL REFERENCE

f

SAMPLE

T

= 25°C

A

±5V RANGE

CODE

= 5V

DRIVE

= 200kSPS

08096-010

Figure 13. Typical INL ± 5 V Range

0.5

0.4

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 2000

08096-019

4000 6000 8000 10,000 12,000 14,000 16,000

Figure 14. Typical DNL ± 5 V Range

AVCC = V
INTERNAL REFERENCE

f

SAMPLE

T

= 25°C

A

±5V RANGE

CODE

= 5V

DRIVE

= 200kSPS

08096-009

Rev. A | Page 14 of 32

AD7607

http://www.BDTIC.com/ADI

5.00

10

3.75

2.50

1.25

0

–1.25

NFS ERROR (LS B)

–2.50

–3.75

–5.00

–40 –25 –10 5 20 35 50 65 80

TEMPERATURE (°C)

±10V RANGE

200kSPS
AV

, V

CC

DRIVE

EXTERNAL REFERENCE

Figure 15. NFS Error vs. Temperature

5.00

3.75

2.50

1.25

0

–1.25

PFS ERROR (LSB)

–2.50

–3.75

–5.00

–40 –25 –10 5 20 35 50 65 80

TEMPERATURE (°C)

±10V RANGE

200kSPS
AV

, V

CC

DRIVE

EXTERNAL REFERENCE

Figure 16. PFS Error vs. Temperature

±5V RANGE

= 5V

±5V RANGE

= 5V

8

6

4

2

PFS/NFS ERROR (%FS)

0

–2

0 120k100k80k60k40k20k

08096-115

AVCC, V
F

SAMPLE

T

= 25°C

A

EXTERNAL REF ERENCE
SOURCE RESIST ANCE IS MATCHED O N
THE VxGND INPUT
±10V AND ±5V RANGE

SOURCE RESIST ANCE (Ω)

= 5V

DRIVE

= 200 kSPS

08096-118

Figure 18. PFS and NFS Error vs. Source Resistance

86

85

84

83

SNR (dB)

82

81

80

10 100 1k 10k 100k

08096-116

INPUT FREQUENCY (Hz)

AVCC = V
INTERNAL REFERENCE

f

SAMPLE

T

= 25°C

A

±5V RANGE
ALL 8 CHANNELS

= 5V

DRIVE

= 200kSPS

08096-022

Figure 19. SNR vs. Input Frequency ± 5 V Range

2.5

2.0
PFS ERROR

1.5

1.0

NFS ERROR

0.5

0

–0.5

–1.0

–1.5

NFS/PFS CHANNEL MATCHING (LSB)

–2.0

–2.5

–40 –25 –10 5 20 35 50 65 80

TEMPERATURE (°C)

10V RANGE
AV

, V

CC

DRIVE

EXTERNAL REF ERENCE

Figure 17. PFS and NFS Error Matching vs. Temperature

= 5V

08096-117

Rev. A | Page 15 of 32

86

85

84

83

SNR (dB)

82

81

80

10 100 1k 10k 100k

INPUT FREQUENCY (Hz)

AVCC = VDRIVE = 5V
INTERNAL REFERENCE

f

= 200kSPS

SAMPLE

T

= 25°C

A

±10V RANGE
ALL 8 CHANNELS

Figure 20. SNR vs. Input Frequency ± 10 V Range

08096-023

AD7607

–

–

http://www.BDTIC.com/ADI

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

BIPOLAR ZERO CODE ERROR (LSB)

–0.20

–0.25

–40 –25 –10 5 20 35 50 65 80

5V RANGE

10V RANGE

200kSPS
AV
EXTERNAL REF ERENCE

TEMPERATURE (°C)

, V

CC

DRIVE

Figure 21. Bipolar Zero Code Error vs. Temperature

= 5V

08096-119

40

±5V RANGE
AV

, V

= +5V

CC

–50

–60

–70

–80

THD (dB)

–90

–100

–110

–120

DRIVE

f

= 200kSPS

SAMPLE

R

MATCHED ON Vx AND VxGND INPUTS

SOURCE

1k 100k10k

INPUT FREQ UENCY (Hz)

105kΩ

48.7kΩ

23.7kΩ
10kΩ
5kΩ

1.2kΩ
100Ω
51Ω
0Ω

Figure 24. THD vs. Input Frequency for Various Source Impedances,

±5 V Range

08096-122

1.00

0.75

0.50

0.25

0

–0.25

–0.50

–0.75

BIPOLAR ZERO CODE ERROR MATCHING (LSB)

–1.00

–40 –25 –10 5 20 35 50 65 80

5V RANGE

10V RANGE

200kSPS
AV
EXTERNAL REF ERENCE

TEMPERATURE (°C)

, V

DRIVE

= 5V

CC

Figure 22. Bipolar Zero Code Error Matching vs. Temperature

40

±10V RANGE
AV

, V

= +5V

CC

–50

–60

–70

–80

THD (dB)

–90

–100

–110

–120

DRIVE

f

= 200kSPS

SAMPLE

R

MATCHED ON Vx AND VxGND INPUTS

SOURCE

1k 100k10k

INPUT FREQ UENCY (Hz)

105kΩ

48.7kΩ

23.7kΩ
10kΩ
5kΩ

1.2kΩ
100Ω
51Ω
0Ω

Figure 23. THD vs. Input Frequency for Various Source Impedances,

±10 V Range

2.5010

2.5005
AVCC = 5V

2.5000

2.4995
AVCC = 4.75V

2.4990

REFOUT VO LTAGE (V )

2.4985

2.4980

–40 –25 –10 5 20 35 50 65 80

08096-120

AVCC = 5.25V

TEMPERATURE (°C)

08096-125

Figure 25. Reference Output Voltage vs. Temperature for

Different Supply Voltages

8

AVCC, V

f

SAMPLE

6

4

2

0

–2

–4

INPUT CURRENT (µ A)

–6

–8

–10

–10 –8 –6 –4 –2 1086420

08096-121

= 5V

DRIVE

= 200kSPS

INPUT VOLTAGE (V)

+85°C
+25°C
–40°C

08096-126

Figure 26. Analog Input Current vs. Input Voltage for Various Temperatures

Rev. A | Page 16 of 32

AD7607

–

http://www.BDTIC.com/ADI

22

20

18

16

14

SUPPLY CURRENT (mA)

12

CC

AV

AVCC, V
T

= 25°C

A

10

INTERNAL REFERENCE

f

SAMPLE

8

NO OS OS2 OS4 OS8 OS16 OS32 OS64

= 5V

DRIVE

VARIES WIT H OS RATE

OVERSAMPLI NG RATIO

Figure 27. Supply Current vs. Oversampling Rate Figure 29. Channel-to-Channel Isolation

140

130

120

110

100

±10V RANGE

±5V RANGE

08096-127

50

AVCC, V
INTERNAL REFERENCE

–60

AD7607 RECOMMENDED DECO UPLING USED

f

SAMPLE

–70

T

= 25°C

A

INTERFERER O N ALL UNSELECTED CHANNELS

–80

–90

–100

–110

–120

–130

CHANNEL-TO-CHANNEL ISOLAT ION (dB)

–140

0114012010080604020

= 5V

DRIVE

= 150kSPS

NOISE FREQUENCY (kHz)

±10V RANGE

±5V RANGE

60

08096-129

90

80

70

POWE R SUPPLY REJECTION RAT IO (d B)

60

0 11001000900800700600500400300200100

AVCC, V
INTERNAL REFERENCE
AD7607 RECOMMENDED DECO UPLING USE D

f

SAMPLE

T

= 25°C

A

AVCC NOISE FREQUENCY (kHz)

= 5V

DRIVE

= 200kSPS

08096-128

Figure 28. PSRR

Rev. A | Page 17 of 32

AD7607

http://www.BDTIC.com/ADI

TERMINOLOGY

Integral Nonlinearity

The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale, at ½ LSB below the first
code transition; and full scale, at ½ LSB above the last code
transition.

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Bipolar Zero Code Error

The deviation of the midscale transition (all 1s to all 0s) from
the ideal, which is 0 V – ½ LSB.

Bipolar Zero Code Error Match

The absolute difference in bipolar zero code error between any
two input channels.

Positive Full-Scale Error

The deviation of the actual last code transition from the ideal
last code transition (10 V − 1½ LSB (9.998) and 5 V − 1½ LSB
(4.99908)) after bipolar zero code error is adjusted out. The
positive full-scale error includes the contribution from the
internal reference buffer.

Positive Full-Scale Error Match

The absolute difference in positive full-scale error between any
two input channels.

Negative Full-Scale Error

The deviation of the first code transition from the ideal first
code transition (−10 V + ½ LSB (−9.9993) and −5 V + ½ LSB
(−4.99969)) after the bipolar zero code error is adjusted out.
The negative full-scale error includes the contribution from the
internal reference buffer.

Negative Full-Scale Error Match

The absolute difference in negative full-scale error between any
two input channels.

Signal-to-(Noise + Distortion) Ratio

The measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (f

/2, excluding dc).

S

The ratio depends on the number of quantization levels in
the digitization process: the more levels, the smaller the
quantization noise.

The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, for a 14-bit converter, the signal-to-(noise + distortion)
is 86.04 dB.

Rev. A | Page 18 of 32

Total Harmonic Distortion (THD)

The ratio of the rms sum of the harmonics to the fundamental.
For the AD7607, it is defined as

THD (dB) =

2

2

2

20log

22222

32

54

V

1

7

6

VVVVVVVV

+++++++

9

8

where:

V

is the rms amplitude of the fundamental.

1

V

to V9 are the rms amplitudes of the second through ninth

2

harmonics.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the
ADC output spectrum (up to f

/2, excluding dc) to the rms value

S

of the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is
determined by a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities create distortion products
at sum and difference frequencies of mfa ± nfb, where m, n = 0,
1, 2, 3. Intermodulation distortion terms are those for which
neither m nor n is equal to 0. For example, the second-order
terms include (fa + fb) and (fa − fb), and the third-order terms
include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The calculation of the intermodulation distortion is per the
THD specification, where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in decibels (dB).

Power Supply Rejection Ratio (PSRR)

Variations in power supply affect the full-scale transition but not
the linearity of the converter. PSR is the maximum change in
full-scale transition point due to a change in power supply voltage
from the nominal value. The PSR ratio (PSRR) is defined as the
ratio of the power in the ADC output at full-scale frequency, f,
to the power of a 200 mV p-p sine wave applied to the ADC’s
V

and VSS supplies of frequency, fS.

DD

PSRR (dB) = 10log (Pf/Pf

)

S

where:

Pf is equal to the power at Frequency f in the ADC output.
Pf

is equal to the power at Frequency fS coupled onto the AVCC

S

supplies.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk
between any two channels. It is measured by applying a full-scale
sine wave signal of up to 160 kHz to all unselected input channels,
and then determining the degree to which the signal attenuates
in the selected channel with a 1 kHz sine wave signal applied
(see Figure 29).

AD7607

V

A

http://www.BDTIC.com/ADI

THEORY OF OPERATION

CONVERTER DETAILS

The AD7607 is a data acquisition system that employs a high
speed, low power, charge redistribution, successive approxi­mation analog-to-digital converter (ADC) and allows the
simultaneous sampling of eight analog input channels. The analog
inputs on the AD7607 can accept true bipolar input signals. The
RANGE pin is used to select either ±10 V or ±5 V as the input
range. The AD7607 operates from a single 5 V supply.

The AD7607 contains input clamp protection, input signal scaling
amplifiers, a second-order antialiasing filter, track-and-hold
amplifiers, an on-chip reference, reference buffers, a high speed
ADC, a digital filter, and high speed parallel and serial interfaces.
Sampling on the AD7607 is controlled using the CONVST signals.

ANALOG INPUT

Analog Input Ranges

The AD7607 can handle true bipolar input voltages. The logic
level on the RANGE pin determines the analog input range of
all analog input channels. If this pin is tied to a logic high, the
analog input range is ±10 V for all channels. If this pin is tied
to a logic low, the analog input range is ±5 V for all channels.
A logic change on this pin has an immediate effect on the analog
input range; however, there is a typical settling time of ~80 µs,
in addition to the normal acquisition time requirement.
Recommended practice is to hardwire the RANGE pin
according to the desired input range for the system signals.

Analog Input Impedance

The analog input impedance of the AD7607 is 1 MΩ. This is
a fixed input impedance that does not vary with the AD7607
sampling frequency. This high analog input impedance elimi­nates the need for a driver amplifier in front of the AD7607,
allowing for direct connection to the source or sensor. With the
need for a driver amplifier eliminated, bipolar supplies (which
are often a source of noise in a system) can be removed from
the signal chain.

Analog Input Clamp Protection

Figure 30 shows the analog input structure of the AD7607. Each
AD7607 analog input contains clamp protection circuitry.
Despite single 5 V supply operation, this analog input clamp
protection allows for an input overvoltage of up to ±16.5 V.

R

FB

1MΩ

CLAMPVx

1MΩ

xGND

CLAMP

SECOND-

R

FB

Figure 30. Analog Input Circuitry

ORDER

LPF

08096-032

Figure 31 shows the voltage vs. current characteristic of the
clamp circuit. For input voltages of up to ±16.5 V, no current
flows in the clamp circuit. For input voltages that are above ±16.5 V,
the AD7607 clamp circuitry turns on and clamps the analog
input to ±16.5 V.

AVCC, V

30

= 25°C

T

A

20

10

0

–10

–20

–30

INPUT CLAMP CURRENT (mA)

–40

–50

–20 –15 –10 –5 0 5 10 15 20

= 5V

DRIVE

SOURCE VOLTAGE (V)

Figure 31. Input Protection Clamp Profile

08096-051

A series resistor should be placed on the analog input channels
to limit the current to ±10 mA for input voltages above ±16.5 V.
In an application where there is a series resistance on an analog
input channel, Vx, a corresponding resistance is required on the
analog input GND channel, VxGND (see Figure 32). If there is
no corresponding resistor on the VxGND channel, an offset
error occurs on that channel.

R

FB

R

FB

8096-032

NALOG

INPUT

SIGNAL

AD7607

R

R

VINx

C

VxGND

CLAMP

CLAMP

1MΩ

1MΩ

Figure 32. Input Resistance Matching on the Analog Input

Rev. A | Page 19 of 32

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Analog Input Antialiasing Filter

An analog antialiasing filter (a second-order Butterworth) is
also provided on the AD7607. Figure 33 and Figure 34 show
the frequency and phase response, respectively, of the analog
antialiasing filter. In the ±5 V range, the −3 dB frequency is
typically 15 kHz. In the ±10 V range, the −3 dB frequency is
typically 23 kHz.

5

0

AV

, V

= 5V

CC

–5

–10

–15

–20

–25

ATTENUATION (dB)

–30

–35

–40

100 1k 10k 100k

DRIVE

f

= 200kSPS

SAMPLE

T

= 25°C

A

±10V RANGE 0.1dB 3d B

–40 10, 303 24,365Hz
+25 9619 23,389Hz
+85 9326 22,607Hz

±5V RANGE 0.1dB 3dB

–40 5225 16,162Hz
+25 5225 15,478Hz
+85 4932 14,990Hz

INPUT FREQ UENCY (Hz)

±5V RANGE

±10V RANGE

08096-053

Figure 33. Analog Antialiasing Filter Frequency Response

18

16

±5V RANGE

14

12

±10V RANGE

10

8

6

4

2

PHASE DELAY (µs)

0

–2

–4

AVCC, V

f

SAMPLE

–6

T

= 25°C

A

–8

10 100k10k1k

= 5V

DRIVE

= 200kSPS

INPUT FREQ UENCY (Hz)

08096-052

Figure 34. Analog Antialiasing Filter Phase Response

Track-and-Hold Amplifiers

The track-and-hold amplifiers on the AD7607 allow the ADC to
accurately acquire an input sine wave of full-scale amplitude to
14-bit resolution. The track-and-hold amplifiers sample their
respective inputs simultaneously on the rising edge of CONVST x.
The aperture time for the track-and-

hold (that is, the delay time between the external CONVST x
signal and the track-and-hold actually going into hold) is well
matched, by design, across all eight track-and-holds on one
device and from device to device. This matching allows more
than one AD7607 device to be sampled simultaneously in
a system.

The end of the conversion process across all eight channels is
indicated by the falling edge of BUSY, and it is at this point that the
track-and-holds return to track mode and the acquisition time
for the next set of conversions begins.

The conversion clock for the part is internally generated, and
the conversion time for all channels is 4 µs. On the AD7607, the
BUSY signal returns low after all eight conversions to indicate the
end of the conversion process. On the falling edge of BUSY, the
track-and-hold amplifiers return to track mode. New data can
be read from the output register via the parallel, parallel byte, or
serial interface after BUSY goes low; or, alternatively, data from
the previous conversion can be read while BUSY is high. Reading
data from the AD7607 while a conversion is in progress has little
effect on performance and allows a faster throughput to be
achieved. In parallel mode at V

> 3.3 V, the SNR is reduced

DRIVE

by ~1.5 dB when reading during a conversion.

ADC TRANSFER FUNCTION

The output coding of the AD7607 is twos complement. The
designed code transitions occur midway between successive
integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is
FSR/16,384. The ideal transfer characteristic is shown in Figure 35.

±10V CODE = × 8182 ×

011...111

011...110

000...001

000...000

111...111

ADC CODE

100...010

100...001

100...000

±10V RANGE +10V 0V –10V 1.22mV
±5V RANGE +5V 0V –5V 610µV

±5V CODE = × 8192 ×

–FS + 1/2LSB 0V – 1LSB + FS – 3/2LSB

+FS MIDSCALE –FS LSB

IN
10V
VIN

5V

ANALOG INPUT

Figure 35. Transfer Characteristics

The LSB size is dependent on the analog input range selected.

REF

2.5V
REF

2.5V

LSB =

+FS – (–FS)

14

2

08096-035

Rev. A | Page 20 of 32

AD7607

V

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INTERNAL/EXTERNAL REFERENCE

The AD7607 contains an on-chip 2.5 V bandgap reference. The
REFIN/REFOUT pin allows access to the 2.5 V reference that
generates the on-chip 4.5 V reference internally, or it allows
an external reference of 2.5 V to be applied to the AD7607. An
externally applied reference of 2.5 V is also gained up to 4.5 V, using
the internal buffer. This 4.5 V buffered reference is the reference
used by the SAR ADC.

The REF SELECT pin is a logic input pin that allows the user to
select between the internal reference or an external reference.
If this pin is set to logic high, the internal reference is selected
and enabled. If this pin is set to logic low, the internal reference
is disabled and an external reference voltage must be applied
to the REFIN/REFOUT pin. The internal reference buffer is
always enabled. After a reset, the AD7607 operates in the reference
mode selected by the REF SELECT pin. Decoupling is required
on the REFIN/REFOUT pin for both the internal and external
reference options. A 10 µF ceramic capacitor is required on the
REFIN/REFOUT pin.

The AD7607 contains a reference buffer configured to gain the
REF voltage up to ~4.5 V, as shown in Figure 36. The REFCAPA
and REFCAPB pins must be shorted together externally, and
a ceramic capacitor of 10 F applied to REFGND, to ensure that
the reference buffer is in closed-loop operation. The reference
voltage available at the REFIN/REFOUT pin is 2.5 V.

When the AD7607 is configured in external reference mode,
the REFIN/REFOUT pin is a high input impedance pin. For
applications using multiple AD7607 devices, the following
configurations are recommended, depending on the application
requirements.

External Reference Mode

One ADR421 external reference can be used to drive the
REFIN/REFOUT pins of all AD7607 devices (see Figure 37).
In this configuration, each REFIN/REFOUT pin of the AD7607
should be decoupled with a 100 nF decoupling capacitor.

Internal Reference Mode

One AD7607 device, configured to operate in the internal
reference mode, can be used to drive the remaining AD7607
devices, which are configured to operate in external reference
mode (see Figure 38). The REFIN/REFOUT pin of the AD7607,
configured in internal reference mode, should be decoupled
using a 10 µF ceramic decoupling capacitor. The other AD7607
devices, configured in external reference mode, should use a
100 nF decoupling capacitor on their REFIN/REFOUT pins.

REFIN/REF OUT

SAR

BUF

2.5V
REF

Figure 36. Reference Circuitry

REFCAPB

REFCAPB

10µF

8096-036

AD7607

REF SELECT

REFIN/REFOUT

100nF

ADR421

Figure 37. Single External Reference Driving Multiple AD7607 REFIN Pins

0.1µF

AD7607

REF SELECT

REFIN/REFOUT

100nF

AD7607

REF SEL ECT

REFIN/R EFOUT

100nF

DRIVE

AD7607

REF SELECT

REFIN/REF OUT

+

10µF

Figure 38. Internal Reference Driving Multiple AD7607 REFIN Pins.

AD7607

REF SELECT

REFIN/REF OUT

100nF

AD7607

REF SELECT

REFIN/RE FOUT

100nF

08096-038

08096-037

Rev. A | Page 21 of 32

AD7607

A

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TYPICAL CONNECTION DIAGRAM

Figure 39 shows the typical connection diagram for the AD7607.
There are four AV

supply pins on the part, and each of the

CC

four pins should be decoupled using a 100 nF capacitor at each
supply pin and a 10 µF capacitor at the supply source. The AD7607
can operate with the internal reference or an externally applied
reference. In this configuration, the AD7607 is configured to
operate with the internal reference. When using a single AD7607
device on the board, the REFIN/REFOUT pin should be
decoupled with a 10 µF capacitor. When using an application
with multiple AD7607 devices, refer to the Internal/External
Reference section. The REFCAPA and REFCAPB pins are
shorted together and decoupled with a 10 µF ceramic capacitor.

The V
processor. The V

supply is connected to the same supply as the

DRIVE

voltage controls the voltage value of the

DRIVE

output logic signals. For layout, decoupling, and grounding
hints, see the Layout Guidelines section.

POWER-DOWN MODES

Two power-down modes are available on the AD7607: standby

STBY

mode and shutdown mode. The
the AD7607 is in normal mode or in one of the two power­down modes.

pin controls whether

The power-down mode is selected through the state of the RANGE
pin when the

STBY

pin is low. shows the configurations

Tabl e 7
required to choose the desired power-down mode. When the
AD7607 is placed in standby mode, current consumption is 8 mA
maximum and power-up time is approximately 100 µs because
the capacitor on the REFCAPA and REFCAPB pins must charge
up. In standby mode, the on-chip reference and regulators
remain powered up, and the amplifiers and ADC core are
powered down.

When the AD7607 is placed in shutdown mode, current
consumption is 6 µA maximum and power-up time is
approximately 13 ms (external reference mode). In shutdown
mode, all circuitry is powered down. When the AD7607 is
powered up from shutdown mode, a RESET signal must be
applied to the AD7607 after the required power-up time has
elapsed.

Table 7. Power-Down Mode Selection

Power-Down Mode

STBY

RANGE

Standby 0 1
Shutdown 0 0

NALOG SUPPL Y

VOLTAGE 5V

DIGITAL SUPPLY

1

VOLTAGE +2.3V TO +5V

+

10µF

REFIN/REF OUT

+

10µF

EIGHT ANALO G

INPUTS V1 TO V8

1

DECOUPLING SHOWN ON THE AVCC PIN APPLIE S TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48).
DECOUPLING CAPACITOR CAN BE SHARED BE TWEEN AV

2

DECOUPLING SHOWN ON T HE REGCAP PIN APPLIES T O EACH REGCAP PI N (PIN 36, PI N 39).

REFCAPA

REFCAPB

REFGND

V1
V1GND

V2
V2GND
V3
V3GND
V4
V4GND
V5
V5GND
V6
V6GND
V7
V7GND
V8
V8GND

1µF

REGCAP

AD7607

AGND

100nF

V

AV

2

CC

DRIVE

DB0 TO DB15

CONVST A, CO NVST B

PAR/SER SEL

CC

CS

RD

BUSY

RESET

OS 2
OS 1
OS 0

REF SELECT

RANGE

STBY

PIN 37 AND PIN 38.

100nF

PARALLEL

INTERFACE

OVERSAMPLING

V

DRIVE

V

MICROPROCESSOR/

DRIVE

DSP

MICROCONVERT ER/

08096-039

Figure 39. Typical Connection Diagram

Rev. A | Page 22 of 32

AD7607

V

http://www.BDTIC.com/ADI

CONVERSION CONTROL

Simultaneous Sampling on All Analog Input Channels

The AD7607 allows simultaneous sampling of all analog input
channels. All channels are sampled simultaneously when both
CONVST pins (CONVST A, CONVST B) are tied together. A
single CONVST signal is used to control both CONVST x inputs.
The rising edge of this common CONVST signal initiates
simultaneous sampling on all analog input channels.

The AD7607 contains an on-chip oscillator that is used to
perform the conversions. The conversion time for all ADC
channels is t
conversions are in progress, so when the rising edge of CONVST
is applied, BUSY goes logic high and transitions low at the end
of the entire conversion process. The falling edge of the BUSY
signal is used to place all eight track-and-hold amplifiers back
into track mode. The falling edge of BUSY also indicates that
the new data can now be read from the parallel bus (DB[15:0]),
the D

OUT

(DB[7:0]).

Simultaneously Sampling Two Sets of Channels

The AD7607 also allows the analog input channels to be sampled
simultaneously in two sets. This can be used in power-line
protection and measurement systems to compensate for phase
differences between current and voltage sensors. In a 50 Hz system,
this allows for up to 9° of phase compensation; and in a 60 Hz
system, it allows for up to 10° of phase compensation.

. The BUSY signal indicates to the user when

CONV

A and D

B serial data lines, or the parallel byte bus

OUT

1 TO V4 TRACK-AND-HOLD

ENTER HO LD

t

CONVST A

CONVST B

BUSY

5

t

V5 TO V8 TRACK-AND-HOLD
ENTER HOLD

AD7607 CONVERTS

ON ALL 8 CHANNELS

CONV

This is accomplished by pulsing the two CONVST pins
independently and is possible only if oversampling is not in use.
CONVST A is used to initiate simultaneous sampling of the first
set of channels (V1 to V4), and CONVST B is used to initiate
simultaneous sampling on the second set of analog input
channels (V5 to V8), as illustrated in Figure 40.

On the rising edge of CONVST A, the track-and-hold
amplifiers for the first set of channels are placed into hold
mode. On the rising edge of CONVST B, the track-and-hold
amplifiers for the second set of channels are placed into hold
mode. The conversion process begins when both rising edges
of CONVST x have occurred; therefore, BUSY goes high on the
rising edge of the later CONVST x signal. In Tab le 3 , Time t

5

indicates the maximum allowable time between CONVST x
sampling points.

There is no change to the data read process when using two
separate CONVST x signals.

Connect all unused analog input channels to AGND. The results
for any unused channels are still included in the data read because
all channels are always converted.

CS/RD

DATA: DB[15:0]

FRSTDATA

Figure 40. Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals—Parallel Interface Mode

V1 V2 V3 V7 V8

Rev. A | Page 23 of 32

8096-040

AD7607

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DIGITAL INTERFACE

The AD7607 provides three interface options: a parallel inter­face, a high speed serial interface, and a parallel byte interface.
The required interface mode is selected via the

PA R

/SER/BYTE

SEL and the DB15/BYTE SEL pins.

Table 8. Interface Mode Selection

/SER/BYTE SEL

PAR

0 0 Parallel interface mode
1 0 Serial interface mode
1 1 Parallel byte interface mode

DB15 Interface Mode

Interface mode operation is discussed in the following sections.

PARALLEL INTERFACE (PAR/SER/BYTE SEL = 0)

Data can be read from the AD7607 via the parallel data bus with

CS

standard
the
input signals are internally gated to enable the conversion result
onto the data bus. The data lines, DB15 to DB0, leave their high
impedance state when both
and
extended bit of the MSB (DB13) of the conversion result.

The rising edge of the CS input signal tristates the bus, and the
falling edge of the
impedance state.
lines; it is the function that allows multiple AD7607 devices to

share the same parallel data bus.

The
can be used to access the conversion results as shown in .
A read operation of new data can take place after the BUSY
signal goes low (see ); or, alternatively, a read operation
of data from the previous conversion process can take place
while BUSY is high (see ).

The
register. Applying a sequence of
AD7607 clocks the conversion results out from each channel
onto the parallel output bus, DB[15:0], in ascending order.
The first
conversion result from Channel V1. The next
updates the bus with the V2 conversion result, and so on. The
eighth falling edge of
Channel V8. When the
conversion result from each channel to be transferred to the

digital host (DSP, FPGA).

and RD signals. To read the data over the parallel bus,

PA R

/SER/BYTE SEL pin should be tied low. The CS and RD

CS

and RD are logic low. When CS

RD

are low, DB15 and DB14 are used to output a sign

AD7607

BUSY

DB[15:0]

Figure 41. Interface Diagram—One AD7607 Using the Parallel Bus,

CS

signal can be permanently tied low, and the RD signal

CS

with

CS

input signal takes the bus out of the high

CS

is the control signal that enables the data

INTERRUPT

14

13

CS

12

RD

33:16

and RD Shorted Together

DIGITAL

HOST

8096-041

Figure 4

Figure 2

Figure 3

RD

pin is used to read data from the output conversion results

RD

pulses to the RD pin of the

RD

falling edge after BUSY goes low clocks out the

RD

falling edge

RD

clocks out the conversion result for

RD

signal is logic low, it enables the data

Rev. A | Page 24 of 32

When there is only one AD7607 in a system/board and it does not
share the parallel bus, data can be read using just one control
signal from the digital host. The
together, as shown in . In this case, the data bus comes

Figure 5

out of three-state on the falling edge of

RD

and

signal allows the data to be clocked out of the AD7607 and

to be read by the digital host. In this case,

CS

and RD signals can be tied

CS

/RD. The combined CS

CS

is used to frame

the data transfer of each data channel.

PARALLEL BYTE INTERFACE (PAR/SER/BYTE SEL = 1, DB15 = 1)

Parallel byte interface mode operates much like the parallel
interface mode, except that each channel conversion result is read
out in two 8-bit transfers. Therefore, 16

RD

pulses are required to
read all eight conversion results from the AD7607. To configure the
AD7607 to operate in parallel byte interface mode, the

PA R

/SER/

BYTE SEL and BYTE SEL/DB15 pins should be tied to logic high

Tabl e 8

(see ). DB[7:0] are used to transfer the data to the digital
host. DB0 is the LSB of the data transfer, and DB7 is the MSB of
the data transfer. In parallel byte mode, DB14 acts as an HBEN
pin. When the DB14/HBEN pin is tied to logic high, the most
significant byte (MSB) of the conversion result is output first,
followed by the LSB byte of the conversion result. When
DB14/HBEN is tied to logic low, the LSB byte of the conversion
result is output first, followed by the MSB byte of the conversion
result. The FRSTDATA pin remains high until the entire 14 bits
of the conversion result from V1 is read. If the MSB byte is
always to be read first, the HBEN pin should be set high and
remain high. If the LSB byte is always to be read first, the HBEN
pin should be set low and remain low. In this circumstance, the
MSB byte contains two sign extended bits in the two MSB
positions.

SERIAL INTERFACE (PAR/SER/BYTE SEL = 1)

To read data back from the AD7607 over the serial interface,

PA R

the
SCLK signals are used to transfer data from the AD7607. The
AD7607 has two serial data output pins, D
Data can be read back from the AD7607 using one or both of
these D
Channel V1 to Channel V4 first appear on D
conversion results from Channel V5 to Channel V8 first appear
on D

The
out of three-state and clocks out the MSB of the conversion result.
The rising edge of SCLK clocks all subsequent data bits onto the
serial data outputs, D
low for the entire serial read, or it can be pulsed to frame each
channel read of 14 SCLK cycles.

/SER/BYTE SEL pin must be tied high. The CS and

A and D

OUT

lines. For the AD7607, conversion results from

OUT

A, and

OUT

B.

OUT

CS

falling edge takes the data output lines, D

A and D

OUT

B. The CS input can be held

OUT

OUT

OUT

A and D

B.

OUT

B,

AD7607

http://www.BDTIC.com/ADI

Figure 42 shows a read of eight simultaneous conversion results
using two D
transfer is used to access data from the AD7607, and

lines on the AD7607. In this case, a 56 SCLK

OUT

CS

is
held low to frame the entire 56 SCLK cycles. Data can also
be clocked out using just one D
recommended that D

A be used to access all conversion data

OUT

line; in which case, it is

OUT

because the channel data is output in ascending order. For the
AD7607 to access all eight conversion results on one D

OUT

line,
a total of 112 SCLK cycles are required. These 112 SCLK cycles
can be framed by one

can be individually framed by the
of using just one D
reading occurs after conversion. The unused D
left unconnected in serial mode. If D
single D

line, the channel results are output in the following

OUT

CS

signal, or each group of 14 SCLK cycles

CS

signal. The disadvantage

line is that the throughput rate is reduced if

OUT

line should be

OUT

B is to be used as a

OUT

order: V5, V6, V7, V8, V1, V2, V3, and V4; however, the
FRSTDATA indicator returns low after V5 is read on D

OUT

B.

Figure 6 shows the timing diagram for reading one channel of
data, framed by the

CS

signal, from the AD7607 in serial mode.
The SCLK input signal provides the clock source for the serial
read operation. The
AD7607. The falling edge of

CS

goes low to access the data from the

CS

takes the bus out of three-state
and clocks out the MSB of the 14-bit conversion result. This
MSB is valid on the first falling edge of the SCLK after the

CS

falling edge.

The subsequent 13 data bits are clocked out of the AD7607 on the
SCLK rising edge. Data is valid on the SCLK falling edge. To access
each conversion result, 14 clock cycles must be provided.

The FRSTDATA output signal indicates when the first channel,
V1, is being read back. When the
output pin is in three-state. In serial mode, the falling edge of

CS

input is high, the FRSTDATA

CS

takes FRSTDATA out of three-state and sets the FRSTDATA pin
high, indicating that the result from V1 is available on the D

OUT

A
output data line. The FRSTDATA output returns to a logic low
following the 14
D

B, the FRSTDATA output does not go high when V1 is output

OUT

th

SCLK falling edge. If all channels are read on

on this serial data output pin. It goes high only when V1 is available
on D

A (and this is when V5 is available on D

OUT

OUT

B).

READING DURING CONVERSION

Data can be read from the AD7607 while BUSY is high and the
conversions are in progress. This has little effect the performance
of the converter, and it allows a faster throughput rate to be
achieved. A parallel, parallel byte, or serial read can be performed
during conversions and when oversampling is or is not
enabled. Figure 3 shows the timing diagram for reading while
BUSY is high in parallel or serial mode. Reading during
conversions allows the full throughput rate to be achieved when
using the serial interface with V

Data can be read from the AD7607 at any time other than on
the falling edge of BUSY because this is when the output data
registers get updated with the new conversion data. Time t
outlined in Tab l e 3 , should be observed in this condition.

above 3.3 V.

DRIVE

, as

6

CS

56

SCLK

A

D

OUT

B

D

OUT

V1 V4V2 V3

V5 V8V6 V7

Figure 42. Serial Interface with Two D

OUT

Lines

08096-042

Rev. A | Page 25 of 32

AD7607

http://www.BDTIC.com/ADI

DIGITAL FILTER

The AD7607 contains an optional first-order digital sinc filter that
should be used in applications where slower throughput rates are
used and digital filtering is required. The oversampling ratio of
the digital filter is controlled using the oversampling pins, OS[2:0]
(see Tabl e 9). OS 2 is the MSB control bit, and OS 0 is the LSB
control bit. Tab l e 9 lists the oversampling bit decoding to select the

Table 9. Oversample Bit Decoding

OS[2:0] Oversampling Ratio 3 dB BW, 5 V Range (kHz) 3 dB BW, 10 V Range (kHz)

000 No oversampling 15 22 200
001 2 15 22 100
010 4 13.7 18.5
011 8 10.3 11.9
100 16 6 6
101 32 3 3
110 64 1.5 1.5
111 Invalid

CONVST A

AND

CONVST B

CONVERSION N CONVERSION N + 1

BUSY

t

OS_SETUP

OS x

OVERSAMPLE RATE
LATCHED FOR CONVERSION N + 1

t

OS_HOLD

Figure 43. OS x Pin Timing

different oversample rates. The OS pins are latched on the falling
edge of BUSY. This sets the oversampling rate for the next
conversion (see Figure 43).

Selection of the oversampling mode has the effect of adding
a digital filter function after the ADC. The different oversampling
rates and the CONVST x sampling frequency produce different
digital filter frequency profiles.

Maximum Throughput,
CONVST Frequency (kHz)

50
25

12.5

6.25

3.125

08096-043

Rev. A | Page 26 of 32

AD7607

A

A

A

A

A

A

A

A

A

A

A

A

http://www.BDTIC.com/ADI

Figure 44 to Figure 49 show the digital filter frequency profiles for
the different oversampling ratios. The combination of the analog
antialiasing filter and the oversampling digital filter helps to reduce
the complexity of the design of the filter before the AD7607. The
digital filtering combines steep roll-off and linear phase response.

0

–10

–20

–30

–40

TION (dB)

–50

TTENU

–60

–70

AVCC = V

= 25°C

T

A

–80

±10V RANGE
OS BY 2

–90

100 1k 10k 100k 1M 10M

DRIVE

= 5V

FREQUENCY (Hz)

08096-011

Figure 44. Digital Filter Response for Oversampling by 2

0

–10

–20

–30

–40

TION (dB)

–50

TTENU

–60

–70

AVCC = V

= 25°C

T

A

–80

±10V RANGE
OS BY 4

–90

100 1k 10k 100k 1M 10M

DRIVE

= 5V

FREQUENCY (Hz)

08096-012

Figure 45. Digital Filter Response for Oversampling by 4

0

–10

–20

–30

–40

TION (dB)

–50

TTENU

–60

–70

AVCC = V

= 25°C

T

A

–80

±10V RANGE
OS BY 8

–90

100 1k 10k 100k 1M 10M

Figure 46. Digital Filter Response for Oversampling by 8

DRIVE

= 5V

FREQUENC Y (Hz)

08096-013

0

–10

–20

–30

–40

TION (dB)

–50

TTENU

–60

–70

AVCC = V

= 25°C

T

A

–80

±10V RANGE
OS BY 16

–90

100 1k 10k 100k 1M 10M

DRIVE

= 5V

FREQUENCY (Hz)

Figure 47. Digital Filter Response for Oversampling by 16

0

–10

–20

–30

–40

TION (dB)

–50

TTENU

–60

–70

AVCC = V
T

= 25°C

A

–80

±10V RANGE
OS BY 32

–90

100 1k 10k 100k 1M 10M

DRIVE

= 5V

FREQUENCY (Hz)

Figure 48. Digital Filter Response for Oversampling by 32

0

–10

–20

–30

–40

TION (dB)

–50

TTENU

–60

–70

AVCC = V

= 25°C

T

A

–80

±10V RANGE
OS BY 64

–90

100 1k 10k 100k 1M 10M

Figure 49. Digital Filter Response for Oversampling by 64

DRIVE

= 5V

FREQUENCY (Hz)

08096-014

08096-015

08096-016

Rev. A | Page 27 of 32

AD7607

http://www.BDTIC.com/ADI

NUMBER OF OCCURANCES

2000

1800

1600

1400

1200

1000

800

600

400

200

0

–2 –1 0

CODE

AVCC = 5V
V

= 5V

DRIVE

T

= 25°C

A

10V RANGE
OS64

12

08096-130

Figure 50. Histogram of Codes, Oversampling by 64

If the OS[2:0] pins are set to select an oversampling ratio of 8,
for example, the next CONVST x rising edge takes the first sample
for each channel. The remaining seven samples for all channels
are taken with an internally generated sampling signal. As the
oversampling ratio is increased, the 3 dB frequency is reduced and
the allowed sampling frequency is also reduced (see Ta ble 9 ). The
OS[2:0] pins should be configured to suit the filtering requirements
of the application.

The CONVST A and CONVST B pins must be tied/driven
together when oversampling is turned on. When the oversampling
function is turned on, the BUSY high time for the conversion

process extends. The actual BUSY high time depends on the over­sampling rate that is selected: the higher the oversampling rate,
the longer the BUSY high or total conversion time (see Tab l e 3).

Figure 51 shows that the conversion time extends as the over­sampling rate is increased. To achieve the fastest throughput
rate possible when oversampling is turned on, the read can be
performed during the BUSY high time. The falling edge of BUSY
is used to update the output data registers with the new conversion
data; therefore, the reading of conversion data should not occur on
this edge.

t

CYCLE

CONVST A

AND

CONVST B

BUSY

CS

RD

DATA:

DB[15:0]

Figure 51. No Oversampling, Oversampling by 4, and Oversampling by 8

t

CONV

39µs

19µs

4µs

OS = 0 OS = 4 OS = 8

t

4

t

4

t

4

Using Read After Conversion

08096-044

Rev. A | Page 28 of 32

AD7607

http://www.BDTIC.com/ADI

LAYOUT GUIDELINES

The printed circuit board that houses the AD7607 should be
designed so that the analog and digital sections are separated
and confined to different areas of the board.

At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the case of the
split plane, the digital and analog ground planes should be joined
in only one place, preferably as close as possible to the AD7607.

If the AD7607 is in a system where multiple devices require
analog-to-digital ground connections, the connection should
still be made at only one point: a star ground point that should be
established as close as possible to the AD7607. Good connections
should be made to the ground plane. Avoid sharing one connection
for multiple ground pins. Use individual vias or multiple vias to
the ground plane for each ground pin.

Avoid running digital lines under the devices because doing so
couples noise onto the die. The analog ground plane should be
allowed to run under the AD7607 to avoid noise coupling. Fast
switching signals like CONVST A, CONVST B, or clocks should
be shielded with digital ground to avoid radiating noise to other
sections of the board, and they should never run near analog
signal paths. Avoid crossover of digital and analog signals. Traces
on layers in close proximity on the board should run at right angles
to each other to reduce the effect of feedthrough through the board.

The power supply lines to the AV

and V

CC

pins should use

DRIVE

as large a trace as possible to provide low impedance paths and
reduce the effect of glitches on the power supply lines. Where
possible, use supply planes and make good connections between
the AD7607 supply pins and the power tracks on the board.
Use a single via or multiple vias for each supply pin.

Good decoupling is also important in lowering the supply
impedance presented to the AD7607 and in reducing the
magnitude of the supply spikes. The decoupling capacitors
should be placed close to (ideally, right up against) these pins
and their corresponding ground pins. Place the decoupling
capacitors for the REFIN/REFOUT pin and the REFCAPA and
REFCAPB pins as close as possible to their respective AD7607
pins; and, where possible, they should be placed on the same
side of the board as the AD7607 device.

Figure 52 shows the recommended decoupling on the top layer
of the AD7607 board. Figure 53 shows bottom layer decoupling,
which is used for the four AV

Figure 52. Top Layer Decoupling REFIN/REFOUT,

REFCAPA, REFCAPB, and REGCAP Pins

pins and the V

CC

DRIVE

pin.

8096-048

08096-049

Figure 53. Bottom Layer Decoupling

Rev. A | Page 29 of 32

AD7607

http://www.BDTIC.com/ADI

To ensure good device-to-device performance matching in
a system that contains multiple AD7607 devices, a symmetrical
layout between the devices is important.

Figure 54 shows a layout with two AD7607 devices. The AV
supply plane runs to the right of both devices. The V

DRIVE

CC

supply
track runs to the left of the two AD7607 devices. The reference
chip is positioned between the two AD7607 devices, and the
reference voltage track runs north to Pin 42 of U1 and south to
Pin 42 of U2. A solid ground plane is used. These symmetrical
layout principles can also be applied to a system that contains
more than two AD7607 devices. The AD7607 devices can be
placed in a north-south direction with the reference voltage
located midway between the AD7607 devices and the reference
track running in the north-south direction, similar to Figure 54.

Figure 54. Layout for Multiple AD7607 Devices—Top Layer and

Supply Plane Layer

U2

U2

U1

U1

AVCC

AVCC

08096-050

Rev. A | Page 30 of 32

AD7607

http://www.BDTIC.com/ADI

OUTLINE DIMENSIONS

12.20

PIN 1

12.00 SQ

11. 80

4964

48

0.75

0.60

0.45

1.60
MAX

1

10.20

10.00 SQ

9.80

33

32

-A

051706

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.20

0.09
7°

3.5°
0°

0.08
COPLANARIT Y

COMPLIANT TO JEDEC STANDARDS MS-026-BCD

16

17

VIEW A

LEAD PITCH

0.50
BSC

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

Figure 55. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

1

Model

AD7607BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
AD7607BSTZ-RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
EVAL-AD7607EDZ −40°C to +85°C Evaluation Board
CED1Z Converter Evaluation Development

1

Z = RoHS Compliant Part.

Temperature Range Package Description Package Option

Rev. A | Page 31 of 32