Datasheet AD7568BS, AD7568BP Datasheet (Analog Devices)

FUNCTIONAL BLOCK DIAGRAM

R B

R F

DAC A

DAC A
LATCH

INPUT

LATCH A

INPUT

LATCH B

INPUT

LATCH C

INPUT

LATCH D

INPUT

LATCH E

INPUT

LATCH F

INPUT

LATCH G

DAC B
LATCH

DAC C
LATCH

DAC D
LATCH

DAC E
LATCH

DAC F

LATCH

DAC G

LATCH

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

V B

REF

V D

REF

R G

FB

V G

REF

V F

REF

V E

REF

FB

FB

R E

R D

R C

FB

FB

R A

FBREF

V AV C

REF

V

DD

DGND

LDAC

CLR

AD7568

12

12

12

12

12

12

12

12

12

12

12

12

12

12

V H

REF

A0

CONTROL LOGIC

+

INPUT SHIFT

REGISTER

CLKIN

SDIN

SDOUT

INPUT

LATCH H

DAC H
LATCH

DAC H

R H

FB

12

12

FSIN

I A
I A

I B
I B

I C

I D

I C

I D

I E

I F

I E

I F

I G

I H

I G

I H

AGND

12

OUT1
OUT2

OUT1

OUT2

OUT1

OUT2

FB

OUT1

OUT2

OUT1

OUT2

OUT1
OUT2

OUT1
OUT2

OUT1
OUT2

a

LC2MOS

Octal 12-Bit DAC

AD7568

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

FEATURES
Eight 12-Bit DACs in One Package
4-Quadrant Multiplication
Separate References
Single +5 V Supply
Low Power: 1 mW
Versatile Serial Interface
Simultaneous Update Capability
Reset Function
44-Pin PQFP and PLCC

APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation

PIN CONFIGURATIONS

Plastic Quad Flatpack Plastic Leaded Chip Carrier

AD7568

TOP VIEW

(Not to Scale)

121314

151617

181920

21

22

4443424140393837363534

33
32
31
30
29
28
27
26
25
24
23

1
2
3
4
5
6
7
8

9
10
11

PIN 1 IDENTIFIER

NC

V B

REF

V D

REF

R G

FB

V G

REF

V F

REF

V E

REF

FB

R F

FB

R E

FB

R D

R C

FB

FB

R B

R A

FB

REF

V A

V C

REF

VDDDGND

LDAC

CLR

V H

REF

A0

CLKIN

SDIN

SDOUT

R H

FB

FSIN

I C

I F

I E

I H

AGND

NC

NC = NO CONNECT

OUT2

I E

OUT1

I D

OUT1

I D

OUT2

OUT1

I C

OUT2

I B

OUT1

I B

OUT2

OUT1

I H

OUT2

I A

OUT2

I A

OUT1

OUT1

I F

OUT2

I G

OUT1

I G

OUT2

AD7568 PQFP

TOP VIEW

Not to Scale

NC = NO CONNECT

NC
V

REF

C

V

REF

B

R

FB

B

I

OUT1

B

I

OUT1

C

NC

V

REF

F

V

REF

G

R

FB

G

R

FB

F

I

OUT2

F

I

OUT2

E

I

OUT1

E

V

DD

DGND

AGND

R

FB

E

I

OUT1

H

I

OUT2

H

LDAC

FSIN

SDIN

SDOUT

CLR

V

REF

E

R

FB

D

I

OUT1

D

A0

I

OUT2

A

I

OUT1

A

CLKIN

V

REF

D

V

REF

A

R

FB

A

I

OUT2

B

I

OUT2

G

V

REF

H

R

FB

H

I

OUT1

G

4412645

21 24

23

22182019

39
38

35
34
33

37
36

3

7
8

11
12
13

9

10

404142

25 28

27

26

43

31
30
29

32
15
16
17

14

TOP VIEW

(Not to Scale)

AD7568 PLCC

I

OUT2

D

I

OUT2

C

R

FB

C

I

OUT1

F

GENERAL DESCRIPTION

The AD7568 contains eight 12-bit DACs in one monolithic de­vice. The DACs are standard current output with separate V

REF

,

I

OUT1

, I

OUT2

and RFB terminals.

The AD7568 is a serial input device. Data is loaded using
FSIN, CLKIN and SDIN. One address pin, A0, sets up a de­vice address, and this feature may be used to simplify device
loading in a multi-DAC environment.

All DACs can be simultaneously updated using the asynchro­nous

LDAC input and they can be cleared by asserting the

asynchronous

CLR input.

The AD7568 is housed in a space-saving 44-pin plastic quad
flatpack and 44-lead PLCC.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

REV. B

–2–

AD7568–SPECIFICA TIONS

1

Parameter AD7568B

2

Units Test Conditions/Comments

ACCURACY

Resolution 12 Bits 1 LSB = V

REF

/212 = 1.22 mV when V

REF

= 5 V
Relative Accuracy ±0.5 LSB max
Differential Nonlinearity ± 0.9 LSB max All Grades Guaranteed Monotonic over Temperature
Gain Error

+25°C ±4 LSBs max
T

MIN

to T

MAX

±5 LSBs max

Gain Temperature Coefficient 2 ppm FSR/°C typ

5 ppm FSR/°C max

Output Leakage Current

I

OUT1

@ +25°C 10 nA max See Terminology Section
T

MIN

to T

MAX

200 nA max

REFERENCE INPUT

Input Resistance 5 kΩ min Typical Input Resistance = 7 kΩ

9kΩ max

Ladder Resistance Mismatch 2 % max Typically 0.6%

DIGITAL INPUTS

V

INH

, Input High Voltage 2.4 V min

V

INL

, Input Low Voltage 0.8 V max

I

INH

, Input Current ±1 µA max

CIN, Input Capacitance 10 pF max

POWER REQUIREMENTS

V

DD

Range 4.75/5.25 V min/V max

Power Supply Sensitivity

∆Gain/∆V

DD

–75 dB typ

I

DD

300 µA max V

INH

= 4.0 V min, V

INL

= 0.4 V max

3.5 mA max V

INH

= 2.4 V min, V

INL

= 0.8 V max

AC PERFORMANCE CHARACTERISTICS

Parameter AD7568B

2

Units Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 500 ns typ To 0.01% of Full-Scale Range. DAC Latch Alternately

Loaded with All 0s and All 1s.

Digital to Analog Glitch Impulse 40 nV–s typ Measured with V

REF

= 0 V. DAC Register Alternately

Loaded with All 0s and All 1s.

Multiplying Feedthrough Error –66 dB max V

REF

= 20 V pk-pk, 10 kHz Sine Wave. DAC Latch

Loaded with All 0s.

Output Capacitance 60 pF max All 1s Loaded to DAC.

30 pF max All 0s Loaded to DAC.

Channel-to-Channel Isolation –76 dB typ Feedthrough from Any One Reference to the Others

with 20 V pk-pk, 10 kHz Sine Wave Applied.

Digital Crosstalk 40 nV–s typ Effect of all 0s to all 1s Code Transition on

Nonselected DACs.

Digital Feedthrough 40 nV–s typ Feedthrough to Any DAC Output with

FSIN High

and Square Wave Applied to SDIN and SCLK.

Total Harmonic Distortion –83 dB typ V

REF

= 6 V rms, 1 kHz Sine Wave.

Output Noise Spectral Density

@ 1 kHz 20 nV/√

Hz All 1s Loaded to the DAC. V

REF

= 0 V. Output Op

Amp is AD OP07.

NOTES

1

Temperature range as follows: B Version: –40°C to +85°C.

2

All specifications also apply for V

REF

= +10 V, except relative accuracy which degrades to ±1 LSB.

Specifications subject to change without notice.

(VDD = +4.75 V to +5.25 V; I

OUT1

= I

OUT2

= O V; V

REF

= +5 V; TA = T

MIN

to T

MAX

,

unless otherwise noted)

(These characteristics are included for Design Guidance and are not subject
to test. DAC output op amp is AD843.)

AD7568

REV. B

–3–

TIMING SPECIFICATIONS

Limit at Limit at

Parameter TA = +258CT

A

= –408C to +858C Units Description

t

1

100 100 ns min CLKIN Cycle Time

t

2

40 40 ns min CLKIN High Time

t

3

40 40 ns min CLKIN Low Time

t

4

30 30 ns min FSIN Setup Time

t

5

30 30 ns min Data Setup Time

t

6

5 5 ns min Data Hold Time

t

7

90 90 ns min FSIN Hold Time

t

8

2

70 70 ns max SDOUT Valid After CLKIN Falling Edge

t

9

40 40 ns min LDAC, CLR Pulse Width

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

t8 is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.

CLKIN (I)

SDIN (I)

SDOUT (O)

DB15 DB0

DB15

DB0

FSIN (I)

LDAC, CLR

t

1

t

4

t

7

t

2

t

3

t

6

t

5

t

8

t

9

NOTES

1. AO IS HARDWIRED HIGH OR LOW.

Figure 1. Timing Diagram

(VDD = +5 V 6 5%; I

OUT1

= I

OUT2

= 0 V; TA = T

MIN

to T

MAX

, unless otherwise noted)

1.6mA I

OL

+2.1V

I

OH

200µA

C

L

50pF

TO OUTPUT

PIN

Figure 2. Load Circuit for Digital Output
Timing Specifications

ORDERING GUIDE

Temperature Linearity Package

Model Range Error (LSBs) Option*

AD7568BS –40°C to +85°C ±0.5 S-44
AD7568BP –40°C to +85°C ±0.5 P-44A

*S = Plastic Quad Flatpack (PQFP), P = Plastic Leaded Chip Carrier (PLCC).

AD7568

REV. B

–4–

ABSOLUTE MAXIMUM RATINGS

1

(TA = +25°C unless otherwise noted)

VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

I

OUT1

to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V

I

OUT2

to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V

Digital Input Voltage to DGND . . . . . . –0.3 V to V

DD

+0.3 V

V

RFB

, V

REF

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V

Input Current to Any Pin Except Supplies

2

. . . . . . . . ±10 mA

Operating Temperature Range

Commercial Plastic (B Versions) . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . . 250 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7568 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

PIN DESCRIPTION

Pin Description

V

DD

Positive power supply. This is +5 V ± 5%.
DGND Digital Ground.
AGND Analog Ground.
V

REF

A – V

REF

H DAC reference inputs.

R

FB

A – RFBH DAC feedback resistor pins.

I

OUT

A – I

OUT

H DAC current output terminals.

AGND This pin connects to the back gates of the current steering switches. It should be connected to the signal ground

of the system.
CLKIN Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN.

FSIN Level-triggered control input (active low). This is the frame synchronization signal for the input data. When

FSIN goes low, it enables the input shift register, and data is transferred on the falling edges of CLKIN. If the

address bit is valid, the 12-bit DAC data is transferred to the appropriate input latch on the sixteenth falling

edge after

FSIN goes low.

SDIN Serial data input. The device accepts a 16-bit word. The first bit (DB15) is the DAC MSB, with the remaining

bits following. Next comes the device address bit, A0. If this does not correspond to the logic level on pin A0,

the data is ignored. Finally come the three DAC select bits. These determine which DAC in the device is se-

lected for loading.
SDOUT This shift register output allows multiple devices to be connected in a daisy chain configuration.
A0 Device address pin. This input gives the device an address. If DB3 of the serial input stream does not corre-

spond to this, the data which follows is ignored and not loaded to any input latch. However it will appear at

SDOUT irrespective of this.
LDAC Asynchronous LDAC input. When this input is taken low, all DAC latches are simultaneously updated with the

contents of the input latches.
CLR Asynchronous CLR input. When this input is taken low, all DAC latch outputs go to zero.

AD7568

REV. B

–5–

TERMINOLOGY
Relative Accuracy

Relative Accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally ex­pressed in Least Significant Bits or as a percentage or full-scale
reading.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.

Gain Error

Gain Error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error has been adjusted out and is
expressed in Least Significant Bits. Gain error is adjustable to
zero with an external potentiometer.

Output Leakage Current

Output leakage current is current which flows in the DAC lad­der switches when these are turned off. For the I

OUT1

terminal,
it can be measured by loading all 0s to the DAC and measuring
the I

OUT1

current. Minimum current will flow in the I

OUT2

line
when the DAC is loaded with all 1s. This is a combination of
the switch leakage current and the ladder termination resistor
current. The I

OUT2

leakage current is typically equal to that in

I

OUT1

.

Output Capacitance

This is the capacitance from the I

OUT1

pin to AGND.

Output Voltage Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For the AD7568, it
is specified with the AD843 as the output op amp.

Digital to Analog Glitch Impulse

This is the amount of charge injected into the analog output
when the inputs change state. It is normally specified as the area
of the glitch in either pA-secs or nV-secs, depending upon
whether the glitch is measured as a current or voltage signal. It
is measured with the reference input connected to AGND and
the digital inputs toggled between all 1s and all 0s.

AC Feedthrough Error

This is the error due to capacitive feedthrough from the DAC
reference input to the DAC I

OUT

terminal, when all 0s are

loaded in the DAC.

Channel-to-Channel Isolation

Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input which appears at the
output of any other DAC in the device and is expressed in dBs.

Digital Crosstalk

The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the Digital Crosstalk and is specified in nV-secs.

Digital Feedthrough

When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the de­vice to show up as noise on the I

OUT

pin and subsequently on

the op amp output. This noise is digital feedthrough.

Table I. AD7568 Loading Sequence

DB15 DB0

DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A0 DS2 DS1 DS0

Table II. DAC Selection

DS2 DS1 DS0 Function

0 0 0 DAC A Selected
0 0 1 DAC B Selected
0 1 0 DAC C Selected
0 1 1 DAC D Selected
1 0 0 DAC E Sclected
1 0 1 DAC F Selected
1 1 0 DAC G Sclected
1 1 1 DAC H Selected

AD7568

REV. B

–6–

5.5

0.0

5.0

1.5

0.5

1.0

1.0

0.0

3.0

2.0

2.5

3.5

4.0

4.5

5.0

4.03.02.0

DIGITAL INPUT – Volts

I – mA

DD

V = +5V
T = +25°C

DD

A

Figure 3. Supply Current vs. Logic
Input Voltage

1.0

0.0

10.0

0.3

0.1

4.0

0.2

2.0

0.6

0.4

0.5

0.7

0.8

0.9

8.06.0

V = +5V
T = +25°C

DD

A

V – Volts

REF

INL – LSBs

Figure 6. Integral Nonlinearity Error
vs. V

REF

10

90

100

0%



50mV



5V



200ns



200ns

DIGITAL INPUTS

AD713 OUTPUT

V = +5V
T = +25°C
V = +10V
OP AMP = AD713

DD
A
REF

Figure 9. Digital-to-Analog Glitch
Impulse

–Typical Performance Curves

2

0

85–15–40

1

6010

35

TEMPERATURE – °C

I – mA

DD

V = +5V

DD

V = +2.4V

IH

V = +4V

IH

Figure 4. Supply Current vs.
Temperature

1.0

0.0
4095

0.6

0.2

2048

0.4

0

0.8

DIGITAL CODE

INL SPREAD – LSBs

V = +10V
V = +5V
T = +25°C

REF
DD

A

Figure 7. Typical DAC to DAC
Linearity Matching

0

–100

–70

–90

–80

–40

–60

–50

–30

–20

–10

10

3

10

4

10

5

10

6

FREQUENCY – Hz

V B/V C – dBs

OUT

OUT

V C = 20V pk-pk SINE WAVE
ALL OTHER REFERENCE INPUTS GROUNDED
DAC C LOADED WITH ALL 1s
ALL OTHER DACs LOADED WITH ALL 0s

REF

Figure 10. Channel-to-Channel
Isolation (1 DAC to 1 DAC)

1.0

0.0

10.0

0.3

0.1

4.0

0.2

2.0

0.6

0.4

0.5

0.7

0.8

0.9

8.0

6.0

V = +5V
T = +25°C

DD
A

V – Volts

REF

DNL – LSBs

Figure 5. Differential Nonlinearity
Error vs. V

REF

–50

–100

–85

–95

–90

–70

–80

–75

–65

–60

–55

10

2

10

3

10

4

10

5

FREQUENCY – Hz

THD – dBs

V = +5V
T = +25°C
V = 6V rms
OP AMP = AD713

DD

A

IN

Figure 8. Total Harmonic Distortion
vs. Frequency

0

–100

–70

–90

–80

–40

–60

–50

–30

–20

–10

10

3

10

4

10

5

10

6

FREQUENCY – Hz

V B/V C – dBs

OUT

OUT

V B GROUNDED
ALL OTHER REFERENCE INPUTS =
20V pk-pk SINE WAVE
DAC B LOADED WITH ALL 0s
ALL OTHER DACs LOADED WITH ALL 1s

REF

Figure 11. Channel-to-Channel
Isolation (1 DAC to All Other DACs)

AD7568

REV. B

–7–

Interface Section

The AD7568 is a serial input device. Three lines control the se­rial interface,

FSIN, CLKIN and SDIN. The timing diagram is

shown in Figure 1.
When the

FSIN input goes low, data appearing on the SDIN
line is clocked into the input shift register on each falling edge of
CLKIN. When sixteen bits have been received, the register
loading is automatically disabled until the next falling edge of
FSIN detected. Also, the received data is clocked out on the
next rising edge of CLKIN and appears on the SDOUT pin.
This feature allows several devices to be connected together in a
daisy chain fashion.

When the sixteen bits have been received in the input shift regis­ter, DB3 (A0) is checked to see if it corresponds to the state of
pin A0. If it does, then the word is accepted. Otherwise, it is dis­regarded. This allows the user to address one of two AD7568s
in a very simple fashion. DB0 to DB2 of the 16-bit word deter­mine which of the eight DAC input latches is to be loaded.
When the

LDAC line goes low, all eight DAC latches in the de­vice are simultaneously loaded with the contents of their respec­tive input latches, and the outputs change accordingly.

Bringing the

CLR line low resets the DAC latches to all 0s. The
input latches are not affected, so that the user can revert to the
previous analog output if desired.

16-BIT INPUT SHIFT REGISTER

CLKIN

SDIN SDOUT

FSIN

Figure 14. Input Logic

0

–100

–70

–90

–80

–40

–60

–50

–30

–20

–10

10

3

10

4

10

5

10

6

10

7

V = +5V
T = +25°C
V = 20V pk-pk
OP AMP = AD713

DD

A

IN

DAC LOADED WITH ALL 1s

DAC LOADED WITH ALL 0s

Figure 12. Multiplying Frequency Response vs.
Digital Code

GENERAL DESCRIPTION
D/A Section

The AD7568 contains eight 12-bit current-output D/A convert­ers. A simplified circuit diagram for one of the D/A converters is
shown in Figure 13.

A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A, B and C.
The remaining 10 bits of the data word drive the switches S0 to
S9 in a standard R–2R ladder configuration.

Each of the switches A to C steers 1/4 of the total reference cur­rent with the remaining current passing through the R–2R
section.

Each DAC in the device has separate V

REF

, I

OUT1

, I

OUT2

and

R

FB

pins. This makes the device extremely versatile and allows

DACs in the same device to be configured differently.
When an output amplifier is connected in the standard configu-

ration of Figure 15, the output voltage is given by:

V

OUT

= –D•V

REF

where D is the fractional representation of the digital word
loaded to the DAC. Thus, in the AD7568, D can be set from
0 to 4095/4096.

V

REF

2R 2R 2R 2R 2R 2R 2R

CBA

S9

S8 S9

R

FB

I

OUT1

I

OUT2

R

R

R

R/2

SHOWN FOR ALL 1s ON DAC

Figure 13. Simplified D/A Circuit Diagram

AD7568

REV. B

–8–

UNIPOLAR BINARY OPERATION
(2-Quadrant Multiplication)

Figure 15 shows the standard unipolar binary connection dia­gram for one of the DACs in the AD7568. When V

IN

is an ac
signal, the circuit performs 2-quadrant multiplication. Resistors
R1 and R2 allow the user to adjust the DAC gain error. Offset
can be removed by adjusting the output amplifier offset voltage.

A1 should be chosen to suit the application. For example, the
AD OP07 or OP177 are ideal for very low bandwidth applica­tions while the AD843 and AD845 offer very fast settling time
in wide bandwidth applications. Appropriate multiple versions
of these amplifiers can be used with the AD7568 to reduce
board space requirements.

The code table for Figure 15 is shown in Table III.

DAC A

A1

I A

OUT1

I A

OUT2

AD7568

V

OUT

R A

FB

V A

REF

V

IN

NOTES

1. ONLY ONE DAC IS SHOWN FOR CLARITY.

2. DIGITAL INPUT CONNECTIONS ARE OMITTED.

3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.

R2 10Ω

R1 20Ω

SIGNAL

GND

A1: OP-177

ADOP-07
AD711
AD843
AD845

C1

Figure 15. Unipolar Binary Operation

Table III. Unipolar Binary Code Table

Digital Input Analog Output
MSB………LSB (V

OUT

As Shown in Figure 15)

1111 1111 1111 –V

REF

(4095/4096)

1000 0000 0001 –V

REF

(2049/4096)

1000 0000 0000 –V

REF

(2048/4096)

0111 1111 1111 –V

REF

(2047/4096)

0000 0000 0001 –V

REF

(1/4096)

0000 0000 0000 –V

REF

(0/4096) = 0

NOTE
Nominal LSB size for the circuit of Figure 15 is given by:
V

REF

(1/4096).

BIPOLAR OPERATION
(4-Quadrant Multiplication)

Figure 16 shows the standard connection diagram for bipolar
operation of any one of the DACs in the AD7568. The coding is
offset binary as shown in Table IV. When V

IN

is an ac signal,
the circuit performs 4-quadrant multiplication. To maintain the
gain error specifications, resistors R3, R4 and R5 should be ra­tio matched to 0.01%.

DAC A

A1

I A

OUT1

I A

OUT2

AD7568

V

OUT

R A

FB

V A

REF

V

IN

NOTES

1. ONLY ONE DAC IS SHOWN FOR CLARITY.

2. DIGITAL INPUT CONNECTIONS ARE OMITTED.

3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.

R2 10Ω

R1 20Ω

SIGNAL

GND

C1

A2

R3

10kΩ

R5

20kΩ

20kΩ

R4

Figure 16. Bipolar Operation (4-Quadrant Multiplication)

Table IV. Bipolar (Offset Binary) Code Table

Digital Input Analog Output

MSB . . . . . LSB (V

OUT

As Shown in Figure 16)

1111 1111 1111 +V

REF

(2047/2048)

1000 0000 0001 +V

REF

(1/2048)

1000 0000 0000 +V

REF

(0/2048) = 0

0111 1111 1111 –V

REF

(1/2048)

0000 0000 0001 –V

REF

(2047/2048)

0000 0000 0000 –V

REF

(2048/2048) = –V

REF

NOTE
Nominal LSB size for the circuit of Figure 16 is given by:
V

REF

(1/2048).

SINGLE SUPPLY CIRCUITS

The AD7568 operates from a single +5 V supply, and this
makes it ideal for single supply systems. When operating in such
a system, it is not possible to use the standard circuits of Figures
15 and 16 since these invert the analog input, V

IN

. There are
two alternatives. One of these continues to operate the DAC as
a current-mode device, while the other uses the voltage switch­ing mode.

DAC A

A1

I A

OUT1

I A

OUT2

AD7568

V

BIAS

V

OUT

R A

FB

V A

REF

V

IN

NOTES

1. ONLY ONE DAC IS SHOWN FOR CLARITY.

2. DIGITAL INPUT CONNECTIONS ARE OMITTED.

3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.

Figure 17. Single Supply Current-Mode Operation

AD7568

REV. B

–9–

Current Mode Circuit

In the current mode circuit of Figure 17, I

OUT2

, and hence

I

OUT1

, is biased positive by an amount V

BIAS

. For the circuit to
operate correctly, the DAC ladder termination resistor must be
connected internally to I

OUT2

. This is the case with the AD7568.

The output voltage is given by:

V

OUT

= D

R

FB

R

DAC

V

BIAS−VIN

()

{}

+V

BIAS

As D varies from 0 to 4095/4096, the output voltage varies from
V

OUT

= V

BIAS

to V

OUT

= 2 V

BIAS

– VIN. V

BIAS

should be a low
impedance source capable of sinking and sourcing all possible
variations in current at the I

OUT2

terminal without any

problems.

Voltage Mode Circuit

Figure 18 shows DAC A of the AD7568 operating in the
voltage-switching mode. The reference voltage, V

IN

is applied to

the I

OUT1

pin, I

OUT2

is connected to AGND and the output volt-

age is available at the V

REF

terminal. In this configuration, a
positive reference voltage results in a positive output voltage
making single supply operation possible. The output from the
DAC is a voltage at a constant impedance (the DAC ladder re­sistance). Thus, an op amp is necessary to buffer the output
voltage. The reference voltage input no longer sees a constant
input impedance, but one which varies with code. So, the volt­age input should be driven from a low impedance source.

It is important to note that V

IN

is limited to low voltages be­cause the switches in the DAC no longer have the same source­drain voltage. As a result, their on-resistance differs and this
degrades the integral linearity of the DAC. Also, V

IN

must not
go negative by more than 0.3 volts or an internal diode will turn
on, causing possible damage to the device. This means that the
full-range multiplying capability of the DAC is lost.

DAC A

A1

I A

OUT1

I A

OUT2

AD7568

V

OUT

R A

FB

V A

REF

V

IN

NOTES

1) ONLY ONE DAC IS SHOWN FOR CLARITY.

2) DIGITAL INPUT CONNECTIONS ARE OMITTED.

3) C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.

R1 R2

Figure 18. Single Supply Voltage Switching
Mode Operation

APPLICATIONS
Programmable State Variable Filter

The AD7568 with its multiplying capability and fast settling
time is ideal for many types of signal conditioning applications.
The circuit of Figure 19 shows its use in a state variable filter
design. This type of filter has three outputs: low pass, high pass
and bandpass. The particular version shown in Figure 19 uses
one half of an AD7568 to control the critical parameters f

0

, Q

and A

0

. Instead of several fixed resistors, the circuit uses the
DAC equivalent resistances as circuit elements. Thus, R1 in
Figure 19 is controlled by the 12-bit digital word loaded to
DAC A of the AD7568. This is also the case with R2, R3 and
R4. The fixed resistor R5 is the feedback resistor, R

FB

B.

DAC Equivalent Resistance, R

EQ

= (R

LADDER

3 4096)/N

where:

R

LADDER

is the DAC ladder resistance.

N is the DAC Digital Code in Decimal (0 < N < 4096).

DAC A

(R1)

DAC B

(R2)

1/2 x AD7568

A1

A1

R8 30kΩ

HIGH
PASS
OUTPUT

DAC C

(R3)

I A

OUT1

I C

OUT1

R BFBV B

REF

V

IN

I B

OUT1

V C

REF

DAC D

(R4)

C3 10pF

C1 1000pF

R7 30kΩ

C1 1000pF

LOW
PASS
OUTPUT

BAND
PASS
OUTPUT

V A

REF

I C

OUT2

I B

OUT2

I A

OUT2

I D

OUT2

V D

REF

I D

OUT1

A2

A3

R6

10kΩ

NOTES

1. A1, A2, A3, A4: 1/4 x AD713

2. DIGITAL INPUT CONNECTIONS ARE OMITTED.

3. C3 IS A COMPENSATION CAPACITOR TO ELIMINATE
Q AND GAIN VARIATIONS CAUSED BY AMPLIFIER GAIN
BANDWIDTH LIMITATIONS.

Figure 19. Programmable 2nd Order State Variable Filter

AD7568

REV. B

–10–

In the circuit of Figure 19:

C1 = C2, R7 = R8, R3 = R4 (i.e., the same code is loaded to
each DAC).

Resonant frequency, f0 = 1/(2πR3C1).
Quality Factor, Q = (R6/R8)•(R2/R5).
Bandpass Gain, A0 = –R2/R1.

Using the values shown in Figure 19, the Q range is 0.3 to 5,
and the f

0

range is 0 to 12 kHz.

APPLICATION HINTS
Output Offset

CMOS D/A converters in circuits such as Figures 15, 16 and 17
exhibit a code dependent output resistance which in turn can
cause a code dependent error voltage at the output of the ampli­fier. The maximum amplitude of this error, which adds to the
D/A converter nonlinearity, depends on V

OS

, where VOS is the
amplifier input offset voltage. For the AD7568 to maintain
specified accuracy with V

REF

at 10 V, it is recommended that

V

OS

be no greater than 500 µV, or (50 3 10–6)•(V

REF

), over the
temperature range of operation. Suitable amplifiers include the
AD OP07, AD OP27, OP177, AD711, AD845 or multiple ver­sions of these.

Temperature Coefficients

The gain temperature coefficient of the AD7568 has a maxi­mum value of 5 ppm/°C and a typical value of 2 ppm/°C. This
corresponds to gain shifts of 2 LSBs and 0.8 LSBs respectively
over a 100°C temperature range. When trim resistors R1 and
R2 are used to adjust full-scale in Figures 15 and 16, their tem­perature coefficients should be taken into account. For further
information see “Gain Error and Gain Temperature Coefficient
of CMOS Multiplying DACs,” Application Note, Publication
Number E630c–5–3/86, available from Analog Devices.

High Frequency Considerations

The output capacitances of the AD7568 DACs work in con­junction with the amplifier feedback resistance to add a pole to
the open loop response. This can cause ringing or oscillation.
Stability can be restored by adding a phase compensation ca­pacitor in parallel with the feedback resistor. This is shown as
C1 in Figures 15, 16 and 17.

MICROPROCESSOR INTERFACING
AD7568–80C51 Interface

A serial interface between the AD7568 and the 80C51 micro­controller is shown in Figure 20. TXD of the 80C51 drives
SCLK of the AD7568 while RXD drives the serial data line of
the part. The

FSIN signal is derived from the port line P3.3.

The 80C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. Therefore, the user will have to ensure
that the data in the SBUF register is arranged correctly so that

the data word transmitted to the AD7568 corresponds to the
loading sequence shown in Table I. When data is to be trans­mitted to the part, P3.3 is taken low. Data on RXD is valid on
the falling edge of TXD. The 80C51 transmits its serial data in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. To load data to the AD7568, P3.3 is left low af­ter the first eight bits are transferred, and a second byte of data
is then transferred serially to the AD7568. When the second se­rial transfer is complete, the P3.3 line is taken high. Note that
the 80C51 outputs the serial data byte in a format which has the
LSB first. The AD7568 expects the MSB first. The 80C51
transmit routine should take this into account.

P3.5

P3.4

P3.3

TXD

RXD

SCLK

SDIN

CLR

LDAC

FSIN

80C51*

AD7568*

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 20. AD7568 to 80C51 Interface

LDAC and CLR on the AD7568 are also controlled by 80C51
port outputs. The user can bring

LDAC low after every two
bytes have been transmitted to update the DAC which has been
programmed. Alternatively, it is possible to wait until all the in­put registers have been loaded (sixteen byte transmits) and then
update the DAC outputs.

AD7568–68HC11 Interface

Figure 21 shows a serial interface between the AD7568 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7568, while the MOSI output drives the serial data line
of the AD7568. The

FSIN signal is derived from a port line

(PC7 shown).
For correct operation of this interface, the 68HC11 should be

configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transmitted to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial
data in 8-bit bytes (MSB first), with only eight falling clock
edges occurring in the transmit cycle. To load data to the
AD7568, PC7 is left low after the first eight bits are transferred,
and a second byte of data is then transferred serially to the
AD7568. When the second serial transfer is complete, the PC7
line is taken high.

AD7568

REV. B

–11–

PC5

PC6

PC7

SCK

MOSI

CLKIN

SDIN

CLR

LDAC

FSIN

68HC11*

AD7568*

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 21. AD7568 to 68HC11 Interface

In Figure 21, LDAC and CLR are controlled by the PC6 and
PC5 port outputs. As with the 80C51, each DAC of the
AD7568 can be updated after each two-byte transfer, or else all
DACs can be simultaneously updated.

AD7568–ADSP-2101 Interface

Figure 22 shows a serial interface between the AD7568 and the
ADSP-2101 digital signal processor. The ADSP-2101 may be
set up to operate in the SPORT Transmit Normal Internal
Framing Mode. The following ADSP-2101 conditions are rec­ommended: Internal SCLK; Active High Framing Signal; 16-bit
word length. Transmission is initiated by writing a word to the
TX register after the SPORT has been enabled. The data is then
clocked out on every rising edge of SCLK after TFS goes low.
TFS stays low until the next data transfer.

FO

TFS

DT

SCLK CLKIN

SDIN

CLR

LDAC

FSIN

ADSP-2101*

AD7568*

*ADDITIONAL PINS OMITTED FOR CLARITY

+5V

Figure 22. AD7568 to ADSP-2101 Interface

AD7568–TMS320C25 Interface

Figure 23 shows an interface circuit for the TMS320C25
digital signal processor. The data on the DX pin is clocked
out of the processor’s Transmit Shift Register by the CLKX
signal. Sixteen-bit transmit format should be chosen by setting
the FO bit in the ST1 register to 0. The transmit operation be­gins when data is written into the data transmit register of the
TMS320C25. This data will be transmitted when the FSX line
goes low while CLKX is high or going high. The data, starting

XF

FSX

DX

CLKX CLKIN

SDIN

CLR

LDAC

FSIN

TMS320C25*

AD7568*

*ADDITIONAL PINS OMITTED FOR CLARITY

+5V

CLOCK

GENERATION

Figure 23. AD7568 to TMS320C25 Interface

with the MSB, is then shifted out to the DX pin on the rising
edge of CLKX. When all bits have been transmitted, the user
can update the DAC outputs by bringing the XF output flag low.

Multiple DAC Systems

If there are only two AD7568s in a system, there is a simple way
of programming each. This is shown in Figure 24. If the user
wishes to program one of the DACs in the first AD7568, then
DB3 of the serial bit stream should be set to 0, to correspond to
the state of the A0 pin on that device. If the user wishes to pro­gram a DAC in the second AD7568, then DB3 should be set to
1, to correspond to A0 on that device.

FO

TFS

DT

SCLK CLKIN

SDIN

CLR

LDAC

FSIN

ADSP-2101*

AD7568*

*ADDITIONAL PINS OMITTED FOR CLARITY

+5V

A0

CLKIN

SDIN

CLR

LDAC

FSIN

AD7568*

+5V

A0

Figure 24. Interfacing ADSP-2101 to Two AD7568s

AD7568

REV. B

–12–

For systems which contain larger numbers of AD7568s and
where the user also wishes to read back the DAC contents for
diagnostic purposes, the SDOUT pin may be used to daisy
chain several devices together and provide the necessary serial
readback. An example with the 68HC11 is shown in Figure 25.
The routine below shows how four AD7568s would be pro­grammed in such a system. Data is transmitted at the MOSI pin
of the 68HC11. It flows through the input shift registers of the
AD7568s and finally appears at the SDOUT pin of DAC N. So,
the readback routine can be invoked any time after the first four
words have been transmitted (the four input shift registers in the
chain will now be filled up and further activity on the CLKIN
pin will result in data being read back to the microcomputer
through the MISO pin). System connectivity can be verified in
this manner. For a four-device system (32 DACs) a two-line to
four-line decoder is necessary.

Note that to program the 32 DACs, 35 transmit operations are
needed. In the routine, three words must be retransmitted. The
first word for DACs #3, #2 and #1 must be transmitted twice in
order to synchronize their arrival at the SDIN pin with A0 going
low.

Table V. Routine for Loading 4 AD7568s Connected As in
Figure 25

Bring PC7 (FSIN) low to allow writing to the AD7568s.

Enable AD7568 #4 (Bring A0 low). Disable the others.

Transmit 1st 16-bit word: Data for DAC H, #4

. . . .

. . . .

Transmit 9th 16-bit word: Data for DAC H, #3
Transmit 9th 16-bit word again: Data for DAC H, #3
Transmit 10th 16-bit word: Data for DAC G, #3
Transmit 11th 16-bit word: Data for DAC F, #3

Enable AD7568 #3, Disable the others.

Transmit 12th 16-bit word: Data for DAC E, #3

. . . .

. . . .

Transmit 17th 16-bit word: Data for DAC H, #2
Transmit 17th 16-bit word again: Data for DAC H, #2
Transmit 18th 16-bit word: Data for DAC G, #2

Enable AD7568 #2, Disable the others.

Transmit 19th 16-bit word: Data for DAC F, #2

. . . .

. . . .

Transmit 25th word: Data for DAC H, #1

Enable AD7568 #1, Disable the others.

Transmit 25th word again: Data for DAC H, #1
Transmit 26th word: Data for DAC G, #1

. . . .

. . . .

Transmit 32nd word: Data for DAC A, #1

Bring PC7 (FSIN) high to disable writing to the AD7568s.

PC7

SCK

PC6

MISO

SCLK

SDIN

LDAC

FSIN

68HC11* AD7568*

(DAC 1)

*ADDITIONAL PINS OMITTED FOR CLARITY

A0

SCLK
LDAC

FSIN

AD7568*

(DAC 2)

A0

DECODE LOGIC

SDIN

MOSI

SDOUT

SDOUT

SCLK
LDAC

FSIN

AD7568*

(DAC N)

A0

SDIN

SDOUT

Figure 25. Multi-DAC System

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

44-Pin PQFP

(Suffix S)

1

44

34

33

23

22

12

11

TOP VIEW

PIN 1

0.014 ± 0.002
(0.35 ± 0.05)

0.031 ± 0.002
(0.8 ± 0.05)

4°± 4°

0.096 (2.45) MAX

0.031 ± 0.006
(0.8 ± 0.15)

0.394 ± 0.004
(10 ± 0.1)

0.079 + 0.004/–0.002
(2 + 0.1/–0.05)

0.036 ± 0.004
(0.92 ± 0.1)

0.036 ± 0.004
(0.92 ± 0.1)

0.394 ± 0.004 SQ
(10 ± 0.1)

0.547 ± 0.01 SQ
(13.9 ± 0.25)

C1565–24–7/91

PRINTED IN U.S.A.