LC2MOS
a
FEATURES
All Grades 14-Bit Monotonic Over the Full Temperature
Range
Low Cost 14-Bit Upgrade for 12-Bit Systems
14-Bit Parallel Load with Double Buffered Inputs
Small 24-Pin, 0.30 DIP and SOIC
Low Output Leakage (<20 nA) Over the Full
Temperature Range
APPLICATIONS
Microprocessor Based Control Systems
Digital Audio
Precision Servo Control
Control and Measurement in High Temperature
Environments
GENERAL DESCRIPTION
The AD7538 is a 14-bit monolithic CMOS D/A converter
which uses laser trimmed thin-film resistors to achieve excellent
linearity.
The DAC is loaded by a single 14-bit wide word using standard
Chip Select and Memory Write Logic. Double buffering, which
is optional using
tem containing multiple AD7538s.
A novel low leakage configuration (U.S. Patent No. 4,590,456)
enables the AD7538 to exhibit excellent output leakage current
characteristics over the specified temperature range.
The AD7538 is manufactured using the Linear Compatible
CMOS (LC
microprocessors and accepts TTL or CMOS logic level inputs.
LDAC, allows simultaneous update in a sys-
2
MOS) process. It is speed compatible with most
mP-Compatible 14-Bit DAC
AD7538
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. Guaranteed Monotonicity
The AD7538 is guaranteed monotonic to 14-bits over the
full temperature range for all grades.
2. Low Cost
The AD7538, with its 14-bit dynamic range, affords a low
cost solution for 12-bit system upgrades.
3. Small Package Size
The AD7538 is packaged in a small 24-pin, 0.3" DIP and a
24-pin SOIC.
4. Low Output Leakage
By tying V
achieve a low output leakage current at high temperatures.
5. Wide Power Supply Tolerance
The device operates on a +12 V to +15 V V
tolerance on this nominal figure. All specifications are
guaranteed over this range.
(Pin 24) to a negative voltage, it is possible to
SS
, with a ±5%
DD
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
(VDD = +11.4 V to +15.75 V2, V
AD7538–SPECIFICA TIONS
Parameter Versions Versions S Version T Version Units Test Conditions/Comments
ACCURACY
Resolution 14 14 14 14 Bits
Relative Accuracy ± 2 ±1 ± 2 ±1 LSB max All Grades Guaranteed Monotonic
Differential Nonlinearity ±1 ±1 ±1 ±1 LSB max Over Temperature.
Full-Scale Error Measured Using Internal R
+25°C ±4 ±4 ±4 ±4 LSB max Registers Loaded with All 1s.
T
to T
MIN
MIN
MIN
MIN
to T
to T
to T
MAX
MAX
MAX
MAX
3
OUT
(Pin 3)
Gain Temperature Coefficient3;
∆Gain/∆Temperature ± 2 ±2 ±2 ± 2 ppm/°C typ
Output Leakage Current I
+25°C ±5 ±5 ±5 ±5 nA max All Digital Inputs 0 V
T
T
REFERENCE INPUT
Input Resistance, Pin 1 3.5 3.5 3.5 3.5 k Ω min Typical Input Resistance = 6 kΩ
DIGITAL INPUTS
VIH (Input High Voltage) 2.4 2.4 2.4 2.4 V min
VIL (Input Low Voltage) 0.8 0.8 0.8 0.8 V max
IIN (Input Current)
+25°C ±1 ±1 ±1 ±1 µA max VIN = 0 V or V
T
CIN (Input Capacitance)
J, K A, B
±8 ±5 ±10 ±6 LSB max
±10 ±10 ±20 ±20 nA max VSS = –300 mV
±25 ±25 ±150 ±150 nA max VSS = 0 V
10 10 10 10 kΩ max
±10 ±10 ±10 ±10 µA max
7 7 7 7 pF max
1
VSS = –300 mV. All specifications T
= +10 V; V
REF
MIN
= V
PIN3
PIN4
to T
unless otherwise noted.)
MAX
= 0 V,
FB
DD
DAC
POWER SUPPLY
VDD Range 11.4/15.75 11.4/15.75 11.4/15.75 11.4/15.75 V min/V max Specification Guaranteed Over
VSS Range –200/–500 –200/–500 –200/–500 –200/–500 mV min/mV max This Range
I
DD
4 4 4 4 mA max All Digital Inputs VIL or V
500 500 500 500 µA max All Digital Inputs 0 V or V
These characteristics are included for Design Guidance only and are not sub-
AC PERFORMANCE CHARACTERISTICS
Parameter TA = +258C TA = T
MIN
ject to test. (VDD = +11.4 V to +15.75 V, V
O V or –300 mV, Output Amplifier is AD711 except where noted.)
, T
MAX
Units Test Conditions/Comments
= +10 V, V
REF
PIN3
= V
= O V, VSS =
PIN4
Output Current Settling Time 1.5 µs max To 0.003% of Full-Scale Range.
I
Load= 100 Ω, C
OUT
= 13 pF.
EXT
DAC Register Alternately Loaded
with All 1s and All 0s. Typical Value
of Settling Time Is 0.8 µs.
Digital to Analog Glitch Impulse 20 nV-sec typ Measured with V
= 100 Ω, C
EXT
= 0 V. I
REF
OUT
Load
= 13 pF. DAC Register
Alternately Loaded with All 1s and All 0s.
Multiplying Feedthrough Error 3 5 mV p-p typ V
= ± 10 V, 10 kHz Sine Wave DAC
REF
Register Loaded with All 0s.
Power Supply Rejection
∆Gain/∆V
DD
±0.01 ±0.02 % per % max ∆VDD = ±5%
Output Capacitance
C
(Pin 3) 260 260 pF max DAC Register Loaded with All 1s
OUT
C
(Pin 3) 130 130 pF max DAC Register Loaded with All 0s
OUT
Output Noise Voltage Density
(10 Hz–100 kHz) 15 nV√Hz typ Measured Between RFB and I
NOTES
Temperature range as follows: J, K Versions: 0°C to +70°C
2
Specifications are guaranteed for a VDD of +11.4 V to +15.75 V. At VDD = 5 V, the device is fully functional with degraded specifications.
3
Sample tested to ensure compliance.
Specifications subject to change without notice.
A, B Versions: –25°C to +85°C
S, T Versions: –55°C to +125°C
OUT
IH
DD
–2–
REV. A
AD7538
WARNING!
ESD SENSITIVE DEVICE
(VDD = +11.4 V to +15.75 V, V
1
TIMING CHARACTERISTICS
All specifications T
MIN
Limit at
Limit at T
Parameter TA = +258CT
t
1
t
2
t
3
t
4
t
5
t
6
NOTES
1
Temperature range as follows: J, K Versions: 0°C to +70°C
Specifications subject to change without notice.
0 0 0 ns min CS to WR Setup Time
0 0 0 ns min CS to WR Hold Time
170 200 240 ns min LDAC Pulse Width
170 200 240 ns min Write Pulse Width
140 160 180 ns min Data Setup Time
20 20 30 ns min Data Hold Time
A, B Versions: –25°C to +85°C
S, T Versions: –55°C to +125°C
= 08C to +708C Limit at
A
= –258C to +858CTA = –558C to +1258C Units Test Conditions/Comments
A
ABSOLUTE MAXIMUM RATINGS*
(TA= +25°C unless otherwise stated)
VDD (Pin 23) to DGND . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V
V
(Pin 24) to AGND . . . . . . . . . . . . . . . . . . .–15 V, +0.3 V
SS
V
(Pin 1) to AGND . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
REF
V
(Pin 2) to AGND . . . . . . . . . . . . . . . . . . . . . . . . .±25 V
RFB
Digital Input Voltage (Pins 6–22)
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
V
to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
PIN3
AGND to DGND . . . . . . . . . . . . . . . . . . –0.3 V, V
+0.3 V
DD
+0.3 V
DD
Power Dissipation (Any Package)
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Derates Above +75°C . . . . . . . . . . . . . . . . . . . . 10 mW/°C
= +10 V, V
REF
to T
unless otherwise noted. See Figure 1 for Timing Diagram.)
MAX
PIN3
= V
= 0 V, VSS = 0 V or –300 mV.
PIN4
Operating Temperature Range
Commercial (J, K Versions) . . . . . . . . . . . . . .0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . . . –25°C to +85°C
Extended (S, T Versions) . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7538 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
DIP, SOIC
REV. A
Figure 1. Timing Diagram
–3–
AD7538
TERMINOLOGY
RELATIVE ACCURACY
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error and is normally expressed in Least Significant Bits or as a percentage of full-scale
reading.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB max over
the operating temperature range ensures monotonicity.
GAIN ERROR
Gain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error has been adjusted out and is expressed
ORDERING GUIDE
Temperature Relative Full-Scale Package
Model Range Accuracy Error Option*
in Least Significant Bits. Gain error is adjustable to zero with an
external potentiometer.
DIGITAL-TO-ANALOG GLITCH IMPULSE
The amount of charge injected from the digital inputs to the
analog output when the inputs change state is called Digitalto-Analog Glitch Impulse. This is normally specified as the area
of the glitch in either pA-secs or nV-secs depending upon
whether the glitch is measured as a current or voltage. It is measured with V
OUTPUT CAPACITANCE
This is the capacitance from I
OUTPUT LEAKAGE CURRENT
Output Leakage Current is current which appears at I
= AGND.
REF
to AGND.
OUT
OUT
with
the DAC register loaded to all 0s.
MULTIPLYING FEEDTHROUGH ERROR
This is the ac error due to capacitive feedthrough from V
terminal to I
with DAC register loaded to all zeros.
OUT
REF
AD7538JN 0°C to +70°C ±2 LSB ± 8 LSB N-24
AD7538KN 0°C to +70°C ±1 LSB ±4 LSB N-24
AD7538JR 0°C to +70°C ±2 LSB ±8 LSB R-24
AD7538KR 0°C to +70°C ±1 LSB ±4 LSB R-24
AD7538AQ –25°C to +85°C ±2 LSB ±8 LSB Q-24
AD7538BQ –25°C to +85°C ±1 LSB ±4 LSB Q-24
AD7538SQ –55°C to +125°C ±2 LSB ±8 LSB Q-24
AD7538TQ –55°C to +125°C ±1 LSB ±4 LSB Q-24
*N = Plastic DIP; Q = Cerdip; R = SOIC.
PIN FUNCTION DESCRIPTION
Pin Mnemonic Description
11V
12R
13I
REF
FB
OUT
Voltage Reference.
Feedback Resistor. Used to close the loop around an external op amp.
Current Output Terminal.
14 AGND Analog Ground
15 DGND Digital Ground
6–19 DB13–DB0 Data Inputs. Bit 13 (MSB) to Bit 0 (LSB).
20
21
22
LDAC Chip Select Input. Active LOW.
CS Asynchronous Load DAC Input. Active LOW.
WR Write Input. Active LOW.
CS LDAC WR OPERATION
0 1 0 Load Input Register.
1 0 X Load DAC Register from Input Register.
0 0 0 Input and DAC Registers are Transparent.
1 1 X No Operation.
X 1 1 No Operation.
NOTE: X Don’t Care.
23 V
24 V
DD
SS
+12 V to +15 V supply input.
Bias pin for High Temperature Low Leakage configuration. To implement low leakage
system, the pin should be at a negative voltage. See Figures 4 and 5 for recommended circuitry.
–4–
REV. A
AD7538
D/A SECTION
Figure 2 shows a simplified circuit diagram for the AD7538
D/A section. The three MSBs of the 14-bit Data Word are decoded to drive the seven switches A-G. The 11 LSBs of the
Data Word consist of an R-2R ladder operated in a current
steering configuration.
CIRCUIT INFORMATION
Figure 2. Simplified Circuit Diagram for the AD7538 D/A Section
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows an equivalent circuit for the analog section of
the AD7538 D/A converter. The current source I
LEAKAGE
composed of surface and junction leakages. The resistor R
is
O
denotes the equivalent output resistance of the DAC which
varies with input code. C
is the capacitance due to the cur-
OUT
rent steering switches and varies from about 90 pF to 180 pF
(typical values) depending upon the digital input. g(V
REF
, N) is
the Thevenin equivalent voltage generator due to the reference
input voltage, V
, and the transfer function of the DAC
REF
ladder, N.
The R-2R ladder current is 1/8 of the total reference input current. 7/8 I flows in the parallel ladder structure. Switches A-G
steer equally weighted currents between I
Since the input resistance at V
is constant, it may be driven
REF
and AGND.
OUT
by a voltage source or a current source of positive or negative
polarity.
Figure 3. AD7538 Equivalent Analog Output Circuit
DIGITAL SECTION
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA. To minimize power
supply currents, it is recommended that the digital input voltages be driven as close as possible to 0 V and 5 V logic levels.
UNIPOLAR BINARY OPERATION (2-QUADRANT
MULTIPLICATION)
Figure 4 shows the circuit diagram for unipolar binary operation. With an ac input, the circuit performs 2 quadrant multiplication. The code table for Figure 4 is given in Table I.
Capacitor C1 provides phase compensation and helps prevent
overshoot and ringing when high-speed op amps are used.
REV. A
–5–
Figure 4. Unipolar Binary Operation
Table I. Unipolar Binary Code Table for AD7538
Binary Number In
DAC Register Analog Output, V
MSB LSB
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0001
–V
–V
–V
IN
IN
IN
16383
16384
8192
16384
1
16384
= –1/2V
00 0000 0000 0000 0 V
OUT
IN
AD7538
For zero offset adjustment, the DAC register is loaded with all
0s and amplifier offset (V
justing V
to 0 V is not necessary in many applications, but it
OUT
is recommended that V
) adjusted so that V
OS
be no greater than (25 × 10–6) (V
OS
is 0 V. Ad-
OUT
REF
)
to maintain specified DAC accuracy (see Applications Hints).
Full-scale trimming is accomplished by loading the DAC register
with all 1s and adjusting R1 so that V
= –VIN (16383/16384).
OUTA
For high temperature operation, resistors and potentiometers
should have a low Temperature Coefficient. In many applications, because of the excellent Gain T.C. and Gain Error specifications of the AD7538, Gain Error trimming is not necessary.
In fixed reference applications, full scale can also be adjusted
by omitting R1 and R2 and trimming the reference voltage
magnitude.
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
The recommended circuit diagram for bipolar operation is
shown in Figure 5. Offset binary coding is used. The code table
for Figure 5 is given in Table II.
With the DAC loaded to 10 0000 0000 0000, adjust R1 for
V
= 0 V. Alternatively, one can omit R1 and R2 and adjust the
O
ratio of R5 and R6 for V
accomplished by adjusting the amplitude of V
= 0 V. Full-scale trimming can be
O
or by varying
IN
the value of R7.
The values given for R1, R2 are the minimum necessary to cali-
brate the system for resistors, R5, R6, R7 ratio matched to 0.1%.
System linearity error is independent of resistor ratio matching
and is affected by DAC linearity error only.
When operating over a wide temperature range, it is important
that the resistors be of the same type so that their temperature
coefficients match.
For further information sec “CMOS DAC Application Guide”,
3rd Edition, Publication Number G872b-8-1/89 available from
Analog Devices.
Table II. Bipolar Code Table for Offset Binary Circuit of
Figure 5.
Binary Number In
DAC Register Analog Output V
OUT
MSB LSB
8191
+V
IN
11 1111 1111 1111
10 0000 0000 0001
+V
IN
8192
8192
1
10 0000 0000 0000 0 V
01 1111 1111 1111
00 0000 0000 0000
–V
–V
1
IN
8192
8191
IN
8192
VSS should be tied to a voltage of approximately –0.3 V as in
Figures 4 and 5. A simple resistor divider (R3, R4) produces approximately –300 mV from –15 V. The capacitor C2 in parallel
with R3 is an integral part of the low leakage configuration and
must be 4.7 µF or greater. Figure 6 is a plot of leakage current
versus temperature for both conditions. It clearly shows the improvement gained by using the low leakage configuration.
Figure 5. Bipolar Operation
LOW LEAKAGE CONFIGURATION
For CMOS Multiplying D/A converters, as the device is operated at higher temperatures, the output leakage current increases. For a 14-bit resolution system, this can be a significant
source of error. The AD7538 features a leakage reduction configuration (U.S. Patent No. 4,590,456) to keep the leakage current low over an extended temperature range. One may operate
the device with or without this configuration. If V
(Pin 24) is
SS
tied to AGND then the DAC will exhibit normal output leakage
current at high temperatures. To use the low leakage facility,
–6–
Figure 6. Graph of Typical Leakage Current vs.
Temperature for AD7538
PROGRAMMABLE GAIN AMPLIFIER
The circuit shown in Figure 7 provides a programmable gain
amplifier (PGA). In it the DAC behaves as a programmable
resistance and thus allows the circuit gain to be digitally
controlled.
Figure 7. Programmable Gain Amplifier (PGA)
REV. A
AD7538
The transfer function of Figure 7 is:
V
Gain =
is the equivalent transfer impedance of the DAC from the
R
EQ
V
pin to the I
REF
pin and can be expressed as
OUT
REQ=
OUT
V
n
R
2
N
R
EQ
= –
IN
IN
(1)
R
FB
(2)
Where: n is the resolution of the DAC
Where: N is the DAC input code in decimal
Where: R
Where: of the DAC (RIN = R
is the constant input impedance
IN
LAD
)
Substituting this expression into Equation 1 and assuming zero
gain error for the DAC (R
= RFB) the transfer function simpli-
IN
fies to
The ratio N/2
n
is commonly represented by the term D and, as
V
OUT
V
IN
= –
n
2
N
(3)
such, is the fractional representation of the digital input word.
V
OUT
V
IN
= –
–2
n
–1
=
N
(4)
D
Equation 4 indicates that the gain of the circuit can be varied
from 16,384 down to unity (actually 16,384/16,383) in 16,383
steps. The all 0s code is never applied. This avoids an openloop condition thereby saturating the amplifier. With the all 0s
code excluded there remains 2
ing a choice of 2
n
– 1 output levels. In dB terms the dynamic
n
– 1 possible input codes allow-
range is
MICROPROCESSOR INTERFACING
The AD7538 is designed for easy interfacing to 16-bit microprocessors and can be treated as a memory mapped peripheral.
This reduces the amount of external logic needed for interfacing
to a minimal.
AD7538-8086 INTERFACE
Figure 8 shows the 8086 processor interface to a single device.
In this setup the double buffering feature (using
LDAC) of the
DAC is not used. The 14-bit word is written to the DAC in one
MOV instruction and the analog output responds immediately.
Figure 8. AD7538-8086 Interface Circuit
In a multiple DAC system the double buffering of the AD7538
allows the user to simultaneously update all DACs. In Figure 9,
a 14-bit word is loaded to the Input Registers of each of the
DACs in sequence. Then, with one instruction to the appropriate address, CS4 (i.e., LDAC) is brought low, updating all the
DACs simultaneously.
V
20log
OUT
10
=20 log10(2n–1)=84 dB.
V
IN
APPLICATION HINTS
Output Offset: CMOS D/A converters in circuits such as Fig-
ures 4 and 5 exhibit a code dependent output resistance which
in turn can cause a code dependent error voltage at the output
of the amplifier. The maximum amplitude of this error, which
adds to the D/A converter nonlinearity, depends on V
V
is the amplifier input offset voltage. To maintain specified
OS
accuracy with V
greater than 0.25 mV, or (25 × 10
at 10 V, it is recommended that VOS be no
REF
–6
) (V
), over the tempera-
REF
, where
OS
ture range of operation. The AD711 is a suitable op amp. The
op amp has a wide bandwidth and high slew rate and is recommended for ac and other applications requiring fast settling.
General Ground Management: Since the AD7538 is specified for high accuracy, it is important to use a proper grounding
technique. AC or transient voltages between AGND and
DGND can cause noise injection into the analog output. The
simplest method of ensuring that voltages at AGND and
DGND are equal is to tie AGND and DGND together at the
AD7538. In more complex systems where the AGND and
DGND intertie is on the backplane, it is recommended that two
diodes be connected in inverse parallel between the AD7538
AGND and DGND pins (1N914 or equivalent).
Figure 9. AD7538-8086 Interface: Multiple DAC System
REV. A
–7–
AD7538
AD7538-MC68000 INTERFACE
Figure 10 shows the MC68000 processor interface to a single
device. In this setup the double buffering feature of the DAC is
not used and the appropriate data is written into the DAC in
one MOVE instruction.
Figure 10. AD7538-MC68000 Interface
DIGITAL FEEDTHROUGH
The digital inputs to the AD7538 are directly connected to the
microprocessor bus in the preceding interface configurations.
These inputs will be constantly changing even when the device
is not selected. The high frequency logic activity on the bus can
feed through the DAC package capacitance to show up as noise
on the analog output. To minimize this Digital Feedthrough
isolate the DAC from the noise source. Figure 11 shows an interface circuit which uses this technique. All data inputs are
latched from the bus by the
CS signal. One may also use other
means, such as peripheral interface devices, to reduce the Digital Feedthrough.
Figure 11. AD7538 Interface Circuit Using Latches to
Minimize Digital Feedthrough
C1054–9–5/87
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Pin Plastic Suffix (N) 24-Pin Cerdip (Suffix Q)
PRINTED IN U.S.A.
–8–
REV. A
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