LC2MOS
a
FEATURES
Two 12-Bit DACs in One Package
DAC Ladder Resistance Matching: 0.5%
Space Saving Skinny DIP and Surface Mount Packages
4-Quadrant Multiplication
Low Gain Error (1 LSB max Over Temperature)
Byte Loading Structure
Fast Interface Timing
APPLICATIONS
Automatic Test Equipment
Programmable Filters
Audio Applications
Synchro Applications
Process Control
GENERAL DESCRIPTION
The AD7537 contains two 12-bit current output DACs on one
monolithic chip. A separate reference input is provided for each
DAC. The dual DAC saves valuable board space, and the
monolithic construction ensures excellent thermal tracking.
Both DACs are guaranteed 12-bit monotonic over the full temperature range.
The AD7537 has a 2-byte (8 LSBs, 4 MSBs) loading structure.
It is designed for right-justified data format. The control signals
for register loading are A0, A1,
loaded to the input registers when
transfer this data to the DAC registers,
with
WR.
Added features on the AD7537 include an asynchronous
line which is very useful in calibration routines. When this is
taken low, all registers are cleared. The double buffering of the
data inputs allows simultaneous update of both DACs. Also,
each DAC has a separate AGND line. This increases the device
versatility; for instance one DAC may be operated with
AGND biased while the other is connected in the standard
configuration.
The AD7537 is manufactured using the Linear Compatible
CMOS (LC
microprocessors and accepts TTL, 74HC and 5 V CMOS logic
level inputs.
2
MOS) process. It is speed compatible with most
CS, WR and UPD. Data is
CS and WR are low. To
UPD must be taken low
CLR
(8+4) Loading Dual 12-Bit DAC
AD7537
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. DAC to DAC Matching:
Since both DACs are fabricated on the same chip, precise
matching and tracking is inherent. Many applications which
are not practical using two discrete DACs are now possible.
Typical matching: 0.5%.
2. Small Package Size:
The AD7537 is packaged in small 24-pin 0.3" DIPs and in
28-terminal surface mount packages.
3. Wide Power Supply Tolerance:
The device operates on a +12 V to +15 V V
tolerance on this nominal figure. All specifications are
guaranteed over this range.
, with ±10%
DD
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
AD7537–SPECIFICA TIONS
(VDD = +12 V to +15 V, 610%, V
I
= AGNDB = 0 V. All specifications T
OUTB
REFA
= V
= 10 V; I
REFB
to T
MIN
= AGND = 0 V,
OUTA
unless otherwise noted.)
MAX
Parameter Versions Versions Versions Version Version Version Units Test Conditions/Comments
J, A K, B L, C S T U
ACCURACY
Resolution 12 12 12 12 12 12 Bits
Relative Accuracy ±1 ±1/2 ±1/2 ± 1 ±1/2 ±1/2 LSB max
Differential Nonlinearity ±1 ±1 ±1 ±1 ±1 ±1 LSB max All grades guaranteed mono-
tonic over temperature.
Gain Error ±6 ±3 ±1 ±6 ±3 ±2 LSB max Measured using R
Both DAC registers loaded
Gain Temperature Coefficient
2
;
with all 1s.
FBA
, R
FBB
.
∆Gain/∆Temperature ±5 ±5 ±5 ±5 ±5 ±5 ppm/°C max Typical value is 1 ppm/°C
Output Leakage Current
I
OUTA
+25°C 10 10 10 10 10 10 nA max DAC A Register loaded
T
to T
MIN
MIN
to T
MAX
MAX
I
OUTB
+25°C 10 10 10 10 10 10 nA max DAC B Register loaded
T
150 150 150 250 250 250 nA max with all 0s
150 150 150 250 250 250 nA max with all 0s
REFERENCE INPUT
Input Resistance 999999kΩ min Typical Input Resistance = 14 kΩ
20 20 20 20 20 20 kΩ max
V
, V
REFA
REFB
Input Resistance Match ±3 ±3 ± 1 ±3 ±3 ±1 % max Typically ±0.5%
DIGITAL INPUTS
V
(lnput High Voltage) 2.4 2.4 2.4 2.4 2.4 2.4 V min
IH
V
(Input Low Voltage) 0.8 0.8 0.8 0.8 0.8 0.8 V max
IIL
I
(Input Current)
IN
+25°C ±1 ±1 ±1 ±1 ±1 ±1 µA max V
T
to T
MIN
CIN (lnput Capacitance)
POWER SUPPLY
V
DD
I
DD
MAX
3
2
±10 ±10 ±10 ±10 ±10 ±10 µA max
10 10 10 10 10 10 pF max
10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 V min/V max
222222mA max
IN
= V
DD
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance only and are not subject to test.
(VDD = +12 V to +15 V; V
Parameter TA = +258CTA = T
Output Current Settling Time 1.5 µs max To 0.01% of full-scale range. I
Digital-to-Analog Glitch lmpulse 7 nV-s typ Measured with V
to I
to I
to I
to I
4
OUTA
OUTB
DD
OUTB
OUTA
AC Feedthrough
V
REFA
V
REFB
Power Supply Rejection
∆Gain/∆V
Output Capacitance
C
OUTA
C
OUTB
C
OUTA
C
OUTB
Channel-to-Channel Isolation
V
REFA
V
REFB
Digital Crosstalk 7 nV-s typ Measured for a Code Transition of all 0s to all 1s.
Output Noise Voltage Density 25 nV/√Hz typ Measured between R
(10 Hz–100 kHz) Frequency of measurement is 10 Hz–100 kHz.
Total Harmonic Distortion –82 dB typ VIN = 6 V rms, 1 kHz. Both DACs loaded with all 1s.
NOTES
1
Temperature range as follows: J, K, L Versions: –40°C to +85°C;
Specifications subject to change without notice.
= V
REFA
= +10 V; I
REFB
OUTA
–70 –65 dB max V
–70 –65 dB max DAC registers loaded with all 0s.
±0.01 ± 0.02 % per % max ∆VDD = VDD max – VDD min
70 70 pF max DAC A, DAC B loaded with all 0s
70 70 pF max
140 140 pF max DAC A, DAC B loaded with all 1s
140 140 pF max
–84 dB typ V
–84 dB typ V
A, B, C Versions: –40°C to +85°C;
S, T, U Versions: –55°C to +125°C
= AGNDA = 0 V, I
MIN
, T
Units Test Conditions/Comments
MAX
2
Sample tested at +25°C to ensure compliance.
3
Functional at VDD = 5 V, with degraded specifications.
4
Pin 12 (DGND) on ceramic DIPs is connected to lid.
= AGNDB = 0 V. Output Amplifiers are AD644 except where noted.)
OUTB
load = 100 Ω, C
DAC output measured from falling edge of
OUT
WR.
EXT
Typical Value of Settling Time is 0.8 µs.
= V
FBA
REFB
and I
= 0 V. I
= 13 pF.
EXT
OUTA
C
= 13 pF. DAC registers alternately loaded with all 0s and all 1s.
EXT
, V
REFA
= 20 V p-p 10 kHz sine wave, V
REFA
Both DACs loaded with all 1s.
= 20 V p-p 10 kHz sine wave, V
REFB
Both DACs loaded with all 1s.
I
, I
OUTA
OUTB
REFA
= 20 V p-p 10 kHz sine wave.
REFB
load = 100 Ω, C
or R
OUTA
REFB
REFA
FBB
, I
OUTB
= 0 V.
= 0 V.
and I
load = 100 Ω,
OUTB.
= 13 pF.
–2–
REV. 0
AD7537
WARNING!
ESD SENSITIVE DEVICE
TIMING CHARACTERISTICS
(VDD = +10.8 V to +16.5 V, V
REFA
= V
= +10 V; I
REFB
= AGNDA = 0 V, I
OUTA
= AGNDB = 0 V.)
OUTB
Limit at Limit at
Limit at T
= –408CT
A
= +558C
A
Parameter TA = +258C to +858C to +1258C Units Test Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise stated)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V
V
, V
REFA
RFBA
, V
REFB
RFBB
V
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
I
, I
OUTA
OUTB
AGNDA, AGNDB to DGND . . . . . . . . . –0.3 V, V
Power Dissipation (Any Package)
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Derates Above +75°C . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
15 15 30 ns min Address Valid to Write Setup Time
15 15 25 ns min Address Valid to Write Hold Time
60 80 80 ns min Data Setup Time
25 25 25 ns min Data Hold Time
0 0 0 ns min Chip Select or Update to Write Setup Time
0 0 0 ns min Chip Select or Update to Write Hold Time
80 80 100 ns min Write Pulse Width
80 80 100 ns min Clear Pulse Width
Operating Temperature Range
Commercial Plastic (J, K, L Versions) . . . . –40°C to +85°C
Industrial Hermetic (A, B, C Versions) . . . –40°C to +85°C
to AGNDA, AGNDB . . . . . . . . . . . . . . . . ±25 V
to AGNDA, AGNDB . . . . . . . . . . . . . . . . ±25 V
+0.3 V
DD
to DGND . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
+0.3 V
DD
Extended Hermetic (S, T, U Versions) . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7537 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
Figure 1. Timing Diagram
1
Model
ORDERING GUIDE
2
Temperature Relative Gain Package
Range Accuracy Error Option
AD7537JN –40°C to +85°C ±1 LSB ±6 LSB N-24
AD7537KN –40°C to +85°C ±1/2 LSB ±3 LSB N-24
AD7537LN –40°C to +85°C ±1/2 LSB ±1 LSB N-24
AD7537JP –40°C to +85°C ±1 LSB ±6 LSB P-28A
AD7537KP –40°C to +85°C ± 1/2 LSB ±3 LSB P-28A
AD7537LP –40°C to +85°C ±1/2 LSB ±1 LSB P-28A
AD7537AQ –40°C to +85°C ±1 LSB ±6 LSB Q-24
AD7537BQ –40°C to +85°C ±1/2 LSB ±3 LSB Q-24
AD7537CQ –40°C to +85°C ±1/2 LSB ±1 LSB Q-24
AD7537SQ –55°C to +125°C ±1 LSB ±6 LSB Q-24
AD7537TQ –55°C to +125°C ±1/2 LSB ±3 LSB Q-24
AD7537UQ –55°C to +125°C ±1/2 LSB ±2 LSB Q-24
AD7537SE –55°C to +125°C ± 1 LSB ±6 LSB E-28A
AD7537TE –55°C to +125°C ± 1/2 LSB ±3 LSB E-28A
AD7537UE –55°C to +125°C ±1/2 LSB ±2 LSB E-28A
NOTES
1
Analog Devices reserves the right to ship ceramic packages (D-24A) in lieu of
cerdip packages (Q-24).
2
To order MIL-STD-883, Class B processed parts, add/883B to part number.
Contact your local sales office for military data sheet.
3
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip.
–3–
3
AD7537
PIN FUNCTION DESCRIPTION (DIP)
PIN MNEMONIC DESCRIPTION
1 AGNDA Analog Ground for DAC A.
2I
3R
4V
5
OUTA
FBA
REFA
CS Chip Select Input Active low.
Current output terminal of DAC A.
Feedback resistor for DAC A.
Reference input to DAC A.
6–14 DB0–DB7 Eight data inputs, DB0–DB7.
12 DGND Digital Ground.
15 A0 Address Line 0.
16 A1 Address Line 1.
17
CLR Clear Input. Active low. Clears all
registers.
18
19
WR Write Input. Active low.
UPD Updates DAC Registers from inputs
registers.
20 V
DD
Power supply input. Nominally +12 V
to +15 V, with ±10% tolerance.
21 V
22 R
23 I
REFB
FBB
OUTB
Reference input to DAC B.
Feedback resistor for DAC B.
Current output terminal of DAC B.
24 AGNDB Analog Ground for DAC B.
PIN CONFIGURATIONS
DIP
LCCC
current flowing in each ladder leg is constant, irrespective of
switch state. The feedback resistor R
(see Figures 4 and 5) to convert the current flowing in I
is used with an op amp
FBA
OUTA
to
a voltage output.
Figure 2. Simplified Circuit Diagram for DAC A
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for one of the D/A converters (DAC A) in the AD7537. A similar equivalent circuit
can be drawn for DAC B.
C
is the output capacitance due to the N-channel switches
OUT
and varies from about 50 pF to 150 pF with digital input code.
The current source I
leakages and approximately doubles every 10°C. R
is composed of surface and junction
LKG
is the
0
equivalent output resistance of the device which varies with
input code.
DIGITAL CIRCUIT INFORMATION
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA.
PLCC
CIRCUIT INFORMATION – D/A SECTION
The AD7537 contains two identical 12-bit multiplying D/A
converters. Each DAC consists of a highly stable R-2R ladder
and 12 N-channel current steering switches. Figure 2 shows a
simplified D/A circuit for DAC A. In the R-2R ladder, binary
weighted currents are steered between I
and AGNDA. The
OUTA
Table I. AD7537 Truth Table
CLR UPD CS WR A1 A0 FUNCTION
1 1 1 X X X No Data Transfer
1 1 X 1 X X No Data Transfer
0 X X X X X All Registers Cleared
1 1 0 0 0 0 DAC A LS Input Register
Loaded with DB7–DB0 (LSB)
1 1 0 0 0 1 DAC A MS Input Register
Loaded with DB3 (MSB)–DB0
1 1 0 0 1 0 DAC B LS Input Register
Loaded with DB7–DB0 (LSB)
1 1 0 0 1 1 DAC B MS Input Register
Loaded with DB3 (MSB)–DB0
1 0 1 0 X X DAC A, DAC B Registers
Updated Simultaneously from
Input Registers
1 0 0 0 X X DAC A, DAC B Registers are
Transparent
NOTES: X = Don’t care
Figure 3. Equivalent Analog Circuit for DAC A
–4–
REV. 0
Applications–
AD7537
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the circuit diagram for unipolar binary operation. With an ac input, the circuit performs 2-quadrant multiplication. The code table for Figure 4 is given in Table II.
Operational amplifiers A1 and A2 can be in a single package
(AD644, AD712) or separate packages (AD544, AD711,
AD OP27). Capacitors C1 and C2 provide phase compensation
to help prevent overshoot and ringing when high-speed op amps
are used.
For zero offset adjustment, the appropriate DAC register is
loaded with all 0s and amplifier offset adjusted so that V
V
is 0 V. Full-scale trimming is accomplished by loading
OUTB
OUTA
or
the DAC register with all 1s and adjusting R1 (R3) so that
V
OUTA
(V
) = –VIN (4095/4096). For high temperature op-
OUTB
eration, resistors and potentiometers should have a low Temperature Coefficient. In many applications, because of the
excellent Gain T.C. and Gain Error specifications of the
AD7537, Gain Error trimming is not necessary. In fixed reference applications, full scale can also be adjusted by omitting R1,
R2, R3, R4 and trimming the reference voltage magnitude.
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
The recommended circuit diagram for bipolar operation is
shown in Figure 5. Offset binary coding is used.
With the appropriate DAC register loaded to 1000 0000 0000,
adjust R1 (R3) so that V
OUTA
(V
) = 0 V. Alternatively, R1,
OUTB
R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, 10)
varied for V
complished by adjusting the amplitude of V
OUTA
(V
) = 0 V. Full-scale trimming can be ac-
OUTB
or by varying the
IN
value of R5 (R8).
If R1, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8,
R9, R10) should be ratio matched to 0.01% to ensure gain error
performance to the data sheet specification. When operating
over a wide temperature range, it is important that the resistors
be of the same type so that their temperature coefficients match.
The code table for Figure 5 is given in Table III.
Figure 4. AD7537 Unipolar Binary Operation
Table II. Unipolar Binary Code Table for
Circuit of Figure 4
Binary Number in
DAC Register Analog Output,
MSB LSB V
1111 1111 1111
1000 0000 0000
0000 0000 0001
OUTA
−V
−V
−V
0000 0000 0000 0 V
REV. 0
IN
IN
IN
or V
4095
4096
2048
4096
4096
1
OUTB
=−
Figure 5. Bipolar Operation (Offset Binary Coding)
Table III. Bipolar Code Table for Offset Binary
Circuit of Figure 5
Binary Number in
DAC Register Analog Output,
MSB LSB V
1111 1111 1111
1000 0000 0001
+V
+V
OUTA
IN
IN
or V
2047
2048
2048
1
OUTB
1000 0000 0000 0 V
0111 1111 1111
1
V
IN
2
0000 0000 0000
−V
−V
1
IN
2048
2048
2048
=−V
IN
IN
–5–
AD7537
SEPARATE AGND PINS
The DACs in the AD7537 have separate AGND lines taken to
pins AGNDA and AGNDB on the package. This increases the
applications versatility of the part. Figure 6 is an example of
this. DAC A is connected in standard fashion as a programmable attenuator. AGNDA is at ground potential. DAC B is operating with AGND B biased to +5 V by the AD584. This gives
an output range of +5 V to +10 V.
Figure 6. AD7537 DACs Used in Different Modes
PROGRAMMABLE OSCILLATOR
Figure 7 shows a conventional state variable oscillator in which
the AD7537 controls the programmable integrators. The frequency of oscillation is given by:
1
where R
EQ1
f =
and R
R6
×
R5
2π
EQ2
C1×C2×R
are the equivalent resistances of the
1
EQ1×REQ2
DACs. The same digital code is loaded into both DACs.
If C1 = C2 and R5 = R6, the expression reduces to
1
R
EQ1×REQ2
= DAC ladder resistance).
2
D=
N
n
2
Since
REQ=
1
f =
n
×R
2
LAD
N
1
f =
×
2π
1
D
=
×
2π
C
1
×
=
2π
C×R
1
×
2π
C
, (R
LAD
(N /2n)
1
R
C
LAD1×RLAD2
R
LAD1×RLAD2
D
LAD m
1
where m is the DAC ladder resistance mismatch ratio, typically
1.005.
With the values shown in Figure 7, the output frequency varies
from 0 Hz to 1.38 kHz. The amplitude of the output signal at
the A3 output is 10 V peak-to-peak and is constant over the
entire frequency span.
Figure 7. Programmable State Variable Oscillator
–6–
REV. 0
AD7537
APPLICATION HINTS
Output Offset: CMOS D/A converters in circuits such as Fig-
ures 4 and 5 exhibit a code dependent output resistance which
in turn can cause a code dependent error voltage at the output
of the amplifier. The maximum amplitude of this error, which
adds to the D/A converter nonlinearity, depends on V
V
is the amplifier input offset voltage. To maintain specified
OS
operation, it is recommended that V
(25 3 10
–6
) (V
) over the temperature range of operation.
REF
be no greater than
OS
, where
OS
Suitable op amps are the AD711C and its dual version, the
AD712C. These op amps have a wide bandwidth and high slew
rate and are recommended for wide bandwidth ac applications.
AD711/AD712 settling time to 0.01% is typically 3 µs.
Temperature Coefficients: The gain temperature coefficient
of the AD7537 has a maximum value of 5 ppm/°C and typical
value of 1 ppm/°C. This corresponds to worst case gain shifts of
2 LSBs and 0.4 LSBs respectively over a 100°C temperature
range. When trim resistors R1 (R3) and R2 (R4) are used to adjust full scale range as in Figure 4, the temperature coefficient of
R1 (R3) and R2 (R4) should also be taken into account. For
further information see “Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs”, Application Note, Publication Number E630c-5-3/86 available from Analog Devices.
High Frequency Considerations: AD7537 output capacitance works in conjunction with the amplifier feedback resistance to add a pole to the open loop response. This can cause
ringing or oscillation. Stability can be restored by adding a
phase compensation capacitor in parallel with the feedback resistor. This is shown as C1 and C2 in Figures 4 and 5.
Feedthrough: The dynamic performance of the AD7537 depends upon the gain and phase stability of the output amplifier,
together with the optimum choice of PC board layout and decoupling components. A suggested printed circuit layout for
Figure 4 is shown in Figure 8 which minimizes feedthrough
from V
REFA
, V
to the output in multiplying applications.
REFB
other for the MC68008. Figure 11 shows how an AD7537 system can be easily expanded by tying all the
UPD lines together
and using a single decoder output to control these. This expanded system is shown using a Z80 microprocessor but it is
just as easily configured using any other 8-bit microprocessor
system. Note how the system shown in Figure 11 produces 4
analog outputs with a minimum amount of hardware.
Figure 9. AD7537–MC6809 Interface
Figure 8. Suggested Layout for AD7537
MICROPROCESSOR INTERFACING
The byte loading structure of the AD7537 makes it very easy to
interface the device to any 8-bit microprocessor system. Figures
9 and 10 show two interfaces: one for the MC6809 and the
REV. 0
–7–
Figure 10. AD7537–MC68008 Interface
Figure 11. Expanded AD7537 System
AD7537
24-Pin Plastic DIP (N-24)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Pin Ceramic DIP (D-24A)
C978a–5–10/87
24-Pin Cerdip (Q-24)
28-Terminal Leadless Ceramic Chip Carrier
(E-28A)
–8–
28-Terminal Plastic Leaded Chip Carrier
(P-28A)
PRINTED IN U.S.A.
REV. 0
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