Datasheet AD7521, AD7520, AD7531, AD7530 Datasheet (Intersil Corporation)

AD7520, AD7530,

AD7521, AD7531

August 1997

Features

• AD7520/AD7530, 10-Bit Resolution; 8-Bit, 9-Bit and
10-Bit Linearity

• AD7521/AD7531, 12-Bit Resolution; 8-Bit, 9-Bit and
10-Bit Linearity

• Low Power Dissipation (Max). . . . . . . . . . . . . . . .20mW

• Low Nonlinearity Tempco at 2ppm of FSR/

• Current Settling Time to 0.05% of FSR . . . . . . . . 1.0µs

• Supply Voltage Range . . . . . . . . . . . . . . . . ±5V to +15V

o

C

10-Bit, 12-Bit, Multiplying D/A Converters

Description

The AD7520/AD7530 and AD7521/AD7531 are monolithic,
high accuracy, low cost 10-bit and 12-bit resolution,
multiplying digital-to-analog converters (DAC). Intersil’
thin-film on CMOS processing gives up to 10-bit accuracy
with TTL/CMOS compatible operation. Digital inputs are fully
protected against static discharge by diodes to ground and
positive supply.

Typical applications include digital/analog interfacing,
multiplication and division, programmable power supplies,
CRT character generation, digitally controlled gain circuits,
integrators and attenuators, etc.

• TTL/CMOS Compatible

The AD7530 and AD7531 are identical to the AD7520 and

• Full Input Static Protection

• /883B Processed Versions Available

AD7521, respectively, with the exception of output leakage
current and feedthrough specifications.

Ordering Information

PART NUMBER LINEARITY (INL, DNL) TEMP. RANGE (oC) PACKAGE PKG. NO.

AD7520JN, AD7530JN 0.2% (8-Bit) 0 to 70 16 Ld PDIP E16.3
AD7520KN, AD7530KN 0.1% (9-Bit) 0 to 70 16 Ld PDIP E16.3
AD7521JN, AD7531JN 0.2% (8-Bit) 0 to 70 18 Ld PDIP E18.3
AD7521KN, AD7531KN 0.1% (9-Bit) 0 to 70 18 Ld PDIP E18.3
AD7520LN, AD7530LN 0.05% (10-Bit) -40 to 85 16 Ld PDIP E16.3
AD7521LN, AD7531LN 0.05% (10-Bit) -40 to 85 18 Ld PDIP E18.3
AD7520JD 0.2% (8-Bit) -25 to 85 16 Ld CERDIP F16.3
AD7520KD 0.1% (9-Bit) -25 to 85 16 Ld CERDIP F16.3
AD7520LD 0.05% (10-Bit) -25 to 85 16 Ld CERDIP F16.3
AD7520SD, AD7520SD/883B 0.2% (8-Bit) -55 to 125 16 Ld CERDIP F16.3
AD7520UD, AD7520UD/883B 0.05% (10-Bit) -55 to 125 16 Ld CERDIP F16.3

Pinouts

AD7520, AD7530

(CERDIP, PDIP)

TOP VIEW

16

1

I

OUT1

2

I

OUT2

3

GND

BIT 2
BIT 3
BIT 4
BIT 5

4
5
6
7
8

| Copyright © Intersil Corporation 1999

BIT 1 (MSB)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

R

FEEDBACK

15

V

REF

14

V+

13

BIT 10 (LSB)

12

BIT 9
BIT 8

11
10

BIT 7

9

BIT 6

BIT 1 (MSB)

10-7

I

OUT1

I

OUT2

GND

BIT 2
BIT 3
BIT 4
BIT 5
BIT 6

1
2
3
4
5
6
7
8
9

AD7521, AD7531

(PDIP)

TOP VIEW

18

R

FEEDBACK

V

17

REF

16

V+

15

BIT 12 (LSB)

14

BIT 11

13

BIT 10

12

BIT 9

11

BIT 8

10

BIT 7

File Number 3104.1

AD7520, AD7530, AD7521, AD7531

Absolute Maximum Ratings Thermal Information

Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . +17V

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V

REF

Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . .V+ to GND

Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . -100mV to V+

Operating Conditions

Temperature Ranges

JN, KN, LN Versions. . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC

JD, KD, LD Versions . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC

SD, UD Versions. . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep
unused units in conductive foam at all times.

Do not apply voltages higher than VDD or less than GND potential on any terminal except V

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

16 Ld PDIP Package. . . . . . . . . . . . . . . . 100 N/A

18 Ld PDIP Package. . . . . . . . . . . . . . . . 90 N/A

CERDIP Package . . . . . . . . . . . . . . . . . . 75 20

Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175oC

Maximum Junction Temperature (Plastic Packages) . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

REF

and R

FEEDBACK

.

Electrical Specifications V+ = +15V, V

= +10V, TA = 25oC Unless Otherwise Specified

REF

AD7520/AD7530 AD7521/AD7531

PARAMETER TEST CONDITIONS

UNITSMIN TYP MAX MIN TYP MAX

SYSTEM PERFORMANCE (Note 2)

Resolution 10 10 10 12 12 12 Bits
Nonlinearity J, S S Over -55oC to 125oC

(Notes 2, 5) (Figure 3)

o

K T Over -55

C to 125oC

(Figure 2)

L, U -10V ≤ V

REF

≤ +10V

U Over -55oC to 125oC

--±0.2
(8-Bit)

--±0.1
(9-Bit)

--±0.05

(10-Bit)

--±0.2
(8-Bit)

--±0.1
(9-Bit)

--±0.05

(10-Bit)

% of
FSR

% of
FSR

% of
FSR

(Figure 2)

Nonlinearity Tempco -10V ≤ V

(Notes 3, 4)

REF

≤ +10V

-- ±2- - ±2 ppm of
FSR/oC

Gain Error - ±0.3 - - ±0.3 - % of

FSR

Gain Error Tempco - - ±10 - - ±10 ppm of

FSR/

Output Leakage Current
(Either Output)

Over the Specified
Temperature Range

--±200

(±300)

--±200
(±300)

nA

DYNAMIC CHARACTERISTICS

Output Current Settling Time To 0.05% of FSR (All Digital

- 1.0 - - 1.0 - µs
Inputs Low To High And High
To Low) (Note 4) (Figure 7)

Feedthrough Error V

REF

= 20V

P-P

, 10kHz

- - 10 - - 10 mV
(50kHz) All Digital Inputs Low
(Note 4) (Figure 6)

REFERENCE INPUT

Input Resistance All Digital Inputs High

at Ground

I

OUT1

5 10 20 5 10 20 kΩ

ANALOG OUTPUT

Output Capacitance I

All Digital Inputs High

OUT1

(Note 4) (Figure 5)

I

OUT2

All Digital Inputs Low

I

OUT1

(Note 4) (Figure 5)

I

OUT2

- 200 - - 200 - pF

-75 --75 - pF

-75 --75 - pF

- 200 - - 200 - pF

P-P

o

C

10-8

AD7520, AD7530, AD7521, AD7531

Electrical Specifications V+ = +15V, V

= +10V, TA = 25oC Unless Otherwise Specified (Continued)

REF

AD7520/AD7530 AD7521/AD7531

PARAMETER TEST CONDITIONS

Output Noise Both Outputs

(Note 4) (Figure 4)

- Equivalent

to 10kΩ

- - Equivalent
to 10kΩ

UNITSMIN TYP MAX MIN TYP MAX

- Johnson
Noise

DIGITAL INPUTS

Low State Threshold, V
High State Threshold, V
Input Current, I

, I

IL

IH

IL

IH

Over the Specified
Temperature Range
VIN = 0V or +15V

- - 0.8 - - 0.8 V

2.4 - - 2.4 - - V

-- ±1- - ±1 µA

Input Coding See Tables 1 and 2 Binary/Offset Binary

POWER SUPPLY CHARACTERISTICS

Power Supply Rejection V+ = 14.5V to 15.5V

(Note 3) (Figure 3)

- ±0.005 - - ±0.005 - % FSR/
% ∆V+

Power Supply Voltage Range +5 to +15 +5 to +15 V
I+ All Digital Inputs at 0V or V+

- ±1--±1-µA

Excluding Ladder Network
All Digital Inputs High or Low

-- 2-- 2mA

Excluding Ladder Network

Total Power Dissipation Including the Ladder Network - 20 - - 20 - mW

NOTES:

2. Full scale range (FSR) is 10V for Unipolar and±10V for Bipolar modes.

3. Using internal feedback resistor R

FEEDBACK

.

4. Guaranteed by design, or characterization and not production tested.

5. Accuracy not guaranteed unless outputs at GND potential.

6. Accuracy is tested and guaranteed at V+ = 15V only.

Functional Diagram

V

REF

SPDT NMOS

SWITCHES

NOTES:
Switches shown for Digital Inputs “High”.
Resistor values are typical.

10kΩ 10kΩ 10kΩ 10kΩ

BIT 3BIT 2MSB

10kΩ

20kΩ

GND

I

OUT2

I

OUT1

R

FEEDBACK

20kΩ20kΩ20kΩ20kΩ20kΩ

10-9

AD7520, AD7530, AD7521, AD7531

Pin Descriptions

AD7520/30 AD7521/31 PIN NAME DESCRIPTION

11I
22I
3 3 GND Digital Ground. Ground potential for digital side of D/A.
4 4 Bits 1(MSB) Most Significant Digital Data Bit.
5 5 Bit 2 Digital Bit 2.
6 6 Bit 3 Digital Bit 3.
7 7 Bit 4 Digital Bit 4.
8 8 Bit 5 Digital Bit 5.

9 9 Bit 6 Digital Bit 6.
10 10 Bit 7 Digital Bit 7.
11 11 Bit 8 Digital Bit 8.
12 12 Bit 9 Digital Bit 9.
13 13 Bit 10 Digital Bit 10 (AD7521/31). Least Significant Digital Data Bit (AD7520/30).

- 14 Bit 11 Digital Bit 11 (AD7521/31).

- 15 Bit 12 Least Significant Digital Data Bit (AD7521/31).
14 16 V+ Power Supply +5V to +15V.
15 17 V
16 18 R

OUT1
OUT2

REF

FEEDBACK

Current Out summing junction of the R2R ladder network.
Current Out virtual ground, return path for the R2R ladder network.

Voltage Reference Input to set the output range. Supplies the R2R resistor ladder.
Feedback resistor used for the current to voltage conversion when using an external Op Amp.

Definition of Terms

Nonlinearity: Error contributed by deviation of the DAC

transfer function from a “best straight line” through the actual
plot of transfer function. Normally expressed as a percent­age of full scale range or in (sub)multiples of 1 LSB.

Resolution: It is addressing the smallest distinct analog
output change that a D/A converter can produce. It is
commonly expressed as the number of converter bits. A
converter with resolution of n bits can resolve output changes

-N

of 2

of the full-scale range, e.g., 2-N V

for a unipolar

REF

conversion. Resolution by no means implies linearity.
Settling Time: Time required for the output of a D AC to set-

tle to within specified error band around its final value (e.g.,

1

/2 LSB) for a given digital input change, i.e., all digital inputs

LOW to HIGH and HIGH to LOW.
Gain Error: The difference between actual and ideal analog

output values at full scale range, i.e., all digital inputs at
HIGH state. It is expressed as a percentage of full scale
range or in (sub)multiples of 1 LSB.

Feedthrough Error: Error caused by capacitive coupling
from V

Output Capacitance: Capacitance from I

REF

to I

with all digital inputs LOW.

OUT1

OUT1

and I

OUT2

terminals to ground.
Output Leakage Current: Current which appears on I

terminal when all digital inputs are LOW or on I

OUT1
OUT2

terminal when all digital inputs are HIGH.

Detailed Description

The AD7520, AD7530, AD7521 and AD7531 are monolithic,
multiplying D/A converters. A highly stable thin film R-2R
resistor ladder network and NMOS SPDT switches form the
basis of the converter circuit, CMOS level shifters permit low
power TTL/CMOS compatible operation. An external voltage

or current reference and an operational amplifier are all that
is required for most voltage output applications.

A simplified equivalent circuit of the DAC is shown in the
Functional Diagram. The NMOS SPDT switches steer the lad­der leg currents between I

OUT1

and I

buses which must

OUT2

be held either at ground potential. This configuration main­tains a constant current in each ladder leg independent of the
input code.

Converter errors are further reduced by using separate
metal interconnections between the major bits and the
outputs. Use of high threshold switches reduce offset (leak­age) errors to a negligible level.

The level shifter circuits are comprised of three inverters with
positive feedbac k from the output of the second to the first, see
Figure 1. This configuration results in TTL/CMOS compatible
operation over the full military temperature range. With the lad­der SPDT switches driven by the level shifter, each switch is
binarily weighted for an ON resistance proportional to the
respective ladder leg current. This assures a constant voltage
drop across each switch, creating equipotential terminations for
the 2R ladder resistors and highly accurate leg currents.

V+

DTL/TTL/

CMOS INPUT

13

4

5

FIGURE 1. CMOS SWITCH

6

TO LADDER

72

I

OUT2IOUT1

89

10-10

AD7520, AD7530, AD7521, AD7531

Test Circuits

V

BIT 1

(MSB)

10-BIT

BINARY

COUNTER

CLOCK

+11V (ADJUST FOR V

15µF

BIT 10

1K

BIT 10

(LSB)

BIT 1
(LSB)

BIT 11
BIT 12

15

4
5

AD7520
13

3

The following test circuits apply for the AD7520. Similar circuits are used for the AD7530, AD7521 and AD7531.

REF

GND

+15V

15

4

16

1

5
AD7520

13

32

V

REF

12-BIT

REFERENCE

DAC

R

FEEDBACK

I

OUT1

I

OUT2

-

HA2600
+

10kΩ 0.01%

10kΩ

0.01%

-

HA2600

+

1MΩ

LINEARITY

ERROR

X 100

+15V

+10V

V

REF

BIT 1

(MSB)

BIT 10

(LSB)

GND

15

14

4

16

5
AD7520

13

32

R

I

OUT1

1

I

OUT2

UNGROUNDED
SINE WAVE
GENERATOR
400Hz 1V

5K 0.01%

5kΩ 0.01%

FEEDBACK

-

HA2600

+

P-P

FIGURE 2. NONLINEARITY FIGURE 3. POWER SUPPLY REJECTION

= 0V)

OUT

+15V

f = 1kHz

V

OUT

BW = 1Hz

QUAN

TECH

MODEL 134D

WAVE

ANALYZER

100Ω

I

14

OUT2

2

10kΩ

-

1kΩ

0.1µF

101ALN
+

50V

I

OUT1

1

50kΩ

+15V

BIT 1 (MSB)

BIT 10 (LSB)

+15VNC

15

14
4
5

AD7520

1332

16

1

NC

1kΩ

SCOPE

500kΩ

-

HA2600

+

100mV
1MHz

P-P

= 20V

V

REF

100kHz SINE WAVE

BIT 10 (LSB)

P-P

BIT 1 (MSB)

FIGURE 6. FEEDTHROUGH ERROR FIGURE 7. OUTPUT CURRENT SETTLING TIME

FIGURE 4. NOISE FIGURE 5. OUTPUT CAPACITANCE

5t: 1% SETTLING (1mV)
8t: 0.03% SETTLING
t = RISE TIME

+100mV

I

OUT2

100Ω

15
4
5

AD7520

13

3

+15V

14

16

GND

EXTRAPOLATE

V

REF

-10V

BIT 1 (MSB)

I

OUT1

3

2

-

HA2600
+

6

V

OUT

1

I

OUT2

2

+5V

0V

DIGITAL

INPUT

BIT 10 (LSB)

+15V

15

14
4
5

AD7520

1332

GND

1

10-11

SCOPE

AD7520, AD7530, AD7521, AD7531

Applications

Unipolar Binary Operation

The circuit configuration for operating the AD7520 in unipo­lar mode is shown in Figure 8. Similar circuits can be used
for AD7521, AD7530 and AD7531. With positive and nega­tive V
cation. The “Digital Input Code/Analog Output Value” table
for unipolar mode is given in Table 1.

DIGITAL

FIGURE 8. UNIPOLAR BINARY OPERATION (2-QUADRANT

NOTES:

1. LSB = 2-N V

2. N = 10 for 7520, 7530;

Zero Offset Adjustment

1. Connect all digital inputs to GND.

2. Adjust the offset zero adjust trimpot of the output

Gain Adjustment

1. Connect all digital inputs to V+.

2. Monitor VOUT f or a -V

3. To decrease V

4. T o increase V

Bipolar (Offset Binary) Operation

The circuit configuration for operating the AD7520 in the
bipolar mode is given in Figure 9. Similar circuits can be
used for AD7521, AD7530 and AD7531. Using offset binary
digital input codes and positive and negative reference volt­age values, 4-Quadrant multiplication can be realized. The

values the circuit is capable of 2-Quadrant multipli-

REF

15
4
5

AD7520

13

.

+15V

14

R

FEEDBACK

16

I

OUT1

1

I

OUT2

2

3

GND

(1-2-N)

REF

(1/2 + 2-N)

REF

/2

REF

(1/2-2-N)

REF

(2-N)

REF

.

OUT

(1-2-N) reading. (N = 10 for

REF

-

V

6

+

OUT

V

REF

BIT 1 (MSB)

INPUT

BIT 10 (LSB)

MULTIPLICATION)

TABLE 1. CODE TABLE - UNlPOLAR BINARY OPERATION

DIGITAL INPUT ANALOG OUTPUT

1111111111 -V
1000000001 -V
1000000000 -V
0111111111 -V
0000000001 -V
0000000000 0

REF

N = 12 for 7521, 7531.

operational amplifier for 0V at V

AD7520/30 and N = 12 for AD7521/31).

, connect a series resistor (0 to 250Ω)

between the reference voltage and the V

the I

OUT1

OUT

, connect a series resistor (0 to 250Ω) in

OUT

amplifier feedback loop.

REF

terminal.

“Digital Input Code/Analog Output Value” table for bipolar
mode is given in Table 2.

V

REF

BIT 1

(MSB)

INPUT

DIGITAL

BIT 10

(LSB)

FIGURE 9. BIPOLAR OPERATION (4-QUADRANT MULTIPLICA TION)

TABLE 2. BlPOLAR (OFFSET BINARY) CODE TABLE

DIGITAL INPUT ANALOG OUTPUT

NOTES:

1. LSB = 2

+15V

15

14

R
4
5

AD7520

13

3

1111111111 -V
1000000001 -V
1000000000 0
0111111111 V
0000000001 V
0000000000 V

-(N-1)

FEEDBACK

16

I

OUT1

1

I

OUT2

2

V

. 2. N = 10 for 7520, 7521;

REF

-

6

+

R1 10K

0.01%

R3

10MΩ

-

R2 10K

0.01%

(1-2

REF

(2

REF

-(N-1)

(2

REF

(1-2

REF
REF

N = 12 for 7530, 7531.

-(N-1)

-(N-1)

-(N-1)

6

+

)

)

)

)

A “Logic 1” input at any digital input forces the corresponding
ladder switch to steer the bit current to I
input forces the bit current to I
I

OUT1

and I

bus currents are complements of one

OUT2

another. The current amplifier at I
I

current and the transconductance amplifier at I

OUT2

bus. For any code the

OUT2

OUT2

bus. A “Logic 0”

OUT1

changes the polarity of

out-

OUT1

put sums the two currents. This configuration doubles the out­put range. The difference current resulting at zero offset binary
code, (MSB = “Logic 1”, All other bits = “Logic 0”), is corrected
by using an external resistor , (10MΩ), from V

REF

to I

OUT2

.

Offset Adjustment

1. Adjust V

to approximately +10V.

REF

2. Connect all digital inputs to “Logic 1”.

3. Adjust I
I

OUT2

amplifier offset adjust trimpot for 0V±1mV at

OUT2

amplifier output.

4. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”.

5. Adjust I
V

OUT

amplifier offset adjust trimpot for 0V±1mV at

OUT1

.

Gain Adjustment

1. Connect all digital inputs to V+.

2. Monitor V

OUT

for a -V

REF

(1-2-

(N-1)

volts reading. (N = 10 for

AD7520 and AD7530, and N = 12 for AD7521 and AD7531).

3. T o increase V
between V

4. To decrease V
between the reference voltage and the V

, connect a series resistor of up to 250Ω

OUT

OUT

and R

FEEDBACK

, connect a series resister of up to 250Ω

OUT

.

REF

terminal.

OUT

V

10-12

Die Characteristics

AD7520, AD7530, AD7521, AD7531

DIE DIMENSIONS:

101 mils x 103 mils (2565micrms x 2616micrms)

METALLIZATION:

Type: Pure Aluminum
Thickness: 10 ±1k

Å

Metallization Mask Layout

PIN 7
BIT 4

PIN 8
BIT 5

AD7520, AD7530

PIN 6
BIT 3

PASSIVATION:

Type: PSG/Nitride
PSG: 7 ±1.4k
Nitride: 8 ±1.2kÅ

PROCESS:

CMOS Metal Gate

PIN 5
BIT 2

Å

PIN 4
BIT 1
(MSB)

PIN 3
GND

PIN 2

2

I

OUT

PIN 1
I

1

OUT

PIN 9
BIT 6

PIN 10

BIT 7

PIN 11

BIT 8

BIT 9

PIN 13
BIT 10

(LSB)

PIN 16
R

FEEDBACK

PIN 15
V

REF

PIN 14
V+

NCNCPIN 12

10-13

Die Characteristics

AD7520, AD7530, AD7521, AD7531

DIE DIMENSIONS:

101 mils x 103 mils (2565micrms x 2616micrms)

METALLIZATION:

Type: Pure Aluminum
Thickness: 10 ±1k

Å

Metallization Mask Layout

PIN 7
BIT 4

PIN 8
BIT 5

AD7521, AD7531

PIN 6
BIT 3

PASSIVATION:

Type: PSG/Nitride
PSG: 7 ±1.4k
Nitride: 8 ±1.2kÅ

PROCESS:

CMOS Metal Gate

PIN 5
BIT 2

Å

PIN 4
BIT 1
(MSB)

PIN 3
GND

PIN 2

2

I

OUT

PIN 1
I

1

OUT

PIN 9
BIT 6

PIN 10

BIT 7

PIN 11

BIT 8

PIN 12

BIT 9

PIN 13
BIT 10

PIN 14

BIT 11

PIN 15
BIT 12

(LSB)

PIN 18
R

FEEDBACK

PIN 17
V

REF

PIN 16
V+

10-14

AD7520, AD7530, AD7521, AD7531

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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