Datasheet AD7528UQ, AD7528TQ, AD7528SQ, AD7528LP, AD7528LN Datasheet (Analog Devices)

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CMOS Dual 8-Bit

REF

AD7528

REF

AGND

DB0

DB7

DATA

INPUTS

DAC A/

DAC B

DGND

CONTROL

LOGIC

INPUT

BUFFER

LATCH

OUT B

OUT A

DAC B

DAC A

RFB A

Buffered Multiplying DAC

AD7528

FEATURES On-Chip Latches for Both DACs +5 V to +15 V Operation DACs Matched to 1% Four Quadrant Multiplication TTL/CMOS Compatible Latch Free (Protection Schottkys not Required)

APPLICATIONS Digital Control of:

Gain/Attenuation Filter Parameters Stereo Audio Circuits X-Y Graphics

GENERAL DESCRIPTION

The AD7528 is a monolithic dual 8-bit digital/analog converter featuring excellent DAC-to-DAC matching. It is available in skinny 0.3" wide 20-lead DIPs and in 20-lead surface mount packages.

Separate on-chip latches are provided for each DAC to allow easy microprocessor interface.

Data is transferred into either of the two DAC data latches via a common 8-bit TTL/CMOS compatible input port. Control input DAC A/DAC B determines which DAC is to be loaded. The AD7528’s load cycle is similar to the write cycle of a random access memory and the device is bus compatible with most 8-bit microprocessors, including 6800, 8080, 8085, Z80.

The device operates from a +5 V to +15 V power supply, dissipating only 20 mW of power.

Both DACs offer excellent four quadrant multiplication characteristics with a separate reference input and feedback resistor for each DAC.

PRODUCT HIGHLIGHTS

1. DAC-to-DAC matching: since both of the AD7528 DACs are fabricated at the same time on the same chip, precise matching and tracking between DAC A and DAC B is inherent.

Model

AD7528JN –40°C to +85°C ±1 LSB ±4 LSB N-20 AD7528KN –40°C to +85°C ±1/2 LSB ±2 LSB N-20 AD7528LN –40°C to +85°C ±1/2 LSB ±1 LSB N-20 AD7528JP –40°C to +85°C ±1 LSB ±4 LSB P-20A AD7528KP –40°C to +85°C ±1/2 LSB ±2 LSB P-20A AD7528LP –40°C to +85°C ±1/2 LSB ±1 LSB P-20A AD7528JR –40°C to +85°C ±1 LSB ±4 LSB R-20 AD7528KR –40°C to +85°C ±1/2 LSB ±2 LSB R-20 AD7528LR –40°C to +85°C ±1/2 LSB ±1 LSB R-20 AD7528AQ –40°C to +85°C ±1 LSB ±4 LSB Q-20 AD7528BQ –40°C to +85°C ±1/2 LSB ±2 LSB Q-20 AD7528CQ –40°C to +85°C ±1/2 LSB ±1 LSB Q-20 AD7528SQ –55°C to +125°C ±1 LSB ±4 LSB Q-20 AD7528TQ –55°C to +125°C ±1/2 LSB ±2 LSB Q-20 AD7528UQ –55°C to +125°C ±1/2 LSB ±1 LSB Q-20

NOTES

Analog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts will be marked with cerdip designator “Q.”

Processing to MIL-STD-883C, Class B is available. To order, add suffix “/883B” to part number. For further information, see Analog Devices’ 1990 Military Products Databook.

N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.

The AD7528’s matched CMOS DACs make a whole new range of applications circuits possible, particularly in the audio, graphics and process control areas.

2. Small package size: combining the inputs to the on-chip DAC latches into a common data bus and adding a DAC A/DAC B select line has allowed the AD7528 to be packaged in either a small 20-lead DIP, SOIC or PLCC.

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998

FUNCTIONAL BLOCK DIAGRAM

ORDERING GUIDE

Temperature Relative Gain Package

Ranges Accuracy Error Options

AD7528–SPECIFICATIONS

REF

A = V

B = +10 V; OUT A = OUT B = O V unless otherwise noted)

REF

VDD = +5 V VDD = +15 V

Parameter Version1T

STATIC PERFORMANCE

= +25°CT

MIN

, T

MAXTA

= +25°CT

MIN

, T

Units Test Conditions/Comments

MAX

Resolution All 8 8 8 8 Bits Relative Accuracy J, A, S ±1 ±1 ±1 ±1 LSB max This is an Endpoint Linearity Specification

K, B, T ±1/2 ±1/2 ±1/2 ±1/2 LSB max L, C, U ±1/2 ±1/2 ±1/2 ±1/2 LSB max

Differential Nonlinearity All ±1 ±1 ±1 ±1 LSB max All Grades Guaranteed Monotonic Over Gain Error J, A, S ± 4 ±6 ±4 ±5 LSB max Measured Using Internal R

K, B, T ±2 ±4 ±2 ±3 LSB max Both DAC Latches Loaded with 11111111

Full Operating Temperature Range

A and RFB B

L, C, U ±1 ±3 ±1 ±1 LSB max Gain Error is Adjustable Using Circuits

Gain Temperature Coefficient

∆Gain/∆Temperature All ± 0.007 ±0.007 ±0.0035 ±0.0035 %/°C max

of Figures 4 and 5

Output Leakage Current

OUT A (Pin 2) All ±50 ±400 ±50 ±200 nA max DAC Latches Loaded with 00000000 OUT B (Pin 20) All ±50 ±400 ±50 ±200 nA max

Input Resistance (V

A/V

REF

DIGITAL INPUTS

Input High Voltage

Input Low Voltage

Input Current

Input Capacitance

B Input Resistance

REF

Match All ±1 ±1 ±1 ±1% max

DB0–DB7 All 10 10 10 10 pF max WR, CS, DAC A/DAC B All 15 15 15 15 pF max

SWITCHING CHARACTERISTICS

Chip Select to Write Set Up Time

Chip Select to Write Hold Time

DAC Select to Write Set Up Time

DAC Select to Write Hold Time

Data Valid to Write Set Up Time

Data Valid to Write Hold Time

Write Pulsewidth

A, V

REF

B) All 8 8 8 8 kΩ min Input Resistance TC = –300 ppm/°C, Typical

REF

15 15 15 15 kΩ max Input Resistance is 11 kΩ

All 2.4 2.4 13.5 13.5 V min

All 0.8 0.8 1.5 1.5 V max All ±1 ±10 ±1 ±10 µA max V

= 0 or V

See Timing Diagram

All 90 100 60 80 ns min

All 0 0 10 15 ns min

All 90 100 60 80 ns min

All 0 0 10 15 ns min

All 80 90 30 40 ns min

All 0 0 0 0 ns min

All 90 100 60 80 ns min

POWER SUPPLY See Figure 3

All 2 2 2 2 mA max All Digital Inputs VIL or V All 100 500 100 500 µA max All Digital Inputs 0 V or V

(Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as

AC PERFORMANCE CHARACTERISTICS

Output Amplifiers)

VDD = +5 V VDD = +15 V

Parameter Version1T

= +25°CT

MIN

, T

MAXTA

= +25°CT

MIN

, T

Units Test Conditions/Comments

MAX

DC SUPPLY REJECTION (∆GAIN/∆VDD) All 0.02 0.04 0.01 0.02 % per % max ∆VDD = ±5%

CURRENT SETTLING TIME

PROPAGATION DELAY (From Digital In- V

put to 90% of Final Analog Output Current) All 220 270 80 100 ns max OUT A, OUT B Load = 100 Ω C

All 350 400 180 200 ns max To 1/2 LSB. OUT A/OUT B Load = 100 Ω.

WR = CS = 0 V. DB0–DB7 = 0 V to V VDD to 0 V

A = V

REF

B = +10 V

REF

WR = CS = 0 V DB0–DB7 = 0 V to VDD or

= 13 pF

EXT

VDD to 0 V

DIGITAL-TO-ANALOG GLITCH IMPULSE All 160 440 nV sec typ For Code Transition 00000000 to 11111111

OUTPUT CAPACITANCE

A All 50 50 50 50 pF max DAC Latches Loaded with 00000000

OUT

B 50 505050pF max

OUT

A 120 120 120 120 pF max DAC Latches Loaded with 11111111

OUT

B 120 120 120 120 pF max

OUT

AC FEEDTHROUGH

A to OUT A All –70 –65 –70 –65 dB max V

REF

B to OUT B –70 –65 –70 –65 dB max @ 100 kHz

REF

A, V

REF

B = 20 V p-p Sine Wave

REF

REV. B–2–

3 2 1 20 19

9 10 11 12 13

18 17 16 15 14

4 5 6 7 8

TOP VIEW

(Not to Scale)

PIN 1 IDENTIFIER

REF

DGND

DAC A/DAC B

(MSB) DB7

DB6

REF

DB0 (LSB)

AD7528

OUT A

AGND

OUT B

DB5

DB4

DB3

DB2

DB1

AD7528

VDD = +5 V VDD = +15 V

Parameter Version1T

CHANNEL-TO-CHANNEL ISOLATION Both DAC Latches Loaded with 11111111.

A to OUT B All –77 –77 dB typ V

REF

B to OUT A –77 –77 dB typ V

REF

DIGITAL CROSSTALK All 30 60 nV sec typ Measured for Code Transition 00000000 to

HARMONIC DISTORTlON All –85 –85 dB typ VIN = 6 V rms @ 1 kHz

NOTES

Temperature Ranges are J, K, L Versions: –40°C to +85°C

Specifications applies to both DACs in AD7528.

Guaranteed by design but not production tested.

Logic inputs are MOS Gates. Typical input current (+25°C) is less than 1 nA.

These characteristics are for design guidance only and are not subject to test.

Feedthrough can be further reduced by connecting the metal lid on the ceramic package (suffix D) to DGND.

Specifications subject to change without notice.

A, B, C Versions: –40°C to +85°C S, T, U Versions: –55°C to +125°C

ABSOLUTE MAXIMUM RATINGS

= +25°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . V

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . V

Digital Input Voltage to DGND . . . . . . . –0.3 V, V

, V

V V V

PIN2

REF

RFB

A, V A, V

to AGND . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V

PIN20

B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V

REF

B to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V

RFB

Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C

Operating Temperature Range

Commercial (J, K, L) Grades . . . . . . . . . . . –40°C to +85°C

Industrial (A, B, C) Grades . . . . . . . . . . . . –40°C to +85°C

Extended (S, T, U) Grades . . . . . . . . . . . –55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C

CAUTION:

1. ESD sensitive device. The digital control inputs are diode

protected; however, permanent damage may occur on unconnected devices subjected to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts.

2. Do not insert this device into powered sockets. Remove

power before insertion or removal.

= +25°CT

+ 0.3 V

MIN

, T

= +25°CT

MAXTA

AD7528, ideal maximum output is V

MIN

, T

Units Test Conditions/Comments

MAX

A = 20 V p-p Sine Wave @ 100 kHz

REF

B = 0 V see Figure 6.

REF

A = 20 V p-p Sine Wave @ 100 kHz

REF

A = 0 V see Figure 6.

REF

11111111

REF

– 1 LSB. Gain error of

both DACs is adjustable to zero with external resistance.

Output Capacitance

Capacitance from OUT A or OUT B to AGND.

Digital to Analog Glitch lmpulse

The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal. Glitch impulse is measured with V

B = AGND.

REF

Propagation Delay

This is a measure of the internal delays of the circuit and is defined as the time from a digital input change to the analog output current reaching 90% of its final value.

Channel-to-Channel Isolation

The proportion of input signal from one DAC’s reference input which appears at the output of the other DAC, expressed as a ratio in dB.

Digital Crosstalk

The glitch energy transferred to the output of one converter due to a change in digital input code to the other converter. Specified in nV secs.

PIN CONFIGURATIONS

PLCC

TERMINOLOGY Relative Accuracy

Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full scale reading.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of ±1 LSB max over

the operating temperature range ensures monotonicity.

Gain Error

Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For the

REV. B

–3–

AGND

OUT A

REF

DGND

DAC A/DAC B

(MSB) DB7

DB6 DB5 DB4

DIP, SOIC

AD7528

TOP VIEW

(Not to Scale)

OUT B

RFB B

DB0 (LSB)

DB1

DB2

DB3

REF

AD7528

RFB A

AGND

OUT A

g(V

REF

A, N)

LKG

OUT

VIN – Volts

800

mA (V

= +5V)

1 2 3 4 5 6 7 8 9 10 11 13 1412

700 600 500 400 300 200 100

mA (V

= +15V)

9 8 7 6 5 4 3 2 1

VDD = +5V

VDD = +15V

= +258C

ALL DIGITAL INPUTS TIED TOGETHER

INTERFACE LOGIC INFORMATION DAC Selection:

Both DAC latches share a common 8-bit input port. The control input DAC A/DAC B selects which DAC can accept data from the input port.

Mode Selection:

Inputs CS and WR control the operating mode of the selected DAC. See Mode Selection Table below.

Write Mode:

When CS and WR are both low the selected DAC is in the write mode. The input data latches of the selected DAC are transparent and its analog output responds to activity on DB0–DB7.

Hold Mode:

The selected DAC latch retains the data which was present on DB0–DB7 just prior to CS or WR assuming a high state. Both analog outputs remain at the values corresponding to the data in their respective latches.

Mode Selection Table

DAC A/DAC B CS WR DAC A DAC B

L L L WRITE HOLD H L L HOLD WRITE X H X HOLD HOLD

X X H HOLD HOLD

L = Low State; H = High State; X = Don’t Care.

WRITE CYCLE TIMING DIAGRAM

CHIP SELECT

DAC A/DAC B

WRITE

DATA IN

(DB0 – DB7)

DATA IN STABLE

NOTES:

1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF V V

DD =

2. TIMING MEASUREMENT REFERENCE LEVEL IS

+5V, t +15V, t

= 20ns;

= 40ns;

+ V

0 V

Figure 1. An inverted R-2R ladder structure is used, that is, binary weighted currents are switched between the DAC output and AGND thus maintaining fixed currents in each ladder leg independent of switch state.

EQUIVALENT CIRCUIT ANALYSIS

Figure 2 shows an approximate equivalent circuit for one of the AD7528’s D/A converters, in this case DAC A. A similar equivalent circuit can be drawn for DAC B. Note that AGND (Pin 1) is common for both DAC A and DAC B.

The current source I

LEAKAGE

is composed of surface and junc-

tion leakages and, as with most semiconductor devices, approxi-

mately doubles every 10°C. The resistor R

as shown in Figure

2 is the equivalent output resistance of the device which varies with input code (excluding all 0s code) from 0.8 R to 2 R. R is

typically 11 kΩ. C

is the capacitance due to the N-channel

OUT

switches and varies from about 50 pF to 120 pF depending upon the digital input. g(V voltage generator due to the reference input voltage V

A, N) is the Thevenin equivalent

REF

A and

the transfer function of the R-2R ladder.

Figure 2. Equivalent Analog Output Circuit of DAC A

CIRCUIT INFORMATION–DIGITAL SECTION

The input buffers are simple CMOS inverters designed such that when the AD7528 is operated with V

= 5 V, the buffer

converts TTL input levels (2.4 V and 0.8 V) into CMOS logic levels. When V

is in the region of 2.0 volts to 3.5 volts the

input buffers operate in their linear region and pass a quiescent current, see Figure 3. To minimize power supply currents it is recommended that the digital input voltages be as close to the supply rails (V

and DGND) as is practically possible.

The AD7528 may be operated with any supply voltage in the

range 5 ≤ V

≤ 15 volts. With V

= +15 V the input logic

levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.

CIRCUIT INFORMATION—D/A SECTION

The AD7528 contains two identical 8-bit multiplying D/A converters, DAC A and DAC B. Each DAC consists of a highly stable thin film R-2R ladder and eight N-channel current steering switches. A simplified D/A circuit for DAC A is shown in

REF

Figure 1. Simplified Functional Circuit for DAC A

2RS12RS22R

DAC A DATA LATCHES

AND DRIVERS

RRR

2RS82R

OUT A AGND

Figure 3. Typical Plots of Supply Current, IDD vs. Logic Input Voltage V

, for VDD = +5 V and +15 V

REV. B–4–

–V

256

 



 



= 0

(± 10V)

DB0

DATA

INPUTS

DB7

DAC A/

DAC B

DGND

NOTES:

SEE TABLE III FOR RECOMMENDED VALUES.

USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.

INPUT

BUFFER

LATCH

DAC A

AD7528

CONTROL

LOGIC

LATCH

R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. C1, C2 PHASE COMPENSATION (10pF–15pF) IS REQUIRED WHEN

DAC B

(± 10V)

RFB A

OUT A

AGND

OUT B

Figure 4. Dual DAC Unipolar Binary Operation (2 Quadrant Multiplication); See Table I

AGND

AD7528

Table I. Unipolar Binary Code Table

DAC Latch Contents Analog Output

OUT

MSB LSB (DAC A or DAC B)





255

–V



1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

–V

 



 



 



 





256

129 256

128 256

127 256

256



 



 



 



 





=−

0 0 0 0 0 0 0 0

Note: 1 LSB =

−8

()

256

DATA

INPUTS

DAC A/

DAC B

DGND

(± 10V)

DB0

DB7

INPUT

BUFFER

LATCH

DAC A

AD7528

CONTROL

LOGIC

DAC B

NOTES:

R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. SEE TABLE III FOR RECOMMENDED VALUES. ADJUST R1 FOR V ADJUST R3 FOR V

MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10.

C1, C2 PHASE COMPENSATION (10pF–15pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER.

A = 0V WITH CODE 10000000 IN DAC A LATCH.

OUT

B = 0V WITH CODE 10000000 IN DAC B LATCH.

OUT

(± 10V)

OUT A

AGND

OUT BLATCH

AGND

Figure 5. Dual DAC Bipolar Operation (4 Quadrant Multiplication); See Table II

20kV

10kV

R11 5kV

AGND

OUT

DAC Latch Contents Analog Output MSB LSB (DAC A or DAC B)

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 1





127









128

1 0 0 0 0 0 0 0 0

Table II. Bipolar (Offset Binary) Code Table

10kV

R10

20kV

R12

5kV

AGND

OUT

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

Note: 1 LSB =

−7

()

128





–V









128





127









128





128









128

Table III. Recommended Trim Resistor Values vs. Grade

Trim Resistor J/A/S K/B/T L/C/U

R1; R3 1 k 500 200 R2; R4 330 150 82

REV. B –5–

AD7528

OUT

A = +5V TO +8V

DATA

INPUTS

DAC A/DAC B

GND

= +15V

SUGGESTED OP AMP: AD644

OUT

B = +5V TO +8V

10kV

2 VOLTS

R2 1kV

AD584J

AD7528

DB0 DB7

DAC A

DAC B

REF

(0V TO +2.5V)

+15V

AD7528

DAC A

OUT A

OUT

VINA – Volts

2.5

ERROR – LSB

3.534567

TA = +258C V

= +15V

4.5 5.5 6.5 7.5

NONLINEARITY

DIFFERENTIAL NONLINEARITY

APPLICATIONS INFORMATION Application Hints

To ensure system performance consistent with AD7528 specifications, careful attention must be given to the following points:

1. GENERAL GROUND MANAGEMENT: AC or transient voltages between the AD7528 AGND and DGND can cause noise injection into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7528. In more complex systems where the AGND–DGND intertie is on the backplane, it is recommended that diodes be connected in inverse parallel between the AD7528 AGND and DGND pins (1N914 or equivalent).

2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a code-dependent output resistance which in turn causes a code-dependent amplifier noise gain. The effect is a codedependent differential nonlinearity term at the amplifier output which depends on V

(VOS is amplifier input offset

voltage). This differential nonlinearity term adds to the R/2R differential nonlinearity. To maintain monotonic operation, it is recommended that amplifier V

be no greater than 10% of

1 LSB over the temperature range of interest.

3. HIGH FREQUENCY CONSIDERATIONS: The output capacitance of a CMOS DAC works in conjunction with the amplifier feedback resistance to add a pole to the open loop response. This can cause ringing or oscillation. Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor.

DYNAMIC PERFORMANCE

The dynamic performance of the two DACs in the AD7528 will depend upon the gain and phase characteristics of the output amplifiers together with the optimum choice of the PC board layout and decoupling components. Figure 6 shows the relation

–100

–90

–80

–70

–60

ISOLATION – dB

–50

TA = +258C V

= +15V

= 20V PEAK TO PEAK

ship between input frequency and channel to channel isolation. Figure 7 shows a printed circuit layout for the AD7528 and the AD644 dual op amp which minimizes feedthrough and crosstalk.

SINGLE SUPPLY APPLICATIONS

The AD7528 DAC R-2R ladder termination resistors are connected to AGND within the device. This arrangement is particularly convenient for single supply operation because AGND may be biased at any voltage between DGND and V

. Figure

8 shows a circuit which provides two +5 V to +8 V analog outputs by biasing AGND +5 V up from DGND. The two DAC reference inputs are tied together and a reference input voltage is obtained without a buffer amplifier by making use of the constant and matched impedances of the DAC A and DAC B reference inputs. Current flows through the two DAC R-2R ladders into R1 and R1 is adjusted until the V

REF

A and V

REF

B inputs are at +2 V. The two analog output voltages range from +5 V to +8 V for DAC codes 00000000 to 11111111.

Figure 8. AD7528 Single Supply Operation

Figure 9 shows DAC A of the AD7528 connected in a positive reference, voltage switching mode. This configuration is useful in that V operation. However, to retain specified linearity, V

is the same polarity as VIN allowing single supply

OUT

must be in

the range 0 V to +2.5 V and the output buffered or loaded with a high impedance, see Figure 10. Note that the input voltage is connected to the DAC OUT A and the output voltage is taken from the DAC V

REF

A pin.

20k 50k 100k 200k 1M500k

INPUT FREQUENCY – Hz

Figure 6. Channel-to-Channel Isolation

PIN 8 OF TO-5 CAN (AD644)

AGND

AD7528

V+

V–

AD7528 PIN 1

REF

DGND DAC A/DAC B

MSB

C2 LOCATION

*NOTE INPUT SCREENS TO REDUCE FEEDTHROUGH. LAYOUT SHOWS COPPER SIDE (i.e., BOTTOM VIEW).

AD644

C1 LOCATION

REF

Figure 7. Suggested PC Board Layout for AD7528 with AD644 Dual Op Amp

LSB

Figure 9. AD7528 in Single Supply, Voltage Switching Mode

Figure 10. Typical AD7528 Performance in Single Supply Voltage Switching Mode (K/B/T, L/C/U Grades)

REV. B–6–

MICROPROCESSOR INTERFACE

ADDRESS BUS

A**

A + 1**

DAC A/DAC B

DAC A

DB0 DB7

AD7528*

DAC B

ADDR/DATA BUS

AD0–AD7

A8–A15

CPU 8085

*ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY **A = DECODED 7528 ADDR DAC A A + 1 = DECODED 7528 ADDR DAC B

NOTE: 8085 INSTRUCTION SHLD (STORE H & L DIRECT) CAN UPDATE BOTH DACs WITH DATA FROM H AND L REGISTERS

ADDRESS

DECODE

LOGIC

LATCH

8212

ALE

AD7528

A**

A + 1**

ADDRESS BUS

DATA BUS

DAC A/DAC B

DAC A

AD7528*

DB0

DAC B

DB7

A0–A15

CPU 6800

D0–D7

ADDRESS

DECODE

LOGIC

*ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY **A = DECODED 7528 ADDR DAC A A + 1 = DECODED 7528 ADDR DAC B

Figure 11. AD7528 Dual DAC to 6800 CPU Interface

PROGRAMMABLE WINDOW COMPARATOR

TEST INPUT

0 TO –V

REF

DATA

INPUTS

DAC A/DAC B

REF

DB0

DB7

AD7528

DAC A

DAC B

RFB B

OUT A

COMPARATOR

OUT B

COMPARATOR

AD311

1kV

PASS/FAIL

OUTPUT

Figure 12. AD7528 Dual DAC to 8085 CPU Interface

In the circuit of Figure 13 the AD7528 is used to implement a programmable window comparator. DACs A and B are loaded with the required upper and lower voltage limits for the test, respectively. If the test input is not within the programmed limits, the pass/fail output will indicate a fail (logic zero).

Figure 13. Digitally Programmable Window Comparator (Upper and Lower Limit Detector)

PROGRAMMABLE STATE VARIABLE FILTER

In this state variable or universal filter configuration (Figure 14) DACs A1 and B1 control the gain and Q of the filter characteristic while DACs A2 and B2 control the cutoff frequency, f

DACs A2 and B2 must track accurately for the simple expression for f

to hold. This is readily accomplished by the AD7528.

Op amps are 2 × AD644. C3 compensates for the effects of op

amp gain bandwidth limitations.

30kV

10kV

AD7528

REV. B –7–

DAC A1

DB0–DB7

DATA 1

DAC B1

DAC A/DAC B

CS WR

Figure 14. Digitally Controlled State Variable Filter

47pF

HIGH PASS OUTPUT

DAC A2

DB0–DB7

DATA 2

1000pF

AD7528

CS WR

The filter provides low pass, high pass and band pass outputs and is ideally suited for applications where microprocessor control of filter parameters is required, e.g., equalizer, tone controls, etc.

Programmable range for component values shown is f

= 0 kHz

to 15 kHz and Q = 0.3 to 4.5.

CIRCUIT EQUATIONS

CCRRR R121245== =,,

211

RRR

=×

–

FBB

NOTE DAC Equivalent Resistance Equals

256 ×()DAC Ladder sis ce

DAC Digital Code

e tan

BAND PASS OUTPUT

DAC B2

DAC A/DAC B

1000pF

LOW PASS OUTPUT

AD7528

SEATING PLANE

0.021 (0.533)

0.015 (0.381)

0.065 (1.66)

0.045 (1.15)

0.11 (2.79)

0.09 (2.28)

0.145 (3.683) MIN

0.125 (3.175) MIN

110

PIN 1

1.07 (27.18) MAX

0.255 (6.477)

0.245 (6.223)

0.32 (8.128)

0.30 (7.62)

0.011 (0.28)

0.009 (0.23)

0.135 (3.429)

0.125 (3.17)

158

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH

LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42

0.021 (0.53)

0.013 (0.33)

0.032 (0.81)

0.026 (0.66)

0.180 (4.47)

0.165 (4.19)

0.12 (3.05)

0.09 (2.29)

0.020 (0.51) MIN

0.025 (0.64) MIN

0.060 (1.53) MIN

PIN 1

IDENTIFIER

TOP VIEW

(PINS DOWN)

0.356 (9.04)

0.350 (8.89)

0.048 (1.21)

0.042 (1.07)

0.02

(0.51)

MAX

0.050 (1.27) BSC

0.02 (0.51) MAX

0.395 (10.02)

0.385 (9.78)

DIGITALLY CONTROLLED DUAL TELEPHONE ATTENUATOR

In this configuration the AD7528 functions as a 2-channel digitally controlled attenuator. Ideal for stereo audio and telephone signal level control applications. Table IV gives input codes vs. attenuation for a 0 dB to 15.5 dB range.



Attenuation dB,

DB0 DB7





−

DATA BUS

SUGGESTED OP AMP: AD644

CS WR

DAC A/DAC B

Input Code = 256 ⫻ 10 exp

OUT

DAC A

AD7528

DAC B

Figure 15. Digitally Controlled Dual Telephone Attenuator

 



OUT

Table IV. Attenuation vs. DAC A, DAC B Code for the Circuit of Figure 15

Attn. DAC Input Code In Attn. DAC Input Code In dB Code Decimal dB Code Decimal

0.0 1 1 1 1 1 1 1 1 255 88.0 0 1 1 0 0 1 1 0 102

0.5 1 1 1 1 0 0 1 0 242 88.5 0 1 1 0 0 0 0 0 96

1.0 1 1 1 0 0 1 0 0 228 89.0 0 1 0 1 1 0 1 1 91

1.5 1 1 0 1 0 1 1 1 215 89.5 0 1 0 1 0 1 1 0 86

2.0 1 1 0 0 1 0 1 1 203 10.0 0 1 0 1 0 0 0 1 81

2.5 1 1 0 0 0 0 0 0 192 10.5 0 1 0 0 1 1 0 0 76

3.0 1 0 1 1 0 1 0 1 181 11.0 0 1 0 0 1 0 0 0 72

3.5 1 0 1 0 1 0 1 1 171 11.5 0 1 0 0 0 1 0 0 68

4.0 1 0 1 0 0 0 1 0 162 12.0 0 1 0 0 0 0 0 0 64

4.5 1 0 0 1 1 0 0 0 152 12.5 0 0 1 1 1 1 0 1 61

5.0 1 0 0 1 0 0 0 0 144 13.0 0 0 1 1 1 0 0 1 57

5.5 1 0 0 0 1 0 0 0 136 13.5 0 0 1 1 0 1 1 0 54

6.0 1 0 0 0 0 0 0 0 128 14.0 0 0 1 1 0 0 1 1 51

6.5 0 1 1 1 1 0 0 1 121 14.5 0 0 1 1 0 0 0 0 48

7.0 0 1 1 1 0 0 1 0 114 15.0 0 0 1 0 1 1 1 0 46

7.5 0 1 1 0 1 1 0 0 108 15.5 0 0 1 0 1 0 1 1 43

For further applications information the reader is referred to Analog Devices Application Note on the AD7528.

C681e–0–9/98

20-Lead Cerdip (Q-20)

PIN 1

0.20 (5.0)

0.14 (3.56)

0.15 (3.8)

0.125 (3.18)

110

0.97 (24.64)

0.935 (23.75)

0.07 (1.78)

0.05 (1.27)

LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42

0.02 (0.5)

0.016 (0.41)

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH

0.11 (2.79)

0.09 (2.28)

0.28 (7.11)

0.24 (6.1)

20-Lead SOIC (R-20)

0.5118 (13.00)

0.4961 (12.60)

PIN 1

0.0118 (0.30)

0.0040 (0.10)

0.0500 (1.27)

BSC

0.1043 (2.65)

0.0926 (2.35)

0.0192 (0.49)

0.0138 (0.35)

0.2992 (7.60)

0.2914 (7.40)

SEATING PLANE

0.4193 (10.65)

0.3937 (10.00)

0.0125 (0.32)

0.0091 (0.23)

0.14 (3.56)

0.125 (3.17)

SEATING PLANE

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

0.32 (8.128)

0.29 (7.366)

0.011 (0.28)

158

0.009 (0.23)

0.0291 (0.74)

0.0098 (0.25)

88 08

3 458

0.0500 (1.27)

0.0157 (0.40)

20-Lead Plastic DIP (N-20)

20-Lead Plastic Leaded Chip Carrier (P-20A)

PRINTED IN U.S.A.

REV. B–8–

Datasheet AD7528UQ, AD7528TQ, AD7528SQ, AD7528LP, AD7528LN Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

PRODUCT HIGHLIGHTS

FUNCTIONAL BLOCK DIAGRAM

ORDERING GUIDE

AC PERFORMANCE CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

WRITE CYCLE TIMING DIAGRAM

EQUIVALENT CIRCUIT ANALYSIS

CIRCUIT INFORMATION–DIGITAL SECTION

CIRCUIT INFORMATION—D/A SECTION

DYNAMIC PERFORMANCE

SINGLE SUPPLY APPLICATIONS

MICROPROCESSOR INTERFACE

PROGRAMMABLE WINDOW COMPARATOR

PROGRAMMABLE STATE VARIABLE FILTER

CIRCUIT EQUATIONS

DIGITALLY CONTROLLED DUAL TELEPHONE ATTENUATOR