Datasheet AD7524-EP Datasheet (ANALOG DEVICES)

CMOS, 8-Bit,
V
Enhanced Product

FEATURES

Microprocessor compatible (6800, 8085, Z80) TTL-/CMOS-compatible inputs On-chip data latches Endpoint linearity Low power consumption Monotonicity guaranteed (full temperature range) Latch free (no protection Schottky required)

ENHANCED PRODUCT FEATURES

Supports defense and aerospace applications (AQEC) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request
CHIP SELECT
WRITE
Buffered Multiplying DAC
AD7524-EP

FUNCTIONAL BLOCK DIAGRAM

DD
10k
10k
S2
5
Figure 1.
10k
20k
S3
DB5
15
V
REF
20k
20k
S1
12
13
4
DB7
(MSB)
DATA LATCHES
DB6
DATA INPUTS
14
20kS820k
AD7524-EP
36
DB0
(LSB)
10k
16
1
2
3
R
FB
OUT1
OUT2
GND
01132-001

APPLICATIONS

Microprocessor controlled gain circuits Microprocessor controlled attenuator circuits Microprocessor controlled function generation Precision AGC circuits Bus structured instruments

GENERAL DESCRIPTION

The AD7524-EP is a low cost, 8-bit monolithic CMOS DAC designed for direct interface to most microprocessors.
An 8-bit DAC with input latches, the load cycle of the AD7524-EP is similar to the write cycle of the random access memory. Using an advanced thin-film on the CMOS fabrication process, the
AD7524-EP provides accuracy to ⅛ LSB with a typical power
dissipation of less than 10 mW.
An improved design eliminates the protection Schottky previously required and guarantees TTL compatibility when using a 5 V supply. The loading speed has also been increased for compatibility with most microprocessors.
Featuring operation from 5 V to 15 V, the AD7524-EP interfaces directly to most microprocessor buses or output ports.
Excellent multiplying characteristics (2- or 4-quadrant) make the AD7524-EP an ideal choice for many microprocessor controlled gain setting and signal control applications.
Additional application and technical information can be found in the AD7524 data sheet.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.
AD7524-EP Enhanced Product

TABLE OF CONTENTS

Features.............................................................................................. 1
Enhanced Product Features ............................................................ 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3

REVISION HISTORY

1/12—Revision 0: Initial Version
Write Cycle Timing Diagram ......................................................4
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Outline Dimensions..........................................................................7
Ordering Guide .............................................................................7
Rev. 0 | Page 2 of 8
Enhanced Product AD7524-EP

SPECIFICATIONS

V
= 10 V, V
REF
OUT1
= V
= 0 V, unless otherwise noted. Temperature range goes from −55°C to +125°C.
OUT2
Table 1.
Limit, TA = 25°C Limit, T
MIN
1
, T
Test Conditions/
MAX
Parameter VDD = 5 V VDD = 15 V VDD = 5 V VDD = 15 V Unit Comments
STATIC PERFORMANCE
Resolution 8 8 8 8 Bits Relative Accuracy ±1/2 ±1/2 ±1/2 ±1/2 LSB max Monotonicity Guaranteed Guaranteed Guaranteed Guaranteed Gain Error2 ±2½ ±1¼ ±3½ ±1½ LSB max Average Gain TC3 ±40 ±10 ±40 ±10 ppm/°C
DC Supply Rejection, ΔGain/ΔV
3
0.08 0.02 0.16 0.04
DD
% FSR/%
Gain TC measured from
= ±10%
DD
or from
MIN
MAX
25°C to T 25°C to T
ΔV
max
0.002 0.001 0.01 0.005 % FSR/% typ Output Leakage Current
I
(Pin 1) ±50 ±50 ±400 ±200 nA max
OUT1
I
(Pin 2) ±50 ±50 ±400 ±200 nA max
OUT2
DB0 to DB7 = 0 V;WR CS
= 0 V; V
= ±10 V
REF
DB0 to DB7 = V CS = 0 V; V
= ±10 V
REF
DYNAMIC PERFORMANCE
Output Current Settling Time
(to ½ LSB)
3
400 250 500 350 ns max
OUT1 load = 100 Ω,
= 13 pF; WR, CS = 0 V;
C
EXT
DB0 to DB7 = 0 V to V
to 0 V
DD
AC Feedthrough3
At OUT1 0.25 0.25 0.5 0.5 % FSR max
= ±10 V, 100 kHz sine
V
REF
wave; DB0 to DB7 = 0 V; WR, CS = 0 V
At OUT2 0.25 0.25 0.5 0.5 % FSR max
= ±10 V, 100 kHz sine
V
REF
wave; DB0 to DB7 = 0 V; WR, CS = 0 V
REFERENCE INPUT
RIN (Pin 15 to GND)4 5 5 5 5 kΩ min
20 20 20 20 kΩ max ANALOG OUTPUTS
Output Capacitance3
C
(Pin 1) 120 120 120 120 pF max
OUT1
C
(Pin 2) 30 30 30 30 pF max
OUT2
C
(Pin 1) 30 30 30 30 pF max
OUT1
C
(Pin 2) 120 120 120 120 pF max
OUT2
DB0 to DB7 = V
, CS = 0 V
WR
DB0 to DB7 = 0 V;
, CS = 0 V
WR
DIGITAL INPUTS
Input High Voltage Requirement, VIH 2.4 13.5 2.4 13.5 V min Input Low Voltage Requirement, VIL 0.8 1.5 0.5 1.5 V max Input Current, IIN ±1 ±1 ±10 ±10 μA max VIN = 0 V or VDD Input Capacitance3
DB0 to DB7 5 5 5 5 pF max VIN = 0 V WR, CS
20 20 20 20 pF max V
= 0 V
IN
DD
DD
,
; WR,
;
Rev. 0 | Page 3 of 8
AD7524-EP Enhanced Product
Limit, TA = 25°C Limit, T
MIN
1
, T
Test Conditions/
MAX
Parameter VDD = 5 V VDD = 15 V VDD = 5 V VDD = 15 V Unit Comments
SWITCHING CHARACTERISTICS See Figure 2
Chip Select to Write Setup Time, t
5
170 100 240 150 ns min tWR = tCS
CS
Chip Select to Write Hold Time, tCH 0 0 0 0 ns min Write Pulse Width, tWR 170 100 240 150 ns min tCS ≥ tWR, tCH ≥ 0 Data Setup Time, tDS 135 60 170 100 ns min Data Hold Time, tDH 10 10 10 10 ns min
POWER SUPPLY
IDD 1 2 2 2 mA max All digital inputs VIL or VIH
100 100 500 500 μA max All digital inputs 0 V or VDD
1
Temperature range is as follows: −55°C to +125°C.
2
Gain error is measured using internal feedback resistor. Full-scale range (FSR) = V
3
Guaranteed not tested.
4
DAC thin-film resistor temperature coefficient is approximately −300 ppm/°C.
5
AC parameter, sample tested @ 25°C to ensure conformance to specification.
.
REF

WRITE CYCLE TIMING DIAGRAM

t
t
CS
CHIP SELECT
t
WR
WRITE
t
DS
DATA IN
(DB0–DB7)
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED F ROM 10% TO 90% OF V
2. TI MING MEASUREM ENT REFERENCE LEVEL IS
3.
t
+ tDH IS APPROXIMATELY CONSTANT AT 145ns MIN
DS
AT 2 5°C, V FOR A MINIMUM
t
> 10ns, tDS MAY BE REDUCED ACCORDINGLY UP TO THE LIMIT
DH
t
= 65ns, tDH = 80ns.
DS
. VDD = 5V, tR = tF = 20ns; VDD = 15V, tR = tF = 40ns.
DD
= 5V AND tWR 170ns MIN. T HE AD7524 IS SPECIF IED
DD
t
OF 10ns. HOWEVER, INAPPLICATIONS WHERE
DH
V
IH
DATA IN STABLE
V
IL
Figure 2. Timing Diagram
CH
t
DH
+V
V
IH
IL
2
V
DD
0
V
DD
0
V
DD
0
1132 -0 02
Rev. 0 | Page 4 of 8
Enhanced Product AD7524-EP

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.
Table 2.
Parameter Rating
VDD to GND −0.3 V to +17 V
V
R
V
REF
Digital Input Voltage to GND −0.3 V to VDD +0.3 V OUT1, OUT2 to GND −0.3 V to VDD +0.3 V Power Dissipation (Any Package)
Operating Temperature, Extended −55°C to +125°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C
to GND
FEEDBACK
to GND ±25 V
To 75°C 450 mW Derates above 75°C by 6 mW/°C
±25 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 8
AD7524-EP Enhanced Product

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OUT1
OUT2
GND
(MSB) DB7
DB6
DB5
DB4
DB3
1
2
3
AD7524-EP
4
TOP VIEW
(Not to Scale)
5
6
7
8
R
16
V
15
V
14
WR
13
CS
12
11
DB0 (LSB)
10
DB1
DB2
9
FEEDBACK
REF
DD
01132-003
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 OUT1 DAC Current Output. 2 OUT2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system. 3 GND Ground. 4
DB7 (MSB) to
Parallel Data Bit 7 to Data Bit 0.
DB0 (LSB)
12 13
CS
Write. When low, use in conjunction with CS to load parallel data.
WR
Chip Select Input. Active low. Used in conjunction with
WR
to load parallel data to the input latch.
14 VDD Positive Power Supply Input. These parts can be operated with a supply of 5 V. 15 V 16 R
DAC Reference Voltage Input Terminal.
REF
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
FEEDBACK
Rev. 0 | Page 6 of 8
Enhanced Product AD7524-EP

OUTLINE DIMENSIONS

10.00 (0.3937)
9.80 (0.3858)
4.00 (0.1575)
3.80 (0.1496)
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
CONTROLL ING DIMENSIONS ARE IN MILLI METERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-O FF MIL LIMET ER EQUIVALENTS FOR REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.
16
1
1.27 (0.0500) BSC
0.51 (0.0201)
0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
9
8
6.20 (0.2441)
5.80 (0.2283)
1.75 (0.0689)
1.35 (0.0531)
SEATING PLANE
8° 0°
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
45°
060606-A
Figure 4. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model
AD7524SR-EP ±0.5 LSB −55°C to +125°C 16-Lead SOIC_N R-16 AD7524SR-EP-RL7 ±0.5 LSB −55°C to +125°C 16-Lead SOIC_N R-16
Nonlinearity (VDD = 15 V) Temperature Range Package Description Package Option
Rev. 0 | Page 7 of 8
AD7524-EP Enhanced Product
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01132-0-1/12(0)
Rev. 0 | Page 8 of 8
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