Datasheet AD7484 Datasheet (Analog Devices)

3 MSPS, 14-Bit SAR ADC

FEATURES

Fast throughput rate: 3 MSPS Wide input bandwidth: 40 MHz No pipeline delays with SAR ADC Excellent DC accuracy performance Two parallel interface modes Low power: 90 mW (full power) and 2.5 mW (NAP mode) Standby mode: 2 µA max Single 5 V supply operation Internal 2.5 V reference Full-scale overrange mode (using 15th bit) System offset removal via user access offset register Nominal 0 V to 2.5 V input with shifted range capability Pin compatible upgrade of 12-Bit AD7482

GENERAL DESCRIPTION

The AD7484 is a 14-bit, high speed, low power, successive approximation ADC. The part features a parallel interface with throughput rates up to 3 MSPS. The part contains a low noise, wide bandwidth track-and-hold that can handle input frequencies in excess of 40 MHz.

The conversion process is a proprietary algorithmic successive approximation technique that results in no pipeline delays. The input signal is sampled and a conversion is initiated on the falling edge of the

CONVST

is controlled via an internally trimmed oscillator. Interfacing is via standard parallel signal lines, making the part directly compatible with microcontrollers and DSPs.

The AD7484 provides excellent ac and dc performance specifications. Factory trimming ensures high dc accuracy resulting in very low INL, offset, and gain errors.

The part uses advanced design techniques to achieve very low power dissipation at high throughput rates. Power consumption in the normal mode of operation is 90 mW. There are two

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

signal. The conversion process

AD7484

FUNCTIONAL BLOCK DIAGRAM

AGND C

REFSEL

VIN

REFERENCE

T/H

2.5V

BIASDVDD

14-BIT

ALGORITHMIC

SAR

AD7484

MODE1

MODE2

CLIP

NAP

STBY

RESET

CONVST

CONTROL

LOGIC AND I/O

REGISTERS

BUSY

WRITE

Figure 1.

power saving modes: NAP mode, which keeps the reference circuitry alive for a quick power-up while consuming 2.5 mW, and standby mode, which reduces power consumption to a mere 10 µW.

The AD7484 features an on-board 2.5 V reference but can also accommodate an externally provided 2.5 V reference source. The nominal analog input range is 0 V to 2.5 V, but an offset shift capability allows this nominal range to be offset by ±200 mV. This allows the user considerable flexibility in setting the bottom end reference point of the signal range, a useful feature when using single-supply op amps.

The AD7484 also provides the user with an 8% overrange capability via a 15th bit. Therefore, if the analog input range strays outside the nominal range by up to 8%, the user can still accurately resolve the signal by using the 15th bit.

The AD7484 is powered by a 4.75 V to 5.25 V supply. The part also provides a V

pin that allows the user to set the voltage

DRIVE

levels for the digital interface lines. The range for this V is from 2.7 V to 5.25 V. The part is housed in a 48-lead LQFP package and is specified over a −40°C to +85°C temperature range.

DRIVE

DGND

REFOUT

REFIN

D14 D13 D12

D11 D10

D9 D8

02642-0-001

DRIVE

AD7484

Specifications..................................................................................... 3

Circuit Description .................................................................... 12

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Terminology ...................................................................................... 9

Typical Performance Characteristics ........................................... 10

REVISION HISTORY

2/04—Data Sheet changed from REV. 0 to REV. A

Updated Format......................................................... UNIVERSAL

Changes to Timing Characteristics............................................... 5

Changes to Pin Function Descriptions......................................... 8

Changes to Figure 9....................................................................... 11

Changes to the Converter Operation section ............................ 13

Changes to the Offset/Overrange section ..................................15

ADC Transfer Function............................................................. 13

Power Saving............................................................................... 13

Offset/Overrange........................................................................ 14

Parallel Interface ......................................................................... 15

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

8/02–Revision 0: Initial Version

Rev. A | Page 2 of 20

AD7484

SPECIFICATIONS

VDD = 5 V ± 5%, AGND = DGND = 0 V, V

5.25 V, unless otherwise noted. Table 1 temperature range is: −40°C to +85°C.

Table 1.

Parameter Specification Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

1, 2

Signal-to-Noise + Distortion (SINAD)3 76.5 dB min FIN = 1 MHz 78 dB typ FIN = 1 MHz 79 dB typ FIN = 1 MHz, Extended Input 77 dB typ FIN = 1 MHz, Internal Reference Total Harmonic Distortion (THD)3 −90 dB max

−95 dB typ

−92 dB typ Internal Reference Peak Harmonic or Spurious Noise (SFDR)3 −90 dB max Intermodulation Distortion (IMD)3

Second-Order Terms −96 dB typ F

Third-Order Terms −94 dB typ Aperture Delay 10 ns typ Full-Power Bandwidth 40 MHz typ @ 3 dB

3.5 MHz typ @ 0.1 dB DC ACCURACY

Resolution 14 Bits Integral Nonlinearity3 ±1 LSB max ±0.5 LSB typ Differential Nonlinearity3 ±0.75 LSB max Guaranteed No Missed Codes to 14 Bits ±0.3 LSB typ Offset Error3 ±6 LSB max

0.036 %FSR max Gain Error3 ±6 LSB max

0.036 %FSR max ANALOG INPUT

Input Voltage −200 mV min +2.7 V max DC Leakage Current ±1 µA max VIN from 0 V to 2.7 V ±2 µA typ VIN =−200 mV Input Capacitance4 35 pF typ

REFERENCE INPUT/OUTPUT

Input Voltage +2.5 V ± 1% for Specified Performance

REFIN

Input DC Leakage Current ±1 µA max

REFIN

Input Capacitance4 25 pF typ

REFIN

Input Current 220 µA typ External Reference

REFIN

Output Voltage +2.5 V typ

REFOUT

Error @ 25°C ±50 mV typ

REFOUT

Error T

REFOUT

Output Impedance 1 Ω typ

REFOUT

MIN

to T

±100 mV max

MAX

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

INH

0.4 V max

INL

Input Current, IIN ±1 µA max Input Capacitance, C

10 pF max

= External, f

REF

= 3 MSPS; all specifications T

SAMPLE

−1 V min

DRIVE

to T

MIN

MAX

= 95.053 kHz, F

IN1

and valid for V

DRIVE

= 105.329 kHz

IN2

= 2.7 V to

Rev. A | Page 3 of 20

AD7484

Parameter Specification Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, VOH 0.7 × V Output Low Voltage, VOL 0.3 × V Floating-State Leakage Current ±10 µA max Floating-State Output Capacitance4 10 pF max Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 300 ns max Track-and-Hold Acquisition Time (t

) 70 ns max Sine Wave Input

ACQ

70 ns max Full-Scale Step Input

Throughput Rate 2.5 MSPS max Parallel Mode 1 3 MSPS max Parallel Mode 2 POWER REQUIREMENTS

VDD 5 V ± 5%

2.7 V min

DRIVE

5.25 V max

IDD

Normal Mode (Static) 12 mA max Normal Mode (Operational) 18 mA max

NAP Mode 0.5 mA max Standby Mode 2 µA max

0.5 µA typ

Power Dissipation

Normal Mode (Operational) 90 mW max NAP Mode 2.5 mW max Standby Mode5 10 µW max

SNR and SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB.

See Typical Performance Characteristics section for analog input circuits used.

See Terminology section.

Sample tested @ 25°C to ensure compliance.

Digital input levels at GND or V

DRIVE

V min

DRIVE

V max

DRIVE

and RD = Logic 1

Rev. A | Page 4 of 20

AD7484

TIMING CHARACTERISTICS

VDD = 5 V ± 5%, AGND = DGND = 0 V, V otherwise noted.

All timing specifications given in Table 2 are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.

Table 2.

Parameter Symbol Min Typ Max Unit

DATA READ

Conversion Time t Quiet Time before Conversion Start t CONVST

CONVST CS

Pulse Width Falling Edge to

BUSY

Falling Edge

Falling Edge to RD Falling Edge Data Access Time t4 25 ns CONVST

BUSY

Falling Edge to New Data Valid

Rising Edge to New Data Valid Bus Relinquish Time t7 10 ns RD

Rising Edge to CS Rising Edge

Pulse Width

DATA WRITE

WRITE Pulse Width t9 5 ns Data Setup Time t10 2 ns Data Hold Time t11 6 ns CS

Falling Edge to WRITE Falling Edge

WRITE Falling Edge to CS Rising Edge

= External; all specifications T

REF

to T

MIN

CONV

QUIET

5 100 ns

20 ns

0 ns

30 ns

5 ns

0 ns

and valid for V

MAX

= 2.7 V to 5.25 V, unless

DRIVE

300 ns 100 ns

30 ns 30 ns

5 ns 0 ns

Rev. A | Page 5 of 20

AD7484

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND −0.3 V to +7 V V

to GND −0.3 V to +7 V

DRIVE

Analog Input Voltage to GND −0.3 V to AVDD + 0.3 V Digital Input Voltage to GND

REFIN to GND −0.3 V to AVDD + 0.3 V Input Current to Any Pin except

Supplies Operating Temperature Range

Commercial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 50°C/W θJC Thermal Impedance 10°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C ESD 1 kV

−0.3 V to V V

±10 mA

DRIVE

+ 0.3

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 6 of 20

AD7484

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

AVDDCLIP

MODE1

MODE2

RESET

CONVST

D14

D13

D12

48 47 46 45 44 39 38 3743 42 41 40

PIN 1

BIAS

AGND AGND

AGND

VIN

REFOUT

REFIN

REFSEL

AGND AGND

IDENTIFIER 3 4 5

6 7 8 9

10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

AGND

AD7484

TOP VIEW

(Not to S cale)

NAP

STBY

WRITE

Figure 2. Pin Configuration

D11

D10

DRIVE

DGND

BUSY

02642-0-002

Rev. A | Page 7 of 20

AD7484

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1, 5, 13, 46 AVDD Positive Power Supply for Analog Circuitry. 2 C 3, 4, 6, 11, 12,

14, 15, 47, 48 7 VIN Analog Input. Single-ended analog input channel. 8 REFOUT

9 REFIN

10 REFSEL

16 STBY

17 NAP

19 20 WRITE

22 to 28, 33 to 39

29 DVDD Positive Power Supply for Digital Circuitry. 30, 31 DGND Ground Reference for Digital Circuitry. 32 V

40 D14

43 MODE2 Operating Mode Logic Input. See Table 7 for details. 44 MODE1 Operating Mode Logic Input. See Table 7 for details. 45 CLIP

Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin and AGND.

BIAS

AGND Power Supply Ground for Analog Circuitry.

Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF capacitor must be placed between this pin and AGND.

Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using an external voltage reference source, the reference voltage should be applied to this pin.

Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected from this pin to AGND. When using an external reference source, this pin should be connected directly to AGND.

Standby Logic Input. When this pin is logic high, the device will be placed in standby mode. See the Power Saving section for further details.

NAP Logic Input. When this pin is logic high, the device will be placed in a very low power mode. See the Power Saving section for further details.

Chip Select Logic Input. This pin is used in conjunction with data bus is brought out of three-state and the current contents of the output register driven onto the

and RD. CS is also used in conjunction with WRITE to

can be hardwired permanently low.

to access the conversion result.

to write data to the offset register. When the desired offset

data lines following the falling edge of both perform a write to the offset register.

Read Logic Input. Used in conjunction with

Write Logic Input. Used in conjunction with word has been placed on the data bus, the WRITE line should be pulsed high. It is the falling edge of this pulse that latches the word into the offset register.

BUSY

Busy Logic Output. This pin indicates the status of the conversion process. The after the falling edge of

BUSY

the

signal returns high when the conversion result has been latched into the output register.

In Parallel Mode 2, the

CONVST

BUSY

and stays low for the duration of the conversion. In Parallel Mode 1,

signal returns high as soon as the conversion has been completed, but the

conversion result does not get latched into the output register until the falling edge of the next pulse.

D0 to D13

Data I/O Bits (D13 is MSB). These are three-state pins that are controlled by The operating voltage level for these pins is determined by the V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin will determine at what voltage the interface logic of the device will operate.

Data Output Bit for Overranging. If the overrange feature is not used, this pin should be pulled to DGND via a 100 kΩ resistor.

CONVST

Convert Start Logic Input. A conversion is initiated on the falling edge of the track-and-hold amplifier goes from track mode to hold mode and the conversion process commences.

RESET

Reset Logic Input. An active low reset pulse must be applied to this pin after power-up to ensure correct operation. A falling edge on this pin resets the internal state machine and terminates a conversion that may be in progress. The contents of the offset register will also be cleared on this edge. Holding this pin low keeps the part in a reset state.

Logic Input. A logic high on this pin enables output clipping. In this mode, any input voltage that is greater than positive full scale or less than negative full scale will be clipped to all 1s or all 0s, respectively. Further details are given in the Offset/Overrange section.

to access the conversion result. The

BUSY

signal goes low

, RD, and WRITE.

input.

DRIVE

CONVST

signal. The input

CONVST

Rev. A | Page 8 of 20

AD7484

(

)

TERMINOLOGY

Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition.

Differential Nonlinearity

This is the difference between the measured and ideal 1 LSB change between any two adjacent codes in the ADC.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the harmonics to the fundamental. For the AD7484, it is defined as

()

dBTHD

= log20

where V

is the rms amplitude of the fundamental and V2, V3,

, V5, and V6 are the rms amplitudes of the second through the

VVVVV

++++

sixth harmonics.

Offset Error This is the deviation of the first code transition (00…000) to (00…001) from the ideal, i.e., AGND + 0.5 LSB.

Gain Error This is the deviation of the last code transition (111…110) to (111…111) from the ideal, i.e., V

− 1.5 LSB, after the offset

REF

error has been adjusted out.

Track-and-Hold Acquisition Time It is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion (the point at which the track-and-hold returns to track mode).

Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f

/2), excluding dc. The ratio is

dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by

()

dB76.102.6 +=+−− NDistortionNoisetoSignal

Thus, for a 14-bit converter, this is 86.04 dB.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f

/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The AD7484 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second-order and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.

Rev. A | Page 9 of 20

AD7484

TYPICAL PERFORMANCE CHARACTERISTICS

–20

–40

–60

–80

–100

–120

–140

0 200 400 600 800 1400

FREQUENCY (kHz)

Figure 3. 64k FFT Plot With 10 kHz Input Tone

= 1.013MHz

SNR = 77.7dB SNR + D = 77.6dB

–20

THD = –95.5dB

–40

–60

–80

–100

SNR = 78.9dB

SNR + D = 78.8dB

THD = –93.9dB

1000 1200

= 10.7kHz

02642-0-003

1.0

0.8

0.6

0.4

0.2

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 4096 8192 16384

ADC (Code)

12288

Figure 6. Typical I NL

SINAD (dB)

02642-0-006

–120

–140

0 200 400 600 800 1400

FREQUENCY (kHz)

1000 1200

Figure 4. 64k FFT Plot With 1 MHz Input Tone

1.0

0.8

0.6

0.4

0.2

DNL(LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 4096 8192 16384

ADC (Code)

12288

Figure 5. Typical D NL

02642-0-004

02642-0-005

10 10000100

INPUT FREQUENCY (kHz)

1000

Figure 7. SINAD vs. In put Tone (AD8021 Input Circuit)

–40

–50

–60

–70

THD (dB)

–80

–90

–100

100 1000

INPUT FREQUENCY (kHz)

100

200

Ω

Figure 8. THD vs. Input Tone for Different Input Resistances

10000

02642-0-007

02642-0-008

Rev. A | Page 10 of 20

AD7484

100mV p-p SINE WAVE ON SUPPLY PINS

–10

–20

–30

–40

PSRR (dB)

–50

–60

–70

–80

10 100

FREQUENCY (kHz)

Figure 9. PSRR Without Decoupling

1000

02642-A-008

0.0004

–0.0004

–0.0008

REFOUT (V)

–0.0012

–0.0016

–0.0020

–55 –25 5 35 95 125

TEMPERATURE (°C)



Figure 10. Reference Error

02642-0-008

Rev. A | Page 11 of 20

AD7484

Ω

SIGNAL

BIAS

VO LTAG E

100

Ω

Figure 11. Analog Input Circuit Used for 10 kHz Input Tone

SIGNAL

BIAS

OLTAGE

Figure 12. Analog Input Circuit Used for 1 MHz Input Tone

Figure 11 shows the analog input circuit used to obtain the data for the FFT plot shown in Figure 3. The circuit uses the Analog Devices AD829 op amp as the input buffer. A bipolar analog signal is applied as shown and biased up with a stable, low noise dc voltage connected to the labeled terminal shown. A 220 pF compensation capacitor is connected between Pin 5 of the AD829 and the analog ground plane. The AD829 is supplied with +12 V and −12 V supplies. The supply pins are decoupled as close to the device as possible, with both a 0.1 µF and 10 µF capacitor connected to each pin. In each case, the 0.1 µF capacitor should be the closer of the two caps to the device. More information on the AD829 is available at:

www.analog.com.

For higher input bandwidth applications, the Analog Devices AD8021 op amp (also available as a dual AD8022 op amp) is the recommended choice to drive the AD7484. Figure 12 shows the analog input circuit used to obtain the data for the FFT plot shown in Figure 4. A bipolar analog signal is applied to the terminal shown and biased up with a stable, low noise dc voltage connected as shown. A 10 pF compensation capacitor is connected between Pin 5 of the AD8021 and the negative supply. As with the previous circuit, the AD8021 is supplied with +12 V and −12 V supplies. The supply pins are decoupled as close to the device as possible, with both a 0.1 µF and 10 µF capacitor connected to each pin. In each case, the 0.1 µF capacitor should be the closer of the two caps to the device. The AD8021 logic reference pin is tied to analog ground, and the DISABLE

pin is tied to the positive supply as shown. Detailed

information on the AD8021 is available at: www.analog.com.

Ω

220

–V

220pF

10pF

Ω

10pF

–V

AD829

–

150

Ω

AD8021

Ω

–

02642-0-011

02642-0-012

CIRCUIT DESCRIPTION

Converter Operation

The AD7484 is a 14-bit algorithmic successive approximation analog-to-digital converter based around a capacitive DAC. It provides the user with track-and-hold, reference, an ADC, and versatile interface logic functions on a single chip. The normal analog input signal range that the AD7484 can convert is 0 V to

2.5 V. By using the offset and overrange features on the ADC, the AD7484 can convert analog input signals from −200 mV to +2.7 V while operating from a single 5 V supply. The part requires a 2.5 V reference, which can be provided from the part’s own internal reference or an external reference source. Figure 13 shows a simplified schematic of the ADC. The control logic, SAR, and capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back to a balanced condition.

COMPARATOR

CAPACITIVE

DAC

CONTROL

INPUTS

Figure 13. Simplified Block Diagram of AD7484

Conversion is initiated on the AD7484 by pulsing the input. On the falling edge of from track mode to hold mode and the conversion sequence is started. Conversion time for the part is 300 ns. Figure 14 shows the ADC during conversion. When conversion starts, SW2 will open and SW1 will move to Position B, causing the comparator to become unbalanced. The ADC then runs through its successive approximation routine and brings the comparator back into a balanced condition. When the comparator is rebalanced, the conversion result is available in the SAR Register.

SW1

GND

SWITCHES

REF

SAR

CONTROL

LOGIC

SW2

OUTPUT DATA

14-BIT PARALLEL

CONVST

–

COMPARATOR

, the track-and-hold goes

Figure 14. ADC Conversion Phase

02642-0-013

CONVST

CAPACITIVE

DAC

CONTROL LOGIC

02642-0-014

Rev. A | Page 12 of 20

AD7484

()(

)

()(

)

()(

)

()(

)

()(

)

At the end of conversion, the track-and-hold returns to track mode and the acquisition time begins. The track-and-hold acquisition time is 70 ns. Figure 15 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on V

SW1

AGND

SW2

Figure 15. ADC Acquisition Phase

–

COMPARATOR

CAPACITIVE

DAC

CONTROL LOGIC

ADC TRANSFER FUNCTION

The output coding of the AD7484 is straight binary. The designed code transitions occur midway between the successive integer LSB values , i.e., 1/2 LSB, 3/2 LSB. The LSB size is V

/16384. The nominal transfer characteristic for the AD7484

REF

is shown in Figure 16. This transfer characteristic may be shifted as detailed in the Offset/Overrange section.

02642-0-015

Therefore, the power dissipated during each cycle is

mWmWmW 694227

Figure 17 shows the AD7484 conversion sequence operating in normal mode.

CONVST

BUSY

300ns

Figure 17. Normal Mode Power Dissipation

In NAP mode, almost all of the internal circuitry is powered down. In this mode, the power dissipation of the AD7484 is reduced to 2.5 mW. When exiting NAP mode, a minimum of 300 ns when using an external reference must be waited before initiating a conversion. This is necessary to allow the internal circuitry to settle after power-up and for the track-and-hold to properly acquire the analog input signal. The internal reference cannot be used in conjunction with the NAP mode.

mWmAVμs/ns 421251700 =

1µs

700ns

02642-0-017

111...111

111...110

111...000

011...111

ADC CODE

000...010

000...001

000...000

0.5LSB

Figure 16. AD7484 Transfer Characteristic

1LSB =V

ANALOG INPUT

REF

/16384

REF

– 1.5LSB

02642-0-016

POWER SAVING

The AD7484 uses advanced design techniques to achieve very low power dissipation at high throughput rates. In addition to this, the AD7484 features two power saving modes, NAP and Standby. These modes are selected by bringing either the NAP or STBY pin to a logic high, respectively.

When operating the AD7484 in normal fully powered mode, the current consumption is 18 mA during conversion and the quiescent current is 12 mA. Operating at a throughput rate of 1 MSPS, the conversion time of 300 ns contributes 27 mW to the overall power dissipation.

mWmAVμsns 271851/300 =××

For the remaining 700 ns of the cycle, the AD7484 dissipates 42 mW of power.

If the AD7484 is put into NAP mode after each conversion, the average power dissipation will be reduced, but the throughput rate will be limited by the power-up time. Using the AD7484 with a throughput rate of 500 kSPS while placing the part in NAP mode after each conversion would result in average power dissipation as follows.

The power-up phase contributes

mWmAVμs/ns 91252300 =

The conversion phase contributes

mW.mAVμs/ns 5131852300 =

While in NAP mode for the rest of the cycle, the AD7484 dissipates only 1.75 mW of power.

mW.mA.Vμs/ns 75150521400 =×

Thus, the power dissipated during each cycle is

mW.mW.mW.mW 25247515139 =

Rev. A | Page 13 of 20

AD7484

(

)

−=−

(

)

−

Figure 18 shows the AD7484 conversion sequence if the part was put into NAP mode after each conversion.

600ns

NAP

300ns

CONVST

BUSY

Figure 18. NAP Mode Power Dissipation

Figure 19 and Figure 20 show a typical graphical representation of power versus throughput for the AD7484 when in normal and NAP modes, respectively.

2µs

1400ns

02642-0-018

conversion is initiated. Initiating a conversion before the required power-up time has elapsed will result in incorrect conversion data. If an external reference source is used and kept powered up while the AD7484 is in standby mode, the power-up time required will be reduced to 80 µs.

OFFSET/OVERRANGE

The AD7484 provides a ±8% overrange capability as well as a programmable offset register. The overrange capability is achieved by the use of a 15th bit (D14) and the CLIP input. If the CLIP input is at logic high and the contents of the offset register are 0, then the AD7484 operates as a normal 14-bit ADC. If the input voltage is greater than the full-scale voltage, the data output from the ADC are all 1s. Similarly, if the input voltage is lower than the zero-scale voltage, the data output from the ADC are all 0s. In this case, D14 acts as an overrange indicator. It is set to 1 if the analog input voltage is outside the nominal 0 V to 2.5 V range.

POWER (mW)

0 3000

500 1000 1500 2000 2500

THROUGHPUT (kSPS)

02642-0-019

Figure 19. Normal Mode, Power vs. Throughput

POWER (mW)

0 2000250

750 1250 1500 1750

500 1000

THROUGHPUT (kSPS)

02642-0-020

Figure 20. NAP Mode, Power vs. Throughput

In standby mode, all internal circuitry is powered down and the power consumption of the AD7484 is reduced to 10 µW. The power-up time necessary before a conversion can be initiated is longer because more of the internal circuitry has been powered down. In using the internal reference of the AD7484, the ADC must be brought out of standby mode 500 ms before a

The default contents of the offset register are 0. If the offset register contains any value other than 0, the contents of the register are added to the SAR result at the end of conversion. This has the effect of shifting the transfer function of the ADC as shown in Figure 21 and Figure 22. However, it should be noted that with the CLIP input set to logic high, the maximum and minimum codes that the AD7484 outputs are 0x3FFF and 0x0000, respectively. Further details are given in Table 5 and Table 6.

Figure 21 shows the effect of writing a positive value to the offset register. If, for example, the contents of the offset register contained the value 1024, then the value of the analog input voltage for which the ADC transitions from reading all 0s to 000…001 (the bottom reference point) is

mV.LSBLSB. 326156102450

The analog input voltage for which the ADC reads full-scale (0x3FFF) in this example is

V2.34352LSB1024LSB1.52.5V =

111...111

111...110

111...000

011...111

ADC CODE

000...010

000...001

000...000

0.5LSB –OFFSET

1LSB =V

REF

– 1.5LSB

REF

–OFFSET

ANALOG INPUT

/16384

02642-0-021

Figure 21. Transfer Characteristic with Positive Offset

Rev. A | Page 14 of 20

AD7484

(

)

(

)

The effect of writing a negative value to the offset register is shown in Figure 22 If a value of −512 was written to the offset register, the bottom end reference point now occurs at

mW.LSBLSB. 207851250 =−−

Following this, the analog input voltage needed to produce a full-scale (0x3FFF) result from the ADC is now

V.LSBLSB.V. 577925125152 =−−−

111...111

111...110

1LSB =V

–OFFSET

111...000

011...111

ADC CODE

000...010

000...001

000...000

Figure 22. Transfer Characteristic with Negative Offset

REF

0.5LSB ANALOG INPUT

/16384

REF

–OFFSET

– 1.5LSB

02642-0-022

Table 5 shows the expected ADC result for a given analog input voltage with different offset values and with CLIP tied to logic high. The combined advantages of the offset and overrange features of the AD7484 are shown clearly in Table 6. It shows the same range of analog input and offset values, as shown in Table 5 but with the clipping feature disabled.

Table 5. Clipping Enabled (CLIP = 1)

−512 0 +1024 Offset VIN ADC DATA, D[0:13] D14

−200 mV 0 0 0 1 1 1

−156.3 mV 0 0 0 1 1 0 0 V 0 0 1024 1 0 0 +78.2 mV 0 512 1536 0 0 0 +2.3435 V 14846 15358 16383 0 0 0 +2.5 V 15871 16383 16383 0 0 1 +2.5779 V 16383 16383 16383 0 1 1 +2.7 V 16383 16383 16383 1 1 1

Table 6. Clipping Disabled (CLIP = 0)

−512 0 +1024 Offset VIN ADC DATA, D[0:13]

−200 mV −1823 −1311 −287

−156.3 mV −1536 −1024 0 0 V −512 0 1024 +78.2 mV 0 512 1536 +2.3435 V 14846 15358 16382 +2.5 V 15872 16384 17408 +2.5779 V 16383 16895 17919 +2.7 V 17183 17695 18719

Values from −1310 to +1310 may be written to the offset register. These values correspond to an offset of ±200 mV. A write to the offset register is performed by writing a 13-bit word to the part, as detailed in the Parallel Interface section. The 12 LSBs of the 15-bit word contain the offset value, while the 3 MSBs must be set to 0. Failure to write 0s to the 3 MSBs may result in incorrect operation of the device.

PARALLEL INTERFACE

The AD7484 features two parallel interfacing modes. These modes are selected by the mode pins (see Table 7).

Table 7. Table III. Operating Modes

MODE2 MODE1

Do Not Use 0 0 Parallel Mode 1 0 1 Parallel Mode 2 1 0 Do Not Use 1 1

In Parallel Mode 1, the data in the output register is updated on the rising edge of available for reading almost immediately afterwards. Using this mode, throughput rates of up to 2.5 MSPS can be achieved. This mode should be used if the conversion data is required immediately after the conversion has completed. An example where this may be of use is if the AD7484 is operating at much lower throughput rates with the NAP mode (for power-saving reasons), and the input signal is being compared with set limits within the DSP or other controller. If the limits are exceeded, the ADC is brought immediately into full power operation and commences sampling at full speed. Figure 31 shows a timing diagram for the AD7484 operating in Parallel Mode 1 with both CS

and RD tied low.

In Parallel Mode 2, the data in the output register is not updated until the next falling edge of used where a single sample delay is not vital to the system operation and conversion speeds of greater than 2.5 MSPS are desired. This may occur, for example, in a system where a large amount of samples are taken at high speed before a Fast Fourier Transform is performed for frequency analysis of the input signal. Figure 32 shows a timing diagram for the AD7484 operating in Parallel Mode 2 with both

Data must not be read from the AD7484 while a conversion is taking place. For this reason, if operating the AD7484 at throughput speeds greater than 2.5 MSPS, it will be necessary to tie both the buffer on the data lines. This situation may also arise in the case where a read operation cannot be completed in the time after the end of one conversion and the start of the quiet period before the next conversion.

BUSY

at the end of a conversion and is

CONVST

and RD pins on the AD7484 low and use a

. This mode could be

and RD tied low.

Rev. A | Page 15 of 20

AD7484

The maximum slew rate at the input of the ADC should be limited to 500 V/µS while ongoing conversion. In any multiplexed application where the channel is switched during conversion, this should happen as early as possible after the

Reading Data from the AD7484

Data is read from the part via a 15-bit parallel data bus with the standard

and RD signals. The CS and RD signals are internally gated to enable the conversion result onto the data bus. The data lines D0 to D14 leave their high impedance state when both

may be permanently tied logic low if required, and the signal used to access the conversion result. Figure 29 shows a timing specification called t that should be left after any data bus activity before the next conversion is initiated.

Writing to the AD7484

The AD7484 features a user-accessible offset register. This allows the bottom of the transfer function to be shifted by ±200 mV. This feature is explained in more detail in the Offset/Overrange section.

To write to the offset register, a 15-bit word is written to the AD7484 with the 12 LSBs containing the offset value in twos complement format. The 3 MSBs must be set to 0. The offset value must be within the range −1310 to +1310, corresponding to an offset from −200 mV to +200 mV. The value written to the offset register is stored and used until power is removed from the device, or the device is reset. The value stored may be updated at any time between conversions by another write to the device. Table 8 shows some examples of offset register values and their effective offset voltage. Figure 30 shows a timing diagram for writing to the AD7484.

Table 8. Offset Register Examples

Code (Dec)

D14 to D12

−1310 000 1010 1110 0010 −200

−512 000 1110 0000 0000 −78.12 +256 000 0001 0000 0000 +39.06 +1310 000 0101 0001 1110 +200

Driving the

CONVST

To achieve the specified performance from the AD7484, the CONVST

pin must be driven from a low-jitter source. Since the falling edge on the instant, any jitter that may exist on this edge will appear as noise

when the analog input signal contains high frequency components. The relationship between the analog input frequency (f

), timing jitter (tj), and resulting SNR is given by

the equation

BUSY

is low to avoid corrupting the

BUSY

falling edge.

and RD are logic low. Therefore, CS

. This is the amount of time

QUIET

D11 to D0 (Twos Complement)

Offset (mV)

CONVST

pin determines the sampling

JITTER

()

dBSNR

log10

()

tfπ

××

jIN

As an example, if the desired SNR due to jitter was 100 dB with a maximum full-scale analog input frequency of

1.5 MHz, ignoring all other noise sources, the result is an allowable jitter on the

CONVST

falling edge of 1.06 ps. For a 14-bit converter (ideal SNR = 86.04 dB), the allowable jitter will be greater than the figure given above, but due consideration must be given to the design of the

CONVST

circuitry to achieve

14-bit performance with large analog input frequencies.

Typical Connection

Figure 23 shows a typical connection diagram for the AD7484 operating in Parallel Mode 1. Conversion is initiated by a falling edge on

CONVST

. Once

CONVST

goes low, the goes low, and at the end of conversion, the rising edge of is used to activate an interrupt service routine. The

BUSY

signal

BUSY

and RD lines are then activated to read the 14 data bits (15 bits if using the overrange feature).

In Figure 23, the V logic output levels being either 0 V or DV to V

controls the voltage value of the output logic signals.

DRIVE

For example, if DV

pin is tied to DVDD, which results i n

DRIVE

. The voltage applied

is supplied by a 5 V supply and V

DRIVE

by a 3 V supply, the logic output levels would be either 0 V or 3 V. This feature allows the AD7484 to interface to 3 V devices while still enabling the ADC to process signals at a 5 V supply.

DIGITAL SUPPLY

.75V TO 5.25V

ADM809

µC/µP

10µµF 1nF+0.1µF 0.1µF

0.1µF

PARALLEL INTERFACE

Figure 23. Typical Connection Diagram

DRIVEDVDDAVDD

RESET MODE1 MODE2 WRITE CLIP NAP STBY

D0 TO D13

CS CONVST RD BUSY

REFSEL

AD7484

REFOUT

BIAS

REFIN

VIN

1nF

0.47µF

0V TO 2.5V

ANALOG

SUPPLY

4.75V TO 5.25V

AD780 2.5V

REFERENCE

02642-0-023

Rev. A | Page 16 of 20

AD7484

Board Layout and Grounding

To obtain optimum performance from the AD7484, it is recommended that a printed circuit board with a minimum of three layers be used. One of these layers, preferably the middle layer, should be as complete a ground plane as possible to give the best shielding. The board should be designed in such a way that the analog and digital circuitry is separated and confined to certain areas of the board. This practice, along with avoiding running digital and analog lines close together, should help to avoid coupling digital noise onto analog lines.

The power supply lines to the AD7484 should be approximately 3 mm wide to provide low impedance paths and reduce the effects of glitches on the power supply lines. It is vital that good decoupling is also present. A combination of ferrites and decoupling capacitors should be used, as shown in Figure 23.

The decoupling capacitors should be as close to the supply pins as possible. This is made easier by the use of multilayer boards.

The signal traces from the AD7484 pins can be run on the top layer, while the decoupling capacitors and ferrites can be mounted on the bottom layer where the power traces exist. The ground plane between the top and bottom planes provide excellent shielding.

Figure 24 to Figure 28 show a sample layout of the board area immediately surrounding the AD7484. Pin 1 is the bottom left corner of the device. Figure 24 shows the top layer where the AD7484 is mounted with vias to the bottom routing layer highlighted. Figure 27 shows the bottom layer where the power routing is with the same vias highlighted. Figure 25 shows the bottom layer silkscreen where the decoupling components are soldered directly beneath the device. Figure 28 shows the silkscreen overlaid on the solder pads for the decoupling components, and Figure 26 shows the top and bottom routing layers overlaid. The black area in each figure indicates the ground plane present on the middle layer.

Figure 24.

Figure 25.

02642-0-024

02642-0-026

Figure 27.

Figure 28.

02642-0-025

02642-0-027

C1 to C6: 100 nF, C7 to C8: 470 nF, C9: 1 nF

L1 to L4: Meggit-Sigma Chip Ferrite Beads (BMB2A0600RS2)

02642-0-028

Figure 26.

Rev. A | Page 17 of 20

AD7484

CONVST

BUSY

D[14:0]

CONV

DATA VALID

ACQ

QUIET

02642-0-029

Figure 29. Parallel Mode READ Cycle

CONVST

WRITE

t10t

D[14:0]

OFFSET DATA

02642-0-030

Figure 30. Parallel Mode WRITE Cycle

Rev. A | Page 18 of 20

AD7484

CONVST

BUSY

D[14:0]

CONVST

BUSY

D[14:0]

N N+1

CONV

DATA N–1 DATA N

Figure 31. Parallel Mode 1 READ Cycle

CONV

DATA N–1 DATA N

Figure 32. Parallel Mode 2 READ Cycle

N+1N

02642-0-031

02642-0-032

Rev. A | Page 19 of 20

AD7484

OUTLINE DIMENSIONS

1.45

1.40

1.35

0.15

0.05

ROTATED 90°CCW

10°

SEATING PLANE

VIEW A

0.75

0.60

0.45

SEATING

PLANE

6°

0.20

2°

0.09 7°

3.5 0°

0.08 MAX COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026BBC

1.60 MAX

VIEW A

Figure 33. 48-Lead Plastic Quad Flatpack (LQFP)

[ST-48]

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Option

AD7484BST −40°C to +85°C Plastic Quad Flatpack Package (LQFP) ST-48 EVAL-AD7484CB1 Evaluation Board EVAL-CONTROL BRD22 Controller Board

0.50 BSC

9.00 BSC SQ

PIN 1

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

7.00

BSC SQ

This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.

This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

C02642-0-2/04(A)

Rev. A | Page 20 of 20

Datasheet AD7484 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

SPECIFICATIONS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

CIRCUIT DESCRIPTION

Converter Operation

ADC TRANSFER FUNCTION

POWER SAVING

OFFSET/OVERRANGE

PARALLEL INTERFACE

Reading Data from the AD7484

Writing to the AD7484

Typical Connection

Board Layout and Grounding

OUTLINE DIMENSIONS

ORDERING GUIDE