Page 1
1 MSPS, 12-/10-/8-Bit ADCs
a
FEATURES
Fast Throughput Rate: 1 MSPS
Specified for V
Low Power:
3.6 mW Typ at 1 MSPS with 3 V Supplies
15 mW Typ at 1 MSPS with 5 V Supplies
Wide Input Bandwidth:
70 dB SNR at 100 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High-Speed Serial Interface
SPI™/QSPI™/MICROWIRE™/DSP Compatible
Standby Mode: 1 A Max
6-Lead SOT-23 Package
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High-Speed Modems
Optical Sensors
GENERAL DESCRIPTION
The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit,
and 8-bit, high-speed, low-power, successive-approximation
ADCs. The parts operate from a single 2.35 V to 5.25 V power
supply and feature throughput rates up to 1 MSPS. The parts
contain a low-noise, wide bandwidth track/hold amplifier that can
handle input frequencies in excess of 1 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is also initiated at this
point. There are no pipelined delays associated with the part.
The AD7476/AD7477/AD7478 use advanced design techniques
to achieve very low-power dissipation at high throughput rates.
The reference for the part is taken internally from V
allows the widest dynamic input range to the ADC. Thus the
analog input range for the part is 0 to V
is determined by the SCLK.
of 2.35 V to 5.25 V
DD
This
DD.
. The conversion rate
DD
in 6-Lead SOT-23
AD7476/AD7477/AD7478
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
PRODUCT HIGHLIGHTS
T/H
IN
AD7476/AD7477/AD7478
1. First 12-/10-/8-bit ADCs in an SOT-23 package.
2. High Throughput with Low Power Consumption.
3. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock speed
increase. This allows the average power consumption to be
reduced while not converting. The part also features a shutdown mode to maximize power efficiency at lower throughput
rates. Power consumption is 1 µA max when in shutdown.
4. Reference derived from the power supply.
5. No Pipeline Delay.
The parts feature a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once-off conversion control.
8-/10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
GND
SCLK
SDATA
CS
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
Page 2
AD7476/AD7477/AD7478
1
AD7476–SPECIFICATIONS
S and B Versions: VDD = 2.35 V to 5.25 V, f
Parameter A Version
DYNAMIC PERFORMANCE f
Signal-to-Noise + Distortion (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)3–82 –80 –80 dB typ
Intermodulation Distortion (IMD)
3
3
= 12 MHz, f
SCLK
3
69 70 69 dB min
70 70 dB min TA = 25°C
70 71 70 dB min
3
–80 –78 –78 dB typ
(A Version: VDD = 2.7 V to 5.25 V, f
= 600 kSPS unless otherwise noted; TA = T
SAMPLE
1, 2
B Version
1, 2
S Version
1, 2
Second Order Terms –78 –78 –78 dB typ fa = 103.5 kHz, fb = 113.5 kHz
Third Order Terms –78 –78 –78 dB typ fa = 103.5 kHz, fb = 113.5 kHz
Aperture Delay 10 10 10 ns max
Aperture Jitter 30 30 30 ps typ
Full Power Bandwidth 6.5 6.5 6.5 MHz typ @ 3 dB
DC ACCURACY S, B Versions, VDD = (2.35 V to 3.6 V)4;
Resolution 12 12 12 Bits
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
3
3
3
3
± 1 ± 0.6 ± 0.6 LSB typ
± 0.75 ± 0.75 ± 0.75 LSB typ
± 1.5 ± 1.5 LSB max
–0.9/+1.5 –0.9/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits
± 1.5 ± 2 LSB max
± 0.5 LSB typ
± 1.5 ± 2 LSB max
± 0.5 LSB typ
ANALOG INPUT
Input Voltage Ranges 0 to V
DD
0 to V
DD
0 to V
DD
DC Leakage Current ± 1 ± 1 ± 1 µA max
Input Capacitance 30 30 30 pF typ
LOGIC INPUTS
Input High Voltage, V
INH
2.4 2.4 2.4 V min
1.8 1.8 1.8 V min VDD = 2.35 V
Input Low Voltage, V
INL
0.4 0.4 0.4 V max VDD = 3 V
0.8 0.8 0.8 V max VDD = 5 V
Input Current, IIN, SCLK Pin ± 1 ± 1 ± 1 µA max Typically 10 nA, V
Input Current, IIN, CS Pin ± 1 ± 1 ± 1 µA typ
Input Capacitance, C
3, 5
IN
10 10 10 pF max
LOGIC OUTPUTS
Output High Voltage, V
Output Low Voltage, V
OH
OL
Floating-State Leakage Current ±10 ± 10 ±10 µA max
Floating-State Output Capacitance
3, 5
VDD – 0.2 VDD – 0.2 VDD – 0.2 V min I
0.4 0.4 0.4 V max I
10 10 10 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 0.8 1.33 1.33 µs max Sixteen SCLK Cycles
Track/Hold Acquisition Time 500 500 500 ns max Full-Scale Step Input
350 400 400 ns max Sine Wave Input ≤100 kHz
Throughput Rate 1000 600 600 kSPS max See Serial Interface Section
POWER REQUIREMENTS
V
DD
I
DD
2.35/5.25 2.35/5.25 2.35/5.25 V min/max
Normal Mode (Static) 2 2 2 mA typ VDD = 4.75 V to 5.25 V. SCLK On or Off
1 1 1 mA typ VDD = 2.35 V to 3.6 V. SCLK On or Off
Normal Mode (Operational) 3.5 3 3 mA max VDD = 4.75 V to 5.25 V. f
1.6 1.4 1.4 mA max VDD = 2.35 V to 3.6 V. f
Full Power-Down Mode 1 1 1 µA max SCLK Off
Power Dissipation
7
80 80 80 µA max SCLK On
Normal Mode (Operational) 17.5 15 15 mW max VDD = 5 V. f
4.8 4.2 4.2 mW max VDD = 3 V. f
Full Power-Down 5 5 5 µW max VDD = 5 V. SCLK Off
333µW max VDD = 3 V. SCLK Off
NOTES
1
Temperature ranges as follows: A, B Versions: –40°C to +85°C, S Version: –55°C to +125°C.
2
Operational from VDD = 2.0 V.
3
See Terminology.
4
Maximum B, S Versions specs apply as typical figures when VDD = 5.25 V.
5
Sample tested at 25°C to ensure compliance.
6
A Version: f
7
See Power Versus Throughput Rate section.
Specifications subject to change without notice.
–2–
= 20 MHz, f
SCLK
MIN
= 1 MSPS unless otherwise noted;
SAMPLE
to T
, unless otherwise noted.)
MAX
Unit Test Conditions/Comments
= 100 kHz Sine Wave
IN
A Version, VDD = (2.7 V to 3.6 V)
V
= 0 V or V
IN
= 200 µA; VDD = 2.35 V to 5.25 V
SOURCE
= 200 µA
SINK
Digital I/Ps = 0 V or V
MAX = 1 MSPS; B, S Versions: f
SAMPLE
SAMPLE
SAMPLE
DD
SAMPLE
SAMPLE
= f
SAMPLE
= f
SAMPLE
MAX = 600 kSPS.
SAMPLE
DD
= f
= f
MAX
MAX
SAMPLE
SAMPLE
6
6
MAX
6
MAX
REV. A
6
Page 3
AD7476/AD7477/AD7478
1
AD7477–SPECIFICATIONS
Parameter A Version
(VDD = 2.7 V to 5.25 V, f
1, 2
S Version
DYNAMIC PERFORMANCE f
Signal-to-Noise + Distortion (SINAD) 61 61 dB min
Total Harmonic Distortion (THD) –73 –73 dB max
Peak Harmonic or Spurious Noise (SFDR) –74 –74 dB max
Intermodulation Distortion (IMD)
Second Order Terms –78 –78 dB typ fa = 103.5 kHz, fb = 113.5 kHz
Third Order Terms –78 –78 dB typ fa = 103.5 kHz, fb = 113.5 kHz
Aperture Delay 10 10 ns max
Aperture Jitter 30 30 ps typ
Full Power Bandwidth 6.5 6.5 MHz typ @ 3 dB
DC ACCURACY
Resolution 10 10 Bits
Integral Nonlinearity ± 1 ±1 LSB max
Differential Nonlinearity ± 0.9 ±0.9 LSB max Guaranteed No Missed Codes to 10 Bits
Offset Error ± 1 ±1 LSB max
Gain Error ± 1 ±1 LSB max
ANALOG INPUT
Input Voltage Ranges 0 to V
DD
0 to V
DC Leakage Current ± 1 ±1 µA max
Input Capacitance 30 30 pF typ
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
INH
INL
2.4 2.4 V min
0.8 0.8 V max VDD = 5 V
0.4 0.4 V max V
Input Current, I
Input Current, IIN, CS Pin ± 1 ±1 µA typ
Input Capacitance, C
, SCLK Pin ± 1 ±1 µA max Typically 10 nA, V
IN
3, 4
IN
10 10 pF max
LOGIC OUTPUTS
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±10 ± 10 µA max
Floating-State Output Capacitance
OH
OL
3, 4
VDD – 0.2 VDD – 0.2 V min I
0.4 0.4 V max I
10 10 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 800 800 ns max 16 SCLK Cycles with SCLK at 20 MHz
Track/Hold Acquisition Time 400 400 ns max
Throughput Rate 1 1 MSPS max See Serial Interface Section
POWER REQUIREMENTS
V
DD
I
DD
2.7/5.25 2.7/5.25 V min/max
Normal Mode (Static) 2 2 mA typ VDD = 4.75 V to 5.25 V. SCLK On or Off
1 1 mA typ V
Normal Mode (Operational) 3.5 3.5 mA max V
1.6 1.6 mA max V
Full Power-Down Mode 1 1 µA max SCLK Off
80 80 µA max SCLK On
Power Dissipation
5
Normal Mode (Operational) 17.5 17.5 mW max VDD = 5 V. f
4.8 4.8 mW max V
Full Power-Down 5 5 µW max VDD = 5 V. SCLK Off
NOTES
1
Temperature ranges as follows: A Version: –40°C to +85°C,
2
Operational from VDD = 2.0 V, with input high voltage, V
3
See Terminology.
4
Sample tested at 25°C to ensure compliance.
5
See Power Versus Throughput Rate section.
Specifications subject to change without notice.
S Version: –55°C to +125°C.
= 1.8 V min.
INH
SCLK
1, 2
DD
= 20 MHz, TA = T
MIN
to T
, unless otherwise noted.)
MAX
Unit Test Conditions/Comments
= 100 kHz Sine Wave, f
IN
V
= 3 V
DD
= 200 µA; VDD = 2.7 V to 5.25 V
SOURCE
= 200 µA
SINK
Digital I/Ps = 0 V or V
= 2.7 V to 3.6 V. SCLK On or Off
DD
= 4.75 V to 5.25 V. f
DD
= 2.7 V to 3.6 V. f
DD
SAMPLE
= 3 V. f
DD
SAMPLE
= 0 V or V
IN
DD
= 1 MSPS
= 1 MSPS
SAMPLE
SAMPLE
SAMPLE
= 1 MSPS
DD
= 1 MSPS
= 1 MSPS
REV. A
–3–
Page 4
AD7476/AD7477/AD7478
AD7478–SPECIFICATIONS
Parameter A Version
DYNAMIC PERFORMANCE f
Signal-to-Noise + Distortion (SINAD) 49 dB min
Total Harmonic Distortion (THD) –65 dB max
Peak Harmonic or Spurious Noise (SFDR) –65 dB max
Intermodulation Distortion (IMD)
Second Order Terms –68 dB typ fa = 498.7 kHz, fb = 508.7 kHz
Third Order Terms –68 dB typ fa = 498.7 kHz, fb = 508.7 kHz
Aperture Delay 10 ns max
Aperture Jitter 30 ps typ
Full Power Bandwidth 6.5 MHz typ @ 3 dB
DC ACCURACY
Resolution 8 Bits
Integral Nonlinearity ±0.5 LSB max
Differential Nonlinearity ± 0.5 LSB max Guaranteed No Missed Codes to 8 Bits
Offset Error ± 0.5 LSB max
Gain Error ± 0.5 LSB max
Total Unadjusted Error (TUE) ±0.5 LSB max
ANALOG INPUT
Input Voltage Ranges 0 to V
DC Leakage Current ± 1 µA max
Input Capacitance 30 pF typ
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current, IIN, CS Pin ± 1 µA typ
Input Capacitance, C
LOGIC OUTPUTS
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ± 10 µA max
Floating-State Output Capacitance
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 800 ns max 16 SCLK Cycles with SCLK at 20 MHz
Track/Hold Acquisition Time 400 ns max
Throughput Rate 1 MSPS max Conversion Time + Quiet Time
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Static) 2 mA typ VDD = 4.75 V to 5.25 V. SCLK On or Off
Normal Mode (Operational) 3.5 mA max V
Full Power-Down Mode 1 µA max SCLK Off
Power Dissipation
Normal Mode (Operational) 17.5 mW max VDD = 5 V. f
Full Power-Down 5 µW max VDD = 5 V. SCLK Off
NOTES
1
Temperature ranges as follows: A Version: –40°C to +85°C.
2
Operational from VDD = 2.0 V, with input high voltage, V
3
See Terminology.
4
Sample tested at 25°C to ensure compliance.
5
See Power Versus Throughput Rate section.
Specifications subject to change without notice.
INH
INL
, SCLK Pin ± 1 µA max Typically 10 nA, V
IN
3, 4
IN
OH
OL
3, 4
5
INH
1
(VDD = 2.7 V to 5.25 V, f
1, 2
DD
Unit Test Conditions/Comments
V
2.4 V min
0.8 V max VDD = 5 V
0.4 V max V
10 pF max
VDD – 0.2 V min I
0.4 V max I
10 pF max
2.7/5.25 V min/max
1 mA typ V
1.6 mA max V
80 µA max SCLK On
4.8 mW max V
= 1.8 V min.
–4–
= 20 MHz, TA = T
SCLK
IN
SOURCE
SINK
Digital I/Ps = 0 V or V
to T
MIN
= 100 kHz Sine Wave, f
= 3 V
DD
, unless otherwise noted.)
MAX
SAMPLE
= 0 V or V
IN
= 1 MSPS
DD
= 200 µA; VDD = 2.7 V to 5.25 V
= 200 µA
DD
= 2.7 V to 3.6 V. SCLK On or Off
DD
= 4.75 V to 5.25 V. f
DD
= 2.7 V to 3.6 V. f
DD
= 1 MSPS
= 3 V. f
DD
SAMPLE
SAMPLE
= 1 MSPS
SAMPLE
SAMPLE
= 1 MSPS
= 1 MSPS
REV. A
Page 5
AD7476/AD7477/AD7478
WARNING!
ESD SENSITIVE DEVICE
1, 2
TIMING SPECIFICATIONS
Limit at T
AD7476/AD7477/AD7478
Parameter 3 V
4
f
SCLK
10 10 kHz min
3
MIN
(VDD = 2.35 V to 5.25 V; TA = T
, T
MAX
3
5V
Unit Description
20 20 MHz max A Version
12 12 MHz max B Version
t
CONVERT
t
QUIET
t
1
t
2
5
t
3
5
t
4
16 × t
SCLK
16 × t
SCLK
50 50 ns min Minimum Quiet Time Required Between Bus Relinquish and
10 10 ns min Minimum CS Pulsewidth
10 10 ns min CS to SCLK Setup Time
20 20 ns max Delay from CS Until SDATA Three-State Disabled
40 20 ns max Data Access Time After SCLK Falling Edge. A Version
70 20 ns max Data Access Time After SCLK Falling Edge. B Version
t
5
t
6
t
7
6
t
8
t
POWER-UP
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2
A Version timing specifications apply to the AD7477 S Version; B Version timing specifications apply to the AD7476 S Version.
3
3 V specifications apply from VDD = 2.7 V to 3.6 V for A Version; 3 V specifications apply from VDD = 2.35 V to 3.6 V for B Version; 5 V specifications apply from
VDD = 4.75 V to 5.25 V.
4
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
5
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
6
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
7
See Power-up Time section.
Specifications subject to change without notice.
0.4 t
0.4 t
SCLK
SCLK
0.4 t
0.4 t
SCLK
SCLK
ns min SCLK Low Pulsewidth
ns min SCLK High Pulsewidth
10 10 ns min SCLK to Data Valid Hold Time
10 10 ns min SCLK Falling Edge to SDATA High Impedance
25 25 ns max SCLK Falling Edge to SDATA High Impedance
7
11µs typ Power-Up Time from Full Power-Down
to T
MIN
, unless otherwise noted.)
MAX
Start of Next Conversion
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
1
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . . . –0.3 V to V
+ 0.3 V
DD
Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V
Digital Output Voltage to GND . . . . . –0.3 V to V
Input Current to Any Pin Except Supplies
2
. . . . . . . ± 10 mA
+ 0.3 V
DD
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . . . . . –40°C to +85°C
200A
Military (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
SOT-23 Package, Power Dissipation . . . . . . . . . . . . . 450 mW
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 230°C/W
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 92°C/W
θ
JC
TO OUTPUT
PIN
50pF
C
L
200A
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Figure 1. Load Circuit for Digital Output Timing
Specifications
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kV
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7476/AD7477/AD7478 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
I
OL
1.6V
I
OH
REV. A
–5–
Page 6
AD7476/AD7477/AD7478
PIN CONFIGURATION
V
1
DD
AD7476/
2
GND
V
IN
AD7477/
3
AD7478
TOP VIEW
(Not to Scale)
PIN FUNCTION DESCRIPTIONS
Pin Pin
No. Mnemonic Function
1V
DD
Power Supply Input. The VDD range for the AD7476/AD7477/AD7478 is from 2.35 V to 5.25 V.
2 GND Analog Ground. Ground reference point for all circuitry on the AD7476/AD7477/AD7478. All analog
input signals should be referred to this GND voltage.
3V
IN
Analog Input. Single-ended analog input channel. The input range is 0 to VDD.
4 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock
input is also used as the clock source for the AD7476/AD7477/AD7478’s conversion process.
5 SDATA Data Out. Logic output. The conversion result from the AD7476/AD7477/AD7478 is provided on
this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The
data stream from the AD7476 consists of four leading zeros followed by the 12 bits of conversion data
which is provided MSB first; the data stream from the AD7477 consists of four leading zeros followed
by the 10 bits of conversion data, followed by two trailing zeros, which is also provided MSB first; the
data stream from the AD7478 consists of four leading zeros followed by the 8 bits of conversion data,
followed by four trailing zeros, which is provided MSB first.
6 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7476/AD7477/AD7478 and framing the serial data transfer.
6
5
4
CS
SDATA
SCLK
ORDERING GUIDE
Temperature Linearity Package Branding
Model Range Error (LSB)
1
Option
2
Information
AD7476ART –40°C to +85°C ± 1 typ RT-6 CEA
AD7476BRT –40°C to +85°C ± 1.5 max RT-6 CEB
AD7476SRT –55°C to +125°C ± 1.5 max RT-6 CES
AD7477ART –40°C to +85°C ± 1 max RT-6 CFA
AD7477SRT –55°C to +125°C ± 1 max RT-6 CFS
AD7478ART –40°C to +85°C ± 0.5 max RT-6 CJA
EVAL-AD7476CB
EVAL-AD7477CB
EVAL-CONTROL BOARD
NOTES
1
Linearity Error here refers to integral linearity error.
2
RT = SOT-23.
3
This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.
4
This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
3
3
4
–6–
REV. A
Page 7
AD7476/AD7477/AD7478
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. For the AD7476/
AD7477, the endpoints of the transfer function are zero scale, a
point 1/2 LSB below the first code transition, and full scale, a
point 1/2 LSB above the last code transition. For the AD7478,
the endpoints of the transfer function are zero scale, a point
1 LSB below the first code transition, and full scale, a point
1 LSB above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000)
to (00 . . . 001) from the ideal (i.e., AGND + 0.5 LSB). For
the AD7478, this is the deviation of the first code transition
(00 . . . 000) to (00 . . . 001) from the ideal (i.e., AGND +
1 LSB).
Gain Error
For the AD7476/AD7477, this is the deviation of the last code
transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e.,
– 1.5 LSB) after the offset error has been adjusted out.
V
REF
For the AD7478, this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., V
REF
– 1 LSB) after the offset error has been adjusted.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode after the end
of conversion. Track/Hold acquisition time is the time required
for the output of the track/hold amplifier to reach its final value,
within ± 0.5 LSB, after the end of conversion. See Serial Interface Timing section for more detail.
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at
the output of the A/D converter. The signal is the rms amplitude
of the fundamental. Noise is the sum of all nonfundamental
signals up to half the sampling frequency (f
/2), excluding dc.
S
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB and for a 10-bit converter it is 62 dB, for an 8-bit converter it is 50 dB.
Total Unadjusted Error
This is a comprehensive specification which includes gain error,
linearity error, and offset error.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7476/AD7477/
AD7478 it is defined as:
232425262
VVVVV
()
++++
THD dB
( ) log
=
20
2
V
1
where V1 is the rms amplitude of the fundamental and V2, V3,
, V5, and V6 are the rms amplitudes of the second through the
V
4
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
/2 and excluding dc) to the rms value of the
S
fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n is equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
The AD7476/AD7477/AD7478 are tested using the CCIF standard
where two input frequencies are used, fa = 498.7 kHz and
fb = 508.7 kHz. In this case, the second order terms are usually
distanced in frequency from the original sine waves while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second and third order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
REV. A
–7–
Page 8
AD7476/AD7477/AD7478
PERFORMANCE CURVES
Figure 2 shows a typical FFT plot for the AD7476 at 1 MHz
sample rate and 100 kHz input frequency.
0
8192 POINT FFT
= 1MSPS
–15
–35
–55
SNR – dB
–75
–95
–115
0
50 100 150 200 250 300 350 400 450 500
FREQUENCY – kHz
f
SAMPLE
= 100kHz
f
IN
SINAD = 71.67dB
THD = –81.00dB
SFDR = –81.63dB
Figure 2. AD7476 Dynamic Performance at 1 MSPS
Figure 3 shows a typical FFT plot for the AD7476 at 600 kHz
sample rate and 100 kHz input frequency.
–15
8192 POINT FFT
= 600kSPS
–15
–35
–55
SNR – dB
–75
–95
–115
50 100 150 200 250 300
0
FREQUENCY – kHz
f
SAMPLE
= 100kHz
f
IN
SINAD = 71.71dB
THD = –80.88dB
SFDR = –83.23dB
Figure 3. AD7476 Dynamic Performance at 600 kSPS
Figure 4 shows a typical FFT plot for the AD7477 at 1 MHz
sample rate and 100 kHz input frequency.
–10
–20
–30
–40
–50
SNR – dB
–60
–70
–80
–90
–100
0
0
50 100 150 200 250 300 350 400 450 500
FREQUENCY – kHz
8192 POINT FFT
f
= 1MSPS
SAMPLE
= 100kHz
f
IN
SINAD = 61.66dB
THD = –80.64dB
SFDR = –85.75dB
Figure 4. AD7477 Dynamic Performance at 1 MSPS
Figure 5 shows a typical FFT plot for the AD7478 at 1 MHz
sample rate and 100 kHz input frequency.
SNR – dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
50
150 200 250 300 350 400 450 500100
FREQUENCY – kHz
8192 POINT FFT
FSAMPLE = 1MSPS
FIN = 100kHz
SINAD = 49.82dB
THD = –75.22dB
SFDR = –67.78dB
Figure 5. AD7478 Dynamic Performance at 1 MSPS
Figure 6 shows the signal-to-(noise + distortion) ratio performance
versus input frequency for various supply voltages while sampling
at 993 kSPS with an SCLK frequency of 20 MHz.
–66
VDD = 2.35V
VDD = 2.7V
VDD = 4.75V
VDD = 3.6V
SINAD – dB
–67
–68
–69
–70
–71
–72
–73
10k
VDD = 5.25V
INPUT FREQUENCY – Hz
100k 1M
Figure 6. AD7476 SINAD vs. Input Frequency at 993 kSPS
Figure 7 shows the signal-to-(noise + distortion) ratio performance
versus input frequency for various supply voltages while sampling
at 605 kSPS with a SCLK frequency of 12 MHz.
–69.0
SINAD – dB
–69.5
–70.0
–70.5
–71.0
–71.5
–72.0
–72.5
10k
100k 1M
INPUT FREQUENCY – Hz
VDD = 2.35V
VDD = 2.7V
VDD = 5.25V
VDD = 4.75V
VDD = 3.6V
Figure 7. AD7476 SINAD vs. Input Frequency at 605 kSPS
–8–
REV. A
Page 9
AD7476/AD7477/AD7478
1LSB = VDD/4096 (AD7476)
1LSB = V
DD
/1024 (AD7477)
ANALOG INPUT
111 ... 111
0V
0.5LSB
ADC CODE
ⴙVDD–1.5LSB
111 ... 110
111 ... 000
011 ... 111
000 ... 010
000 ... 001
000 ... 000
ANALOG INPUT
111 ... 111
0V
1LSB
ADC CODE
ⴙVDD–1LSB
111 ... 110
111 ... 000
011 ... 111
000 ... 010
000 ... 001
000 ... 000
1LSB = VDD/256 (AD7478)
CIRCUIT INFORMATION
The AD7476/AD7477/AD7478 are, respectively, fast, micropower, 12-bit, 10-bit, and 8-bit, single supply, A/D converters.
The parts can be operated from a 2.35 V to 5.25 V supply.
When operated from either a 5 V supply or a 3 V supply, the
AD7476/AD7477/AD7478 are capable of throughput rates of
1 MSPS when provided with a 20 MHz clock.
The AD7476/AD7477/AD7478 provide the user with an on-chip
track/hold, A/D converter, and a serial interface housed in a tiny
6-lead SOT-23 package, which offers the user considerable
space-saving advantages over alternative solutions. The serial
clock input accesses data from the part and also provides the
clock source for the successive-approximation A/D converter. The
analog input range is 0 to V
. An external reference is not
DD
required for the ADC, nor is there a reference on-chip. The reference for the AD7476/AD7477/AD7478 is derived from the
power supply and thus gives the widest dynamic input range.
The AD7476/AD7477/AD7478 also feature a power-down option
to save power between conversions. The power-down feature is
implemented across the standard serial interface as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7476/AD7477/AD7478 is a successive-approximation analog-to-digital converter based around a charge redistribution DAC.
Figures 8 and 9 show simplified schematics of the ADC. Figure 8
shows the ADC during its acquisition phase. SW2 is closed and
SW1 is in position A, the comparator is held in a balanced condi-
CHARGE
DAC
CONTROL
LOGIC
.
IN
tion, and the sampling capacitor acquires the signal on V
REDISTRIBUTION
AGND
SAMPLING
A
CAPACITOR
B
ACQUISITION
PHASE
VDD/2
V
IN
SW1
COMPARATOR
SW2
ADC TRANSFER FUNCTION
The output coding of the AD7476/AD7477/AD7478 is straight
binary. For the AD7476/AD7477, designed code transitions
occur midway between successive integer LSB values (i.e.,
1/2 LSB, 3/2 LSBs, etc.). The LSB size for the AD7476 is =
/4096 and the LSB size for the AD7477 is = VDD/1024. The
V
DD
ideal transfer characteristic for the AD7476/AD7477 is shown
in Figure 10.
For the AD7478, designed code transitions occur midway between successive integer LSB values (i.e., 1 LSB, 2 LSBs, etc.).
The LSB size for the AD7478 is V
/256. The ideal transfer
DD
characteristic for the AD7478 is shown in Figure 11.
Figure 10. Transfer Characteristic for the AD7476/AD7477
Figure 8. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 9), SW2 will open
and SW1 will move to Position B causing the comparator to
become unbalanced. The Control Logic and the Charge Redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the ADC
output code. Figures 10 and 11 show the ADC transfer function.
CHARGE
REDISTRIBUTION
V
IN
SW1
SAMPLING
A
CAPACITOR
B
CONVERSION
AGND
PHASE
VDD/2
Figure 9. ADC Conversion Phase
COMPARATOR
SW2
DAC
CONTROL
LOGIC
REV. A
Figure 11. Transfer Characteristic for AD7478
TYPICAL CONNECTION DIAGRAM
Figure 12 shows a typical connection diagram for the AD7476/
AD7477/AD7478. V
such V
should be well decoupled. This provides an analog
DD
input range of 0 V to V
is taken internally from VDD and as
REF
. The conversion result is output in a
DD
16-bit word with four leading zeros followed by the MSB of the
12-bit, 10-bit, or 8-bit result. The 10-bit result from the AD7477
will be followed by two trailing zeros. The 8-bit result from
the AD7478 will be followed by four trailing zeros.
–9–
Page 10
AD7476/AD7477/AD7478
Alternatively, because the supply current required by the AD7476/
AD7477/AD7478 is so low, a precision reference can be used as
the supply source to the AD7476/AD7477/AD7478. A REF19x
voltage reference (REF195 for 5 V or REF193 for 3 V) can be
used to supply the required voltage to the ADC (see Figure 12).
This configuration is especially useful if the power supply is
quite noisy or if the system supply voltages are at some value
other than 5 V or 3 V (e.g., 15 V). The REF19x will output a
steady voltage to the AD7476/AD7477/AD7478. If the low dropout REF193 is used, the current it typically needs to supply to
the AD7476/AD7477/AD7478 is 1 mA. When the ADC is converting at a rate of 1 MSPS, the REF193 will need to supply a
maximum of 1.6 mA to the AD7476/AD7477/AD7478. The
load regulation of the REF193 is typically 10 ppm/mA (REF193,
= 5 V), which results in an error of 16 ppm (80 µV) for the
V
S
1.6 mA drawn from it. This corresponds to a 0.11 LSB error for
the AD7476 with V
= 3 V from the REF193, a 0.03 LSB
DD
error for the AD7477, and a 0.0068 LSB error for the AD7478.
For applications where power consumption is of concern, the
power-down mode of the ADC and the sleep mode of the REF19x
reference should be used to improve power performance. See
Modes of Operation section.
680nF
0V TO V
INPUT
3V
SCLK
SDATA
CS
REF193
10F 0.1F
SERIAL
INTERFACE
1mA
1F
0.1F
TANT
V
DD
DD
V
IN
AD7476/
AD7477/
GND
AD7478
5V
SUPPLY
C/P
Figure 12. REF193 as Power Supply to AD7476/AD7477/
AD7478
Table I provides some typical performance data with various
references used as a V
source with a low frequency analog
DD
input. Under the same setup conditions the references were
compared and the AD780 proved the optimum reference.
Table I.
Reference Tied AD7476 SNR Performance
to V
DD
1 kHz Input
AD780 @ 3 V 71.17 dB
REF193 70.4 dB
AD780 @ 2.5 V 71.35 dB
REF192 70.93 dB
AD1852 70.05 dB
Analog Input
Figure 13 shows an equivalent circuit of the analog input structure
of the AD7476/AD7477/AD7478. The two diodes D1 and D2
provide ESD protection for the analog inputs. Care must be
taken to ensure that the analog input signal never exceeds the
supply rails by more than 200 mV. This will cause these diodes
to become forward-biased and start conducting current into
the substrate. 20 mA is the maximum current these diodes can
conduct without causing irreversible damage to the part. The
capacitor C1 in Figure 13 is typically about 4 pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped
component made up of the on resistance of a switch. This
resistor is typically about 100 Ω. The capacitor C2 is the ADC
sampling capacitor and typically has a capacitance of 30 pF. For
ac applications, removing high-frequency components from the
analog input signal is recommended by use of a bandpass filter
on the relevant analog input pin. In applications where harmonic
distortion and signal-to-noise ratio are critical, the analog input
should be driven from a low impedance source. Large source
impedances will significantly affect the ac performance of the
ADC. This may necessitate the use of an input buffer amplifier.
The choice of the op amp will be a function of the particular
application.
V
DD
D1
V
IN
4pF
C1
D2
CONVERSION PHASE - SWITCH OPEN
TRACK PHASE - SWITCH CLOSED
C2
30pF
R1
Figure 13. Equivalent Analog Input Circuit
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance will depend on the amount of total harmonic distortion
(THD) that can be tolerated. The THD will increase as the source
impedance increases and performance will degrade. Figure 14
shows a graph of the total harmonic distortion versus source
impedance for different analog input frequencies when using
a supply voltage of 2.7 V and sampling at a rate of 605 kSPS.
Figures 15 and 16 each show a graph of the total harmonic distortion versus analog input signal frequency for various supply
voltages while sampling at 993 kSPS with an SCLK frequency
of 20 MHz and 605 kSPS with a SCLK frequency of 12 MHz
respectively.
0
–10
–20
–30
–40
–50
THD – dB
–60
–70
–80
–90
–100
1 10k
FIN = 300kHz
10
SOURCE IMPEDANCE – ⍀
100 1k
FIN = 200kHz
FIN = 10kHz
VDD = 2.7V
= 605kSPS
F
S
FIN = 100kHz
Figure 14. THD vs. Analog Input Frequency for Various
Source Impedance
–10–
REV. A
Page 11
AD7476/AD7477/AD7478
–50
–55
–60
THD – dB
–65
–70
–75
–80
–85
–90
10k
VDD = 5.25V
100k 1M
INPUT FREQUENCY – Hz
VDD = 2.35V
VDD = 2.7V
VDD = 4.75V
VDD = 3.6V
Figure 15. THD vs. Analog Input Frequency, fS = 993 kSPS
–72
VDD = 2.35V
VDD = 2.7V
VDD = 4.75V
VDD = 5.25V
VDD = 3.6V
THD – dB
–74
–76
–78
–80
–82
–84
10k
INPUT FREQUENCY – Hz
100k 1M
Figure 16. THD vs. Analog Input Frequency, fS = 605 kSPS
Digital Inputs
The digital inputs applied to the AD7476/AD7477/AD7478 are
not limited by the maximum ratings which limit the analog inputs. Instead, the digitals inputs applied can go to 7 V and are
not restricted by the V
+ 0.3 V limit as on the analog inputs.
DD
For example, if the AD7476/AD7477/AD7478 were operated with
a V
of 3 V, then 5 V logic levels could be used on the digital
DD
inputs. However, it is important to note that the data output
on SDATA will still have 3 V logic levels when V
= 3 V.
DD
Another advantage of SCLK and CS not being restricted by
the V
issues are avoided. If CS or SCLK are applied before V
+ 0.3 V limit is the fact that power supply sequencing
DD
DD
then
there is no risk of latch-up as there would be on the analog inputs
if a signal greater than 0.3 V was applied prior to V
DD
.
MODES OF OPERATION
The mode of operation of the AD7476/AD7477/AD7478 is
selected by controlling the (logic) state of the CS signal during a
conversion. There are two possible modes of operation, Normal
Mode and Power-Down Mode. The point at which CS is pulled
high after the conversion has been initiated will determine whether
or not the AD7476/AD7477/AD7478 will enter power-down
mode. Similarly, if already in power-down, CS can control whether
the device will return to normal operation or remain in powerdown. These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for differing application requirements.
Normal Mode
This mode is intended for fastest throughput rate performance,
as the user does not have to worry about any power-up times
with the AD7476/AD7477/AD7478 remaining fully powered all
the time. Figure 17 shows the general diagram of the operation of the AD7476/AD7477/AD7478 in this mode.
The conversion is initiated on the falling edge of CS as described in
the Serial Interface section. To ensure the part remains fully
powered up at all times, CS must remain low until at least
10 SCLK falling edges have elapsed after the falling edge of CS.
If CS is brought high any time after the 10th SCLK falling edge,
but before the 16th SCLK falling edge, the part will remain
powered up but the conversion will be terminated and SDATA
will go back into three-state. Sixteen serial clock cycles are
REV. A
CS
SCLK
SDATA
SCLK
SDATA
CS
1
4 LEADING ZEROS + CONVERSION RESULT
10
Figure 17. Normal Mode Operation
1
2
10
THREE-STATE
Figure 18. Entering Power-Down Mode
–11–
16
16
Page 12
AD7476/AD7477/AD7478
THE PART BEGINS
TO POWER UP
CS
A
11016 161
SCLK
SDATA
INVALID DATA VALID DATA
Figure 19. Exiting Power-Down Mode
required to complete the conversion and access the complete
conversion result. CS may idle high until the next conversion or
may idle low until CS returns high sometime prior to the next
conversion, (effectively idling CS low).
Once a data transfer is complete (SDATA has returned to threestate), another conversion can be initiated after the quiet time,
t
, has elapsed by again bringing CS low.
QUIET
Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions may be performed at a high throughput rate and the ADC is then powered
down for a relatively long duration between these bursts of several conversions. When the AD7476/AD7477/AD7478 is in
power-down, all analog circuitry is powered down.
To enter power-down, the conversion process must be interrupted
by bringing CS high anywhere after the second falling edge of
SCLK and before the 10th falling edge of SCLK as shown in
Figure 18. Once CS has been brought high in this window of
SCLKs, the part will enter power-down and the conversion that
was initiated by the falling edge of CS will be terminated and
SDATA will go back into three-state. If CS is brought high
before the second SCLK falling edge, the part will remain in
normal mode and will not power-down. This will avoid accidental power-down due to glitches on the CS line.
In order to exit this mode of operation and power the AD7476/
AD7477/AD7478 up again, a dummy conversion is performed.
On the falling edge of CS the device will begin to power up, and
will continue to power up as long as CS is held low until after
the falling edge of the 10th SCLK. The device will be fully powered up once 16 SCLKs have elapsed and, as shown in Figure
19, valid data will result from the next conversion. If CS is brought
high before the 10th falling edge of SCLK, the AD7476/AD7477/
AD7478 will again go back into power-down. This avoids
accidental power-up due to glitches on the CS line or an inadvertent
burst of eight SCLK cycles while CS is low. So although the
device may begin to power up on the falling edge of CS, it will
again power down on the rising edge of CS as long as it occurs
before the 10th SCLK falling edge.
Power-Up Time
The power-up time of the AD7476/AD7477/AD7478 is typically 1 µs, which means that with any frequency of SCLK up to
20 MHz, one dummy cycle will always be sufficient to allow the
device to power-up. Once the dummy cycle is complete, the ADC
will be fully powered up and the input signal will be acquired
properly. The quiet time t
must still be allowed from the
QUIET
THE PART IS FULLY POWERED
UP WITH V
FULLY ACQUIRED
IN
point at which the bus goes back into three-state after the dummy
conversion, to the next falling edge of CS. When running at 1 MSPS
throughput rate, the AD7476/AD7477/AD7478 will power up and
acquire a signal within ±0.5 LSB in one dummy cycle, i.e., 1 µs.
When powering up from the power-down mode with a dummy
cycle, as in Figure 19, the track and hold that was in hold mode
while the part was powered down, returns to track mode after
the first SCLK edge the part receives after the falling edge of
CS. This is shown as Point A in Figure 19. Although at any SCLK
frequency one dummy cycle is sufficient to power up the device
and acquire V
, it does not necessarily mean that a full dummy
IN
cycle of 16 SCLKs must always elapse to power up the device
and fully acquire V
; 1 µs will be sufficient to power up the
IN
device and acquire the input signal. If, for example, a 5 MHz
SCLK frequency were applied to the ADC, the cycle time would
be 3.2 µs. In one dummy cycle, 3.2 µs, the part would be powered
up and V
fully acquired. However after 1 µs with a 5 MHz
IN
SCLK only five SCLK cycles would have elapsed. At this stage,
the ADC would be fully powered up and the signal acquired. So,
in this case, the CS can be brought high after the 10th SCLK falling edge and brought low again after a time t
to initiate the
QUIET
conversion.
When power supplies are first applied to the AD7476/AD7477/
AD7478, the ADC may power up in either power-down mode
or in normal mode. Because of this, it is best to allow a dummy
cycle to elapse to ensure the part is fully powered up before
attempting a valid conversion. Likewise, if it is intended to keep
the part in the power-down mode while not in use and the user
wishes the part to power up in power-down mode, the dummy
cycle may be used to ensure the device is in power-down by executing a cycle such as that shown in Figure 18. Once supplies are
applied to the AD7476/AD7477/AD7478, the power-up time is
the same as that when powering up from the power-down mode.
It takes approximately 1 µs to fully power up if the part powers
up in normal mode. It is not necessary to wait 1 µs before executing a dummy cycle to ensure the desired mode of operation.
Instead, the dummy cycle can occur directly after power is
supplied to the ADC. If the first valid conversion is then performed directly after the dummy conversion, care must be taken
to ensure that adequate acquisition time has been allowed. As
mentioned earlier, when powering up from the power-down
mode, the part will return to track upon the first SCLK edge
applied after the falling edge of CS. However, when the ADC
powers up initially after supplies are applied, the track and hold
will already be in track. This means that if the ADC powers up
in the desired mode of operation, and a dummy cycle is not required to change mode, a dummy cycle is not required to place
the track and hold into track.
–12–
REV. A
Page 13
AD7476/AD7477/AD7478
POWER VERSUS THROUGHPUT RATE
By using the power-down mode on the AD7476/AD7477/AD7478
when not converting, the average power consumption of the
ADC decreases at lower throughput rates. Figure 20 shows how
as the throughput rate is reduced, the device remains in its powerdown state longer and the average power consumption over time
drops accordingly.
For example if the AD7476/AD7477/AD7478 is operated in a
continuous sampling mode with a throughput rate of 100 kSPS
and a SCLK of 20 MHz (V
= 5 V), and the device is placed
DD
in the power-down mode between conversions, then the power
consumption is calculated as follows. The power dissipation
during normal operation is 17.5 mW (V
= 5 V). If the power-
DD
up time is one dummy cycle, i.e., 1 µs, and the remaining
conversion time is another cycle, i.e., 1 µs, then the AD7476/
AD7477/AD7478 can be said to dissipate 17.5 mW for 2 µs
during each conversion cycle. If the throughput rate is 100 kSPS,
the cycle time is 10 µs and the average power dissipated during
each cycle is (2/10) × (17.5 mW) = 3.5 mW. If V
= 3 V,
DD
SCLK = 20 MHz and the device is again in power-down mode
between conversions, the power dissipation during normal operation is 4.8 mW. The AD7476/AD7477/AD7478 can now be said
to dissipate 4.8 mW for 2 µs during each conversion cycle. With
a throughput rate of 100 kSPS, the average power dissipated
during each cycle is (2/10) × (4.8 mW) = 0.96 mW. Figure
20 shows the power versus throughput rate when using the
power-down mode between conversions with both 5 V and
3 V supplies.
100
10
1
POWER – mW
VDD = 5V, SCLK = 20MHz
VDD = 3V, SCLK = 20MHz
The power-down mode is intended for use with throughput
rates of approximately 333 kSPS and under as at higher sampling rates power is not saved by using the power-down mode.
SERIAL INTERFACE
Figures 21, 22, and 23 show the detailed timing diagram for
serial interfacing to the AD7476, AD7477, and AD7478 respectively. The serial clock provides the conversion clock and
also controls the transfer of information from the AD7476/
AD7477/AD7478 during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode,
takes the bus out of three-state and the analog input is sampled
at this point. The conversion is also initiated at this point and
will require 16 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the track and hold will go back into
track on the next SCLK rising edge as shown in Figures 21, 22,
and 23 at Point B. On the 16th SCLK falling edge the SDATA
line will go back into three-state. If the rising edge of CS occurs
before 16 SCLKs have elapsed, the conversion will be terminated
and the SDATA line will go back into three-state; otherwise,
SDATA returns to three-state on the 16th SCLK falling edge as
shown in Figures 21, 22, and 23. Sixteen serial clock cycles
are required to perform the conversion process and to access
data from the AD7476/AD7477/AD7478. CS going low provides the first leading zero to be read in by the microcontroller
or DSP. The remaining data is then clocked out by subsequent
SCLK falling edges, beginning with the second leading zero. Thus
the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero.
The final bit in the data transfer is valid on the 16th falling
edge, having being clocked out on the previous (15th) falling
edge. In applications with a slower SCLK, it is possible to read
in data on each SCLK rising edge, i.e., the first rising edge of SCLK
after the CS falling edge would have the first leading zero provided and the 15th rising SCLK edge would have DB0 provided,
or the final zero provided for the AD7477 and AD7478.
REV. A
0.1
0.01
50 100 150 200 250 300 350
0
THROUGHPUT – kSPS
Figure 20. Power vs. Throughput
–13–
Page 14
AD7476/AD7477/AD7478
CS
t
2
SCLK
SDATA
SCLK
SDATA
CS
THREE-
STATE
THREE-
STATE
12345 13141516
t
3
ZERO ZERO ZEROZ DB11 DB10 DB2 DB1 DB0
4 LEADING ZEROS
t
2
12345 13141516
t
3
ZERO ZERO ZEROZ DB9 DB8 DB0 ZERO ZERO
4 LEADING ZEROS
t
CONVERT
t
6
t
4
t
B
t
7
5
t
8
Figure 21. AD7476 Serial Interface Timing Diagram
t
CONVERT
t
6
t
4
t
B
t
7
5
TWO TRAILING
ZEROS
t
8
Figure 22. AD7477 Serial Interface Timing Diagram
THREE-STATE
THREE-STATE
t
QUIET
t
QUIET
t
1
t
1
SCLK
SDATA
CS
THREE-
STATE
t
CONVERT
t
2
1 2 3 4 13 14 15 16
t
3
ZERO ZERO ZEROZ DB7 ZERO ZERO
4 LEADING ZEROS
t
6
t
4
8 BITS OF DATA
12
t
7
ZERO ZERO
B
t
5
4 TRAILING ZERO'S
Figure 23. AD7478 Serial Interface Timing Diagram
t
8
THREE-STATE
t
QUIET
t
1
–14–
REV. A
Page 15
AD7476/AD7477/AD7478
MICROPROCESSOR INTERFACING
The serial interface on the AD7476/AD7477/AD7478 allows
the part to be directly connected to a range of many different
microprocessors. This section explains how to interface the
AD7476/AD7477/AD7478 with some of the more common
microcontroller and DSP serial interface protocols.
AD7476/AD7477/AD7478 to TMS320C5x/C54x Interface
The serial interface on the TMS320C5x uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7476/
AD7477/AD7478. The CS input allows easy interfacing between
the TMS320C5x/C54x and the AD7476/AD7477/AD7478 without any glue logic required. The serial port of the TMS320C5x/
C54x is set up to operate in burst mode with internal CLKX (Tx
serial clock) and FSX (Tx frame sync). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1,
MCM = 1 and TXM = 1. The format bit, FO, may be set to 1 to
set the word length to eight bits, in order to implement the
power-down mode on the AD7476/AD7477/AD7478. The connection diagram is shown in Figure 24. It should be noted that for
signal processing applications, it is imperative that the frame synchronization signal from the TMS320C5x/C54x will provide
equidistant sampling.
AD7476/
AD7477/
AD7478*
SCLK
SDATA
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
TMS320C5x/
TMS320C54x*
CLKX
CLKR
DR
FSX
FSR
Figure 24. Interfacing to the TMS320C5x/C54x
AD7476/AD7477/AD7478 to ADSP-21xx Interface
The ADSP21xx family of DSPs are interfaced directly to the
AD7476/AD7477/AD7478 without any glue logic required. The
SPORT control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1
To implement the power-down mode SLEN should be set to
1001 to issue an 8-bit SCLK burst. The connection diagram is
shown in Figure 25. The ADSP-21xx has the TFS and RFS of
the SPORT tied together, with TFS set as an output and RFS
set as an input. The DSP operates in Alternate Framing Mode
and the SPORT control register is set up as described. The
frame synchronization signal generated on the TFS is tied to
CS and as with all signal processing applications equidistant
sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC and, under
certain conditions, equidistant sampling may not be achieved.
The timer registers etc., are loaded with a value that will provide
an interrupt at the required sample interval. When an interrupt
is received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and hence the reading
of data. The frequency of the serial clock is set in the SCLKDIV
register. When the instruction to transmit with TFS is given
(i.e., AX0 = TX0), the state of the SCLK is checked. The DSP
will wait until the SCLK has gone High, Low, and High before
transmission will start. If the timer and SCLK values are chosen
such that the instruction to transmit occurs on or near the rising
edge of SCLK, the data may be transmitted or it may wait until
the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
a SCLK of 2 MHz is obtained, and eight master clock periods
will elapse for every one SCLK period. If the timer registers
are loaded with the value 803, 100.5 SCLKs will occur between
interrupts and subsequently between transmit instructions. This
situation will result in nonequidistant sampling as the transmit
instruction is occurring on an SCLK edge. If the number of
SCLKs between interrupts is a whole integer figure of N, equidistant sampling will be implemented by the DSP.
AD7476/
AD7477/
AD7478*
SCLK
SDATA
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
ADSP-21xx*
SCLK
DR
RFS
TFS
Figure 25. Interfacing to the ADSP-21xx
REV. A
–15–
Page 16
AD7476/AD7477/AD7478
AD7476/AD7477/AD7478 to DSP56xxx Interface
The connection diagram in Figure 26 shows how the AD7476/
AD7477/AD7478 can be connected to the SSI (Synchronous
Serial Interface) of the DSP56xxx family of DSPs from Motorola.
The SSI is operated in Synchronous Mode (SYN bit in CRB
=1) with internally generated 1-bit clock period frame sync
for both Tx and Rx (Bits FSL1 = 1 and FSL0 = 0 in CRB). Set
the word length to 16 by setting bits WL1 = 1 and WL0 = 0 in
CRA. To implement the power-down mode on the AD7476/
AD7477/AD7478, the word length can be changed to eight bits
by setting bits WL1 = 0 and WL0 = 0 in CRA. It should be
noted that for signal processing applications, it is imperative
that the frame synchronization signal from the DSP56xxx will
provide equidistant sampling.
AD7476/
AD7477/
AD7478*
SCLK
SDATA
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
DSP56xxx*
SCK
SRD
SC2
Figure 26. Interfacing to the DSP56xxx
AD7476/AD7477/AD7478 to MC68HC16 Interface
The Serial Peripheral Interface (SPI) on the MC68HC16 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 1 and the Clock Phase Bit (CPHA) = 0. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC16 User Manual. The serial transfer will take place as a
16-bit operation when the SIZE bit in the SPCR register is set
to SIZE = 1. To implement the power-down mode with an
8-bit transfer set SIZE = 0. A connection diagram is shown in
Figure 27.
AD7476/
AD7477/
AD7478*
SCLK
SDATA
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
MC68HC16*
SCLK/PMC2
MISO/PMC0
SS/PMC3
Figure 27. Interfacing to the MC68HC16
C3752a–2.5–4/00 (rev. A) 01024
0.071 (1.80)
0.059 (1.50)
0.051 (1.30)
0.035 (0.90)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
6-Lead SOT-23
(RT-6)
0.122 (3.10)
0.106 (2.70)
4 5 6
0.118 (3.00)
0.098 (2.50)
3
0.037 (0.95) BSC
0.057 (1.45)
0.035 (0.90)
SEATING
PLANE
PIN 1
0.006 (0.15)
0.000 (0.00)
1
0.075 (1.90)
2
BSC
0.020 (0.50)
0.010 (0.25)
0.009 (0.23)
0.003 (0.08)
10ⴗ
0ⴗ
0.022 (0.55)
0.014 (0.35)
PRINTED IN U.S.A.
–16–
REV. A
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