Page 1
V
V
12-Bit ADC
FEATURES
Specified for VDD of 2.35 V to 5.25 V
Low power
3.6 mW at 600 kSPS with 3 V supplies
15 mW at 600 kSPS with 5 V supplies
Wide input bandwidth
70 dB SNR at 100 kHz input frequency
High speed serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
Standby mode: 1 μA maximum
6-lead SOT-23 package
ENHANCED PRODUCT FEATURES
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available upon request
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
GENERAL DESCRIPTION
The AD74761 is a 12-bit, high speed, low power, successive
approximation ADC. The part operates from a single 2.35 V
to 5.25 V power supply and features throughput rates up to
600 kSPS. The part contains a low noise, wide bandwidth, trackand-hold amplifier that can handle input frequencies in excess
of 6 MHz.
The conversion process and data acquisition are controlled
CS
using
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
point. There are no pipeline delays associated with this part.
The AD7476 uses advanced design techniques to achieve very
low power dissipation at high throughput rates.
1
Protected by U.S. Patent No. 6,681,332.
and the serial clock, allowing the device to interface
CS
and the conversion is initiated at this
in 6-Lead SOT-23
AD7476-EP
FUNCTIONAL BLOCK DIAGRAM
DD
12-BIT
IN
The reference for the part is taken internally from V
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 V to V
rate is determined by the SCLK pin.
Additional application and technical information can be found
in the AD7476 data sheet.
PRODUCT HIGHLIGHTS
1. First 12-Bit ADC in a SOT-23 Package.
2. High Throughput with Low Power Consumption.
3. Flexible Power/Serial Clock Speed Management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced while not converting. The part also features a
shutdown mode to maximize power efficiency at lower
throughput rates. Current consumption is 1 μA maximum
when in shutdown mode.
4. Reference Derived from the Power Supply.
5. No Pipeline Delay. The part features a standard successive-
approximation ADC with accurate control of the sampling
instant via a
SUCCESSIVE-
APPROXIMATION
ADC
CONTROL
LOGIC
AD7476-EP
GND
Figure 1.
CS
input and once-off conversion control.
SCLK
SDATA
CS
09224-001
DD
. The conversion
DD
. This
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
Page 2
AD7476-EP
TABLE OF CONTENTS
Features.............................................................................................. 1
Timing Specifications ...................................................................5
Enhanced Product Features ............................................................ 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
REVISION HISTORY
8/10—Revision 0: Initial Version
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions..............................7
Typical Performance Characteristics..............................................8
Outline Dimensions..........................................................................9
Ordering Guide .............................................................................9
Rev. 0 | Page 2 of 12
Page 3
AD7476-EP
SPECIFICATIONS
VDD = 2.35 V to 5.25 V, f
Table 1.
Parameter S Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 100 kHz sine wave
Signal-to-(Noise + Distortion) (SINAD) 69 dB min
70 dB min TA = 25°C
Signal-to-Noise Ratio (SNR) 70 dB min
Total Harmonic Distortion (THD) −78 dB typ
Peak Harmonic or Spurious Noise (SFDR) −80 dB typ
Intermodulation Distortion (IMD)
Second-Order Terms −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz
Third-Order Terms −78 dB typ fa = 103.5 kHz, fb = 113.5 kHz
Aperture Delay 10 ns typ
Aperture Jitter 30 ps typ
Full Power Bandwidth 6.5 MHz typ At 3 dB
DC ACCURACY VDD = (2.35 V to 3.6 V)1
Resolution 12 Bits
Integral Nonlinearity ±1.5 LSB max
±0.6 LSB typ
Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits
±0.75 LSB typ
Offset Error ±2 LSB max
LSB typ
Gain Error ±2 LSB max
LSB typ
ANALOG INPUT
Input Voltage Ranges 0 to VDD V
DC Leakage Current ±1 μA max
Input Capacitance 30 pF typ
LOGIC INPUT
Input High Voltage, V
1.8 V min VDD = 2.35 V
Input Low Voltage, V
0.8 V max VDD = 5 V
Input Current, IIN, SCLK Pin ±1 μA max Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
Input Capacitance, C
LOGIC OUTPUT
Output High Voltage, VOH VDD − 0.2 V min I
Output Low Voltage, VOL 0.4 V max I
Floating-State Leakage Current ±10 μA max
Floating-State Output Capacitance2 10 pF max
Output Coding Straight (natural) binary
CONVERSION RATE
Conversion Time 1.33 μs max 16 SCLK cycles
Track-and-Hold Acquisition Time 500 ns max Full-scale step input
400 ns max Sine wave input ≤ 100 kHz
Throughput Rate 600 kSPS max
= 12 MHz, f
SCLK
2.4 V min
INH
0.4 V max VDD = 3 V
INL
= 600 kSPS, unless otherwise noted; TA = T
SAMPLE
MIN
±1 μA typ
2
10 pF max
IN
SOURCE
= 200 μA
SINK
to T
, unless otherwise noted.
MAX
= 200 μA; VDD = 2.35 V to 5.25 V
Rev. 0 | Page 3 of 12
Page 4
AD7476-EP
Parameter S Version Unit Test Conditions/Comments
POWER REQUIREMENTS
VDD 2.35/5.25 V min/max
IDD Digital I/Ps = 0 V or VDD
Normal Mode (Static) 2 mA typ VDD = 4.75 V to 5.25 V, SCLK on or off
1 mA typ VDD = 2.35 V to 3.6 V, SCLK on or off
Normal Mode (Operational) 3 mA max
1.4 mA max
Full Power-Down Mode 1 μA max SCLK off
80 μA max SCLK on
Power Dissipation
Normal Mode (Operational) 15 mW max VDD = 5 V, f
4.2 mW max VDD = 3 V, f
Full Power-Down 5 μW max VDD = 5 V, SCLK off
3 μW max VDD = 3 V, SCLK off
1
S version specifications apply as typical figures when VDD = 5.25 V.
2
Guaranteed by characterization.
3
f
MAX = 600 kSPS.
SAMPLE
= 4.75 V to 5.25 V,
V
DD
= f
f
V
SAMPLE
DD
f
SAMPLE
SAMPLE
= 2.35 V to 3.6 V,
= f
SAMPLE
SAMPLE
SAMPLE
MAX3
MAX4
= f
SAMPLE
= f
SAMPLE
MAX4
MAX4
Rev. 0 | Page 4 of 12
Page 5
AD7476-EP
TIMING SPECIFICATIONS
VDD = 2.35 V to 5.25 V, TA = T
MIN
to T
, unless otherwise noted.
MAX
Table 2.
Limit at T
MIN
1
, T
MAX
Parameter2 3 V 5 V Unit Description
3
f
10 10 kHz min
SCLK
12 12 MHz max
t
16 × t
CONVER T
t
50 50 ns min Minimum quiet time required between bus relinquish and start of next conversion
QUIET
t1 10 10 ns min
t2 10 10 ns min
4
t
20 20 ns max
3
4
t
40 20 ns max Data access time after SCLK falling edge, A version
4
16 × t
SCLK
SCLK
Minimum CS
to SCLK setup time
CS
Delay from CS
pulse width
until SDATA three-state disabled
70 20 ns max Data access time after SCLK falling edge, B version
t5 0.4 × t
t6 0.4 × t
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK low pulse width
SCLK
ns min SCLK high pulse width
SCLK
t7 10 10 ns min SCLK to data valid hold time
5
t
10 10 ns min SCLK falling edge to SDATA high impedance
8
25 25 ns max SCLK falling edge to SDATA high impedance
t
1 1 μs typ Power-up time from full power-down
POWER-UP
1
3 V specifications apply from VDD = 2.35 V to 3.6 V; 5 V specifications apply from VDD = 4.75 V to 5.25 V.
2
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
3
Mark/space ratio for the SCLK input is 40/60 to 60/40.
4
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
5
t8 is derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated to
remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, is the true bus relinquish time of the part and is independent of the bus
loading.
TO OUTPUT
PIN
50pF
C
200µA I
L
200µA I
OL
1.6V
OH
09224-002
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. 0 | Page 5 of 12
Page 6
AD7476-EP
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range
Enhanced Plastic (EP Version) −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
SOT-23 Package
θJA Thermal Impedance 230°C/W
θJC Thermal Impedance 92°C/W
Lead Temperature, Soldering Reflow
(10 sec to 30 sec) 235 (0/+5)°C
Pb-free Temperature Soldering Reflow 255 (0/+5)°C
ESD 3.5 kV
1
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 12
Page 7
AD7476-EP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
DD
AD7476-EP
2
GND
V
TOP VIEW
3
(Not to Scale)
IN
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Power Supply Input. The VDD range for the AD7476-EP is from 2.35 V to 5.25 V.
2 GND
Analog Ground. Ground reference point for all circuitry on the part. All analog input signals should be referred
to this GND voltage.
3 VIN Analog Input. Single-ended analog input channel. The input range is 0 V to VDD.
4 SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also
used as the clock source for the AD7476-EP conversion process.
5 SDATA
Data Out. Logic output. The conversion result is provided on this output as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input. The data stream from the AD7476-EP consists of four leading
zeros followed by the 12 bits of conversion data; this is provided MSB first.
6
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
CS
AD7476-EP and framing the serial data transfer.
6
5
4
CS
SDATA
SCLK
09224-003
Rev. 0 | Page 7 of 12
Page 8
AD7476-EP
–
TYPICAL PERFORMANCE CHARACTERISTICS
8192 POINT FFT
f
= 600kSPS
–15
–35
–55
SNR (dB)
–75
–95
SAMPLE
f
= 100kHz
IN
SINAD = 71.71dB
THD = –80.88dB
SFDR = –83.23 dB
SINAD (dB)
69.0
–69.5
–70.0
–70.5
–71.0
–71.5
–72.0
SCLK = 12MHz
VDD = 2.35V
= 2.7V
V
DD
= 5.25V
V
DD
= 4.75V
V
DD
= 3.6V
V
DD
–115
0325020015010050
FREQUENCY ( kHz )
Figure 4. AD7476-EP Dynamic Performance at 600 kSPS
09224-005
00
–72.5
10k 1M100k
INPUT FRE QUENCY (kHz)
Figure 5. AD7476-EP SINAD vs. Input Frequency at 605 kSPS
09224-009
Rev. 0 | Page 8 of 12
Page 9
AD7476-EP
0
0
OUTLINE DIMENSIONS
3.00
2.90
2.80
1.70
1.60
1.50
PIN 1
INDICATOR
1.30
1.15
0.90
.15 MAX
.05 MIN
65
123
4
1.90
BSC
0.50 MAX
0.30 MIN
COMPLI ANT TO JEDE C STANDARDS MO - 178-AB
0.95 BSC
1.45 MAX
0.95 MIN
3.00
2.80
2.60
SEATING
PLANE
0.20 MAX
0.08 MIN
10°
0.55
0.60
4°
BSC
0°
0.45
0.35
121608-A
Figure 6. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Linearity Error (LSB)2
AD7476SRTZ-EP-RL7 −55°C to +125°C ±1.5 maximum 6-Lead SOT-23 RJ-6 C73#
1
Z = RoHS Compliant Part, # denotes RoHS compliant part maybe top or bottom marked.
2
Linearity error refers to integral linearity error.
Package Description
Package Option Branding
Rev. 0 | Page 9 of 12
Page 10
AD7476-EP
NOTES
Rev. 0 | Page 10 of 12
Page 11
AD7476-EP
NOTES
Rev. 0 | Page 11 of 12
Page 12
AD7476-EP
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09224-0-8/10(0)
Rev. 0 | Page 12 of 12
Loading...