Datasheet AD7476A, AD7477A Datasheet (ANALOG DEVICES)

2.35 V to 5.25 V, 1 MSPS,

FEATURES

Fast throughput rate: 1 MSPS
Specified for V
Low power

3.6 mW at 1 MSPS with 3 V supplies

12.5 mW at 1 MSPS with 5 V supplies

Wide input bandwidth

71 dB SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface

SPI®/QSPI™/MICROWIRE™/DSP compatible
Standby mode: 1 μA maximum
6-lead SC70 package
8-lead MSOP package
Qualified for automotive applications

APPLICATIONS

Battery-powered systems

Personal digital assistants

Medical instruments

Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors

of 2.35 V to 5.25 V

DD

12-/10-/8-Bit ADCs in 6-Lead SC70

AD7476A/AD7477A/AD7478A

FUNCTIONAL BLOCK DIAGRAM

V

DD

12-/10-/8-BIT

V

T/H

IN

AD7476A/AD7477A/AD7478A

SUCCESSIVE-

APPROXIMATION

ADC

CONTROL

LOGIC

GND

Figure 1.

SCLK
SDATA
CS

02930-001

GENERAL DESCRIPTION

The AD7476A/AD7477A/AD7478A are 12-bit, 10-bit, and 8-bit
high speed, low power, successive-approximation analog-to­digital converters (ADCs), respectively. The parts operate from
a single 2.35 V to 5.25 V power supply and feature throughput
rates up to 1 MSPS. The parts contain a low noise, wide
bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 13 MHz. The conversion process and
data acquisition are controlled using
allowing the devices to interface with microprocessors or DSPs.
The input signal is sampled on the falling edge of
conversion is also initiated at this point. There are no pipeline
delays associated with the parts. The AD7476A/AD7477A/
AD7478A use advanced design techniques to achieve low power
dissipation at high throughput rates. The reference for the part
is taken internally from V

to allow the widest dynamic input

DD

range to the ADC. Thus, the analog input range for the part is
0 V to V

Rev. F

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. The conversion rate is determined by the SCLK.

DD

CS

and the serial clock,

CS

, and the

PRODUCT HIGHLIGHTS

1. First 12-/10-/8-bit ADCs in a SC70 package.

2. High throughput with low power consumption.

3. Flexible power/serial clock speed management. The

conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced when a power-down mode is used while not
converting. The parts also feature a power-down mode to
maximize power efficiency at lower throughput rates.
Current consumption is 1 μA maximum and 50 nA
typically when in power-down mode.

4. Reference derived from the power supply.

5. No pipeline delay. The parts feature a standard successive

approximation ADC with accurate control of the sampling
instant via a

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CS

input and once-off conversion control.