Datasheet AD7476 Datasheet (Analog Devices)

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1 MSPS, 12-/10-/8-Bit ADCs

in 6-Lead SOT-23

FEATURES Fast Throughput Rate: 1 MSPS Speciﬁed for V

of 2.35 V to 5.25 V

Low Power:

3.6 mW Typ at 1 MSPS with 3 V Supplies 15 mW Typ at 1 MSPS with 5 V Supplies

Wide Input Bandwidth:

70 dB SNR at 100 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface

/QSPI™/MICROWIRE™/DSP Compatible

SPI Standby Mode: 1 ␮A Max 6-Lead SOT-23 Package

APPLICATIONS Battery-Powered Systems

Personal Digital Assistants

Medical Instruments

Mobile Communications Instrumentation and Control Systems Data Acquisition Systems High Speed Modems Optical Sensors

AD7476/AD7477/AD7478

FUNCTIONAL BLOCK DIAGRAM

T/H

AD7476/AD7477/AD7478

8-/10-/12-BIT

SUCCESSIVE-

APPROXIMATION

ADC

CONTROL

LOGIC

GND

SCLK

SDATA

GENERAL DESCRIPTION

The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit, and 8-bit, high speed, low power, successive-approximation ADCs. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low noise, wide bandwidth track-and-hold ampliﬁer that can handle input frequencies in excess of 6 MHz.

The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipeline delays associated with the part.

The AD7476/AD7477/AD7478 use advanced design techniques to achieve very low power dissipation at high throughput rates.

The reference for the part is taken internally from V

DD.

This allows the widest dynamic input range to the ADC. Thus the analog input range for the part is 0 V to V

. The conversion

rate is determined by the SCLK.

*Protected by U.S.Patent No. 6,681,332.

REV. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

PRODUCT HIGHLIGHTS

1. First 12-/10-/8-Bit ADCs in a SOT-23 Package.

2. High Throughput with Low Power Consumption.

3. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced while not converting. The part also features a shutdown mode to maximize power efﬁciency at lower throughput rates. Current consumption is 1 µA maximum when in shutdown.

4. Reference Derived from the Power Supply.

5. No Pipeline Delay.

The parts feature a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.

AD7476–SPECIFICATIONS

(A Version: VDD = 2.7 V to 5.25 V, f noted; S and B Versions: VDD = 2.35 V to 5.25 V, f

unless otherwise noted; TA = T

MIN

to T

= 20 MHz, f

SCLK

, unless otherwise noted.)

MAX

= 1 MSPS, unless otherwise

SAMPLE

= 12 MHz, f

SCLK

SAMPLE

= 600 kSPS,

Parameter A Version

1, 2

B Version

1, 2

S Version

1, 2

Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 100 kHz Sine Wave

Signal-to-(Noise + Distortion) (SINAD)369 70 69 dB min B Version, VDD = 2.4 V to 5.25 V

= 25°C

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD)

70 70 dB min T

71.5 dB typ

70 71 70 dB min B Version, VDD = 2.4 V to 5.25 V

72.5 dB typ –80 –78 –78 dB typ –82 –80 –80 dB typ

Second-Order Terms –78 –78 –78 dB typ fa = 103.5 kHz, fb = 113.5 kHz

Third-Order Terms –78 –78 –78 dB typ fa = 103.5 kHz, fb = 113.5 kHz Aperture Delay 10 10 10 ns typ Aperture Jitter 30 30 30 ps typ Full Power Bandwidth 6.5 6.5 6.5 MHz typ @ 3 dB

DC ACCURACY S, B Versions, V

= (2.35 V to 3.6 V)4;

A Version, VDD = (2.7 V to 3.6 V) Resolution 12 12 12 Bits Integral Nonlinearity

Differential Nonlinearity

Offset Error

Gain Error

± 1 ± 0.6 ± 0.6 LSB typ

± 0.75 ± 0.75 ± 0.75 LSB typ

± 1.5 ± 1.5 LSB max

–0.9/+1.5 –0.9/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits

± 1.5 ± 2 LSB max

± 0.5 LSB typ

± 1.5 ± 2 LSB max

± 0.5 LSB typ

ANALOG INPUT

Input Voltage Ranges 0 to V

0 to V

V DC Leakage Current ± 1 ± 1 ± 1 µA max Input Capacitance 30 30 30 pF typ

LOGIC INPUTS

Input High Voltage, V

INH

2.4 2.4 2.4 V min

1.8 1.8 1.8 V min VDD = 2.35 V

Input Low Voltage, V

INL

0.4 0.4 0.4 V max VDD = 3 V

0.8 0.8 0.8 V max VDD = 5 V Input Current, IIN, SCLK Pin ± 1 ± 1 ± 1 µA max Typically 10 nA, V Input Current, IIN, CS Pin ± 1 ± 1 ± 1 µA typ Input Capacitance, C

10 10 10 pF max

= 0 V or V

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V

Floating-State Leakage Current ±10 ± 10 ±10 µA max Floating-State Output Capacitance

VDD – 0.2 VDD – 0.2 VDD – 0.2 V min I

0.4 0.4 0.4 V max I

10 10 10 pF max

= 200 µA; VDD = 2.35 V to 5.25 V

SOURCE

= 200 µA

SINK

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 0.8 1.33 1.33 µs max 16 SCLK Cycles Track-and-Hold Acquisition Time 500 500 500 ns max Full-Scale Step Input

350 400 400 ns max Sine Wave Input ≤100 kHz

Throughput Rate 1000 600 600 kSPS max See Serial Interface Section

POWER REQUIREMENTS

2.35/5.25 2.35/5.25 2.35/5.25 V min/max

Digital I/Ps = 0 V or V

Normal Mode (Static) 222mA typ VDD = 4.75 V to 5.25 V. SCLK On or Off

111mA typ VDD = 2.35 V to 3.6 V. SCLK On or Off

Normal Mode (Operational) 3.5 3 3 mA max VDD = 4.75 V to 5.25 V; f

1.6 1.4 1.4 mA max VDD = 2.35 V to 3.6 V; f

SAMPLE

Full Power-Down Mode 1 1 1 µA max SCLK Off

Power Dissipation

Normal Mode (Operational) 17.5 15 15 mW max VDD = 5 V; f

80 80 80 µA max SCLK On

4.8 4.2 4.2 mW max VDD = 3 V; f

SAMPLE

= f = f

SAMPLE

Full Power-Down 5 5 5 µW max VDD = 5 V; SCLK Off

333µW max VDD = 3 V; SCLK Off

NOTES

Temperature ranges as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.

Operational from VDD = 2.0 V.

See Terminology section.

Maximum B, S version specifications apply as typical ﬁgures when VDD = 5.25 V.

Guaranteed by characterization.

A Version: f

See Power vs. Throughput Rate section.

MAX = 1 MSPS; B, S Versions: f

SAMPLE

Speciﬁcations subject to change without notice.

SAMPLE

= f

MAX MAX

SAMPLE

MAX

MAX = 600 kSPS.

REV. D–2–

AD7477–SPECIFICATIONS

(VDD = 2.7 V to 5.25 V, f

= 20 MHz, TA = T

SCLK

MIN

to T

, unless otherwise noted.)

MAX

Parameter A Version

1, 2

S Version

DYNAMIC PERFORMANCE f

1, 2

Unit Test Conditions/Comments

= 100 kHz Sine Wave, f

SAMPLE

= 1 MSPS Signal-to-(Noise + Distortion) (SINAD) 61 61 dB min Total Harmonic Distortion (THD) –73 –73 dB max Peak Harmonic or Spurious Noise (SFDR) –74 –74 dB max Intermodulation Distortion (IMD)

Second-Order Terms –78 –78 dB typ fa = 103.5 kHz, fb = 113.5 kHz

Third-Order Terms –78 –78 dB typ fa = 103.5 kHz, fb = 113.5 kHz Aperture Delay 10 10 ns typ Aperture Jitter 30 30 ps typ Full Power Bandwidth 6.5 6.5 MHz typ @ 3 dB

DC ACCURACY

Resolution 10 10 Bits Integral Nonlinearity ± 1 ± 1 LSB max Differential Nonlinearity ± 0.9 ± 0.9 LSB max Guaranteed No Missed Codes to 10 Bits Offset Error ± 1 ± 1 LSB max Gain Error ± 1 ± 1 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

0 to V

V DC Leakage Current ± 1 ± 1 µA max Input Capacitance 30 30 pF typ

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

Input Current, I Input Current, IIN, CS Pin ± 1 ± 1 µA typ Input Capacitance, C

INH

INL

, SCLK Pin ± 1 ± 1 µA max Typically 10 nA, V

2.4 2.4 V min

0.8 0.8 V max VDD = 5 V

0.4 0.4 V max V

= 3 V

10 10 pF max

= 0 V or V

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±10 ±10 µA max Floating-State Output Capacitance

VDD – 0.2 VDD – 0.2 V min I

0.4 0.4 V max I

10 10 pF max

= 200 µA; VDD = 2.7 V to 5.25 V

SOURCE

= 200 µA

SINK

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 800 800 ns max 16 SCLK Cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 400 400 ns max Throughput Rate 1 1 MSPS max See Serial Interface Section

POWER REQUIREMENTS

2.7/5.25 2.7/5.25 V min/max Digital I/Ps = 0 V or V

Normal Mode (Static) 2 2 mA typ VDD = 4.75 V to 5.25 V; SCLK On or Off

11mA typ V

Normal Mode (Operational) 3.5 3.5 mA max V

1.6 1.6 mA max V

= 2.7 V to 3.6 V; SCLK On or Off

= 4.75 V to 5.25 V; f

= 2.7 V to 3.6 V; f

SAMPLE

= 1 MSPS

Full Power-Down Mode 1 1 µA max SCLK Off

Power Dissipation

Normal Mode (Operational) 17.5 17.5 mW max VDD = 5 V; f

80 80 µA max SCLK On

4.8 4.8 mW max V

= 3 V; f

SAMPLE

= 1 MSPS = 1 MSPS

Full Power-Down 5 5 µW max VDD = 5 V; SCLK Off

NOTES

Temperature ranges as follows: A Version: –40°C to +85°C; S Version: –55°C to +125°C.

Operational from VDD = 2.0 V, with input high voltage, V

See Terminology section.

Guaranteed by characterization.

See Power vs. Throughput Rate section.

Speciﬁcations subject to change without notice.

= 1.8 V min.

INH

REV. D –3–

AD7476–SPECIFICATIONS

(VDD = 2.7 V to 5.25 V, f

= 20 MHz, TA = T

SCLK

MIN

to T

, unless otherwise noted.)

MAX

Parameter A Version

1, 2

S Version

DYNAMIC PERFORMANCE f

1, 2

Unit Test Conditions/Comments

= 100 kHz Sine Wave, f

SAMPLE

= 1 MSPS Signal-to-(Noise + Distortion) (SINAD) 49 49 dB min Total Harmonic Distortion (THD) –65 –65 dB max Peak Harmonic or Spurious Noise (SFDR) –65 –65 dB max Intermodulation Distortion (IMD)

Second-Order Terms –68 –68 dB typ fa = 498.7 kHz, fb = 508.7 kHz

Third-Order Terms –68 –68 dB typ fa = 498.7 kHz, fb = 508.7 kHz Aperture Delay 10 10 ns typ Aperture Jitter 30 30 ps typ Full Power Bandwidth 6.5 6.5 MHz typ @ 3 dB

DC ACCURACY

Resolution 8 8 Bits Integral Nonlinearity ± 0.5 ±0.5 LSB max Differential Nonlinearity ± 0.5 ± 0.5 LSB max Guaranteed No Missed Codes to Eight Bits Offset Error ± 0.5 ±0.5 LSB max Gain Error ± 0.5 ±0.5 LSB max Total Unadjusted Error (TUE) ± 0.5 ±0.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

0 to V

V DC Leakage Current ± 1 ± 1 µA max Input Capacitance 30 30 pF typ

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

Input Current, I Input Current, IIN, CS Pin ± 1 ± 1 µA typ Input Capacitance, C

INH

INL

, SCLK Pin ± 1 ± 1 µA max Typically 10 nA, V

2.4 2.4 V min

0.8 0.8 V max VDD = 5 V

0.4 0.4 V max V

= 3 V

10 10 pF max

= 0 V or V

LOGIC OUTPUTS

Output High Voltage, V Output Low Voltage, V Floating-State Leakage Current ±10 ±10 µA max Floating-State Output Capacitance

VDD – 0.2 VDD – 0.2 V min I

0.4 0.4 V max I

10 10 pF max

= 200 µA; VDD = 2.7 V to 5.25 V

SOURCE

= 200 µA

SINK

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 800 800 ns max 16 SCLK Cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 400 400 ns max Throughput Rate 1 1 MSPS max See Serial Interface Section

POWER REQUIREMENTS

2.7/5.25 2.7/5.25 V min/max Digital I/Ps = 0 V or V

Normal Mode (Static) 2 2 mA typ VDD = 4.75 V to 5.25 V; SCLK On or Off

11mA typ V

Normal Mode (Operational) 3.5 3.5 mA max V

1.6 1.6 mA max V

= 2.7 V to 3.6 V; SCLK On or Off

= 4.75 V to 5.25 V; f

= 2.7 V to 3.6 V; f

SAMPLE

= 1 MSPS

Full Power-Down Mode 1 1 µA max SCLK Off

Power Dissipation

Normal Mode (Operational) 17.5 17.5 mW max VDD = 5 V; f

80 80 µA max SCLK On

4.8 4.8 mW max V

= 3 V; f

SAMPLE

= 1 MSPS = 1 MSPS

Full Power-Down 5 5 µW max VDD = 5 V; SCLK Off

NOTES

Temperature ranges as follows: A Version: –40°C to +85°C; S Version: –55°C to +125°C.

Operational from VDD = 2.0 V, with input high voltage, V

See Terminology section.

Guaranteed by characterization.

See Power vs. Throughput Rate section.

Speciﬁcations subject to change without notice.

= 1.8 V min.

INH

REV. D–4–

AD7476/AD7477/AD7478

TIMING SPECIFICATIONS

Limit at T

AD7476/AD7477/AD7478

Parameter 3 V

SCLK

10 10 kHz min

1, 2

(VDD = 2.35 V to 5.25 V, TA = T

, T

MIN

MAX

to T

MIN

, unless otherwise noted.)

MAX

Unit Description

20 20 MHz max A Version 12 12 MHz max B Version

CONVERT

QUIET

16 × t

SCLK

16 × t

SCLK

50 50 ns min Minimum Quiet Time Required between Bus Relinquish and

Start of Next Conversion

10 10 ns min Minimum CS Pulsewidth 10 10 ns min CS to SCLK Setup Time 20 20 ns max Delay from CS until SDATA Three-State Disabled 40 20 ns max Data Access Time after SCLK Falling Edge, A Version 70 20 ns max Data Access Time after SCLK Falling Edge, B Version

POWER-UP

NOTES

Guaranteed by characterization. All input signals are speciﬁed with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

A Version timing specifications apply to the AD7477 S Version and AD7478 S Version; B Version timing specifications apply to the AD7476 S Version.

3 V specifications apply from VDD = 2.7 V to 3.6 V for A Version; 3 V specifications apply from VDD = 2.35 V to 3.6 V for B Version; 5 V specifications apply from VDD = 4.75 V to 5.25 V.

Mark/Space ratio for the SCLK input is 40/60 to 60/40.

Measured with the load circuit of Figure 1 and deﬁned as the time required for the output to cross 0.8 V or 2.0 V.

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish time of the part and is independent of the bus loading.

See Power-Up Time section.

Speciﬁcations subject to change without notice.

0.4 × t

SCLK

0.4 × t

SCLK

ns min SCLK Low Pulsewidth

ns min SCLK High Pulsewidth 10 10 ns min SCLK to Data Valid Hold Time 10 10 ns min SCLK Falling Edge to SDATA High Impedance 25 25 ns max SCLK Falling Edge to SDATA High Impedance

11µs typ Power-Up Time from Full Power-Down

REV. D

TO OUTPUT

50pF

200␮A

1.6V

Figure 1. Load Circuit for Digital Output Timing Speciﬁcations

–5–

AD7476/AD7477/AD7478

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to GND . . . . . . . . –0.3 V to V

+ 0.3 V

Digital Input Voltage to GND . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Output Voltage to GND . . . . . . –0.3 V to V

Input Current to Any Pin Except Supplies

. . . . . . . . ± 10 mA

+ 0.3 V

Operating Temperature Range

Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

Military (S Version) . . . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

SOT-23 Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 230°C/W

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 92°C/W

Lead Temperature, Soldering

Reflow (10 sec to 30 sec) . . . . . . . . . . . . . . . . 235 (0/+5)°C

Pb-Free Temperature Soldering

Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 (0/+5)°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kV

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speciﬁcation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Model Range Error (LSB)

Temperature Linearity Package Branding

Option

Information

AD7476ART-500RL7 –40°C to +85°C ± 1 typ RT-6 CEA AD7476ART-REEL –40°C to +85°C ± 1 typ RT-6 CEA AD7476ART-REEL7 –40°C to +85°C ± 1 typ RT-6 CEA AD7476ARTZ-500RL7 AD7476ARTZ-REEL AD7476ARTZ-REEL7

–40°C to +85°C ± 1 typ RT-6 CEA –40°C to +85°C ± 1 typ RT-6 CEA

–40°C to +85°C ± 1 typ RT-6 CEA AD7476BRT-REEL –40°C to +85°C ± 1.5 max RT-6 CEB AD7476BRT-REEL7 –40°C to +85°C ± 1.5 max RT-6 CEB AD7476BRTZ-REEL AD7476BRTZ-REEL7

–40°C to +85°C ± 1.5 max RT-6 CEB

–40°C to +85°C ± 1.5 max RT-6 CEB AD7476SRT-500RL7 –55°C to +125°C ±1.5 max RT-6 CES AD7476SRT-R2 –55°C to +125°C ± 1.5 max RT-6 CES AD7476SRT-REEL –55°C to +125°C ±1.5 max RT-6 CES AD7476SRT-REEL7 –55°C to +125°C ±1.5 max RT-6 CES AD7476SRTZ-500RL7 AD7476SRTZ-R2 AD7476SRTZ-REEL AD7476SRTZ-REEL7

–55°C to +125°C ±1.5 max RT-6 CES

–55°C to +125°C ±1.5 max RT-6 CES AD7477ART-500RL7 –40°C to +85°C ± 1 max RT-6 CFA AD7477ART-REEL –40°C to +85°C ± 1 max RT-6 CFA AD7477ART-REEL7 –40°C to +85°C ± 1 max RT-6 CFA AD7477SRT-500RL7 –55°C to +125°C ±1 max RT-6 CFS AD7477SRT-R2 –55°C to +125°C ± 1 max RT-6 CFS AD7477SRT-REEL –55°C to +125°C ±1 max RT-6 CFS AD7477SRT-REEL7 –55°C to +125°C ±1 max RT-6 CFS AD7478ART-500RL7 –40°C to +85°C ± 0.5 max RT-6 CJA AD7478ART-REEL –40°C to +85°C ± 0.5 max RT-6 CJA AD7478ART-REEL7 –40°C to +85°C ± 0.5 max RT-6 CJA AD7478SRT-500RL7 –55°C to +125°C ±0.5 max RT-6 CJS AD7478SRT-R2 –55°C to +125°C ± 0.5 max RT-6 CJS AD7478SRT-REEL7 –55°C to +125°C ±0.5 max RT-6 CJS EVAL-AD7476CB EVAL-AD7477CB

EVAL-CONTROL BRD2

NOTES

Linearity Error here refers to integral linearity error.

RT = SOT-23.

Z = Pb free.

This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.

This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, you need to order the particular ADC evaluation board, e.g., EVAL-AD7476CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See relevant evaluation board application note for more information.

Evaluation Board Evaluation Board

Control Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7476/AD7477/AD7478 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. D–6–

PIN CONFIGURATION

AD7476/AD7477/AD7478

GND

AD7476/

AD7477/

AD7478

TOP VIEW

(Not to Scale)

SDATA

SCLK

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

Power Supply Input. The VDD range for the AD7476/AD7477/AD7478 is from 2.35 V to 5.25 V.

2GND Analog Ground. Ground reference point for all circuitry on the AD7476/AD7477/AD7478. All analog

input signals should be referred to this GND voltage.

Analog Input. Single-ended analog input channel. The input range is 0 V to VDD.

4 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock

input is also used as the clock source for the AD7476/AD7477/AD7478’s conversion process.

5 SDATA Data Out. Logic output. The conversion result from the AD7476/AD7477/AD7478 is provided on

this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7476 consists of four leading zeros followed by the 12 bits of conversion data, which is provided MSB ﬁrst; the data stream from the AD7477 consists of four leading zeros followed by the 10 bits of conversion data, followed by two trailing zeros, which is also provided MSB first; the data stream from the AD7478 consists of four leading zeros followed by the eight bits of conversion data, followed by four trailing zeros, which is provided MSB first.

6 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the AD7476/AD7477/AD7478 and framing the serial data transfer.

REV. D

–7–

AD7476/AD7477/AD7478

TERMINOLOGY Integral Nonlinearity

This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7476/ AD7477, the endpoints of the transfer function are zero scale, a point 1/2 LSB below the ﬁrst code transition, and full scale, a point 1/2 LSB above the last code transition. For the AD7478, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the ﬁrst code transition (00 . . . 000) to (00 . . . 001) from the ideal (i.e., AGND + 0.5 LSB). For the AD7478, this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal (i.e., AGND + 1 LSB).

Gain Error

For the AD7476/AD7477, this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e.,

– 1.5 LSB) after the offset error has been adjusted out. For

REF

the AD7478, this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., V

– 1 LSB)

REF

after the offset error has been adjusted.

Track-and-Hold Acquisition Time

The track-and-hold ampliﬁer returns into track mode after the end of conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold ampliﬁer to reach its ﬁnal value, within ±0.5 LSB, after the end of conversion. See the Serial Interface Timing section for more detail.

Signal-to-(Noise + Distortion) Ratio

This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f

/2), excluding dc.

The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Total Unadjusted Error

This is a comprehensive specification that includes gain error, linearity error, and offset error.

Total Harmonic Distortion (THD)

Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the AD7476/AD7477/AD7478, it is deﬁned as:

THD

() log

dB =

VVVVV

()

++++

223242526

where V1 is the rms amplitude of the fundamental and V2, V3,

, V5, and V6 are the rms amplitudes of the second through the

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is deﬁned as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f

/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this speciﬁcation is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and (fa – fb), while the third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).

The AD7476/AD7477/AD7478 are tested using the CCIF standard where two input frequencies are used, fa = 498.7 kHz and fb = 508.7 kHz. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are speciﬁed separately. The calculation of the intermodulation distortion is as per the THD speciﬁcation where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in dB.

Thus for a 12-bit converter, this is 74 dB; for a 10-bit converter it is 62 dB; and for an 8-bit converter it is 50 dB.

REV. D–8–

FREQUENCY – kHz

–10

050

SNR – dB

150 200 250 300 350 400 450 500100

–20

–30

–40

–50

–60

–70

–80

–90

8192 POINT FFT f

SAMPLE

= 1MSPS

= 100kHz

SINAD = 49.82dB THD = –75.22dB SFDR = –67.78dB

INPUT FREQUENCY – Hz

–69.0

10k

SINAD – dB

–69.5

–70.0

–70.5

–71.0

–71.5

–72.0

–72.5

100k 1M

VDD = 2.35V

VDD = 2.7V

VDD = 5.25V

VDD = 4.75V

VDD = 3.6V

SCLK = 12MHz

–15

–35

–55

SNR – dB

–75

–95

Typical Performance Characteristics–AD7476/AD7477/AD7478

8192 POINT FFT

= 1MSPS

SAMPLE

= 100kHz

SINAD = 71.67dB THD = –81.00dB SFDR = –81.63dB

–115

50 100 150 200 250 300 350 400 450 500

FREQUENCY – kHz

TPC 1. AD7476 Dynamic Performance at 1 MSPS

–15

8192 POINT FFT

= 600kSPS

–15

–35

–55

SNR – dB

–75

–95

–115

50 100 150 200 250 300

FREQUENCY – kHz

SAMPLE

= 100kHz

SINAD = 71.71dB THD = –80.88dB SFDR = –83.23dB

TPC 2. AD7476 Dynamic Performance at 600 kSPS

–10

–20

–30

–40

–50

SNR – dB

–60

–70

–80

–90

–100

TPC 3. AD7477 Dynamic Performance at 1 MSPS

50 100 150 200 250 300 350 400 450 500

FREQUENCY – kHz

8192 POINT FFT f

= 1MSPS

SAMPLE

= 100kHz

SINAD = 61.66dB THD = –80.64dB SFDR = –85.75dB

REV. D

TPC 4. AD7478 Dynamic Performance at 1 MSPS

–66

–67

–68

–69

–70

SINAD – dB

–71

–72

–73

10k

SCLK = 20MHz

INPUT FREQUENCY – Hz

VDD = 5.25V

100k 1M

VDD = 2.35V

VDD = 2.7V

VDD = 4.75V

VDD = 3.6V

TPC 5. AD7476 SINAD vs. Input Frequency at 993 kSPS

TPC 6. AD7476 SINAD vs. Input Frequency at 605 kSPS

–9–

AD7476/AD7477/AD7478

CIRCUIT INFORMATION

The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit, and 8-bit, fast, micropower, single-supply ADCs. The parts can be operated from a 2.35 V to 5.25 V supply. When operated from either a 5 V supply or a 3 V supply, the AD7476/AD7477/AD7478 are capable of throughput rates of 1 MSPS when provided with a 20 MHz clock.

The AD7476/AD7477/AD7478 provide the user with an on-chip, track-and-hold ADC, and a serial interface housed in a tiny 6-lead SOT-23 package, which offers the user considerable space saving advantages over alternative solutions. The serial clock input accesses data from the part and also provides the clock source for the successive-approximation ADC. The analog input range is 0 V to V

. An external reference is not required

for the ADC, nor is there a reference on-chip. The reference for the AD7476/AD7477/AD7478 is derived from the power supply and thus gives the widest dynamic input range.

The AD7476/AD7477/AD7478 also feature a power-down option to save power between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section.

CONVERTER OPERATION

The AD7476/AD7477/AD7478 are successive-approximation analog-to-digital converters based around a charge redistribution DAC. Figures 2 and 3 show simpliﬁed schematics of the ADC. Figure 2 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on V

ADC TRANSFER FUNCTION

The output coding of the AD7476/AD7477/AD7478 is straight binary. For the AD7476/AD7477, designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB, and so on). The LSB size for the AD7476

/4096 and the LSB size for the AD7477 is VDD/1024. The

is V

ideal transfer characteristic for the AD7476/AD7477 is shown in Figure 4.

For the AD7478, designed code transitions occur midway between successive integer LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size for the AD7478 is V

/256. The ideal transfer

characteristic for the AD7478 is shown in Figure 5.

111 ... 111

111 ... 110

111 ... 000

ADC CODE

011 ... 111

000 ... 010

000 ... 001

000 ... 000

0.5LSB

1LSB = VDD/4096 (AD7476) 1LSB = V

ANALOG INPUT

/1024 (AD7477)

ⴙVDD–1.5LSB

Figure 4. Transfer Characteristic for the AD7476/AD7477

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

AGND

SAMPLING

CAPACITOR

ACQUISITION

PHASE

VDD/2

SW1

COMPARATOR

SW2

Figure 2. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 3), SW2 will open and SW1 will move to Position B, causing the comparator to become unbalanced. The Control Logic and the Charge Redistribution DAC are used to add and subtract ﬁxed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The Control Logic generates the ADC output code. Figures 4 and 5 show the ADC transfer function.

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

AGND

SAMPLING

CAPACITOR

CONVERSION

PHASE

VDD/2

SW1

COMPARATOR

SW2

Figure 3. ADC Conversion Phase

111 ... 111

111 ... 110

111 ... 000

ADC CODE

011 ... 111

000 ... 010

000 ... 001

000 ... 000

1LSB

1LSB = VDD/256 (AD7478)

ⴙVDD–1LSB

ANALOG INPUT

Figure 5. Transfer Characteristic for AD7478

TYPICAL CONNECTION DIAGRAM

Figure 6 shows a typical connection diagram for the AD7476/ AD7477/AD7478. V such, V

should be well decoupled. This provides an analog

input range of 0 V to V

is taken internally from VDD and as

REF

. The conversion result is output in a

16-bit word with four leading zeros followed by the MSB of the 12-bit, 10-bit, or 8-bit result. The 10-bit result from the AD7477 will be followed by two trailing zeros. The 8-bit result from the AD7478 will be followed by four trailing zeros.

REV. D–10–

AD7476/AD7477/AD7478

Alternatively, because the supply current required by the AD7476/AD7477/AD7478 is so low, a precision reference can be used as the supply source to the AD7476/AD7477/AD7478. A REF19x voltage reference (REF195 for 5 V, or REF193 for 3 V) can be used to supply the required voltage to the ADC (see Figure 6). This conﬁguration is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V or 3 V (e.g., 15 V). The REF19x will output a steady voltage to the AD7476/AD7477/AD7478. If the low dropout REF193 is used, the current it typically needs to supply to the AD7476/AD7477/AD7478 is 1 mA. When the ADC is converting at a rate of 1 MSPS, the REF193 will need to supply a maximum of 1.6 mA to the AD7476/AD7477/AD7478. The load regulation of the REF193 is typically 10 ppm/mA (REF193, V

5 V), which results in an error of 16 ppm (48 µV) for the 1.6 mA drawn from it. This corresponds to a 0.065 LSB error for the AD7476 with V

= 3 V from the REF193, a 0.016 LSB error for

the AD7477, and a 0.004 LSB error for the AD7478. For applications where power consumption is of concern, the Power-Down mode of the ADC and the Sleep mode of the REF19x reference should be used to improve power performance. See the Modes of Operation section.

680nF

0V TO V

INPUT

SCLK

SDATA

REF193

10␮F 0.1␮F

SERIAL

INTERFACE

1mA

1␮F

0.1␮F

TANT

AD7476/ AD7477/

GND

AD7478

5V SUPPLY

␮C/␮P

Figure 6. REF193 as Power Supply to AD7476/AD7477/ AD7478

Table I provides some typical performance data with various references used as a V

source with a low frequency analog

input. Under the same setup conditions, the references were compared and the AD780 proved the optimum reference.

Table I.

Reference Tied AD7476 SNR Performance to V

1 kHz Input (dB)

AD780 @ 3 V 71.17 REF193 70.4

AD780 @ 2.5 V 71.35 REF192 70.93 AD1582 70.05

Analog Input

Figure 7 shows an equivalent circuit of the analog input structure of the AD7476/AD7477/AD7478. The two diodes D1 and D2 provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV. This will cause these diodes to become forward-biased and start conducting current into

the substrate. These diodes can conduct a maximum of 10 mA without causing irreversible damage to the part. The capacitor C1 in Figure 7 is typically about 4 pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of a switch. This resistor is typically about 100 Ω. The capacitor C2 is the ADC sampling capacitor and typically has a capacitance of 30 pF. For ac applications, removing high frequency components from the analog input signal is recommended by use of a band-pass ﬁlter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will signiﬁcantly affect the ac performance of the ADC. This may necessitate the use of an input buffer ampliﬁer. The choice of the op amp will be a function of the particular application.

4pF

CONVERSION PHASE - SWITCH OPEN TRACK PHASE - SWITCH CLOSED

30pF

Figure 7. Equivalent Analog Input Circuit

When no ampliﬁer is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The THD will increase as the source impedance increases and performance will degrade. Figure 8 shows a graph of the total harmonic distortion versus source impedance for different analog input frequencies when using a supply voltage of 2.7 V and sampling at a rate of 605 kSPS. Figures 9 and 10 each show a graph of the total harmonic distortion versus analog input signal frequency for various supply voltages while sampling at 993 kSPS with an SCLK frequency of 20 MHz and 605 kSPS with an SCLK frequency of 12 MHz, respectively.

–10

–20

–30

–40

–50

THD – dB

–60

–70

–80

–90

–100

1 10k

= 300kHz

SOURCE IMPEDANCE – ⍀

100 1k

= 10kHz

VDD = 2.7V

= 200kHz

= 605kSPS

= 100kHz

Figure 8. THD vs. Source Impedance for Various Analog Input Frequencies

REV. D

–11–

AD7476/AD7477/AD7478

–50

–55

–60

–65

–70

THD – dB

–75

–80

–85

–90

10k

VDD = 5.25V

INPUT FREQUENCY – Hz

100k 1M

VDD = 2.35V

VDD = 2.7V

VDD = 4.75V

VDD = 3.6V

Figure 9. THD vs. Analog Input Frequency, fS = 993 kSPS

–72

–74

–76

–78

THD – dB

–80

–82

–84

10k

INPUT FREQUENCY – Hz

100k 1M

VDD = 2.35V

VDD = 2.7V

VDD = 4.75V

VDD = 5.25V

VDD = 3.6V

Figure 10. THD vs. Analog Input Frequency, fS = 605 kSPS

Digital Inputs

The digital inputs applied to the AD7476/AD7477/AD7478 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not

restricted by the V

+ 0.3 V limit as on the analog inputs. For

example, if the AD7476/AD7477/AD7478 were operated with a

of 3 V, then 5 V logic levels could be used on the digital

inputs. However, it is important to note that the data output on SDATA will still have 3 V logic levels when V advantage of SCLK and CS not being restricted by the V

= 3 V. Another

0.3 V limit is the fact that power supply sequencing issues are avoided. If CS or SCLK is applied before V

, there is no risk of

latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to V

MODES OF OPERATION

The mode of operation of the AD7476/AD7477/AD7478 is selected by controlling the (logic) state of the CS signal during a conversion. There are two possible modes of operation, Normal mode and Power-Down mode. The point at which CS is pulled high after the conversion has been initiated will determine whether or not the AD7476/AD7477/AD7478 will enter Power-Down mode. Similarly, if already in power-down, CS can control whether the device will return to normal operation or remain in power-down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for different application requirements.

Normal Mode

This mode is intended for fastest throughput rate performance, as the user does not have to worry about any power-up times with the AD7476/AD7477/AD7478 remaining fully powered all the time. Figure 11 shows the general diagram of the operation of the AD7476/AD7477/AD7478 in this mode.

The conversion is initiated on the falling edge of CS as described in the Serial Interface section. To ensure the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the tenth SCLK falling edge, but before the sixteenth SCLK falling edge, the part will remain powered up but the conversion will be terminated and SDATA will go back into three-state. Sixteen serial clock cycles are required to complete the conversion and access the complete

SCLK

SDATA

SCLK

SDATA

4 LEADING ZEROS + CONVERSION RESULT

Figure 11. Normal Mode Operation

THREE-STATE

Figure 12. Entering Power-Down Mode

REV. D–12–

11016 161

SCLK

SDATA

THE PART BEGINS TO POWER UP

THE PART IS FULLY POWERED UP WITH V

FULLY ACQUIRED

INVALID DATA VALID DATA

Figure 13. Exiting Power-Down Mode

AD7476/AD7477/AD7478

conversion result. CS may idle high until the next conversion or may idle low until CS returns high sometime prior to the next conversion (effectively idling CS low).

Once a data transfer is complete (SDATA has returned to threestate), another conversion can be initiated after the quiet time, t

, has elapsed by again bringing CS low.

QUIET

Power-Down Mode

This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and the ADC is then powered down for a relatively long duration between these bursts of several conversions. When the AD7476/AD7477/AD7478 is in powerdown, all analog circuitry is powered down.

To enter power-down, the conversion process must be interrupted by bringing CS high any time after the second falling edge of SCLK and before the tenth falling edge of SCLK, as shown in Figure 12. Once CS has been brought high in this window of SCLKs, the part will enter power-down and the conversion that was initiated by the falling edge of CS will be terminated and SDATA will go back into three-state. If CS is brought high before the second SCLK falling edge, the part will remain in Normal mode and will not power down. This will avoid accidental power-down due to glitches on the CS line.

To exit this mode of operation and power up the AD7476/ AD7477/AD7478 again, a dummy conversion is performed. On the falling edge of CS, the device will begin to power up, and will continue to power up as long as CS is held low until after the falling edge of the tenth SCLK. The device will be fully powered up once 16 SCLKs have elapsed and, as shown in Figure 13, valid data will result from the next conversion. If CS is brought high before the tenth falling edge of SCLK, the AD7476/ AD7477/AD7478 will again go back into power-down. This avoids accidental power-up due to glitches on the CS line or an inadvertent burst of eight SCLK cycles while CS is low. So although the device may begin to power up on the falling edge of CS, it will again power down on the rising edge of CS as long as it occurs before the tenth SCLK falling edge.

Power-Up Time

The power-up time of the AD7476/AD7477/AD7478 is typically 1 ␮s, which means that with any frequency of SCLK up to 20 MHz, one dummy cycle will always be sufﬁcient to allow the device to power up. Once the dummy cycle is complete, the ADC will be fully powered up and the input signal will be acquired properly. The quiet time (t

) must still be allowed from the

QUIET

point at which the bus goes back into three-state after the dummy

REV. D

–13–

conversion, to the next falling edge of CS. When running at 1MSPS throughput rate, the AD7476/AD7477/AD7478 will power up and acquire a signal within ±0.5 LSB in one dummy cycle, i.e., 1 ␮s.

When powering up from the Power-Down mode with a dummy cycle, as in Figure 13, the track-and-hold that was in Hold mode while the part was powered down returns to Track mode after the ﬁrst SCLK edge the part receives after the falling edge of CS. This is shown as Point A in Figure 13. Although at any SCLK frequency one dummy cycle is sufﬁcient to power up the device and acquire V

, it does not necessarily mean that a full

dummy cycle of 16 SCLKs must always elapse to power up the device and fully acquire V

; 1 µs will be sufﬁcient to power up the

device and acquire the input signal. If, for example, a 5 MHz SCLK frequency were applied to the ADC, the cycle time would be 3.2 µs. In one dummy cycle, 3.2 µs, the part would be powered up and V

fully acquired. However, after 1 µs with a 5 MHz

SCLK, only ﬁve SCLK cycles would have elapsed. At this stage, the ADC would be fully powered up and the signal acquired. So, in this case, the CS can be brought high after the tenth SCLK falling edge and brought low again after a time t

QUIET

to initiate

the conversion.

When power supplies are ﬁrst applied to the AD7476/AD7477/ AD7478, the ADC may power up in either Power-Down mode or Normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, if it is intended to keep the part in the Power-Down mode while not in use and the user wants the part to power up in Power-Down mode, the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as that shown in Figure 12. Once supplies are applied to the AD7476/AD7477/AD7478, the power-up time is the same as that when powering up from the Power-Down mode. It takes approximately 1 µs to fully power up if the part powers up in Normal mode. It is not necessary to wait 1 µs before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the ﬁrst valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. As mentioned earlier, when powering up from the Power-Down mode, the part will return to track upon the ﬁrst SCLK edge applied after the falling edge of CS. However, when the ADC powers up initially after supplies are applied, the track-and-hold will already be in track. This means that if the ADC powers up in the desired mode of operation, and a dummy cycle is not required to change mode, then a dummy cycle is not required to place the track-and-hold into track.

AD7476/AD7477/AD7478

POWER VS. THROUGHPUT RATE

By using the Power-Down mode on the AD7476/AD7477/AD7478 when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 14 shows how as the throughput rate is reduced, the device remains in its power-down state longer, and the average power consumption over time drops accordingly.

For example, if the AD7476/AD7477/AD7478 is operated in a continuous sampling mode with a throughput rate of 100 kSPS and a SCLK of 20 MHz (V

= 5 V), and the device is placed

in the Power-Down mode between conversions, then the power consumption is calculated as follows. The power dissipation during normal operation is 17.5 mW (V

= 5 V). If the

power-up time is one dummy cycle, i.e., 1 µs, and the remaining conversion time is another cycle, i.e., 1 µs, then the AD7476/ AD7477/AD7478 can be said to dissipate 17.5 mW for 2 µs during each conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 µs and the average power dissipated during each cycle is (2/10) × (17.5 mW) = 3.5 mW. If V

= 3 V, SCLK = 20 MHz, and the device is again in Power-Down mode between conversions, the power dissipation during normal operation is 4.8 mW. The AD7476/AD7477/AD7478 can now be said to dissipate 4.8 mW for 2 µs during each conversion cycle. With a throughput rate of 100 kSPS, the average power dissipated during each cycle is (2/10) × (4.8 mW) = 0.96 mW. Figure 14 shows the power versus throughput rate when using the Power-Down mode between conversions with both 5 V and 3 V supplies.

100

POWER – mW

0.1

VDD = 5V, SCLK = 20MHz

VDD = 3V, SCLK = 20MHz

The Power-Down mode is intended for use with throughput rates of approximately 333 kSPS and under, because at higher sampling rates power is not saved by using the Power-Down mode.

SERIAL INTERFACE

Figures 15, 16, and 17 show the detailed timing diagrams for serial interfacing to the AD7476, AD7477, and AD7478, respectively. The serial clock provides the conversion clock and also controls the transfer of information from the AD7476/ AD7477/AD7478 during conversion.

The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into Hold mode, takes the bus out of three-state, and the analog input is sampled at this point. The conversion is also initiated at this point and will require sixteenth SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the track-and-hold will go back into track on the next SCLK rising edge as shown in Figures 15, 16, and 17 at Point B. On the sixteenth SCLK falling edge, the SDATA line will go back into three-state. If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion will be terminated and the SDATA line will go back into three-state; otherwise, SDATA returns to three-state on the sixteenth SCLK falling edge as shown in Figures 15, 16, and 17. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7476/AD7477/AD7478. CS going low provides the ﬁrst leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges, beginning with the second leading zero. Thus the ﬁrst falling clock edge on the serial clock has the ﬁrst leading zero provided and also clocks out the second leading zero. The ﬁnal bit in the data transfer is valid on the sixteenth falling edge, having been clocked out on the previous (fifteenth) falling edge. In applications with a slower SCLK, it is possible to read in data on each SCLK rising edge, i.e., although the first leading zero will have to be read on the first SCLK falling edge after the CS falling edge. Therefore, the first rising edge of SCLK after the CS falling edge will provide the second leading zero and the fifteenth rising SCLK edge will have DB0 provided or the final zero for the AD7477 and AD7478. This may not work with most microcontrollers/DSPs, but could possibly be used with FPGAs and ASICs.

0.01 0

50 100 150 200 250 300 350

THROUGHPUT RATE – kSPS

Figure 14. Power vs. Throughput Rate

REV. D–14–

AD7476/AD7477/AD7478

SCLK

SDATA

QUIET

THREE-STATE

12345 13141516

4 LEADING ZEROS

THREE-

STATE

ZERO ZERO ZEROZ DB11 DB10 DB2 DB1 DB0

CONVERT

SCLK

SDATA

QUIET

THREE-STATE

12345 13141516

2 TRAILING

ZEROS

4 LEADING ZEROS

THREE-

STATE

ZERO ZERO ZEROZ DB9 DB8 DB0 ZERO ZERO

CONVERT

SCLK

SDATA

QUIET

THREE-STATE

1234 1314 15 16

4 LEADING ZEROS

THREE-

STATE

ZERO ZERO ZEROZ DB7 ZERO ZERO

CONVERT

8 BITS OF DATA

ZERO ZERO

4 TRAILING ZEROS

Figure 15. AD7476 Serial Interface Timing Diagram

Figure 16. AD7477 Serial Interface Timing Diagram

Figure 17. AD7478 Serial Interface Timing Diagram

REV. D

–15–

AD7476/AD7477/AD7478

MICROPROCESSOR INTERFACING

The serial interface on the AD7476/AD7477/AD7478 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7476/AD7477/AD7478 with some of the more common microcontroller and DSP serial interface protocols.

AD7476/AD7477/AD7478 to TMS320C5x/C54x Interface

The serial interface on the TMS320C5x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7476/ AD7477/AD7478. The CS input allows easy interfacing between the TMS320C5x/C54x and the AD7476/AD7477/AD7478 without any glue logic required. The serial port of the TMS320C5x/C54x is set up to operate in burst mode with internal CLKX (Tx serial clock) and FSX (Tx frame sync). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The format bit, FO, may be set to 1 to set the word length to eight bits, in order to implement the Power-Down mode on the AD7476/AD7477/AD7478. The connection diagram is shown in Figure 18. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the TMS320C5x/C54x provides equidistant sampling.

AD7476/ AD7477/

AD7478*

SCLK

SDATA

*ADDITIONAL PINS OMITTED FOR CLARITY

TMS320C5x/

TMS320C54x*

CLKX

CLKR

FSX

FSR

Figure 18. Interfacing to the TMS320C5x/C54x

AD7476/AD7477/AD7478 to ADSP-21xx Interface

The ADSP-21xx family of DSPs are interfaced directly to the AD7476/AD7477/AD7478 without any glue logic required. The SPORT control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing INVRFS = INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right Justify Data SLEN = 1111, 16-Bit Data-Words ISCLK = 1, Internal Serial Clock TFSR = RFSR = 1, Frame Every Word IRFS = 0 ITFS = 1

To implement the Power-Down mode, SLEN should be set to 0111 to issue an 8-bit SCLK burst. The connection diagram is shown in Figure 19. The ADSP-21xx has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in Alternate Framing mode and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to CS and as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC and, under certain conditions, equidistant sampling may not be achieved.

The timer registers, for example, are loaded with a value that will provide an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and therefore the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given (i.e., TX0 = AX0), the state of the SCLK is checked. The DSP will wait until the SCLK has gone high, low, and high before transmission will start. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data may be transmitted, or it may wait until the next clock edge.

For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, a SCLK of 2 MHz is obtained, and eight master clock periods will elapse for every one SCLK period. If the timer registers are loaded with the value 803, 100.5 SCLKs will occur between interrupts and subsequently between transmit instructions. This situation will result in nonequidistant sampling as the transmit instruction is occurring on an SCLK edge. If the number of SCLKs between interrupts is a whole integer ﬁgure of N, equidistant sampling will be implemented by the DSP.

AD7476/ AD7477/

AD7478*

SCLK

SDATA

*ADDITIONAL PINS OMITTED FOR CLARITY

ADSP-21xx*

SCLK

RFS

TFS

Figure 19. Interfacing to the ADSP-21xx

REV. D–16–

AD7476/AD7477/AD7478

AD7476/AD7477/AD7478 to DSP56xxx Interface

The connection diagram in Figure 20 shows how the AD7476/ AD7477/AD7478 can be connected to the SSI (Synchronous Serial Interface) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in Synchronous Mode (SYN bit in CRB =1) with internally generated word frame sync for both Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in CRB). Set the word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. To implement the Power-Down mode on the AD7476/AD7477/ AD7478, the word length can be changed to eight bits by setting bits WL1 = 0 and WL0 = 0 in CRA. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the DSP56xxx provides equidistant sampling.

AD7476/ AD7477/

AD7478*

SCLK

SDATA

*ADDITIONAL PINS OMITTED FOR CLARITY

DSP56xxx*

SCK

SRD

SC2

Figure 20. Interfacing to the DSP56xxx

AD7476/AD7477/AD7478 to MC68HC16 Interface

The Serial Peripheral Interface (SPI) on the MC68HC16 is conﬁgured for Master Mode (MSTR = 1), the Clock Polarity Bit (CPOL) = 1, and the Clock Phase Bit (CPHA) = 0. The SPI is conﬁgured by writing to the SPI Control Register (SPCR)—see the 68HC16 User Manual. The serial transfer will take place as a 16-bit operation when the SIZE bit in the SPCR register is set to SIZE = 1. To implement the Power-Down mode with an 8-bit transfer, set SIZE = 0. A connection diagram is shown in Figure 21.

AD7476/ AD7477/

AD7478*

SCLK

SDATA

*ADDITIONAL PINS OMITTED FOR CLARITY

MC68HC16*

SCLK/PMC2

MISO/PMC0

SS/PMC3

Figure 21. Interfacing to the MC68HC16

REV. D

–17–

AD7476/AD7477/AD7478

OUTLINE DIMENSIONS

6-Lead Plastic Surface-Mount Package [SOT-23]

(RT-6)

Dimensions shown in millimeters

2.90 BSC

1.60 BSC

1.30

1.15

0.90

0.15 MAX

1.90 BSC

0.50

0.30

4 5

0.95 BSC

2.80 BSC

1.45 MAX

SEATING PLANE

1 3

PIN 1

COMPLIANT TO JEDEC STANDARDS MO-178AB

0.22

0.08 10ⴗ

0.60

0ⴗ

0.45

0.30

REV. D–18–

AD7476/AD7477/AD7478

Revision History

Location Page

3/04—Data Sheet changed from REV. C to REV. D.

Added U.S. Patent number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to AD7476/AD7477/AD7478 to ADSP-21xx Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2/03—Data Sheet changed from REV. B to REV. C.

Change to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Change to TYPICAL CONNECTION DIAGRAM SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Change to Figure 8 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Change to Figure 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Change to Figure 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

OUTLINE DIMENSIONS updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

REV. D

–19–

C01024–0–3/04(D)

–20–

Datasheet AD7476 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ORDERING GUIDE

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

Differential Nonlinearity

Offset Error

Gain Error

Track-and-Hold Acquisition Time

Signal-to-(Noise + Distortion) Ratio

Total Unadjusted Error

Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise

Intermodulation Distortion

CIRCUIT INFORMATION

CONVERTER OPERATION

ADC TRANSFER FUNCTION

TYPICAL CONNECTION DIAGRAM

Analog Input

Digital Inputs

MODES OF OPERATION

Normal Mode

Power-Down Mode

Power-Up Time

POWER VS. THROUGHPUT RATE

SERIAL INTERFACE

MICROPROCESSOR INTERFACING

AD7476/AD7477/AD7478 to TMS320C5x/C54x Interface

AD7476/AD7477/AD7478 to ADSP-21xx Interface

AD7476/AD7477/AD7478 to DSP56xxx Interface

AD7476/AD7477/AD7478 to MC68HC16 Interface

OUTLINE DIMENSIONS

Revision History