Page 1
1 MSPS,
a
FEATURES
Fast Throughput Rate: 1 MSPS
Specified for V
Low Power:
4.5 mW Max at 1 MSPS with 3 V Supplies
10.5 mW Max at 1 MSPS with 5 V Supplies
Wide Input Bandwidth:
68 dB SNR at 300 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High-Speed Serial Interface SPI™/QSPI™/
MICROWIRE™/DSP-Compatible
On-Board Reference 2.5 V (AD7495 Only)
Standby Mode: 1 A Max
8-Lead SOIC and SOIC Packages
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High-Speed Modems
Optical Sensors
GENERAL DESCRIPTION
The AD7475/AD7495 are 12-bit high-speed, low-power,
successive-approximation ADCs. The parts operate from a single
2.7 V to 5.25 V power supply and feature throughput rates up to
1 MSPS. The parts contain a low-noise, wide bandwidth track/hold
amplifier that can handle input frequencies in excess of 1 MHz.
The conversion process and data acquisition are controlled using
CS and the serial clock allowing the devices to interface with
microprocessors or DSPs. The input signal is sampled on the
falling edge of CS and conversion is also initiated at this point.
There are no pipelined delays associated with the part.
The AD7475/AD7495 use advanced design techniques to achieve
very low power dissipation at high throughput rates. With 3 V
supplies and 1 MSPS throughput rate, the AD7475 consumes just
1.5 mA, while the AD7495 consumes 2 mA. With 5 V supplies
and 1 MSPS, the current consumption is 2.1 mA for the AD7475
and 2.6 mA for the AD7495.
The analog input range for the part is 0 V to REF IN. The 2.5 V
reference for the AD7475 is applied externally to the REF IN pin
while the AD7495 has an on-board 2.5 V reference. The conversion time is determined by the SCLK frequency.
MICROWIRE is a trademark of National Semiconductor Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
of 2.7 V to 5.25 V
DD
12-Bit ADCs
AD7475/AD7495
FUNCTIONAL BLOCK DIAGRAMS
V
DD
V
REF IN
V
REF OUT
IN
IN
T/H
AD7475
V
DD
T/H
BUF
2.5V
REFERENCE
AD7495
PRODUCT HIGHLIGHTS
1. High throughput with low power consumption. The
AD7475 offers 1 MSPS throughput rates with 4.5 mW
power consumption.
2. Single-supply operation with V
AD7495 operate from a single 2.7 V to 5.25 V supply. The
V
function allows the serial interface to connect directly
DRIVE
to either 3 V or 5 V processor systems independent of V
3. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the
conversion time to be reduced through the serial clock speed
increase. The part also features shutdown modes to maximize
power efficiency at lower throughput rates. This allows the
average power consumption to be reduced while not converting. Power consumption is 1 µA when in full shutdown.
4. No pipeline delay. The part features a standard successiveapproximation ADC with accurate control of the sampling
instant via a CS input and once off conversion control.
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
GND
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
GND
function. The AD7475/
DRIVE
SCLK
SDATA
CS
V
DRIVE
SCLK
SDATA
CS
V
DRIVE
DD
.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
Page 2
AD7475/AD7495–SPECIFICATIONS
1
(VDD = 2.7 V to 5.25 V, V
1
AD7475–SPECIFICATIONS
noted; TA = T
MIN
to T
Parameter A Version1B Version1Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio 68 68 dB min f
(SINAD)
Total Harmonic Distortion (THD) –75 –75 dB max f
Peak Harmonic or Spurious Noise –76 –76 dB max f
(SFDR)
Intermodulation Distortion (IMD)
Second Order Terms –78 –78 dB typ
Third Order Terms –78 –78 dB typ
Aperture Delay 10 10 ns typ
Aperture Jitter 50 50 ps typ
Full Power Bandwidth 8.3 8.3 MHz typ @ 3 dB
Full Power Bandwidth 1.3 1.3 MHz typ @ 0.1 dB
DC ACCURACY
Resolution 12 12 Bits
Integral Nonlinearity ± 1.5 ± 1 LSB max @ 5 V (typ @ 3 V)
± 0.5 ± 0.5 LSB typ @ 25°C
Differential Nonlinearity +1.5/–0.9 +1.5/–0.9 LSB max @ 5 V Guaranteed No Missed Codes to 12 Bits
± 0.5 ± 0.5 LSB typ @ 25°C
Offset Error ± 8 ± 8 LSB max Typically ± 2.5 LSB
Gain Error ± 3 ± 3LSB max
ANALOG INPUT
Input Voltage Ranges 0 to REF IN Volts
DC Leakage Current ± 1 ± 1 µA max
Input Capacitance 20 20 pF typ
REFERENCE INPUT
REF IN Input Voltage Range 2.5 2.5 Volts ± 1% for Specified Performance
DC Leakage Current ± 1 ± 1 µA max
Input Capacitance 20 20 pF typ
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C
INL
IN
IN
INH
2
V
– 1 V
DRIVE
DRIVE
0.4 0.4 V max
± 1 ± 1 µA max Typically 10 nA, VIN = 0 V or V
10 10 pF max
LOGIC OUTPUTS
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ± 10 ± 10 µA max
Floating-State Output Capacitance
OL
OH
0.4 0.4 V max I
2
10 10 pF max
V
– 0.2 V min I
DRIVE
Output Coding Straight (Natural) Binary
CONVERSION RATE
Conversion Time 800 800 ns max 16 SCLK Cycles with SCLK at 20 MHz
Track/Hold Acquisition Time 300 300 ns max Sine Wave Input
325 325 ns max Full-Scale Step Input
Throughput Rate 1 1 MSPS max See Serial Interface Section
POWER REQUIREMENTS
V
DD
V
DRIVE
I
DD
3
2.7/5.25 2.7/5.25 V min/max
2.7/5.25 2.7/5.25 V min/max
Normal Mode (Static) 750 750 A typ VDD = 2.7 V to 5.25 V. SCLK On or Off
Normal Mode (Operational) 2.1 2.1 mA max V
1.5 1.5 mA max V
Partial Power-Down Mode 450 450 µA typ f
Partial Power-Down Mode 100 100 µA max (Static)
Full Power-Down Mode 1 1 µA max SCLK On or Off
= 2.7 V to 5.25 V, REF IN = 2.5 V, f
DRIVE
, unless otherwise noted.)
MAX
– 1 V min
= 20 MHz unless otherwise
SCLK
= 300 kHz Sine Wave, f
IN
= 300 kHz Sine Wave, f
IN
= 300 kHz Sine Wave, f
IN
(typ @ 3 V)
= 200 µA; V
SOURCE
= 200 µA
SINK
DRIVE
Digital I/Ps = 0 V or V
= 4.75 V to 5.25 V. f
DD
= 2.7 V to 3.6 V. f
DD
= 100 kSPS
SAMPLE
= 1 MSPS
SAMPLE
= 1 MSPS
SAMPLE
= 1 MSPS
SAMPLE
DRIVE
= 2.7 V to 5.25 V
DRIVE
= 1 MSPS
SAMPLE
= 1 MSPS
SAMPLE
–2–
REV. A
Page 3
AD7475/AD7495
AD7475–SPECIFICATIONS (continued)
Parameter A Version1B Version1Unit Test Conditions/Comments
POWER REQUIREMENTS
(continued)
Power Dissipation
Normal Mode (Operational) 10.5 10.5 mW max VDD = 5 V. f
Partial Power-Down (Static) 500 500 W max V
Full Power-Down 5 5 W max V
NOTES
1
Temperature ranges as follows: A, B Versions: –40C to +85C.
2
Sample tested @ 25C to ensure compliance.
3
See Power Versus Throughput Rate section.
Specifications subject to change without notice.
3
= 1 MSPS
4.5 4.5 mW max V
300 300 W max V
= 3 V. f
DD
= 5 V
DD
= 3 V
DD
= 5 V
DD
SAMPLE
SAMPLE
= 1 MSPS
33W max VDD = 3 V
(VDD = 2.7 V to 5.25 V, V
AD7495–SPECIFICATIONS
1
T
, unless otherwise noted.)
MAX
Parameter A Version1B Version
= 2.7 V to 5.25 V, f
DRIVE
1
Unit Test Conditions/Comments
= 20 MHz unless otherwise noted; TA = T
SCLK
DYNAMIC PERFORMANCE
Signal to Noise + Distortion 68 68 dB min f
= 300 kHz Sine Wave, f
IN
SAMPLE
= 1 MSPS
(SINAD)
Total Harmonic Distortion (THD) –75 –75 dB max f
Peak Harmonic or Spurious Noise –76 –76 dB max f
= 300 kHz Sine Wave, f
IN
= 300 kHz Sine Wave, f
IN
SAMPLE
SAMPLE
= 1 MSPS
= 1 MSPS
(SFDR)
Intermodulation Distortion (IMD)
Second Order Terms –78 –78 dB typ
Third Order Terms –78 –78 dB typ
Aperture Delay 10 10 ns typ
Aperture Jitter 50 50 ps typ
Full Power Bandwidth 8.3 8.3 MHz typ @ 3 dB
Full Power Bandwidth 1.3 1.3 MHz typ @ 0.1 dB
DC ACCURACY
Resolution 12 12 Bits
Integral Nonlinearity ±1.5 ±1 LSB max @ 5 V (typ @ 3 V)
± 0.5 ±0.5 LSB typ @ 25°C
Differential Nonlinearity +1.5/–0.9 +1.5/–0.9 LSB max @ 5 V Guaranteed No Missed Codes to 12 Bits
(typ @ 3 V)
± 0.6 ±0.6 LSB typ @ 25°C
Offset Error ± 8 ± 8 LSB max Typically ±2.5 LSB
Gain Error ± 7 ± 7 LSB max Typically ±2.5 LSB
ANALOG INPUT
Input Voltage Ranges 0 to 2.5 0 to 2.5 Volts
DC Leakage Current ± 1 ± 1 µA max
Input Capacitance 20 20 pF typ
REFERENCE OUTPUT
REF OUT Output Voltage 2.4625/2.5375 2.4625/2.5375 V min/max
REF OUT Impedance 10 10 Ω typ
REF OUT Temperature Coefficient 50 50 ppm/C typ
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C
INL
IN
IN
INH
2
V
DRIVE
– 1 V
– 1 V min
DRIVE
0.4 0.4 V max
± 1 ± 1 µA max Typically 10 nA, VIN = 0 V or V
10 10 pF max
DRIVE
LOGIC OUTPUTS
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±10 ±10 µA max
Floating-State Output Capacitance
OH
OL
2
V
– 0.2 V min I
DRIVE
0.4 0.4 V max I
10 10 pF max
= 200 µA; VDD = 2.7 V to 5.25 V
SOURCE
= 200 µA
SINK
Output Coding Straight (Natural) Binary
MIN
to
REV. A
–3–
Page 4
AD7475/AD7495–SPECIFICATIONS
1
AD7495–SPECIFICATIONS (continued)
Parameter A Version1B Version1Unit Test Conditions/Comments
CONVERSION RATE
Conversion Time 800 800 ns max 16 SCLK Cycles with SCLK at 20 MHz
Track/Hold Acquisition Time 300 300 ns max Sine Wave Input
325 325 ns max Full-Scale Step Input
Throughput Rate 1 1 MSPS max See Serial Interface Section
POWER REQUIREMENTS
V
DD
V
DRIVE
I
DD
Normal Mode (Static) 1 1 mA typ VDD = 2.7 V to 5.25 V. SCLK On or Off
Normal Mode (Operational) 2.6 2.6 mA max V
Partial Power-Down Mode 650 650 µA typ f
Partial Power-Down Mode 230 230 µA max (Static)
Full Power-Down Mode 1 1 µA max (Static) SCLK On or Off
Power Dissipation
3
Normal Mode (Operational) 13 13 mW max VDD = 5 V. f
Partial Power-Down (Static) 1.15 1.15 mW max V
Full Power-Down 5 5 µW max V
NOTES
1
Temperature ranges as follows: A, B Versions: –40C to +85C.
2
Sample tested @ 25C to ensure compliance.
3
See Power Versus Throughput Rate section.
Specifications subject to change without notice.
2.7/5.25 2.7/5.25 V min/max
2.7/5.25 2.7/5.25 V min/max
Digital I/Ps = 0 V or V
= 4.75 V to 5.25 V. f
DD
2 2 mA max V
6 6 mW max V
690 690 µW max V
= 2.7 V to 3.6 V. f
DD
= 100 kSPS
SAMPLE
= 3 V. f
DD
= 5 V
DD
= 3 V
DD
= 5 V
DD
33µW max VDD = 3 V
SAMPLE
SAMPLE
DRIVE
SAMPLE
SAMPLE
= 1 MSPS
= 1 MSPS
= 1 MSPS
= 1 MSPS
TIMING SPECIFICATIONS
Limit at T
(VDD = 2.7 V to 5.25 V, V
1
otherwise noted.)
, T
MIN
MAX
= 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475); TA = T
DRIVE
MIN
to T
MAX
, unless
Parameter AD7475/AD7495 Unit Description
f
SCLK
2
10 kHz min
20 MHz max
t
CONVERT
t
QUIET
t
2
3
t
3
3
t
4
t
5
t
6
t
7
4
t
8
4
t
9
t
POWER-UP
16 × t
SCLK
800 ns max f
100 ns min Minimum Quiet Time Required between Conversions
10 ns min CS to SCLK Setup Time
22 ns max Delay from CS Until SDATA 3-State Disabled
40 ns max Data Access Time after SCLK Falling Edge
0.4 t
0.4 t
SCLK
SCLK
ns min SCLK Low Pulsewidth
ns min SCLK High Pulsewidth
10 ns min SCLK to Data Valid Hold Time
10 ns min SCLK Falling Edge to SDATA High Impedance
45 ns max SCLK Falling Edge to SDATA High Impedance
20 ns max CS Rising Edge to SDATA High Impedance
20 µs max Power-Up Time from Full Power-Down AD7475
t
SCLK
SCLK
= 1/f
SCLK
= 20 MHz
650 µs max Power-Up Time from Full Power-Down AD7495
NOTES
1
Sample tested at 25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t8 and t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t8 and t9, quoted in the timing characteristics are
the true bus relinquish time of the part and are independent of the bus loading.
Specifications subject to change without notice.
) and timed from a voltage level of 1.6 V.
DRIVE
–4–
REV. A
Page 5
AD7475/AD7495
CS
t
SCLK
SDATA
THREE-STATE
2
1
t
3
00
FOUR LEADING ZEROS
2
0
34
0
Figure 1. Serial Interface Timing Diagram
Timing Example 1
Having f
time of t
leaves t
300 ns for t
+ t
QUIET
= 20 MHz and a throughput of 1 MSPS gives a cycle
SCLK
+ 12.5(1/f
2
to be 365 ns. This 365 ns satisfies the requirement of
ACQ
. From Figure 2, t
ACQ
SCLK
) + t
= 1 µs. With t2 = 10 ns min, this
ACQ
comprises of 2.5(1/f
ACQ
, where t8 = 45 ns. This allows a value of 195 ns for t
satisfying the minimum requirement of 100 ns.
Timing Example 2
Having f
cycle time of t
= 5 MHz and a throughput of 315 KSPS, gives a
SCLK
CS
SCLK
+ 12.5(1/f
2
t
2
10ns
SCLK
1
) + t
= 3.174 s.
ACQ
2
34
12.5 (1/f
t
CONVERT
t
6
5
t
7
t
4
DB11 DB10
) + t
SCLK
QUIET
t
CONVERT
t
6
5
)
SCLK
B
13
With t
14
DB2
= 10 ns min, this leaves t
2
satisfies the requirement of 300 ns for t
is comprised of 2.5(1/f
a value of 119 ns for t
of 100 ns. As in this example and with other slower clock values,
8
,
the signal may already be acquired before the conversion is
15
16
t
5
DB1
t
8
DB0
THREE-STATE
) + t8 + t
SCLK
satisfying the minimum requirement
QUIET
t
QUIET
to be 664 ns. This 664 ns
acq
. From Figure 2, t
ACQ
, t8 = 45 ns. This allows
QUIET
complete, but it is still necessary to leave 100 ns minimum
between conversions. In Example 2 the signal should be
t
QUIET
fully acquired at approximately Point C in Figure 2.
B
13
1/THROUGHPUT
C
14
t
15
16
5
t
8
45ns
t
ACQUISITION
t
QUIET
ACQ
REV. A
Figure 2. Serial Interface Timing Example
TO OUTPUT
PIN
50pF
200A
C
L
200A
I
OL
1.6V
I
OH
Figure 3. Load Circuit for Digital Output Timing Specifications
–5–
Page 6
AD7475/AD7495
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
REF OUT
V
IN
GND
V
DD
CS
V
DRIVE
SDATASCLK
AD7495
ABSOLUTE MAXIMUM RATINGS
(TA = 25C unless otherwise noted)
1
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DRIVE
Analog Input Voltage to GND . . . . . . . . –0.3 V to V
+ 0.3 V
DD
Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V
V
to DVDD . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
DRIVE
Digital Output Voltage to GND . . . . . . –0.3 V to V
REF IN to GND . . . . . . . . . . . . . . . . . . –0.3 V to V
Input Current to Any Pin Except Supplies
2
. . . . . . . 10 mA
+ 0.3 V
DD
+ 0.3 V
DD
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . . . . . –40C to +85C
Storage Temperature Range . . . . . . . . . . . –65C to +150C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
SOIC, µSOIC Package, Power Dissipation . . . . . . . . 450 mW
Thermal Impedance . . . . . . . . . . . . . . 157C/W (SOIC)
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.9C/W (µSOIC)
Thermal Impedance . . . . . . . . . . . . . . . 56C/W (SOIC)
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.74C/W (µSOIC)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
PIN CONFIGURATIONS
AD7475 SOIC/SOIC
REF IN
V
GND
1
2
IN
3
4
AD7475
TOP VIEW
(Not to Scale)
8
V
DD
7
CS
6
V
DRIVE
SDATASCLK
5
AD7495 SOIC/SOIC
Linearity Package Branding
Model Range Error (LSB)
1
Option
2
Information
AD7495AR –40C to +85C ± 1.5 SO-8 AD7495AR
AD7495BR –40C to +85C ± 1 SO-8 AD7495BR
AD7495ARM –40C to +85C ± 1.5 RM-8 CCA
AD7495BRM –40C to +85C ± 1 RM-8 CCB
AD7475AR –40C to +85C ± 1.5 SO-8 AD7475AR
AD7475BR –40C to +85C ± 1 SO-8 AD7475BR
AD7475ARM –40C to +85C ± 1.5 RM-8 C9A
AD7475BRM –40C to +85C ± 1 RM-8 C9B
EVAL-AD7495CB
EVAL-AD7475CB
EVAL-CONTROL BRD2
NOTES
1
Linearity Error here refers to Integral Linearity Error.
2
SO = SOIC; RM = µSOIC.
3
This can be used as a standalone evaluation board or in conjunction with the EVAL-BOARD CONTROLLER for evaluation/demonstration purposes.
4
This EVALUATION BOARD CONTROLLER is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in
the CB designators.
3
3
4
Evaluation Board
Evaluation Board
Controller Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
WARNING!
the AD7475/AD7495 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
–6–
REV. A
Page 7
AD7475/AD7495
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1 REF IN Reference Input for the AD7475. An external reference must be applied to this input. The voltage range
for the external reference is 2.5 V ±1% for specified performance. A cap of a least 0.1 F should be placed
on the REF IN pin.
REF OUT Reference Output for the AD7495. A minimum 100 nF capacitance is required from this pin to GND. The
internal reference can be taken from this pin but buffering is required before it is applied elsewhere in a system.
2V
IN
3 GND Analog Ground. Ground reference point for all circuitry on the AD7475/AD7495. All analog input signals
4 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is
5 SDATA Data Out. Logic Output. The conversion result from the AD7475/AD7495 is provided on this output as a
6V
DRIVE
7 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
8V
DD
Analog Input. Single-ended analog input channel. The input range is 0 to REF IN.
and any external reference signal should be referred to this GND voltage.
also used as the clock source for the AD7475/AD7495’s conversion process.
serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists
of four leading zeros followed by the 12 bits of conversion data which is provided MSB first.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface
of the AD7475/AD7495 will operate.
AD7475/AD7495 and also frames the serial data transfer.
Power Supply Input. The VDD range for the AD7475/AD7495 is from 2.7 V to 5.25 V.
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of the
transfer function are zero scale, a point 1/2 LSB below the first
code transition, and full scale, a point 1/2 LSB above the last
code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 0.5 LSB.
Gain Error
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., V
– 1.5 LSB) after the offset
REF
error has been adjusted out.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode on the 13th
SCLK rising edge (see Serial Interface section). The Track/Hold
Acquisition Time is the minimum time required for the trackand-hold amplifier to remain in track mode for its output to
reach and settle to within 0.5 LSB of the applied input signal,
given a step change to the input signal.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (f
/2), excluding dc. The ratio
S
is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7475/AD7495, it is
defined as:
2
THD dB
( ) log=
20
VVVVV
++++
223242526
V
1
where V1 is the rms amplitude of the fundamental and V2, V3, V4,
V
and V6 are the rms amplitudes of the second through the sixth
5
harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the rms
value of the next largest component in the ADC output spectrum
(up to f
/2 and excluding dc) to the rms value of the fundamental.
S
Normally, the value of this specification is determined by the
largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those
for which neither m nor n is equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7475/AD7495 are tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per
the THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
REV. A
–7–
Page 8
AD7475/AD7495
AD7475/AD7495 TYPICAL PERFORMANCE CURVES
TPC 1 shows a typical FFT plot for the AD7475 at 1 MHz
sample rate and 100 kHz input frequency.
8192 POINT FFT
= 1MSPS
f
–15
–35
–55
SINAD – dB
–75
–95
–115
0
50 100 150 200 250 300
FREQUENCY – kHz
SAMPLE
= 100kHz
f
IN
SINAD = 70.46dB
THD = –87.7dB
SFDR = –89.5dB
350 400 500450
TPC 1. AD7475 Dynamic Performance
TPC 2 shows a typical FFT plot for the AD7495 at 1 MHz sample
rate and 100 kHz input frequency.
8192 POINT FFT
= 1MSPS
f
–15
–35
–55
SINAD – dB
–75
SAMPLE
f
= 100kHz
IN
SINAD = 69.95dB
THD = –89.2dB
SFDR = –91.2dB
CIRCUIT INFORMATION
The AD7475/AD7495 are fast, micropower, 12-bit, single-supply,
A/D converters. The parts can be operated from a 2.7 V to 5.25 V
supply. When operated from either a 5 V supply or a 3 V supply, the AD7475/AD7495 are capable of throughput rates of
1 MSPS when provided with a 20 MHz clock.
The AD7475/AD7495 provide the user with an on-chip track/
hold, A/D converter, and a serial interface housed in either an
8-lead SOIC or µSOIC package, which offers the user considerable
space-saving advantages over alternative solutions. The AD7495
also has an on-chip 2.5 V reference. The serial clock input accesses
data from the part but also provides the clock source for the
successive-approximation A/D converter. The analog input range
is 0 V to REF IN for the AD7475 and 0 V to REF OUT for
the AD7495.
The AD7475/AD7495 also feature power-down options to allow
power saving between conversions. The power-down feature is
implemented across the standard serial interface as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7475/AD7495 are 12-bit successive approximation
analog-to-digital converters based around a capacitive DAC.
The AD7475/AD7495 can convert analog input signals in the
range 0 V to 2.5 V. Figures 4 and 5 show simplified schematics
of the ADC. The ADC comprises of Control Logic, SAR and a
Capacitive DAC, which are used to add and subtract fixed
amounts of charge from the sampling capacitor to bring the
comparator back into a balanced condition. Figure 4 shows the
ADC during its acquisition phase. SW2 is closed and SW1 is in
Position A. The comparator is held in a balanced condition and
the sampling capacitor acquires the signal on V
.
IN
–95
–115
50 100 150 200 250 300
0
FREQUENCY – kHz
350 400 500450
TPC 2. AD7495 Dynamic Performance
TPC 3 shows the signal-to-(noise + distortion) ratio performance
versus input frequency for various supply voltages while sampling
at 1 MSPS with an SCLK of 20 MHz.
71.0
70.5
70.0
SINAD – dB
69.5
69.0
68.5
10 100
VDD = V
VDD = V
VDD = V
VDD = V
DRIVE
= 3.60V
DRIVE
INPUT FREQUENCY – kHz
DRIVE
DRIVE
= 5.25V
= 4.75V
= 2.70V
1000
TPC 3. AD7495 SINAD vs. Input Frequency at 1 MSPS
CAPACITIVE
DAC
V
AGND
A
IN
SW1
4k⍀
B
SW2
COMPARATOR
CONTROL LOGIC
Figure 4. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 5), SW2 will
open and SW1 will move to position B causing the comparator to become unbalanced. The Control Logic and the Capacitive
DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the ADC
output code. Figure 6 shows the ADC transfer function.
CAPACITIVE
DAC
V
AGND
IN
SW1AB
4k⍀
SW2
CONTROL LOGIC
COMPARATOR
Figure 5. ADC Conversion Phase
–8–
REV. A
Page 9
AD7475/AD7495
ADC TRANSFER FUNCTION
The output coding of the AD7475/AD7495 is straight binary.
The designed code transitions occur midway between successive
integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, etc.). The LSB size
is = V
/4096. The ideal transfer characteristic for the AD7475/
REF
AD7495 is shown in Figure 6 below.
111...111
111...110
111...000
011...111
ADC CODE
000...010
000...001
000...000
0V
0.5LSB
1LSB = V
V
–1.5LSB
REF
ANALOG INPUT
REF
/4096
Figure 6. AD7475/AD7495 Transfer Characteristic
TYPICAL CONNECTION DIAGRAM
Figure 7 and Figure 8 show a typical connection diagram for the
AD7475 and AD7495 respectively. In both setups the GND pin is
connected to the analog ground plane of the system. In Figure 7
REF IN is connected to a decoupled 2.5 V supply from a reference
source, the AD780, to provide an analog input range of 0 V to
2.5 V. Although the AD7475 is connected to a V
serial interface is connected to a 3 V microprocessor. The V
of 5 V, the
DD
DRIVE
pin of the AD7475 is connected to the same 3 V supply of the
microprocessor to allow a 3 V logic interface, see Digital Inputs
Section. In Figure 8, the REF OUT pin of the AD7495 is connected to a buffer and then applied to a level-shifting circuit used
on the analog input to allow a bipolar signal to be applied to the
AD7495. A minimum 100 nF capacitance is required on the
REF OUT pin to GND. The conversion result from both ADCs is
output in a 16-bit word with four leading zeros followed by the
MSB of the 12-bit result. For applications where power consumption is of concern, the power-down modes should be
used between conversions or bursts of several conversions to
improve power performance. See Modes of Operation section
of the data sheet.
0V TO
2.5V
INPUT
0.1F
(MIN)
0.1F 10F
V
DD
V
IN
GND
REF IN
AD7475
2.5V
AD780
5V
SUPPLY
SCLK
SDATA
V
DRIVE
CS
SERIAL
INTERFACE
0.1F 10F
C/P
3V
SUPPLY
Figure 7. AD7475 Typical Connection Diagram
Analog Input
Figure 9 shows an equivalent circuit of the analog input structure
of the AD7475/AD7495. The two diodes D1 and D2 provide ESD
protection for the analog inputs. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more than
200 mV. This will cause these diodes to become forward-biased
and start conducting current into the substrate. 20 mA is the
maximum current these diodes can conduct without causing
irreversible damage to the part. The capacitor C1 in Figure 9 is
typically about 4 pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the
on resistance of a switch. This resistor is typically about 100 Ω.
The capacitor C2 is the ADC sampling capacitor and has a capacitance of 16 pF typically. For ac applications, removing high
frequency components from the analog input signal is recommended by use of an RC low-pass filter on the relevant analog
input pin. In applications where harmonic distortion and signal
to noise ratio are critical, the analog input should be driven from
a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate
the use of an input buffer amplifier. The choice of the op amp will
be a function of the particular application.
V
DD
C2
V
IN
C1
4pF
D1
D2
R1
CONVERSION PHASE–SWITCH OPEN
TRACK PHASE–SWITCH CLOSED
16pF
Figure 9. Equivalent Analog Input Circuit
REV. A
5V
0.1F 10F
V
R
R
V0V
3R
R
0V TO
2.5V
INPUT
V
DD
V
IN
GND
REF OUT
0.1F
(MIN)
AD7495
SUPPLY
SCLK
SDATA
V
DRIVE
CS
SERIAL
INTERFACE
0.1F 10F
C/P
3V
SUPPLY
Figure 8. AD7495 Typical Connection Diagram
–9–
Page 10
AD7475/AD7495
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance will depend on the amount of total harmonic distortion
(THD) that can be tolerated. The THD will increase as the source
impedance increases and performance will degrade. Figure 10
shows a graph of the total harmonic distortion versus source
impedance for various analog input frequencies.
–10
–20
–30
–40
–50
THD – dB
–60
–70
–80
–90
1 100
10 1000
SOURCE IMPEDANCE – Ohms
fIN = 500kHz
fIN = 200kHz
fIN = 10kHz
fIN = 100kHz
10000
Figure 10. THD vs. Source Impedance for Various Analog Input Frequencies
Figure 11 shows a graph of total harmonic distortion versus analog
Input frequency for various supply voltages while sampling at
1 MSPS with an SCLK of 20 MHz.
–75
VDD = V
10 100
THD – dB
–77
–79
–81
–83
–85
–87
–89
–91
–93
–95
= 5.25V
DRIVE
VDD = V
= 4.75V
DRIVE
INPUT FREQUENCY – kHz
VDD = V
VDD = V
DRIVE
= 2.70V
DRIVE
= 3.60V
1000
Figure 11. THD vs. Analog Input Frequency for Various
Supply Voltages
Digital Inputs
The digital inputs applied to the AD7475/AD7495 are not limited
by the maximum ratings which limit the analog inputs. Instead,
the digital inputs applied can go to 7 V and are not restricted by
the V
+ 0.3 V limit as on the analog inputs.
DD
Another advantage of SCLK and CS not being restricted by the
V
+ 0.3 V limit is the fact that power supply sequencing issues
DD
are avoided. If CS or SCLK are applied before V
, there is no
DD
risk of latch-up as there would be on the analog inputs if a
signal greater than 0.3 V were applied prior to V
V
DRIVE
The AD7475/AD7495 also has the V
DRIVE
controls the voltage at which the serial interface operates. V
.
DD
feature. V
DRIVE
DRIVE
allows the ADC to easily interface to both 3 V and 5 V processors.
For example, if the AD7475/AD7495 were operated with a V
of 5 V, and the V
pin could be powered from a 3 V supply.
DRIVE
DD
The AD7475/AD7495 has better dynamic performance with a
of 5 V while still being able to interface to 3 V digital parts.
V
DD
Care should be taken to ensure V
does not exceed VDD by
DRIVE
more than 0.3 V. (See Absolute Maximum Ratings.)
Reference Section
An external reference source should be used to supply the 2.5 V
reference to the AD7475. Errors in the reference source will result
in gain errors in the AD7475 transfer function and will add the
specified full-scale errors on the part. A capacitor of at least 0.1 µF
should be placed on the REF IN pin. Suitable reference sources
for the AD7475 include the AD780, the AD680, and the AD1852.
The AD7495 contains an on-chip 2.5 V reference. As shown in
Figure 12, the voltage that appears at the REF OUT pin is internally buffered before being applied to the ADC, the output
impedance of this buffer is typically 10 Ω. The reference is capable
of sourcing up to 2 mA. The REF OUT pin should be decoupled
to AGND using a 100 nF or greater capacitor.
If the 2.5 V internal reference is to be used to drive another device
that is capable of glitching the reference at critical times, then the
reference will have to be buffered before driving the device. To
ensure optimum performance of the AD7495 it is recommended
that the Internal Reference not be over driven. If the use of an
external reference is required the AD7475 should be used.
160k⍀
V
40k⍀
25⍀
REF OUT
Figure 12. AD7495 Reference Circuit
MODES OF OPERATION
The mode of operation of the AD7475/AD7495 is selected by
controlling the (logic) state of the CS signal during a conversion.
There are three possible modes of operation, Normal Mode,
Partial Power-Down Mode, and Full Power-Down Mode. The
point at which CS is pulled high after the conversion has been
initiated will determine which power-down mode, if any, the device
will enter. Similarly, if already in a power-down mode, CS can
control whether the device will return to Normal operation or
remain in power-down. These modes of operation are designed to
provide flexible power management options. These options can be
chosen to optimize the power dissipation/throughput rate ratio for
differing application requirements.
Normal Mode
This mode is intended for fastest throughput rate performance as
the user does not have to worry about any power-up times with
the AD7475/AD7495 remaining fully powered all the time.
Figure 13 shows the general diagram of the operation of the
AD7475/AD7495 in this mode.
The conversion is initiated on the falling edge of CS as described in
the Serial Interface section. To ensure the part remains fully powered up at all times, CS must remain low until at least 10 SCLK
falling edges have elapsed after the falling edge of CS. If CS is
brought high any time after the 10th SCLK falling edge, but
–10–
REV. A
Page 11
CS
AD7475/AD7495
1
SCLK
SDATA
FOUR LEADING ZEROS + CONVERSION RESULT
Figure 13. Normal Mode Operation
CS
2
1
SCLK
Figure 14. Entering Partial Power-Down Mode
THE PART BEGINS
TO POWER UP
CS
16
SCLK
SDATA
A
1
INVALID DATA
10
Figure 15. Exiting Partial Power-Down Mode
before the 16th SCLK falling edge, the part will remain powered
up but the conversion will be terminated and SDATA will go
back into three-state. Sixteen serial clock cycles are required
to complete the conversion and access the conversion result. CS
may idle high until the next conversion or may idle low until sometime prior to the next conversion (effectively idling CS low).
Once a data transfer is complete (SDATA has returned to
three-state), another conversion can be initiated after the quiet
time, t
, has elapsed by bringing CS low again.
QUIET
Partial Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and then the ADC is powered
down for a relatively long duration between these bursts of several
conversions. When the AD7475 is in partial power-down, all analog circuitry is powered down except for the bias current generator;
and, in the case of the AD7495, all analog circuitry is powered
down except for the on-chip reference and reference buffer.
To enter partial power-down, the conversion process must be
interrupted by bringing CS high anywhere after the second falling
edge of SCLK and before the tenth falling edge of SCLK as shown
in Figure 14. Once CS has been brought high in this window of
SCLKs, the part will enter partial power-down, and the conversion that was initiated by the falling edge of CS will be
terminated, and SDATA will go back into three-state. If CS
is brought high before the second SCLK falling edge, the part
will remain in Normal Mode and will not power down. This will
avoid accidental power-down due to glitches on the CS line.
In order to exit this mode of operation and power the AD7475/
AD7495 up again, a dummy conversion is performed. On the
10
10
THE PART IS FULLY
POWERED UP
1
16
16
16
VALID DATA
falling edge of CS the device will begin to power up, and will
continue to power up as long as CS is held low until after the
falling edge of the tenth SCLK. The device will be fully powered
up once 16 SCLKs have elapsed, and valid data will result from
the next conversion as shown in Figure 15. If CS is brought high
before the second falling edge of SCLK, the AD7475/AD7495
will go back into partial power-down again. This avoids accidental
power-up due to glitches on the CS line; although the device
may begin to power up on the falling edge of CS, it will power
down again on the rising edge of CS. If in partial power-down
and CS is brought high between the second and tenth falling
edges of SCLK, the device will enter full power-down mode.
Power-Up Time
The power-up time of the AD7475/AD7495 from partial powerdown is typically 1 µs, which means that with any frequency of
SCLK up to 20 MHz, one dummy cycle will always be sufficient to allow the device to power up from partial power-down.
Once the dummy cycle is complete, the ADC will be fully powered up and the input signal will be acquired properly. The quiet
time t
must still be allowed from the point where the bus
QUIET
goes back into three-state after the dummy conversion, to the
next falling edge of CS. When running at 1 MSPS throughput
rate, the AD7475/AD7495 will power up and acquire a signal
within ± 0.5 LSB in one dummy cycle, i.e., 1 µs.
When powering up from the power-down mode with a dummy
cycle, as in Figure 15, the track-and-hold that was in hold mode
while the part was powered down, returns to track mode after the
first SCLK edge the part receives after the falling edge of CS.
This is shown as Point A in Figure 15. Although at any SCLK
frequency one dummy cycle is sufficient to power the device up
and acquire V
, it does not necessarily mean that a full dummy
IN
REV. A
–11–
Page 12
AD7475/AD7495
THE PART ENTERS
PARTIAL POWER-DOWN
CS
16
SCLK
SDATA
1
2
INVALID DATA
10
THREE-STATE THREE-STATE
Figure 16. Entering Full Power-Down Mode
THE PART BEGINS
CS
SCLK
SDATA
TO POWER UP
1
INVALID DATA
t
POWER-UP
10
16
Figure 17. Exiting Full Power-Down Mode
cycle of 16 SCLKs must always elapse to power up the device
and fully acquire V
; 1 µs will be sufficient to power the device
IN
up and acquire the input signal. If, for example, a 5 MHz SCLK
frequency was applied to the ADC, the cycle time would be 3.2 s.
In one dummy cycle, 3.2 µs, the part would be powered up and
fully acquired. However, after 1 µs with a 5 MHz SCLK,
V
IN
only 5 SCLK cycles would have elapsed. At this stage, the ADC
would be fully powered up and the signal acquired. So, in this
case the CS can be brought high after the tenth SCLK falling edge
and brought low again after a time t
to initiate the conversion.
QUIET
Full Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required than that in the partial power-down
mode, as power up from a full power-down would not be complete in just one dummy conversion. This mode is more suited to
applications where a series of conversions performed at a relatively
high throughput rate would be followed by a long period of
inactivity and hence power-down. When the AD7475/AD7495
is in full power-down, all analog circuitry is powered down.
Full power-down is entered in a way similar to partial power-down,
except the timing sequence shown in Figure 14 must be executed
twice. The conversion process must be interrupted in a similar
fashion by bringing CS high anywhere after the second falling
edge of SCLK and before the tenth falling edge of SCLK. The
device will enter partial power-down at this point. To reach full
power-down, the next conversion cycle must be interrupted
in the same way as shown in Figure 16. Once CS has been
brought high in this window of SCLKs, then the part will
power down completely.
NOTE: It is not necessary to complete the 16 SCLKs once CS
has been brought high to enter a power-down mode.
To exit full power-down, and power the AD7475/AD7495 up
again, a dummy conversion is performed as when powering
up from partial power-down. On the falling edge of CS the
device will begin to power up, and will continue to power up as
THE PART BEGINS
TO POWER UP
1
2
INVALID DATA
THE PART IS FULLY
POWERED UP
1
VALID DATA
THE PART ENTERS
FULL POWER-DOWN
10
16
16
long as CS is held low until after the falling edge of the tenth
SCLK. The power-up time is longer than one dummy conversion
cycle however, and this time, t
POWER-UP
, must elapse before
a conversion can be initiated as shown in Figure 17. (See
Timing Specifications.)
When power supplies are first applied to the AD7475/AD7495,
the ADC may power up in either of the power-down modes or
normal mode. Because of this, it is best to allow a dummy cycle
to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, if it is intended to keep the part
in the partial power-down mode immediately after the supplies
are applied, then two dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the tenth SCLK
falling edge, Figure 13; in the second cycle CS must be brought
high before the tenth SCLK edge but after the second SCLK
falling edge, Figure 14. Alternatively, if it is intended to place
the part in full power-down mode when the supplies have been
applied, then three dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the tenth SCLK
edge, Figure 13; the second and third dummy cycle place the
part in full power-down, Figure 16. See Modes of Operation
section. Once supplies are applied to the AD7475/AD7495,
enough time must be allowed, for the AD7475, for the external
reference to power up and charge the reference capacitor to its
final value. For the AD7495, enough time should be allowed for
the internal reference buffer to charge the reference capacitor.
Then, to place the AD7475/AD7495 in normal mode, a dummy
cycle, 1 µs, should be initiated. If the first valid conversion is then
performed directly after the dummy conversion, care must be
taken to ensure that adequate acquisition time has been allowed.
As mentioned earlier, when powering up from the power-down
mode, the part will return to track upon the first SCLK edge
applied after the falling edge of CS. However, when the ADC
powers up initially after supplies are applied, the track-and-hold
will already be in track. This means (assuming one has the facility to monitor the ADC supply current) if the ADC powers up
–12–
REV. A
Page 13
AD7475/AD7495
THROUGHPUT – SPS
2.0
10
CURRENT – mA
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100 1k 10k 100k 1M
VDD = 5V
FULL
POWER-DOWN
PARTIAL
POWER-DOWN
NORMAL
in the desired mode of operation, and thus a dummy cycle is not
required to change mode, then neither is a dummy cycle required
to place the track-and-hold into track. If no current monitoring
facility is available, the relevant dummy cycle(s) should be performed to ensure the part is in the required mode.
POWER VERSUS THROUGHPUT RATE
By using the partial power-down mode on the AD7475/AD7495
when not converting, the average power consumption of the
ADC decreases at lower throughput rates. Figure 18 shows
how, as the throughput rate is reduced, the part remains in its
partial power-down state longer and the average power consumption over time drops accordingly.
100
AD7495 5V
SCLK = 20MHz
AD7475 3V
SCLK = 20MHz
AD7495 3V
SCLK = 20MHz
POWER – mW
0.01
AD7475 5V
10
SCLK = 20MHz
1
0.1
remaining 8 µs where the part is in partial power-down. With a
throughput rate of 100 kSPS, the average power dissipated during
each conversion cycle is (2/10) (6 mW) + (8/10) (0.69 mW)
= 1.752 mW. Figure 18 shows the power versus throughput rate
when using the partial power-down mode between conversions
with both 5 V and 3 V supplies for both the AD7475 and AD7495.
For the AD7475, partial power-down current is lower than that
of the AD7495.
Full power-down mode is intended for use in applications with
slower throughput rates than required for the partial powerdown mode. It is necessary to leave 650 µs for the AD7495 to
be fully powered up from full power-down before initiating a
conversion. Current consumptions between conversions is typically less than 1 µA.
Figure 19 shows a typical graph of current versus throughput for
the AD7495 while operating in different modes. At slower
throughput rates, e.g., 10 SPS to 1 kSPS, the AD7495 was
operated in Full Power-Down mode. As the throughput rate
increased, up to 100 kSPS, the AD7495 was operated in Partial
Power-Down mode, with the part being powered down between
conversions. With throughput rates from 100 kSPS to 1 MSPS,
the part operated in Normal mode, remaining fully powered up
at all times.
0.001
0
50 100
150 200 250 300 350
THROUGHPUT – kSPS
Figure 18. AD7495 Power vs. Throughput for Partial
Power-Down
For example if the AD7495 is operated in a continuous sampling
mode with a throughput rate of 100 kSPS and an SCLK of
20 MHz (V
= 5 V), and the device is placed in partial power-
DD
down mode between conversions, then the power consumption
is calculated as follows. The maximum power dissipation during
normal operation is 13 mW (V
= 5 V). If the power-up time
DD
from partial power-down is one dummy cycle, i.e., 1 µs, and the
remaining conversion time is another cycle, i.e., 1 µs, then the
AD7495 can be said to dissipate 13 mW for 2 µs during each
conversion cycle. For the remainder of the conversion cycle,
8 µs, the part remains in partial power-down mode. The AD7495
can be said to dissipate 1.15 mW for the remaining 8 µs of the
conversion cycle. If the throughput rate is 100 kSPS, the cycle
time is 10 µs and the average power dissipated during each cycle
is (2/10) (13 mW) + (8/10) (1.15 mW) = 3.52 mW. If V
= 3 V, SCLK = 20 MHz and the device is again in partial powerdown mode between conversions, the power dissipated during
normal operation is 6 mW. The AD7495 can be said to dissipate
6 mW for 2 µs during each conversion cycle and 0.69 mW for the
t
CONVERT
t
2
1
t
3
00
FOUR LEADING ZEROS
2
0
34
0
t
6
5
t
t
4
DB11 DB10
CS
SCLK
SDATA
THREE-STATE
Figure 20. Serial Interface Timing Diagram
REV. A
Figure 19. Typical AD7495 Current vs. Throughput
SERIAL INTERFACE
Figure 20 shows the detailed timing diagram for serial interfacing
to the AD7475/AD7495. The serial clock provides the conversion
clock and also controls the transfer of information from the
DD
AD7475/AD7495 during conversion.
CS initiates the data transfer and conversion process. The falling
edge of CS puts the track and hold into hold mode, takes the bus
out of three-state, and the analog input is sampled at this point.
B
13
7
14
DB2
15
16
t
5
DB1
t
8
DB0
THREE-STATE
t
QUIET
–13–
Page 14
AD7475/AD7495
CS
SCLK
SDATA
THREE-STATE
t
2
1
t
3
0
FOUR LEADING ZEROS
2
0 0
34
0
t
CONVERT
t
6
5
t
7
t
4
DB11 DB10
Figure 21. Serial Interface Timing Diagram—Conversion Termination
The conversion is also initiated at this point and will require
16 SCLK cycles to complete. Once 13 SCLK falling edges have
elapsed, the track and hold will go back into track on the next
SCLK rising edge as shown in Figure 20 at Point B. On the
16th SCLK falling edge the SDATA line will go back into threestate. If the rising edge of CS occurs before 16 SCLKs have
elapsed, the conversion will be terminated and the SDATA line
will go back into three-state, as shown in Figure 21, otherwise
SDATA returns to three-state on the 16th SCLK falling edge as
shown in Figure 20.
Sixteen serial clock cycles are required to perform the conversion
process and to access data from the AD7475/AD7495. CS going
low provides the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by
subsequent SCLK falling edges beginning with the 2nd leading
zero, thus the first falling clock edge on the serial clock has the
second leading zero provided. The final bit in the data transfer
is valid on the sixteenth falling edge, having being clocked out on
the previous (15th) falling edge.
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge, although the first leading zero will
still have to be read on the first SCLK falling edge after the CS
falling edge. Therefore, the first rising edge of SCLK after the CS
falling edge would provide the second leading zero and the 15th
rising SCLK edge would have DB0 provided. This method may
not work with most Micros/DSPs, but could possibly be used
with FPGAs and ASICs.
MICROPROCESSOR INTERFACING
The serial interface on the AD7475/AD7495 allows the parts to
be directly connected to a range of many different microprocessors.
This section explains how to interface the AD7475/AD7495 with
some of the more common microcontroller and DSP serial
interface protocols.
AD7475/AD7495 to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize the
data transfer operations with peripheral devices like the AD7475/
AD7495. The CS input allows easy interfacing between the
TMS320C5x/C54x and the AD7475/AD7495 without any glue
logic required. The serial port of the TMS320C5x/C54x is set
up to operate in burst mode with internal CLKX (Tx serial clock)
and FSX (Tx frame sync). The serial port control register (SPC)
must have the following setup: FO = 0, FSM = 1, MCM = 1 and
TXM = 1. The format bit, FO, may be set to 1 to set the word
length to 8 bits, in order to implement the power-down modes
on the AD7475/AD7495.
B
13
14
t
9
DB2
15
16
t
QUIET
THREE-STATE
The connection diagram is shown in Figure 22. It should be noted
that for signal processing applications, it is imperative that
the frame synchronization signal from the TMS320C5x/C54x
provide equidistant sampling. The V
pin of the AD7475/
DRIVE
AD7495 takes the same supply voltage as that of the TMS320C5x/
C54x. This allows the ADC to operate at a higher voltage than
the serial interface, i.e., TMS320C5x/C54x, if necessary.
AD7475/AD7495*
SCLK
SDATA
CS
V
DRIVE
*
ADDITIONAL PINS OMITTED FOR CLARITY
TMS320C5x/C54x*
CLKX
CLKR
DR
FBX
FSR
V
DD
Figure 22. Interfacing to the TMS320C5x/C54x
AD7475/AD7495 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced directly to the
AD7475/AD7495 without any glue logic required. The V
DRIVE
pin
of the AD7475/AD7495 takes the same supply voltage as that of
the ADSP-21xx. This allows the ADC to operate at a higher
voltage than the serial interface, i.e., ADSP-21xx, if necessary.
The SPORT control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0,
ITFS = 1.
To implement the power-down modes SLEN should be set to
1001 to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 23. The ADSP21xx has the TFS and RFS of the SPORT tied together, with
TFS set as an output and RFS set as an input. The DSP operates in Alternate Framing Mode and the SPORT control register is
set up as described. The Frame synchronizations signal generated
on the TFS is tied to CS and as with all signal processing applications equidistant sampling is necessary. However, in this
example, the timer interrupt is used to control the sampling rate
of the ADC and under certain conditions, equidistant sampling
may not be achieved.
–14–
REV. A
Page 15
AD7475/AD7495
SCLK
DR
RFS
TFS
ADSP-21xx*
V
DD
AD7475/AD7495*
SCLK
SDATA
CS
V
DRIVE
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. Interfacing to the ADSP-21xx
The Timer registers etc., are loaded with a value that will provide
an interrupt at the required sample interval. When an interrupt
is received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and hence the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given, (i.e., AX0 = TX0), the state of the SCLK is checked. The
DSP will wait until the SCLK has gone high, low, and high
before transmission will start. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, the data may be transmitted or it may
wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained, and eight master clock periods will
elapse for every 1 SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs will occur between interrupts
and subsequently between transmit instructions. This situation
will result in nonequidistant sampling as the transmit instruction is occurring on a SCLK edge. If the number of SCLKs
between interrupts is a whole integer figure of N, equidistant
sampling will be implemented by the DSP.
AD7475/AD7495 to DSP56xxx
The connection diagram in Figure 24 shows how the AD7475/
AD7495 can be connected to the SSI (Synchronous Serial Interface) of the DSP56xxx family of DSPs from Motorola. The SSI
is operated in Synchronous Mode (SYN bit in CRB = 1) with
internally generated 1-bit clock period frame sync for both Tx
and Rx (bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word
length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. To
implement the power-down modes on the AD7475/AD7495
then the word length can be changed to eight bits by setting bits
WL1 = 0 and WL0 = 0 in CRA. It should be noted that for
signal processing applications, it is imperative that the frame
synchronization signal from the DSP56xxx provide equidistant
sampling. The V
pin of the AD7475/AD7495 takes the
DRIVE
same supply voltage as that of the DSP56xxx. This allows the
ADC to operate at a voltage higher than the serial interface, i.e.,
DSP56xxx, if necessary.
SCLK
SRD
SC2
DSP56xxx*
V
DD
AD7475/AD7495*
SCLK
SDATA
CS
V
DRIVE
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 24. Interfacing to the DSP56xxx
AD7475/AD7495 to MC68HC16
The Serial Peripheral Interface (SPI) on the MC68HC16 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 1 and the Clock Phase Bit (CPHA) = 0. The SPI
is configured by writing to the SPI Control Register (SPCR), see
68HC16 user manual. The serial transfer will take place as a
16-bit operation when the SIZE bit in the SPCR register is
set to SIZE = 1. To implement the power-down modes with an
8-bit transfer set SIZE = 0. A connection diagram is shown in
Figure 25. The V
pin of the AD7475/AD7495 takes the same
DRIVE
supply voltage as that of the MC68HC16. This allows the ADC
to operate at a higher voltage than the serial interface, i.e.,
MC68HC16, if necessary.
AD7475/AD7495*
SCLK
SDATA
CS
V
DRIVE
MC68HC16*
SCLK/PCM2
MISO/PMC0
SS/PMC3
REV. A
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. Interfacing to the MC68HC16
–15–
V
DD
Page 16
AD7475/AD7495
0.1574 (4.00)
0.1497 (3.80)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
85
0.2440 (6.20)
0.2284 (5.80)
41
PIN 1
0.0098 (0.25)
0.0040 (0.10)
SEATING
0.122 (3.10)
0.114 (2.90)
0.006 (0.15)
0.002 (0.05)
0.0500 (1.27)
BSC
0.020 (0.51)
0.013 (0.33)
PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0075 (0.19)
8-Lead microSOIC
(RM-8)
0.122 (3.10)
0.114 (2.90)
PIN 1
0.0256 (0.65) BSC
SEATING
PLANE
85
0.120 (3.05)
0.112 (2.84)
0.018 (0.46)
0.008 (0.20)
0.199 (5.05)
0.187 (4.75)
41
0.043 (1.09)
0.037 (0.94)
0.011 (0.28)
0.003 (0.08)
0.120 (3.05)
0.112 (2.84)
33ⴗ
27ⴗ
0.0196 (0.50)
0.0099 (0.25)
8ⴗ
0.050 (1.27)
0ⴗ
0.016 (0.40)
0.028 (0.71)
0.016 (0.41)
ⴛ 45ⴗ
C01684–2.5–4/01(A)
–16–
PRINTED IN U.S.A.
REV. A
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