Datasheet AD7468 Datasheet (ANALOG DEVICES)

V

www.BDTIC.com/ADI

1.6 V, Micropower 12-/10-/8-Bit ADCs

FEATURES

Specified for V
Low power:

0.62 mW typical at 100 kSPS with 3 V supplies

0.48 mW typical at 50 kSPS with 3.6 V supplies

0.12 mW typical at 100 kSPS with 1.6 V supplies
Fast throughput rate: 200 kSPS
Wide input bandwidth:
71 dB SNR at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI/QSPI™/MICROWIRE™/DSP compatible
Automatic power-down
Power-down mode: 8 nA typical
6-lead SOT-23 package
8-lead MSOP package

APPLICATIONS

Battery-powered systems
Medical instruments
Remote data acquisition
Isolated data acquisition

of 1.6 V to 3.6 V

DD

AD7466/AD7467/AD7468

FUNCTIONAL BLOCK DIAGRAM

V

DD

12-/10-/8-BIT

T/H

IN

SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

AD7466/AD7467/AD7468

GND

Figure 1.

SCLK
SDATA
CS

02643-001

GENERAL DESCRIPTION

The AD7466/AD7467/AD74681 are 12-/10-/8-bit, high speed,
low power, successive approximation analog-to-digital
converters (ADCs), respectively. The parts operate from a single

1.6 V to 3.6 V power supply and feature throughput rates up to
200 kSPS with low power dissipation. The parts contain a low
noise, wide bandwidth track-and-hold amplifier, which can
handle input frequencies in excess of 3 MHz.

The conversion process and data acquisition are controlled

CS

usin

g

and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of
point. There are no pipeline delays associated with the part.

The reference for the part is taken internally from V
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 V to V
rate is determined by the SCLK.

1

Protected by U.S. Patent No. 6,681,332.

CS

, and the conversion is also initiated at this

. This

DD

. The conversion

DD

PRODUCT HIGHLIGHTS

1. Specified for supply voltages of 1.6 V to 3.6 V.

2. 12-, 10-, an

igh throughput rate with low power consumption.

3. H

Power consumption in normal mode of operation at
100 kSPS and 3 V is 0.9 mW maximum.

4. Flexi

The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through
increases in the serial clock speed. Automatic power-down
after conversion allows the average power consumption to
be reduced when in power-down. Current consumption is

0.1 μA maximum and 8 nA typically when in power-down.

5. Refer

6. No

pipeline delay.

he part features a standard successive approximation

7. T

ADC with accurate control of conversions via a

d 8-bit ADCs in SOT-23 and MSOP packages.

ble power/serial clock speed management.

ence derived from the power supply.

CS

input.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2003–2007 Analog Devices, Inc. All rights reserved.

AD7466/AD7467/AD7468

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

General Description......................................................................... 1

Product Highlights........................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

AD7466.......................................................................................... 3

AD7467.......................................................................................... 5

AD7468.......................................................................................... 7

Timing Specifications ..................................................................9

Timing Examples........................................................................ 10

Absolute Maximum Ratings.......................................................... 11

ESD Caution................................................................................ 11

Pin Configurations and Function Descriptions......................... 12

Typical Performance Characteristics........................................... 13

Dynamic Performance Curves .................................................13

DC Accuracy Curves ................................................................. 13

Power Requirement Curves ......................................................13

Terminology.................................................................................... 16

Theory of Operation ......................................................................17

Circuit Information.................................................................... 17

Converter Operation.................................................................. 17

ADC Transfer Function............................................................. 17

Typical Connection Diagram ...................................................17

Analog Input............................................................................... 18

Digital Inputs.............................................................................. 18

Normal Mode.............................................................................. 19

Power Consumption.................................................................. 20

Serial Interface ................................................................................ 22

Microprocessor Interfacing....................................................... 23

Application Hints ...........................................................................25

Grounding and Layout.............................................................. 25

Evaluating the Performance of the AD7466 and AD7467.... 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 27

REVISION HISTORY

5/07—Rev. B to Rev. C

Deleted Figure 3.............................................................................. 10

Updated Outline Dimensions....................................................... 26

Changes to Ordering Guide.......................................................... 27

4/05—Rev. A to Rev. B

Moved Terminology Section......................................................... 16

C

hanges to Ordering Guide.......................................................... 27

11/04—Rev. 0 to Rev. A

Updated Format..................................................................Universal

hanges to General Description .................................................... 1

C

Added Patent Number..................................................................... 1

Updated Outline Dimensions....................................................... 26

Changes to Ordering Guide.......................................................... 27

5/03—Revision 0: Initial Version

Rev. C | Page 2 of 28

AD7466/AD7467/AD7468

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SPECIFICATIONS

AD7466

VDD = 1.6 V to 3.6 V, f
The temperature range for the B version is −40°C to +85°C.

Table 1.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 30 kHz sine wave

Signal-to-Noise and Distortion (SINAD) 69 dB min 1.8 V ≤ VDD ≤ 2 V; see the Terminology section
70 dB min 2.5 V ≤ VDD ≤ 3.6 V
70 dB typ VDD = 1.6 V
Signal-to-Noise Ratio (SNR) 70 dB min 1.8 V ≤ VDD ≤ 2 V; see the Terminology section
71 dB typ 1.8 V ≤ VDD ≤ 2 V
71 dB min 2.5 V ≤ VDD ≤ 3.6 V

70.5 dB typ VDD = 1.6 V
Total Harmonic Distortion (THD) −83 dB typ See the Terminology section
Peak Harmonic or Spurious Noise (SFDR) −85 dB typ See the Terminology section
Intermodulation Distortion (IMD)

Second-Order Terms −84 dB typ

Third-Order Terms −86 dB typ
Aperture Delay 10 ns typ
Aperture Jitter 40 ps typ
Full Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V

1.9 MHz typ @ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V
750 kHz typ @ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V

450 kHz typ @ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V
DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity ±1.5 LSB max See the Terminology section
Differential Nonlinearity −0.9/+1.5 LSB max

Offset Error ±1 LSB max See the Terminology section
Gain Error ±1 LSB max See the Terminology section
Total Unadjusted Error (TUE) ±2 LSB max See the Terminology section

ANALOG INPUT

Input Voltage Ranges 0 to VDD V
DC Leakage Current ±1 μA max
Input Capacitance 20 pF typ

LOGIC INPUTS

Input High Voltage, V
2 V min 2.7 V ≤ VDD ≤ 3.6 V
Input Low Voltage, V

0.3 × VDD V max 1.8 V ≤ VDD < 2.7 V

0.8 V max 2.7 V ≤ VDD ≤ 3.6 V
Input Current, IIN, SCLK Pin ±1 μA max Typically 20 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
Input Capacitance, CIN 10 pF max Sample tested at 25°C to ensure compliance

= 3.4 MHz, f

SCLK

0.7 × VDD V min 1.6 V ≤ VDD < 2.7 V

INH

0.2 × VDD V max 1.6 V ≤ VDD < 1.8 V

INL

= 100 kSPS, unless otherwise noted. TA = T

SAMPLE

±1 μA t

yp

to T

MIN

fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology

tion

sec

Maximum specifications apply as typical figures when

= 1.6 V

V

DD

Guaranteed no missed codes to 12 bits; see the
Terminology section

, unless otherwise noted.

MAX

Rev. C | Page 3 of 28

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Parameter B Version Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, VOH V
Output Low Voltage, VOL 0.2 V max I
Floating-State Leakage Current ±1 μA max
Floating-State Output Capacitance 10 pF max
Output Coding

CONVERSION RATE

Conversion Time 4.70 μs max 16 SCLK cycles with SCLK at 3.4 MHz
Throughput Rate 200 kSPS max See the Serial Interface section

POWER REQUIREMENTS

VDD 1.6/3.6 V min/max
IDD Digital inputs = 0 V or VDD

Normal Mode (Operational) 300 μA max VDD = 3 V, f
110 μA typ VDD = 3 V, f
20 μA typ VDD = 3 V, f
240 μA max VDD = 2.5 V, f
80 μA typ VDD = 2.5 V, f
16 μA typ VDD = 2.5 V, f
165 μA max VDD = 1.8 V, f
50 μA typ VDD = 1.8 V, f
10 μA typ VDD = 1.8 V, f

Power-Down Mode 0.1 μA max SCLK on or off, typically 8 nA
Power Dissipation See the Power Consumption section

Normal Mode (Operational) 0.9 mW max VDD = 3 V, f

0.6 mW max VDD = 2.5 V, f

0.3 mW max VDD = 1.8 V, f

Power-Down Mode 0.3 μW max VDD = 3 V

− 0.2 V min I

DD

Straight (natural)

y

binar

= 200 μA, VDD = 1.6 V to 3.6 V

SOURCE

= 200 μA

SINK

= 100 kSPS

SAMPLE

= 50 kSPS

SAMPLE

= 10 kSPS

SAMPLE

= 100 kSPS

SAMPLE

= 50 kSPS

SAMPLE

= 10 kSPS

SAMPLE

= 100 kSPS

SAMPLE

= 50 kSPS

SAMPLE

= 10 kSPS

SAMPLE

= 100 kSPS

SAMPLE

= 100 kSPS

SAMPLE

= 100 kSPS

SAMPLE

Rev. C | Page 4 of 28

AD7466/AD7467/AD7468

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AD7467

VDD = 1.6 V to 3.6 V, f

The temperature range for the B version is −40°C to +85°C.

Table 2.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise and Distortion (SINAD) 61 dB min See the Terminology section
Total Harmonic Distortion (THD) −72 dB max See the Terminology section
Peak Harmonic or Spurious Noise (SFDR) −74 dB max See the Terminology section

Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section
Second-Order Terms −83 dB typ
Third-Order Terms −83 dB typ

Aperture Delay 10 ns typ

Aperture Jitter 40 ps typ

Full Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V

1.9 MHz typ @ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V

750 kHz typ @ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V
450 kHz typ @ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V
DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity ±0.5 LSB max See the Terminology section

Differential Nonlinearity ±0.5 LSB max

Offset Error ±0.2 LSB max See the Terminology section

Gain Error ±0.2 LSB max See the Terminology section

Total Unadjusted Error (TUE) ±1 LSB max See the Terminology section
ANALOG INPUT

Input Voltage Ranges 0 to VDD V

DC Leakage Current ±1 μA max

Input Capacitance 20 pF typ
LOGIC INPUTS

Input High Voltage, V

2 V min 2.7 V ≤ VDD ≤ 3.6 V

Input Low Voltage, V

0.3 × VDD V max 1.8 V ≤V DD < 2.7 V

0.8 V max 2.7 V ≤ VDD ≤ 3.6 V

Input Current, IIN, SCLK Pin ±1 μA max Typically 20 nA, VIN = 0 V or VDD

Input Current, IIN, CS Pin

Input Capacitance, CIN 10 pF max Sample tested at 25°C to ensure compliance
LOGIC OUTPUTS

Output High Voltage, VOH V

Output Low Voltage, VOL 0.2 V max I

Floating-State Leakage Current ±1 μA max

Floating-State Output Capacitance 10 pF max Sample tested at 25°C to ensure compliance

Output Coding

CONVERSION RATE

Conversion Time 3.52 μs max 12 SCLK cycles with SCLK at 3.4 MHz

Throughput Rate 275 kSPS max See the Serial Interface section

= 3.4 MHz, f

SCLK

0.7 × VDD V min 1.6 V ≤ VDD < 2.7 V

INH

0.2 × VDD V max 1.6 V ≤ VDD < 1.8 V

INL

= 100 kSPS, unless otherwise noted. TA = T

SAMPLE

±1 μA t

− 0.2 V min I

DD

Straight (natural)

y

binar

yp

MIN

Maximum/minimum specifications apply as typical figures
when V

Maximum specifications apply as typical figures when
V

DD

Guaranteed no missed codes to 10 bits; see the
Terminology section

SOURCE

SINK

= 1.6 V, fIN = 30 kHz sine wave

DD

= 1.6 V

= 200 μA, VDD = 1.6 V to 3.6 V

= 200 μA

to T

, unless otherwise noted.

MAX

Rev. C | Page 5 of 28

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Parameter B Version Unit Test Conditions/Comments

POWER REQUIREMENTS

VDD 1.6/3.6 V min/max
IDD Digital inputs = 0 V or VDD

Normal Mode (Operational) 210 μA max VDD = 3 V, f
170 μA max VDD = 2.5 V, f
140 μA max VDD = 1.8 V, f

Power-Down Mode 0.1 μA max SCLK on or off, typically 8 nA
Power Dissipation See the Power Consumption section

Normal Mode (Operational) 0.63 mW max VDD = 3 V, f

0.42 mW max VDD = 2.5 V, f

0.25 mW max VDD = 1.8 V, f

Power-Down Mode 0.3 μW max VDD = 3 V

= 100 kSPS

SAMPLE

SAMPLE

SAMPLE

= 100 kSPS

SAMPLE

SAMPLE

SAMPLE

= 100 kSPS
= 100 kSPS

= 100 kSPS
= 100 kSPS

Rev. C | Page 6 of 28

AD7466/AD7467/AD7468

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AD7468

VDD = 1.6 V to 3.6 V, f
The temperature range for the B version is −40°C to +85°C.

Table 3.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise and Distortion (SINAD) 49 dB min See the Terminology section
Total Harmonic Distortion (THD) −66 dB max See the Terminology section
Peak Harmonic or Spurious Noise

(SFDR)

Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section
Second-Order Terms −77 dB typ
Third-Order Terms −77 dB typ

Aperture Delay 10 ns typ

Aperture Jitter 40 ps typ

Full Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V

1.9 MHz typ @ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V
750 kHz typ @ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V
450 kHz typ @ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V

DC ACCURACY

Resolution 8 Bits

Integral Nonlinearity ±0.2 LSB max See the Terminology section

Differential Nonlinearity ±0.2 LSB max

Offset Error ±0.1 LSB max See the Terminology section

Gain Error ±0.1 LSB max See the Terminology section

Total Unadjusted Error (TUE) ±0.3 LSB max See the Terminology section
ANALOG INPUT

Input Voltage Ranges 0 to VDD V

DC Leakage Current ±1 μA max

Input Capacitance 20 pF typ
LOGIC INPUTS

Input High Voltage, V

2 V min 2.7 V ≤ VDD ≤ 3.6 V

Input Low Voltage, V

0.3 × VDD V max 1.8 V ≤ VDD < 2.7 V

0.8 V max 2.7 V ≤ VDD ≤ 3.6 V

Input Current, IIN, SCLK Pin ±1 μA max Typically 20 nA, VIN = 0 V or VDD

Input Current, IIN, CS Pin

Input Capacitance, CIN 10 pF max Sample tested at 25°C to ensure compliance
LOGIC OUTPUTS

Output High Voltage, VOH V

Output Low Voltage, VOL 0.2 V max I

Floating-State Leakage Current ±1 μA max

Floating-State Output Capacitance 10 pF max Sample tested at 25°C to ensure compliance

Output Coding

CONVERSION RATE

Conversion Time 2.94 μs max 10 SCLK cycles with SCLK at 3.4 MHz

Throughput Rate 320 kSPS max See the Serial Interface section

= 3.4 MHz, f

SCLK

0.7 × VDD V min 1.6 V ≤ VDD < 2.7 V

INH

0.2 × VDD V max 1.6 V ≤ VDD < 1.8 V

INL

= 100 kSPS, unless otherwise noted. TA = T

SAMPLE

Maximum/minimum specifications apply as typical figures
when V

−66 dB max See the Terminology section

Maximum specifications apply as typical figures when
V

Guaranteed no missed codes to 8 bits; see the Terminology
sec

±1 μA t

− 0.2 V min I

DD

Straight (natural)

y

binar

yp

SOURCE

SINK

= 1.6 V, fIN = 30 kHz sine wave

DD

= 1.6 V

DD

tion

= 200 μA; VDD = 1.6 V to 3.6 V

= 200 μA

MIN

to T

, unless otherwise noted.

MAX

Rev. C | Page 7 of 28

AD7466/AD7467/AD7468

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Parameter B Version Unit Test Conditions/Comments

POWER REQUIREMENTS

VDD 1.6/3.6 V min/max
IDD Digital inputs = 0 V or VDD

Normal Mode (Operational) 190 μA max VDD = 3 V, f
155 μA max VDD = 2.5 V, f
120 μA max VDD = 1.8 V, f
Power-Down Mode 0.1 μA max SCLK on or off, typically 8 nA

Power Dissipation See the Power Consumption section

Normal Mode (Operational) 0.57 mW max VDD = 3 V, f

0.4 mW max VDD = 2.5 V, f

0.2 mW max VDD = 1.8 V, f
Power-Down Mode 0.3 μW max VDD = 3 V

SAMPLE

SAMPLE

SAMPLE

SAMPLE

SAMPLE

SAMPLE

= 100 kSPS

= 100 kSPS
= 100 kSPS

= 100 kSPS

= 100 kSPS
= 100 kSPS

Rev. C | Page 8 of 28

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TIMING SPECIFICATIONS

For all devices, VDD = 1.6 V to 3.6 V; TA = T
signals are specified with tr = tf = 5 ns (10% to 90% of V

Table 4.

Parameter Limit at T

f

3.4 MHz max Mark/space ratio for the SCLK input is 40/60 to 60/40.

SCLK

MIN

, T

Unit Description

MAX

10 kHz min 1.6 V ≤ VDD ≤ 3 V; minimum f
20 kHz min VDD = 3.3 V; minimum f
150 kHz min VDD = 3.6 V; minimum f
t

16 × t

CONVER T

12 × t
10 × t

AD7466.

SCLK

AD7467.

SCLK

AD7468.

SCLK

Acquisition Time

780 ns max VDD = 1.6 V.
640 ns max 1.8 V ≤ VDD ≤ 3.6 V.
t

10 ns min

QUIET

t1 10 ns min
t2 55 ns min

t3 55 ns max

t4 140 ns max

t5 0.4 t
t6 0.4 t

ns min SCLK low pulse width.

SCLK

ns min SCLK high pulse width.

SCLK

t7 10 ns min

t8 60 ns max

7 ns min SCLK falling edge to SDATA three-state.

MIN

to T

, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input

MAX

) and timed from a voltage level of 1.4 V.

DD

at which specifications are guaranteed.

SCLK

at which specifications are guaranteed.

SCLK

at which specifications are guaranteed.

SCLK

Acquisition time/power-up time from power-down. See the Terminology section.

quisition time is the time required for the part to acquire a full-scale step

The ac
input value within ±1 LSB or a 30 kHz ac input value within ±0.5 LSB.

Minimum quiet time required between bus relinquish and the start of the next

nversion.

co
Minimum CS

to SCLK setup time. If VDD = 1.6 V and f

CS

pulse width.

= 3.4 MHz, t2 has to be 192 ns

SCLK

minimum in order to meet the maximum figure for the acquisition time.
Delay from CS

until SDATA is three-state disabled. Measured with the load circuit
in Figure 2 and defined as the time required for the output to cross the VIH or VIL
voltage.

Data access time after SCLK falling edge. M
and defined as t

he time required for the output to cross the V

SCLK to data valid hold time. Measur
defined as the ti

me required for the output to cross the V

SCLK falling edge to SDATA three-state. t

easured with the load circuit in Figure 2

ed with the load circuit in Figure 2 and

or VIL voltage.

IH

is derived from the measured time taken

8

by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The

ed number is then extrapolated back to remove the effects of charging or

measur
discharging the 50 pF capacitor. This means that the time, t

, quoted in the timing

8

characteristics, is the true bus relinquish time of the part, and is independent of
the bus loading.

or VIL voltage.

IH

200μAI

TO OUTPUT

PIN

C

L

50pF

200μAI

Figure 2. Load Circuit for Digital Out

Rev. C | Page 9 of 28

OL

1.4V

OH

put Timing Specifications

02643-002

AD7466/AD7467/AD7468

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TIMING EXAMPLES

Figure 3 shows some of the timing parameters from Tabl e 4 in
the Timing Specifications section.

Timing Example 1

As shown in Figure 3, f
100 kSPS gives a cycle time of t
Assuming V

= 1.8 V, t

DD

4.41 μs = 4.46 μs, and t
which satisfies the requirement of 10 ns for t
fully powered up and the signal is fully acquired at Point A.
This means that the acquisition/power-up time is t
= 55 ns + 588 ns = 643 ns, satisfying the maximum requirement
of 640 ns for the power-up time.

CS

SCLK

= 3.4 MHz and a throughput of

SCLK

+ t8 + t

CONVERT

= t2 + 15(1/f

CONVERT

= 60 ns maximum, then t

8

t

2

1

ACQUISITION TIME
TRACK-AND-HOLD

IN TRACK

B A

2

SCLK

3

QUIET

) = 55 ns +

QUIET

= 10 μs.

= 5.48 μs,

QUIET

. The part is

+ 2(1/f

2

t

CONVERT

5

4

SCLK

)

TRACK-AND-HOLD IN HOLD

Timing Example 2

The AD7466 can also operate with slower clock frequencies.
As shown in Figure 3, assuming V
and a throughput of 50 kSPS gives a cycle time of t
t

= 20 μs. With t

QUIET

7.55 μs, and t

= 60 ns maximum, this leaves t

8

CONVERT

= t2 + 15(1/f

μs, which satisfies the requirement of 10 ns for t

= 1.8 V, f

DD

= 2 MHz,

SCLK

CONVERT

) = 55 ns + 7.5 μs =

SCLK

to be 12.39

QUIET

. The part is

QUIET

fully powered up and the signal is fully acquired at Point A,
which means the acquisition/power-up time is t

+ 2(1/f

2

SCLK

55 ns + 1 μs = 1.05 μs, satisfying the maximum requirement of
640 ns for the power-up time. In this example and with other
slower clock values, the part is fully powered up and the signal
already acquired before the third SCLK falling edge; however,
the track-and-hold does not go into hold mode until that point.
In this example, the part can be powered up and the signal can
be fully acquired at approximately Point B in

13

14

15

16

t

8

t

QUIET

AUTOMATIC

POWER-DOWN

Figure 3.

+ t8 +

) =

1/THROUGHPUT

POINT A: THE PART IF FULLY POWERED UP WITH VIN FULLY ACQUIRED.

Figure 3. AD7466 Serial Interface Timing Diagram Example

02643-004

Rev. C | Page 10 of 28

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Input Current to any Pin Except Supplies ±10 mA
Operating Temperature Range

Commercial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C

SOT-23 Package

θJA Thermal Impedance 229.6°C/W
θJC Thermal Impedance 91.99°C/W

MSOP Package

θJA Thermal Impedance 205.9°C/W
θJC Thermal Impedance 43.74°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

ESD 3.5 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. C | Page 11 of 28

AD7466/AD7467/AD7468

S

A

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

GND

V

DD

IN

1

AD7466/

2

AD7467/
AD7468

3

TOP VIEW

(Not to Scale)

6

5

4

CS

SDATA
SCLK

Figure 4. SOT-23 Pin Configuration

02643-005

1

CS

AD7466/

2

DAT

SCLK

AD7467/
AD7468

3

TOP VIEW

4

NC

(Not to Scale)

NC = NO CONNECT

Figure 5. MSOP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

SOT-23 MSOP

6 1

Mnemonic

CS

Description

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the

devices and frames the serial data transfer.
1 8 VDD Power Supply Input. The VDD range for the devices is from 1.6 V to 3.6 V.
2 7 GND

Analog Ground. Ground reference point for all circuitry on the devices. All analog input signals should

be referred to this GND voltage.
3 6 V
5 2 SDATA

Analog Input. Single-ended analog input channel. The input range is 0 V to VDD.

IN

Data Out. Logic output. The conversion result from the AD7466/AD7467/AD7468 is provided on this

output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data

stream from the AD7466 consists of four leading zeros followed by the 12 bits of conversion data,

provided MSB first. The data stream from the AD7467 consists of four leading zeros followed by the 10

bits of conversion data, provided MSB first. The data stream from the AD7468 consists of four leading

zeros followed by the 8 bits of conversion data, provided MSB first.
4 3 SCLK

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the parts. This clock

input is also used as the clock source for the conversion process of the parts.
4, 5 NC No Connect.

V

8

DD



7

GND



6

V

IN

NC

5

02643-006

Rev. C | Page 12 of 28

AD7466/AD7467/AD7468

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

DYNAMIC PERFORMANCE CURVES

Figure 6, Figure 7, and Figure 8 show typical FFT plots for the
AD7466, AD7467, and AD7468, respectively, at a 100 kSPS
sample rate and a 30 kHz input tone.

Figure 9 shows the signal-to-noise and distortion ratio

erformance vs. input frequency for various supply voltages

p
while sampling at 100 kSPS with an SCLK frequency of 3.4 MHz
for the AD7466.

Figure 10 shows the signal-to-noise ratio (SNR) performance

put frequency for various supply voltages while sampling

vs. in
at 100 kSPS with an SCLK frequency of 3.4 MHz for the
AD7466.

Figure 11 shows the total harmonic distortion (THD) vs. analog
in

put signal frequency for various supply voltages while sam­pling at 100 kSPS with an SCLK frequency of 3.4 MHz for
the AD7466.

Figure 12 shows the THD vs. analog input frequency for

ferent source impedances with a supply voltage of 2.7 V, an

dif

25

–15

–35

–55

SNR (dB)

–75

–95

5

8192 POINT FFT
V

= 1.8V

DD

f

= 100kSPS

SAMPLE

f

= 30kHz

IN

SINAD = 70.82dB
THD = –84.18dB
SFDR = –85.48dB

SCLK frequency of 3.4 MHz, and sampling at a rate of 100 kSPS
for the AD7466 (see the Analog Input section).

DC ACCURACY CURVES

Figure 13 and Figure 14 show typical INL and DNL perform­ance for the AD7466.

POWER REQUIREMENT CURVES

Figure 15 shows the supply current vs. supply voltage for the
AD7466 at −40°C, +25°C, and +85°C, with SCLK frequency of

3.4 MHz and a sampling rate of 100 kSPS.
Figure 16 shows the maximum current vs. supply voltage for the

AD7466
Figure 17 shows the shutdown current vs. supply voltage.
Figure 18 shows the power consumption vs. throughput rate for

th
voltages. See the

with different SCLK frequencies.

e AD7466 with an SCLK of 3.4 MHz and different supply

Power Consumption section for more details.

15

–5

–25

–45

SNR (dB)

–65

–85

8192 POINT FFT
V

= 1.8V

DD

f

= 100kSPS

SAMPLE

f

= 30kHz

IN

SINAD = 61.51dB
THD = –80.61dB
SFDR = –82.10dB

–115

0 5 10 15 20 25 30 35 40 45 50

Figure 6. AD7466 Dynamic Performance at 100 kSPS

FREQUENCY (kHz)

02643-007

Rev. C | Page 13 of 28

–105

0 5 10 15 20 25 30 35 40 45 50

Figure 7. AD7467 Dynamic Performance at 100 kSPS

FREQUENCY (kHz)

02643-008

AD7466/AD7467/AD7468

www.BDTIC.com/ADI

5

–5

–15

–25

–35

–45

SNR (dB)

–55

–65

–75

–85
–95

0 5 10 15 20 25 30 35 40 45 50

FREQUENCY (kHz)

8192 POINT FFT
V

DD

f

SAMPLE

f

= 30kHz

IN

SINAD = 49.83dB
THD = –79.37dB
SFDR = –70.46dB

Figure 8. AD7468 Dynamic Performance at 100 kSPS

= 1.8V

= 100kSPS

02643-009

–65

–67

–69

–71

–73

–75

THD (dB)

–77

–79

–81

–83

–85

= 1.6V

V

DD

10 100

INPUT FREQUENCY (kHz)

V

= 3V

DD

VDD = 3.6V

V

DD

V

DD

= 2.2V

TEMP = 25°C

= 1.8V

Figure 11. AD7466 THD vs. Analog Input Frequency

100 kSPS for Various Supply Voltages

at

= 2.7V

V

DD

02643-012

–65

–66

–67

–68

–69

SINAD (dB)

–70

–71

–72

–73

10 100

V

= 1.8V VDD = 1.6V VDD = 2.2V

DD

VDD = 3.6V VDD = 3V VDD = 2.7V

INPUT FREQUENCY (kHz)

TEMP = 25°C

Figure 9. AD7466 SINAD vs. Analog Input Frequency

100 kSPS for Various Supply Voltages

at

–68.0

–68.5

–69.0

–69.5

–70.0

–70.5

SNR (dB)

–71.0

–71.5

–72.0

–72.5

–73.0

10 100

V

DD

VDD = 3.6V VDD = 3V VDD = 2.7V

V

= 1.6V

DD

= 1.8V

INPUT FREQUENCY (kHz)

V

DD

TEMP = 25°C

= 2.2V

Figure 10. AD7466 SNR vs. Analog Input Frequency

at

100 kSPS for Various Supply Voltages

02643-010

02643-011

–76

–77

–78

–79

–80

R

= 10Ω

THD (dB)

IN

–81

–82

RIN = 510Ω

–83

–84

10 100

RIN = 100Ω

INPUT FREQUENCY (kHz)

TEMP = 25°C
V

DD

= 1kΩ

R

IN

Figure 12. AD7466 THD vs. Analog Input Frequency

for Va

rious Source Impedances

1.0
VDD = 1.8V
TEMP = 25°C

0.8

f

= 50Hz

IN

f

= 100kSPS

SAMPLE

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 512 1024 1536 2048 2560 3072 3584 4096

CODE

Figure 13. AD7466 INL Performance

= 2.7V

RIN = 0Ω

02643-013

02643-014

Rev. C | Page 14 of 28

AD7466/AD7467/AD7468

www.BDTIC.com/ADI

1.0
VDD = 1.8V
TEMP = 25°C

0.8

f

= 50Hz

IN

f

= 100kSPS

SAMPLE

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

0 512 1024 1536 2048 2560 3072 3584 4096

CODE

Figure 14. AD7466 DNL Performance

02643-015

2.5

2.0

1.5

1.0

SHUTDOWN CURRENT (nA)

0.5

0

1.5 2.0 2.5 3.0 3.5 4.0

TEMP = +85

°

C

TEMP = +25°C

SUPPLY VOLTAGE (V)

TEMP = –40

Figure 17. Shutdown Current vs. Supply Voltage

°

C

02643-018

290

f

= 100kSPS

SAMPLE

265

240

215

190

165

140

SUPPLY CURRENT (μA)

TEMP = +85°C

115

90

65

1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
SUPPLY VOLTAGE (V)

TEMP = –40°C

TEMP = +25°C

Figure 15. AD7466 Supply Current vs. Supply Voltage, SCLK 3.4 MHz

560

TEMP = 25°C

500

440

A)

μ

380

320

260

f

SCLK

f

= 3.4MHz,

SCLK

= 2.4MHz,

f

SAMPLE

f

SAMPLE

= 140kSPS

= 200kSPS

02643-016

1.4
TEMP = 25°C

1.2

= 3.0V

V

1.0

0.8

0.6

POWER (mW)

0.4

0.2

0

0 50 100 150 200 250

THROUGHPUT (kSPS)

DD

V

= 2.7V

DD

VDD = 2.2V

VDD = 1.8V

02643-019

Figure 18. AD7466 Power Consumption vs. Throughput Rate, SCLK 3.4 MHz

MAXIMUM CURRENT (

200

f

= 1.2MHz,

140

80

1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

SCLK

SUPPLY VOLTAGE (V)

f

SAMPLE

= 50kSPS

02643-017

Figure 16. AD7466 Maximum Current vs. Supply Voltage

r Different SCLK Frequencies

fo

Rev. C | Page 15 of 28

AD7466/AD7467/AD7468

www.BDTIC.com/ADI

TERMINOLOGY

Integral Nonlinearity (INL)

The maximum deviation from a straight line passing through
th

e endpoints of the ADC transfer function. For the AD7466/
AD7467/AD7468, the endpoints of the transfer function are
zero scale, a point 1 LSB below the first code transition, and full
scale, a point 1 LSB above the last code transition.

Differential Nonlinearity (DNL)

The difference between the measured and the ideal 1 LSB
ch

ange between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (00 . . . 000) to
(00 . . . 001) f

Gain Error

The deviation of the last code transition (111 . . . 110) to
(111…111) f
error has been adjusted out.

Track-and-Hold Acquisition Time

The time required for the part to acquire a full-scale step

put value within ±1 LSB, or a 30 kHz ac input value within

in
±0.5 LSB. The AD7466/AD7467/AD7468 enter track mode on

CS

the
falling edge. The parts remain in hold mode until the following
CS

falling edge. See Figure 3 and the Serial Interface section for

more details.

Signal-to-Noise Ratio (SNR)

The measured ratio of signal to noise at the output of the ADC.
The sig
rms quantization error within the Nyquist bandwidth (f
The rms value of the sine wave is half of its peak-to-peak value
divided by √2, and the rms value for the quantization noise is
q/√12. The ratio depends on the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise.

For an ideal N-bit converter, the SNR is defined as

SNR = 6.02 N +

Thus, for a 12-bit converter, it is 74 dB; for a 10-bit converter, it
is 62 dB; an

However, in practice, various error sources in the ADCs cause
t

he measured SNR to be less than the theoretical value. These
errors occur due to integral and differential nonlinearities,
internal ac noise sources, and so on.

rom the ideal (that is, AGND + 1 LSB).

rom the ideal (that is, V

falling edge, and return to hold mode on the third SCLK

nal is the rms value of the sine wave input. Noise is the

1.76 db

d for an 8-bit converter, it is 50 dB.

− 1 LSB) after the offset

REF

/2).

S

Signal-to-Noise and Distortion Ratio (SINAD)

The measured ratio of signal-to-noise and distortion at the
o

utput of the ADC. The signal is the rms value of the sine wave,
and noise is the rms sum of all nonfundamental signals up to
half the sampling frequency (f
excluding dc.

Tot a l U n ad ju s te d E rr o r ( TU E)

A comprehensive specification that includes gain error, linearity
er

ror, and offset error.

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental. For
th

e AD7466/AD7467/AD7468, it is defined as

()

THD

where V
V

sixth harmonics.

Peak Harmonic or Spurious Noise (SFDR)

The ratio of the rms value of the next-largest component in the
ADC output spectrum (up to f
value of the fundamental. Typically, the value of this specifica­tion is determined by the largest harmonic in the spectrum, but
for ADCs where the harmonics are buried in the noise floor, it
is a noise peak.

Intermodulation Distortion (IMD)

With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to zero. For
example, the second-order terms include (fa + fb) and (fa − fb),
while the third-order terms include (2fa + fb), (2fa – fb),
(fa + 2fb), and (fa − 2fb).

The AD7466/AD7467/AD7468 are tested using the CCIF

tandard where two input frequencies are used. In this case,

s
the second-order terms are usually distanced in frequency from
the original sine waves, while the third-order terms are usually
at a frequency close to the input frequencies. As a result, the
second- and third-order terms are specified separately. The
calculation of the intermodulation distortion is as per the
THD specification, where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals, expressed in dB.

is the rms amplitude of the fundamental, and V2, V3,

1

, V5, and V6 are the rms amplitudes of the second through

4

log20dB

=

/2), including harmonics, but

S

22222

++++

VVVVV

65432

V

1

/2 and excluding dc) to the rms

S

Rev. C | Page 16 of 28

AD7466/AD7467/AD7468

V

www.BDTIC.com/ADI

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7466/AD7467/AD7468 are fast, micropower, 12-bit,
10-bit, and 8-bit ADCs, respectively. The parts can be operated
from a 1.6 V to 3.6 V supply. When operated from any supply
voltage within this range, the AD7466/AD7467/AD7468 are
capable of throughput rates of 200 kSPS when provided with a

3.4 MHz clock.
The AD7466/AD7467/AD7468 provide the user with an on-

p track-and-hold, an ADC, and a serial interface housed in a

chi
tiny 6-lead SOT-23 or an 8-lead MSOP package, which offer the
user considerable space-saving advantages over alternative
solutions. The serial clock input accesses data from the part, but
also provides the clock source for the successive approximation
ADC. The analog input range is 0 V to V

. An external refer-

DD

ence is not required for the ADC, and there is no on-chip
reference. The reference for the AD7466/AD7467/AD7468 is
derived from the power supply, thus giving the widest possible
dynamic input range.

The AD7466/AD7467/AD7468 also feature an automatic

ower-down mode to allow power savings between conversions.

p
The power-down feature is implemented across the standard
serial interface, as described in the

Normal Mode section.

CONVERTER OPERATION

The AD7466/AD7467/AD7468 are successive approximation
analog-to-digital converters based around a charge redistribu­tion DAC.
of

the ADC.

p

hase. SW2 is closed and SW1 is in Position A, the comparator
is held in a balanced condition, and the sampling capacitor
acquires the signal on V

V

IN

When the ADC starts a conversion, as shown in Figure 20,
SW2 opens and SW1 moves to Position B, causing the com­parator to become unbalanced. The control logic and the
charge redistribution DAC are used to add and subtract fixed
amounts of charge from the sampling capacitor to bring the
comparator back into a balanced condition. When the com­parator is rebalanced, the conversion is complete. The control
logic generates the ADC output code.

nsfer function.

tra

Figure 19 and Figure 20 show simplified schematics

Figure 19 shows the ADCs during the acquisition

.

IN

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

A
SW1

B

AGND

SAMPLING

CAPACITOR

ACQUISITION

PHASE

VDD/2

SW2

COMPARATOR

Figure 19. ADC Acquisition Phase

Figure 21 shows the ADC

02643-020

SAMPLING

CAPACITOR

A

IN

SW1

B

AGND

CONVERSION

PHASE

VDD/2

SW2

COMPARATOR

Figure 20. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding of the AD7466/AD7467/AD7468 is straight
binary. The designed code transitions occur at successive
integer LSB values; that is, 1 LSB, 2 LSB, and so on. The LSB size
for the devices is as follows:

V

/4096 for the AD7466

DD

/1024 for the AD7467

V

DD

/256 for the AD7468

V

DD

The ideal transfer characteristics for the devices are shown in
Figure 21.

111...111

111...110

111...000

011...111

ADC CODE

000...010

000...001

000...000

Figure 21. AD7466/AD7467/AD7468 Transfer Characteristics

1LSB = VDD/4096 (AD7466)
1LSB = V
1LSB = V

ANALOG INPUT

+V

DD

/1024 (AD7467)

DD

/256 (AD7468)

DD

– 1LSB0V 1LSB

TYPICAL CONNECTION DIAGRAM

Figure 22 shows a typical connection diagram for the devices.

is taken internally from VDD and, therefore, VDD should

V

REF

be well decoupled. This provides an analog input range of

INPUT

.

DD

2.5V
REF192

240μA

DD

V

V

IN

GND

0.1μF

DD

1μF

TANT

AD7466

SCLK

SDATA

CS

Figure 22. REF192 as Power Supply to AD7466

10μF

SERIAL

INTERFACE

0 V to V

680nF

0VTOV

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

02643-022

0.1μF

5V
SUPPLY

μC/μP

02643-021

02643-023

Rev. C | Page 17 of 28

AD7466/AD7467/AD7468

www.BDTIC.com/ADI

The conversion result consists of four leading zeros followed by
the MSB of the 12-bit, 10-bit, or 8-bit result from the AD7466,
AD7467, or AD7468, respectively. See the Serial Interface
section. Alternatively, because the supply current required by
the AD7466/AD7467/AD7468 is so low, a precision reference
can be used as the supply source to the devices.

The REF19x series devices are precision micropower, low drop-

ut voltage references. For the AD7466/AD7467/AD7468

o
voltage range operation, the REF193, REF192, and REF191 can
be used to supply the required voltage to the ADC, delivering
3 V, 2.5 V, and 2.048 V, respectively (see

iguration is especially useful if the power supply is quite noisy

f

Figure 22). This con-

or if the system supply voltages are at a value other than 3 V or

2.5 V (for example, 5 V). The REF19x outputs a steady voltage
to the AD7466/AD7467/AD7468. If the low dropout REF192 is
used when the AD7466 is converting at a rate of 100 kSPS, the
REF192 needs to supply a maximum of 240 μA to the AD7466.
The load regulation of the REF192 is typically 10 ppm/mA
(REF192, V

= 5 V), which results in an error of 2.4 ppm (6 μV)

S

for the 240 μA drawn from it. This corresponds to a 0.0098 LSB
error for the AD7466 with V

= 2.5 V from the REF192. For

DD

applications where power consumption is important, the
automatic power-down mode of the ADC and the sleep mode
of the REF19x reference should be used to improve power
performance. See the

Normal Mode section.

Table 7 provides some typical performance data with various
re

ferences used as a V

source under the same setup

DD

conditions. The ADR318, for instance, is a 1.8 V band gap
voltage reference. Its tiny footprint, low power consumption,
and additional shutdown capability make the ADR318 ideal for
battery-powered applications.

Table 7. AD7466 Performance for Voltage Reference IC

Reference Tied to VDD AD7466 SNR Performance (dB)

ADR318 @ 1.8 V 70.73
ADR370 @ 2.048 V 70.72
ADR421 @ 2.5 V 71.13
ADR423 @ 3 V 71.44

ANALOG INPUT

An equivalent circuit of the AD7466/AD7467/AD7468 analog
input structure is shown in Figure 23. The two diodes, D1 and

rovide ESD protection for the analog inputs. Care must be

D2, p
taken to ensure that the analog input signal never exceeds the
supply rails by more than 300 mV. This causes these diodes to
become forward-biased and to start conducting current into the
substrate. Capacitor C1 in

n primarily be attributed to pin capacitance. Resistor R1 is a

ca
lumped component made up of the on resistance of a switch.
This resistor is typically about 200 Ω. Capacitor C2 is the ADC
sampling capacitor with a typical capacitance of 20 pF.

Figure 23 is typically about 4 pF and

V

DD

D1

V

IN

4pF

C1

D2 CONVERSION PHASE—SWITCH OPEN

Figure 23. Equivalent Analog Input Circuit

C2

20pF

R1

TRACK PHASE—SWITCH CLOSED

02643-024

For ac applications, removing high frequency components
from the analog input signal by using a band-pass filter on
the relevant analog input pin is recommended. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This might necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application.

Table 8 provides typical performance data for various op amps

ed as the input buffer under constant setup conditions.

us

Table 8. AD7466 Performance for Input Buffers

Op Amp in the
Input Buffer

AD8510 70.75
AD8610 71.45
AD797 71.42

AD7466 SNR Performance (dB)
30 kHz Input, V

= 1.8 V

DD

When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases and performance degrades.
Figure 12 shows a graph of THD vs. analog input signal

requency for different source impedances when using a supply

f
voltage of 2.7 V and sampling at a rate of 100 kSPS.

DIGITAL INPUTS

The digital inputs applied to the AD7466/AD7467/AD7468
are not limited by the maximum ratings that limit the analog
inputs. Instead, the digital inputs applied can go to 7 V and are
not restricted by the V
For example, if the AD7466/AD7467/AD7468 are operated with

of 3 V, 5 V logic levels could be used on the digital inputs.

a V

DD

However, the data output on SDATA still has 3 V logic levels
when V

= 3 V. Another advantage of SCLK and CS not being

DD

restricted by the V
sequencing issues are avoided. If

, there is no risk of latch-up as there would be on the analog

V

DD

inputs if a signal greater than 0.3 V is applied prior to V

+ 0.3 V limit as on the analog input.

DD

+ 0.3 V limit is that power supply

DD

CS

or SCLK is applied before

DD

.

Rev. C | Page 18 of 28

AD7466/AD7467/AD7468

S

A

www.BDTIC.com/ADI

NORMAL MODE

The AD7466/AD7467/AD7468 automatically enter power­down at the end of each conversion. This mode of operation is
designed to provide flexible power management options and to
optimize the power dissipation/throughput rate ratio for low
power application requirements.
o

peration of the AD7466/AD7467/AD7468. On the
edge, the part begins to power up and the track-and-hold,
which was in hold while the part was in power-down, goes into
track mode. The conversion is also initiated at this point. On
the third SCLK falling edge after the
and-hold returns to hold mode.

For the AD7466, 16 serial clock cycles are required to complete

he conversion and access the complete conversion result. The

t
AD7466 automatically enters power-down mode on the 16th
SCLK falling edge.

For the AD7467, 14 serial clock cycles are required to complete
t

he conversion and access the complete conversion result. The
AD7467 automatically enters power-down mode on the 14th
SCLK falling edge.

For the AD7468, 12 serial clock cycles are required to complete

he conversion and access the complete conversion result.

t

Figure 24 shows the general

CS

falling edge, the track-

THE PART BEGINS

TO POWER UP

CS

CS

falling

THE PART IS POWERED UP

AND VIN FULLY ACQUIRED

The AD7468 automatically enters power-down mode on the
12th SCLK falling edge.

CS

The AD7466 also enters power-down mode if

is brought
high any time before the 16th SCLK falling edge. The conver­sion that was initiated by the

CS

falling edge terminates and
SDATA goes back into three-state. This also applies for the
AD7467 and AD7468; if

CS

is brought high before the conver­sion is complete (the 14th SCLK falling edge for the AD7467,
and the 12th SCLK falling edge for the AD7468), the part enters
power-down, the conversion terminates, and SDATA goes back
into three-state.

CS

Although
bringing

can idle high or low between conversions,

CS

high once the conversion is complete is recom-

mended to save power.
When supplies are first applied to the devices, a dummy conver-

ion should be performed to ensure that the parts are in power-

s
down mode, the track-and-hold is in hold mode, and SDATA is
in three-state.

Once a data transfer is complete (SDATA has returned to three­s

tate), another conversion can be initiated after the quiet time,

, has elapsed, by bringing CS low again.

t

QUIET

AD7468 ENTERS POWER-DOWN

AD7467 ENTERS POWER-DOWN

AD7466 ENTERS POWER-DOWN

SCLK

DAT

123 12 14 16

VALID DATA

Figure 24. Normal Mode Operation

02643-025

Rev. C | Page 19 of 28

AD7466/AD7467/AD7468

S

www.BDTIC.com/ADI

POWER CONSUMPTION

The AD7466/AD7467/AD7468 automatically enter power­down mode at the end of each conversion or if
high before the conversion is finished.

When the AD7466/AD7467/AD7468 are in power-down mode,

ll the analog circuitry is powered down and the current con-

a
sumption is typically 8 nA.

To achieve the lowest power dissipation, there are some

nsiderations the user should keep in mind.

co
The conversion time is determined by the serial clock

f

requency; the faster the SCLK frequency, the shorter the
conversion time. This implies that as the frequency increases,
the part dissipates power for a shorter period of time when the
conversion is taking place, and it remains in power-down mode
for a longer percentage of the cycle time or throughput rate.

Figure 26 shows two AD7466s running with two different
SCLK f

requencies, SCLK A and SCLK B, with SCLK A having
the higher SCLK frequency. For the same throughput rate, the
AD7466 using SCLK A has a shorter conversion time than the
AD7466 using SCLK B, and it remains in power-down mode
longer. The current consumption in power-down mode is very
low; thus, the average power consumption is greatly reduced.

CONVERSION TIME B

SCLK A

SCLK B

CS

CONVERSION TIME A

116

116

Figure 26. Conversion Time Comparison for Different SCLK Frequencies and a Fixed Throughput Rate

CS

is brought

1/THROUGHPUT

This reduced power consumption can be seen in Figure 25,
which sh

ows the supply current vs. SCLK frequency for various
supply voltages at a throughput rate of 100 kSPS. For a fixed
throughput rate, the supply current (average current) drops as
the SCLK frequency increases because the part is in power­down mode most of the time. It can also be seen that, for a
lower supply voltage, the supply current drops accordingly.

390
360
330
300
270
240
210
180

SUPPLY CURRENT (μA)

150
120

= 2.7V

V

DD

= 1.8V

V

DD

90

V

= 1.6V

DD

60

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SCLK FREQUENCY (MHz)

Figure 25. Supply Current vs. SCLK Frequency

for

a Fixed Throughput Rate and Different Supply Voltages

f

= 100kSPS

SAMPLE

TEMP = 25°C

VDD = 3.6V

V

DD

V

DD

= 3.0V

= 2.2V

02643-026

02643-027

1/THROUGHPUT B

1/THROUGHPUT A

CONVERSION TIME A

CS A

CONVERSION TIME B

CS B

116

CLK

POWER DOWN TIME A

POWER DOWN TIME B

Figure 27. Conversion Time vs. Power-Down Time for a Fixed SCLK Frequency and Different Throughput Rates

Rev. C | Page 20 of 28

02643-028

AD7466/AD7467/AD7468

www.BDTIC.com/ADI

Figure 18 shows power consumption vs. throughput rate for a

3.4 MHz SCLK frequency. In this case, the conversion time is
the same for all cases because the SCLK frequency is a fixed
parameter. Low throughput rates lead to lower current con­sumptions, with a higher percentage of the time in power-down

Figure 27 shows two AD7466s running with the same

mode.

requency, but at different throughput rates. The A

SCLK f
throughput rate is higher than the B throughput rate. The
slower the throughput rate, the longer the period of time the
part is in power-down mode, and the average power consump­tion drops accordingly.

Figure 28 shows the power vs. throughput rate for different

voltages and SCLK frequencies. For this plot, all the

supply
elements regarding power consumption that were explained
previously (the influence of the SCLK frequency, the influence
of the throughput rate, and the influence of the supply voltage)
are taken into consideration.

1.4
TEMP = 25°C

1.2
VDD = 3.0V, SCLK = 2.4MHz

1.0

0.8

V

= 3.0V, SCLK = 3.4MHz

0.6

POWER (mW)

0.4

0.2

0

0 50 100 150 200 250

Figure 28. Power vs. Throughput Rate

fo

r Different SCLK and Supply Voltages

V

DD

THROUGHPUT (kSPS)

DD

= 1.8V, SCLK = 2.4MHz

V

= 1.8V, SCLK = 3.4MHz

DD

02643-029

The following examples show calculations for the information
in this section.

Power Consumption Example 1

This example shows that, for a fixed throughput rate, as the
SCLK frequency increases, the average power consumption
drops. From

1.2 MH

Figure 26, for SCLK A = 3.4 MHz, SCLK B =

z, and a throughput rate of 50 kSPS, which gives a cycle

time of 20 μs, the following values can be obtained:

Conversion Time A

= 16 × (1/SCLK A) = 4.7 μs

(23.5% of the cycle time)

Power-Down Time A

= (1/Throughput) − Conversion

Time A = 20 μs − 4.7 μs = 15.3 μs (76.5% of the cycle time)

Conversion Time B

= 16 × (1/SCLK B) = 13 μs

(65% of the cycle time)

Power-Down Time B

= (1/Throughput) − Conversion

Time B = 20 μs − 13 μs = 7 μs (35% of the cycle time)

The average power consumption includes the power dissipated
when t

he part is converting and the power dissipated when the
part is in power-down mode. The average power dissipated
during conversion is calculated as the percentage of the cycle
time spent when converting, multiplied by the maximum
current during conversion. The average power dissipated in
power-down mode is calculated as the percentage of cycle time
spent in power-down mode, multiplied by the current figure for
power-down mode. In order to obtain the value for the average
power, these terms must be multiplied by the voltage.

Considering the maximum current for each SCLK frequency

= 1.8 V,

r V

fo

DD

Power Consumption A

= ((4.7/20) × 186 μA + (15.3/20) ×

100 nA) × 1.8 V = (43.71 + 0.076) μA × 1.8 V = 78.8 μW
= 0.07 mW

Power Consumption B

= ((13/20) × 108 μA + (7/20) ×

100 nA) × 1.8 V = (70.2 + 0.035) μA × 1.8 V = 126.42 μW
= 0.126 mW

It can be concluded that for a fixed throughput rate, the average
p

ower consumption drops as the SCLK frequency increases.

Power Consumption Example 2

This example shows that, for a fixed SCLK frequency, as the
throughput rate decreases, the average power consumption
drops. From
100 kS

Figure 27, for SCLK = 3.4 MHz, Throughput A =

PS (which gives a cycle time of 10 μs), and Throughput B
= 50 kSPS (which gives a cycle time of 20 μs), the following
values can be obtained:

Conversion Time A

= 16 × (1/SCLK) = 4.7 μs

(47% of the cycle time for a throughput of 100 kSPS)
Power-Down Time A

= (1/Throughput A) − Conversion

Time A = 10 μs − 4.7 μs = 5.3 μs (53% of the cycle time)

Conversion Time B

= 16 × (1/SCLK) = 4.7 μs

(23.5% of the cycle time for a throughput of 50 kSPS)
Power-Down Time B

= (1/Throughput B) − Conversion

Time B = 20 μs − 4.7 μs = 15.3 μs (76.5% of the cycle time)

The average power consumption is calculated as explained in
Power Consumption Example 1, considering the maximum
c

urrent for a 3.4 MHz SCLK frequency for V

Power Consumption A

= ((4.7/10) × 186 μA + (5.3/10) ×

= 1.8 V.

DD

100 nA) × 1.8 V= (87.42 + 0.053) μA × 1.8 V = 157.4 μW =

0.157 mW
Power Consumption B

= ((4.7/20) × 186 μA + (15.3/20) ×

100 nA) × 1.8 V = (43.7 + 0.076) μA × 1.8 V = 78.79 μW =

0.078 mW

It can be concluded that for a fixed SCLK frequency, the average

ower consumption drops as the throughput rate decreases.

p

Rev. C | Page 21 of 28

AD7466/AD7467/AD7468

S

A

S

A

www.BDTIC.com/ADI

SERIAL INTERFACE

Figure 29, Figure 30, and Figure 31 show the timing diagrams
for serial interfacing to the AD7466/AD7467/AD7468. The
serial clock provides the conversion clock and controls the
transfer of information from the ADC during a conversion.

The part begins to power up on the

CS

edge of

puts the track-and-hold into track mode and takes

CS

falling edge. The falling

the bus out of three-state. The conversion is also initiated at this
point. On the third SCLK falling edge after the

CS

falling edge,
the part should be powered up fully at Point B, as shown in
Figure 29, and the track-and-hold returns to hold.

For the AD7466, the SDATA line goes back into three-state and
t

he part enters power-down on the 16th SCLK falling edge. If

CS

the rising edge of

occurs before 16 SCLKs elapse, the
conversion terminates, the SDATA line goes back into three­state, and the part enters power-down; otherwise SDATA
returns to three-state on the 16th SCLK falling edge, as shown

Figure 29. Sixteen serial clock cycles are required to perform

in

e conversion process and to access data from the AD7466.

th
For the AD7467, the 14th SCLK falling edge causes the SDATA

line t

o go back into three-state, and the part enters power-down.

CS

If the rising edge of

occurs before 14 SCLKs elapse, the con­version terminates, the SDATA line goes back into three-state,
and the AD7467 enters power-down; otherwise SDATA returns
to three-state on the 14th SCLK falling edge, as shown in

ourteen serial clock cycles are required to perform the

F

Figure 30.

conversion process and to access data from the AD7467.
For the AD7468, the 12th SCLK falling edge causes the SDATA

line t

o go back into three-state, and the part enters power-

CS

t

CONVERT

t

6

5

t

DB11 DB10 DB2 DB1 DB0

7

12 BITS OF DATA

SCLK

DAT

THREE-STATE

t

2

1

t

3

B

2

00

0

4 LEADING ZEROS

43

t

4

0

Figure 29. AD7466 Serial Interface Timing Diagram

CS

SCLK

DAT

THREE-STATE

t

2

12345 1314

t

3

00

4 LEADING ZEROS

B

0

0

Figure 30. AD7467 Serial Interface Timing Diagram

t

CONVERT

t

6

t

4

DB9 DB8 DB0

down. If the rising edge of
the conversion terminates, the SDATA line goes back into three­state, and the AD7468 enters power-down; otherwise SDATA
returns to three-state on the 12th SCLK falling edge, as shown

Figure 31. Twelve serial clock cycles are required to perform

in
th

e conversion process and to access data from the AD7468.

CS

going low provides the first leading zero to be read in by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero; thus, the first clock falling edge on the serial clock
has the first leading zero provided and also clocks out the
second leading zero. For the AD7466, the final bit in the data
transfer is valid on the 16th SCLK falling edge, having been
clocked out on the previous (15th) SCLK falling edge.

In applications with a slow SCLK, it is possible to read in data
o

n each SCLK rising edge. In such a case, the first falling edge

of SCLK after the

CS
zero and can be read in the following rising edge. If the first
SCLK edge after the
leading zero that was clocked out when
unless it is not read on the first SCLK falling edge. The 15th

falling edge of SCLK clocks out the last bit, and it can be read in
the following rising SCLK edge.

If the first SCLK edge after the
clocks out the first leading zero, and it can be read on the SCLK
rising edge. The next SCLK falling edge clocks out the second
leading zero, and it can be read on the following rising edge.

13 14 15 16

t

5

t

t

7

10 BITS OF DATA

5

t

8

CS

occurs before 12 SCLKs elapse,

falling edge clocks out the second leading

CS

falling edge is a falling edge, the first

CS

went low is missed,

CS

falling edge is a rising edge, CS

t

1

t

8

THREE-STATE

t

QUIET

THREE-STATE

t

1

t

QUIET

02643-030

02643-031

Rev. C | Page 22 of 28

AD7466/AD7467/AD7468

S

A

www.BDTIC.com/ADI

CS

SCLK

DAT

THREE-STATE

t

2

1 2 3 4 11 12

t

3

00

4 LEADING ZEROS

B

0

Figure 31. AD7468 Serial Interface Timing Diagram

t

CONVERT

t

0

DB7 DB0

MICROPROCESSOR INTERFACING

The serial interface on the AD7466/AD7467/AD7468 allows
the parts to be connected directly to many different micro­processors. This section explains how to interface the AD7466/
AD7467/AD7468 with some of the more common microcontroller
and DSP serial interface protocols.

AD7466/AD7467/AD7468 to TMS320C541 Interface

The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the

CS

AD7466/AD7467/AD7468. The
facing between the TMS320C541 and the AD74xx devices,
without requiring any glue logic. The serial port of the
TMS320C541 is set up to operate in burst mode (FSM = 1
in the serial port control register, SPC) with internal CLKX
(MCM = 1 in the SPC register) and internal frame signal
(TXM = 1 in the SPC register), so both pins are configured as
outputs. For the AD7466, the word length should be set to
16 bits (FO = 0 in the SPC register). The standard synchronous
serial port interface in this DSP allows only frames with a word
length of 16 bits or 8 bits. Therefore, for the AD7467 and
AD7468 where 14 and 12 bits are required, the FO bit also
would be set up to 16 bits. In these cases, the user should keep
in mind that the last 2 bits and 4 bits for the AD7467 and
AD7468, respectively, are invalid data as the SDATA line goes
back into three-state on the 14th and 12th SCLK falling edge.

To summarize, the values in the SPC register are FO = 0,

M = 1, MCM = 1, and TXM = 1.

FS

input allows easy inter-

t

6

4

t

1

t

t

5

t

7

8 BITS OF DATA

8

t

QUIET

THREE-STATE

Figure 32 shows the connection diagram. For signal processing

pplications, it is imperative that the frame synchronization

a
signal from the TMS320C541 provide equidistant sampling.

AD7466/
AD7467/

1

AD7468

1

ADDITIONAL PINS OMITTED FOR CLARITY.

SCLK

SDATA

CS

Figure 32. Interfacing to the TMS320C541

TMS320C541

CLKX
CLKR
DR

FSX
FSR

AD7466/AD7467/AD7468 to ADSP-218x Interface

The ADSP-218x family of DSPs is interfaced directly to the
AD7466/AD7467/AD7468 without any glue logic. The SPORT
control register must be set up as described in

Table 9 .

Table 9. SPORT Control Register Setup

Setting Description

TFSW = RFSW = 1 Alternate framing
INVRFS = INVTFS = 1 Active low frame signal
DTYPE = 00 Right-justify data
ISCLK = 1 Internal serial clock
TFSR = RFSR = 1 Frame every word
IRFS = 0 Sets up RFS as an input
ITFS = 1 Sets up TFS as an output
SLEN = 1111 16 bits for the AD7466
SLEN = 1101 14 bits for the AD7467
SLEN = 1011 12 bits for the AD7468

02643-032

1

02643-033

Rev. C | Page 23 of 28

AD7466/AD7467/AD7468

www.BDTIC.com/ADI

The connection diagram in Figure 33 shows how the ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode, and the SPORT control register is set
up as described. The frame synchronization signal generated on

CS

the TFS is tied to

, and as with all signal processing applica­tions, equidistant sampling is necessary. However, in this example,
the timer interrupt is used to control the sampling rate of the
ADC and, under certain conditions, equidistant sampling might
not be achieved.

The timer registers, for example, are loaded with a value that
p

rovides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and, there­fore, the reading of data. The frequency of the serial clock is set
in the SCLKDIV register. When the instruction to transmit with
TFS is given (that is, AX0 = TX0), the state of the SCLK is
checked. The DSP waits until the SCLK goes high, low, and high
again before transmission starts. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or
near the rising edge of SCLK, the data can be transmitted, or it
can wait until the next clock edge.

For example, the ADSP-2181 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained, and eight master clock periods
elapse for every SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and,
subsequently, between transmit instructions. This situation
results in nonequidistant sampling as the transmit instruction is
occurring on an SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling is
implemented by the DSP.

AD7466/
AD7467/

1

AD7468

1

ADDITIONAL PINS OMITTED FOR CLARITY.

SCLK

SDATA

CS

Figure 33. Interfacing to the ADSP-218x

ADSP-218x

SCLK
DR

RFS
TFS

1

02643-034

AD7466/AD7467/AD7468 to DSP563xx Interface

The connection diagram in Figure 34 shows how the AD7466/
AD7467/AD7468 can be connected to the synchronous serial
interface (SSI) of the DSP563xx family of DSPs from Motorola.
The SSI is operated in synchronous mode and normal mode
(SYN = 1 and MOD = 0 in Control Register B, CRB) with an
internally generated word frame sync for both Tx and Rx
(Bit FSL1 = 0 and Bit FSL0 = 0 in the CRB register). Set the
word length in Control Register A (CRA) to 16 by setting Bits
WL2 = 0, WL1 = 1, and WL0 = 0 for the AD7466. The word
length for the AD7468 can be set to 12 bits (WL2 = 0, WL1 = 0,
and WL0 = 1). This DSP does not offer the option for a 14-bit
word length, so the AD7467 word length is set up to 16 bits like
the AD7466 word length. In this case, the user should keep in
mind that the last two bits are invalid data because the SDATA
goes back into three-state on the 14th SCLK falling edge.

The frame sync polarity bit (FSP) in the CRB register can be set

o 1, which means the frame goes low and a conversion starts.

t
Likewise, by means of Bits SCD2, SCKD, and SHFD in the CRB
register, it is established that Pin SC2 (the frame sync signal)
and Pin SCK in the serial port are configured as outputs, and
the most significant bit (MSB) is shifted first. To summarize,

MOD = 0

N = 1

SY
WL2, WL1, WL0 depend on the word length
FSL1 = 0, FSL0 = 0
FSP = 1, negative frame sync
SCD2 = 1
SCKD = 1
SHFD = 0

For signal processing applications, it is imperative that the

rame synchronization signal from the DSP563xx provides

f
equidistant sampling.

AD7466/
AD7467/

1

AD7468

1

ADDITIONAL PINS OMITTED FOR CLARITY.

SCLK SCK

SDATA

CS

Figure 34. Interfacing to the DSP563xx

DSP563xx

SRD

SC2

1

02643-035

Rev. C | Page 24 of 28

AD7466/AD7467/AD7468

www.BDTIC.com/ADI

APPLICATION HINTS

GROUNDING AND LAYOUT

The printed circuit board that houses the AD7466/AD7467/
AD7468 should be designed such that the analog and digital
sections are separated and confined to certain areas. This facili­tates the use of ground planes that can be separated easily. A
minimum etch technique is generally best for ground planes
because it gives the best shielding. Digital and analog ground
planes should be joined at only one place. If the devices are in a
system where multiple devices require an AGND to DGND
connection, the connection should still be made at one point
only, a star ground point, which should be established as close
as possible to the AD7466/AD7467/AD7468.

Avoid running digital lines under the device because these
co

uple noise onto the die. The analog ground plane should be
allowed to run under the AD7466/AD7467/AD7468 to avoid
noise coupling. The power supply lines to the devices should
use as large a trace as possible to provide low impedance paths
and to reduce the effects of glitches on the power-supply line.
Fast switching signals, like clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never be run near the analog
inputs. Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other to reduce the effects of feedthrough on the board. A
microstrip technique is the best choice, but is not always
possible with a double-sided board. With this technique, the

component side of the board is dedicated to ground planes,
while signals are placed on the solder side.

Good decoupling is also very important. All analog supplies
s

hould be decoupled with 10 μF tantalum in parallel with 0.1 μF
capacitors to AGND. All digital supplies should have a 0.1 μF
ceramic disc capacitor to DGND. To achieve the best perform­ance from these decoupling components, the user should keep
the distance between the decoupling capacitor and the V
GND pins to a minimum, with short track lengths connecting
the respective pins.

DD

and

EVALUATING THE PERFORMANCE OF THE AD7466 AND AD7467

The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from the PC via an evaluation board
controller. To evaluate the ac and dc performance of the
AD7466 and AD7467, the evaluation board controller can be
used in conjunction with the AD7466/AD7467CB evaluation
board and other Analog Devices evaluation boards ending in
the CB designator.

The software allows the user to perform ac tests (fast Fourier

nsform) and dc tests (histogram of codes) on the AD7466

tra
and AD7467. See the data sheet in the evaluation board package
for more information.

Rev. C | Page 25 of 28

AD7466/AD7467/AD7468

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

2.90 BSC

6

1.60 BSC

PIN 1

INDICATOR

1.30

1.15

0.90

0.15 MAX

1 3452

1.90
BSC

0.50

0.30

2.80 BSC

0.95 BSC

1.45 MAX

SEATING
PLANE

0.22

0.08
10°

0.60

4°

0.45

0°

0.30

COMPLIANT TO JEDEC STANDARDS MO-178-AB

Figure 35. 6-Lead Small Outline Transistor Package [SOT-23]

(RJ-6)

Dim

ensions shown in millimeters

3.20

3.00

2.80

8

5

3.20

3.00

1

2.80

PIN 1

0.65 BSC

0.95

0.85

0.75

0.15

0.38

0.00

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 36. 8-Lead Mini Small Outline Package [MSOP]

5.15

4.90

4.65

4

1.10 MAX

0.23

SEATING
PLANE

0.08

(RM-8)

Dim

ensions shown in millimeters

8°
0°

0.80

0.60

0.40

Rev. C | Page 26 of 28

AD7466/AD7467/AD7468

www.BDTIC.com/ADI

ORDERING GUIDE

Model Temperature Range Linearity Error (LSB)

AD7466BRT-REEL7 −40°C to +85°C ±1.5 max 6-Lead SOT-23 RJ-6 CLB
AD7466BRT-R2 −40°C to +85°C ±1.5 max 6-Lead SOT-23 RJ-6 CLB
AD7466BRTZ-REEL
AD7466BRTZ-REEL7
AD7466BRTZ-R2
AD7466BRM −40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CLB
AD7466BRM-REEL −40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CLB
AD7466BRM-REEL7 −40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CLB
AD7466BRMZ
AD7466BRMZ-REEL
AD7466BRMZ-REEL7
AD7467BRT-REEL −40°C to +85°C ±0.5 max 6-Lead SOT-23 RJ-6 CMB
AD7467BRT-REEL7 −40°C to +85°C ±0.5 max 6-Lead SOT-23 RJ-6 CMB
AD7467BRT-R2 −40°C to +85°C ±0.5 max 6-Lead SOT-23 RJ-6 CMB
AD7467BRTZ-REEL
AD7467BRTZ-REEL7
AD7467BRTZ-R2
AD7467BRM −40°C to +85°C ±0.5 max 8-Lead MSOP RM-8 CMB
AD7467BRM-REEL −40°C to +85°C ±0.5 max 8-Lead MSOP RM-8 CMB
AD7467BRM-REEL7 −40°C to +85°C ±0.5 max 8-Lead MSOP RM-8 CMB
AD7467BRMZ
AD7468BRT-REEL −40°C to +85°C ±0.2 max 6-Lead SOT-23 RJ-6 CNB
AD7468BRT-REEL7 −40°C to +85°C ±0.2 max 6-Lead SOT-23 RJ-6 CNB
AD7468BRT-R2 −40°C to +85°C ±0.2 max 6-Lead SOT-23 RJ-6 CNB
AD7468BRTZ-REEL
AD7468BRTZ-REEL7
AD7468BRM −40°C to +85°C ±0.2 max 8-Lead MSOP RM-8 CNB
AD7468BRM-REEL −40°C to +85°C ±0.2 max 8-Lead MSOP RM-8 CNB
AD7468BRM-REEL7 −40°C to +85°C ±0.2 max 8-Lead MSOP RM-8 CNB
AD7468BRMZ
AD7468BRMZ-REEL
AD7468BRMZ-REEL7
EVAL-AD7466CB
EVAL-AD7467CB
EVAL-CONTROL BRD2

1

Linearity error refers to integral nonlinearity.

2

Z = RoHS Compliant Part, # denotes lead-free product may be top or bottom marked.

3

This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

4

This board is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. For a complete

evaluation kit, order a particular ADC evaluation board (such as EVAL-AD7466CB), the EVAL-CONTROL BRD2, and a 12 V ac transformer. See relevant evaluation board
data sheets for more information.

2

2

2

2

2

2

2

2

3

3

−40°C to +85°C ±1.5 max 6-Lead SOT-23 RJ-6 C2T

2

−40°C to +85°C ±1.5 max 6-Lead SOT-23 RJ-6 C2T

−40°C to +85°C ±1.5 max 6-Lead SOT-23 RJ-6 C2T

−40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CLB#

2

−40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CLB#

2

−40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CLB#

−40°C to +85°C ±0.5 max 6-Lead SOT-23 RJ-6 CMB#

2

−40°C to +85°C ±0.5 max 6-Lead SOT-23 RJ-6 CMB#

−40°C to +85°C ±0.5 max 6-Lead SOT-23 RJ-6 CMB#

−40°C to +85°C ±0.5 max 8-Lead MSOP RM-8 CMU

−40°C to +85°C ±0.2 max 6-Lead SOT-23 RJ-6 CNU#

2

−40°C to +85°C ±0.2 max 6-Lead SOT-23 RJ-6 CNU#

−40°C to +85°C ±0.2 max 8-Lead MSOP RM-8 CNU#

2

−40°C to +85°C ±0.2 max 8-Lead MSOP RM-8 CNU#

2

−40°C to +85°C ±0.2 max 8-Lead MSOP RM-8 CNU#
Evaluation Board
Evaluation Board

4

Control Board

1

Package Description Package Option Branding

Rev. C | Page 27 of 28

AD7466/AD7467/AD7468

www.BDTIC.com/ADI

NOTES

©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02643-0-5/07(C)

Rev. C | Page 28 of 28